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4 Bit Shift

The document describes a 4-bit shift and add multiplier implemented in Verilog, which multiplies two 4-bit inputs and produces an 8-bit product. It includes a test bench that verifies the functionality of the multiplier with various test cases. The multiplier operates based on a clock signal and a start signal, accumulating results based on the least significant bit of the multiplier.

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2 views3 pages

4 Bit Shift

The document describes a 4-bit shift and add multiplier implemented in Verilog, which multiplies two 4-bit inputs and produces an 8-bit product. It includes a test bench that verifies the functionality of the multiplier with various test cases. The multiplier operates based on a clock signal and a start signal, accumulating results based on the least significant bit of the multiplier.

Uploaded by

prafullaenc
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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4 BIT SHIFT & ADD MULTIPLIER

module shift_multiplier(input [3:0] multiplicand, input [3:0] multiplier, input clk,


input start, output reg [7:0] product, output reg done );

reg [2:0] count; // Counter for shift steps

reg [7:0] temp_product; // 8-bit register to hold intermediate result

reg [3:0] temp_multiplier; // Copy of multiplier for shifting

always @(posedge clk) begin

if (start) begin // Initialize values at start

temp_product <= 8'b00000000;

temp_multiplier <= multiplier;

count <= 0;

done <= 0;

end

else if (count < 4) begin // Add multiplicand if LSB of multiplier is 1

if (temp_multiplier[0] == 1)

temp_product <= temp_product + (multiplicand << count); // Accumulate shifted


multiplicand

// Shift multiplier right to process next bit

temp_multiplier <= temp_multiplier >> 1;

count <= count + 1;

end

else if (count == 4) begin // Store final result

product <= temp_product;

done <= 1;

end

end

endmodule
TEST BENCH

module tbw_v;

reg [3:0] multiplicand;

reg [3:0] multiplier;

reg clk;

reg start;

wire [7:0] product;

wire done;

shift_multiplier uut (

.multiplicand(multiplicand),

.multiplier(multiplier),

.clk(clk),

.start(start),

.product(product),

.done(done)

);

// Clock Generation

always #5 clk = ~clk;

initial begin

clk = 0;

start = 0;

multiplicand = 0;
multiplier = 0;

// Test Case 1: 3 x 2

#10 multiplicand = 4'b0011; multiplier = 4'b0010; start = 1;

#10 start = 0; // Ensure pulse for 1 cycle

wait (done);

$display("3 x 2 = %d", product);

// Test Case 2: 7 x 5

#20 multiplicand = 4'b0111; multiplier = 4'b0101; start = 1;

#10 start = 0;

wait (done);

$display("7 x 5 = %d", product);

// Test Case 3: 15 x 15

#20 multiplicand = 4'b1111; multiplier = 4'b1111; start = 1;

#10 start = 0;

wait (done);

$display("15 x 15 = %d", product);

// End Simulation

#20 $finish;

end

endmodule

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