Sequential Circuits

Flip Flops

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Sequential Digital Circuits
• Sequential circuits are digital circuits in which the outputs
depend not only on the current inputs, but also on the previous
state of the output.
• The basic sequential circuit elements can be divided in two
categories:
• Level-sensitive (Latches)
• High-level sensitive
• Low-level sensitive
• Edge-triggered (Flip-flops)
• Rising (positive) edge triggered
• Falling (negative) edge triggered
• Dual-edge triggered

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 Sequential Logic Circuits

Every digital system is likely to have combinational circuits, most systems encountered in
practice also include storage elements, which require that the system be described in term
of sequential logic.

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 Synchronous Clocked Sequential Circuit
A sequential circuit may use many flip-flops to store as many bits as necessary. The
outputs can come either from the combinational circuit or from the flip-flops or both.

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 Clock Response in Latch
• In Fig (a) a positive level response in the control input allows changes, in the output when
the D input changes while the clock pulse stays at logic 1.

• Latches are also called transparent or level triggered flip flops, because the change on the
outputs will follow the changes of the inputs as long as the Enable input is set.

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5-3 Flip-Flops

• The state of a latch or flip-flop is switched by a change in the control input. This momentary
change is called a trigger and the transition it cause is said to trigger the flip-flop. The D latch
with pulses in its control input is essentially a flip-flop that is triggered every time the pulse
goes to the logic 1 level. As long as the pulse input remains in the level, any changes in the data
input will change the output and the state of the latch.

• Edge triggered flip flops are the flip flops that change there outputs only at the transition of
the Enable input. The enable is called the Clock input.

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Clock Response in Flip-Flop

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SR Latch With NOR Gate
The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND
gates. It has two inputs labeled S for set and R for reset.
NOR: Any Input High, output is Low. All Input Low, output is High.
NAND: Any Input Low, output is high. All Input High, output is low.

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SR Latch with NAND Gates
NAND: Any Input Low, output is high. All Input High, output is
low.

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 Excitation Table

& SR = 0

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The Set/Reset (SR) Latch
The Set/Reset latch is the most basic unit of sequential digital circuits. It has two
inputs (S and R) and two outputs outputs Q and Q’. The two outputs must always be
complementary, i.e if Q is 0 then Q’ must be 1, and vice-versa. The S input sets the Q
output to a logic 1. The R input resets the Q output to a logic 0.

SR flip-flop Characteristic Equations, Q(t ) = S+R’Q & SR = 0 12

Clocked SR Flip Flop

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SR Latch with Control Input
• The operation of the basic SR latch can be modified by providing an additional control
input that determines when the state of the latch can be changed. In Fig. 5-5, it
consists of the basic SR latch and two additional NAND gates.
• NAND: Any Input Low, output is high. All Input High, output is low.

In case of Nand gate

F/F, if Both I/P to F/F
= 1. no change in
output

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The Gated Set/Reset (SR) Latch
To be able to control when the S and R inputs of the SR latch can be applied to the
latch and thus change the outputs, an extra input is used. This input is called the
Enable. If the Enable is 0 then the S and R inputs have no effect on the outputs of
the SR latch. If the Enable is 1 then the Gated SR latch behaves as a normal SR latch.

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 SR Latch :- Example
Complete the timing diagrams for :
(a) Simple SR Latch
(b) SR Latch with Enable input.
Assume that for both cases the Q output is initially at logic zero.

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 (C)
D F/F variants

(A)

(B)
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D Latch
One way to eliminate the undesirable condition of the indeterminate state in SR latch is
to ensure that inputs S and R are never equal to 1 at the same time in Fig 5-5. This is
done in the D latch.
NAND: Any Input Low, output is high. All Input High, output is low.

D flip-flop Characteristic Equations

Q(t + 1) = D 18
The Data (D) Latch
A problem with the SR latch is that the S and R inputs can not be at logic 1 at the
same time. To ensure that this can not happen, the S and R inputs can by connected
through an inverter. In this case the Q output is always the same as the input, and
the latch is called the Data or D latch. The D latch is used in Registers and memory
devices.

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The JK Latch
The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the
illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”.

JK flip-flop Characteristic Equations Q(t + 1) = JQ` + K`Q

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JK- Flip Flop variants
With NOR Gate With NAND Gate

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Master-Slave JK F/F

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The D Edge Triggered Flip Flop

The D edge triggered flip flop can be obtained by connecting the J with the K inputs
of a JK flip through an inverter as shown below. The D edge trigger can also be
obtained by connecting the S with the R inputs of a SR edge triggered flip flop
through an inverter.

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The Toggle (T) Edge Triggered Flip Flop

The T edge triggered flip flop can be obtained by connecting the J with the K inputs
of a JK flip directly. When T is zero then both J and K are zero and the Q output does
not change. When T is one then both J and K are one and the Q output will change
to the opposite state, or toggle.

T flip-flop Characteristic Equations Q(t + 1) = TQ` + T`Q

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Characteristic Table

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Excitation Table of F/Fs

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Summary

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Flip Flops with asynchronous inputs (Preset and Clear)

Two extra inputs are often found on flip flops, that either clear or preset the output.
These inputs are effective at any time, thus are called asynchronous. If the Clear is at
logic 0 then the output is forced to 0, irrespective of the other normal inputs. If the
Preset is at logic 0 then the output is forced to 1, irrespective of the other normal
inputs. The preset and the clear inputs can not be 0 simultaneously. In the Preset
and Clear are both 1 then the flip flop behaves according to its normal truth table.

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Level Triggered Master Slave JK Flip Flop
A Master Slave flip flop is obtained by connecting two SR latches as shown below. This flip flop
reads the inputs when the clock is 1 and changes the output when the clock is at logic zero.

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Edge Triggered Master Slave JK Flip Flop
A Master Slave flip flop is obtained by connecting two SR latches as shown below. This flip flop
reads the inputs when the clock is 1 and changes the output when the clock is at logic zero.

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Convert a SR Flip Flop to D Flip Flop

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Convert a D F/F to SR F/F

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• Convert a SR F/F to JK F/F

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Convert a JK Flip Flop to T F/F

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Convert a JK F/F to D F/F

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 5-4 Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of obtaining a

table or a diagram for the time sequence of inputs, outputs,
and internal states. It is also possible to write Boolean
expressions that describe the behavior of the sequential
circuit. These expressions must include the necessary time
sequence, either directly or indirectly.

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 State Equations

The behavior of a clocked sequential circuit can be

described algebraically by means of state equations. A state
equation specifies the next state as a function of the
present state and inputs. Consider the sequential circuit
shown in Fig. 5-15. It consists of two D flip-flops A and B,
an input x and an output y.

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Fig.5-15 Example of Sequential Circuit

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 State Equation

A(t+1) = A(t) x(t) + B(t) x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that specifies

the condition for a flip-flop state transition. The left side of
the equation with (t+1) denotes the next state of the
flip-flop one clock edge later. The right side of the equation
is Boolean expression that specifies the present state and
input conditions that make the next state equal to 1.

Y(t) = (A(t) + B(t)) x(t)`

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 State Table

The time sequence of inputs, outputs, and flip-flop states

can be enumerated in a state table (sometimes called
transition table).

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 State Diagram

The information available in a state table can be

represented graphically in the form of a state diagram. In
this type of diagram, a state is represented by a circle, and
the transitions between states are indicated by directed
lines connecting the circles.

1/0 or input/output:
Means, input =1
output =0
Here, x/y

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 Flip-Flop Input Equations

The part of the combinational circuit that generates

external outputs is descirbed algebraically by a set of
Boolean functions called output equations. The part of the
circuit that generates the inputs to flip-flops is described
algebraically by a set of Boolean functions called flip-flop
input equations. The sequential circuit of Fig. 5-15 consists
of two D flip-flops A and B, an input x, and an output y. The
logic diagram of the circuit can be expressed algebraically
with two flip-flop input equations and an output equation:

DA = Ax + Bx
DB = A`x
y = (A + B)x`
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 Analysis with D Flip-Flop

The circuit we want to analyze is described by the input

equation DA = A x y
The DA symbol implies a D flip-flop with output A. The x and
y variables are the inputs to the circuit. No output equations
are given, so the output is implied to come from the output
of the flip-flop.

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 Analysis with D Flip-Flop

The binary numbers under Axy are listed from 000 through
111 as shown in Fig. 5-17(b). The next state values are
obtained from the state equation A(t+1) = A x y

The state diagram consists of two circles-one for each state

as shown in Fig. 5-17(c)

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 Mealy and Moore Models (1)

• The most general model of a sequential circuit has inputs,

outputs, and internal states. It is customary to distinguish
between two models of sequential circuits:

the Mealy model and the Moore model

• They differ in the way the output is generated.

- In the Mealy model, the output is a function of both the
present state and input.
- In the Moore model, the output is a function of the present
state only.

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 Mealy and Moore Models (2)

When dealing with the two models, some books and other
technical sources refer to a sequential circuit as a finite state
machine abbreviated FSM.

- The Mealy model of a sequential circuit is referred to as a

Mealy FSM or Mealy machine.

- The Moore model is refereed to as a Moore FSM or Moore

machine.

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