International Journal of All Research Education and Scientific Methods (IJARESM),

ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Design and Implementation of Low Power and Area

Efficient of Arithmetic Circuit by Using Gate Diffusion
Input (GDI) Technique
Attili Krishna Murali Gowtham1, M. Sanjivi Naidu2
1
P.GScholor, SanketikaVidyaParishad Engineering College, Visakhapatnam, India
2
Assistant Professor, SanketikaVidyaParishad Engineering College, Visakhapatnam, India

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ABSTRACT

Lot of advancement in VLSI technology makes low power and low energy as important issues in consumer
electronics.In digital circuits, multiplexer or data selector plays an important role where it processes multiple input
lines and gives a single output.With regard to Pass Transistor Logic (PTL), the paper proposes to construct a 4 Bit
Arithmetic Circuit by using the Innovative Gate Diffusion Input (GDI) technique. In this paper, the arithmetic
circuit is designed using basic GDI cell. The design of digital combinational circuit by GDI technique is done using
Tanner EDA tool.The GDI technique overcomes the disadvantages in PTL. These logic styles are simulated, andto
compare the propagation delay, power, and transistor count.The pass transistor logic has a propagation delay of
0.06378ns and a power dissipation of 0.06191 w, compared to the GDI technique’s propagation delay and power
dissipation of 0.04759ns and 0.04007w, respectively. Innovative GDI technique gives less propagation delay and
power consumption when compared with pass transistor logic.

Keywords: Gate Diffusion Input, Pass Transistor Logic, Arithmetic Circuit, Power Dissipation, Propagation delay.

INTRODUCTION

In comparison to conventional CMOS design and existing PTL techniques, the GDI technique is appropriate for the
construction of quick, low-power circuits employing fewer transistors. [12].At the beginning of the 80s, CMOS logic was
introduced and various design technique have been developed to reduced delay propagation and speed up operation. Delay
performance and power reduction is the important parameter for determining circuit efficiency in VLSI digital circuits
[28].The primary factor for high performance computing applications, image processing, portable [3] digital equipment is
need of low power. Numerous research efforts are prompted by the rapid development of portable digital applications, the
necessity for rising speed, small implementation, delay performance, and low power dissipation.Pass transistor logic is a
type of logic that is common in low power digital circuitry (PTL) [15].

Pass transistors logic are designed by using NMOS alone. Different combinational selections are applied to the nMOS
transistors’ gates depending on the selection line.The most common PTL (pass transistor logic) application is in low power
digital circuitry. Benefits of PTL over conventional CMOS are typically described as follows. Small node capacitances
result in 1) high speed and 2) reduced power consumption. it requires less number of transistors; and 3)Small area is
required for lower interconnection [5]. Compared to other logic types, the GDI-based technique is employed to reduce
power delay and complexity in the design of the encoder.

Background

2.1Conventional CMOS Logic

In conventional or complementary CMOS logic gates are made up of an pmos pull-up and a nmos pull down logic network.
CMOS logic style has an advantage of robustness against voltage scaling and transistor sizing .It has high noise margins
and operates reliably at low voltages. Connection of input signals to transistor gates only, facilitates the usage and
characterization of logic cells. The complementary transistor pair makes the layout of CMOS gates efficient and
straightforward. The major disadvantage of CMOS is substantial number of large PMOS transistors which results in high
input loads

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Figure 1: Conventional CMOS Logic

2.2Pass Transistor Logic (PTL)

Pass transistor logic (PTL) is a design technique used in Very Large Scale Integration (VLSI) to implement digital logic
circuits. Instead of using traditional logic gates like AND, OR, and NOT (which rely on transistors and resistors), pass
transistor logic uses transistors to pass logic levels directly between nodes of the circuit.In PTL, MOSFETs (typically
NMOS or PMOS transistors) are used as switches to pass or block signals. The source or drain terminals of the transistor
are connected to the input or output, and the gate terminal is used to control whether the transistor is on or off.

Figure 2: Pass Transistor Logic

One of the challenges with pass transistor logic is the voltage degradation that can occur. NMOS transistors pass a strong
logic '0' but a weak logic '1', while PMOS transistors pass a strong logic '1' but a weak logic '0'. This can introduce logic
level issues, which must be managed. PTL circuits can be faster than conventional CMOS circuits because fewer transistors
are involved, reducing parasitic capacitance. This leads to faster signal propagation in some cases.

3. PROPOSED WORK
3.1 Gate Diffusion Input (GDI) Logic:
Gate Diffusion Input (GDI) is a design technique used in VLSI to reduce power consumption, area, and complexity of
digital circuits, while maintaining or improving performance. GDI is an alternative to traditional CMOS logic and pass
transistor logic, offering benefits like reduced transistor count and lower power dissipation.
Unlike conventional CMOS logic, where a logic gate typically has two terminals (input and output), the GDI cell has three
inputs:

G: The gate of the transistor (as in standard logic gates).

P: Connected to the source/drain of the PMOS transistor.
N: Connected to the source/drain of the NMOS transistor.
This allows the GDI method to implement various logic functions by controlling these three inputs.

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

GDI typically uses fewer transistors than traditional CMOS logic circuits to implement the same logic functions. For
example, inverters, multiplexers, and XOR gates can be implemented with only 2 transistors, compared to the 6 transistors
required in standard CMOS logic.

Figure 3: Gate Diffusion Input Logic

3.24-Bit Arithmetic Circuit

The basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to the adder, it is possible
to obtain different types of arithmetic operations.The diagram of a 4-bit arithmetic circuit is shown in Figure. It has four
full-adder circuits that Constitute the 4-bit adder and four multiplexers for choosing different operations.There are two 4-bit
inputs A and B and a 4-bit output D. The four inputs from A go directly to the X inputs of the binary adder.Each of the four
inputs from B are connected to the data inputs of the multiplexers.

Figure 4: Circuit Diagram for Arithmetic Circuit

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International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

4. SIMULATION RESULTS

Figure 5: Conventional CMOS based 4x1 MUX Schematic diagram and output waveform

Figure 6: Pass Transistor based 4x1 MUX Schematic diagram and output waveform

Figure 7: Gate Diffusion Input based 4x1 MUX Schematic diagram and output waveform

Figure 8: Conventional CMOS based Full Adder Schematic diagram and output waveform

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International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

Figure 9: Gate Diffusion Input based Full Adder Schematic diagram and output waveform

Figure 10: Gate Diffusion Input based Arithmetic Circuit Schematic diagram

Figure 11: Gate Diffusion Input based Arithmetic Circuit output waveform

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 International Journal of All Research Education and Scientific Methods (IJARESM),
ISSN: 2455-6211, Volume 12, Issue 10, October-2024, Available online at: www.ijaresm.com

CONCLUSION

The paper was constructed a 4 Bit Arithmetic Circuit by using the Innovative Gate Diffusion Input (GDI) technique. The
design of digital combinational circuit by GDI technique is done using Tanner EDA tool.The GDI technique overcomes the
disadvantages in PTL. These logic styles are simulated, and to compare the propagation delay, power, and transistor
count.The pass transistor logic has a propagation delay of 0.06378ns and a power dissipation of 0.06191 w, compared to the
GDI technique’s propagation delay and power dissipation of 0.04759ns and 0.04007w, respectively. Innovative GDI
technique gives less propagation delay and power consumption when compared with pass transistor logic.

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