IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO.

2, FEBRUARY 2014 473

TFET Inverters With n-/p-Devices on the Same

Technology Platform for Low-Voltage/Low-Power
Applications
Emanuele Baravelli, Elena Gnani, Member, IEEE, Antonio Gnudi, Member, IEEE,
Susanna Reggiani, Member, IEEE, and Giorgio Baccarani, Fellow, IEEE

Abstract— This paper investigates feasible inverter configura- associated with the TFET architecture include: 1) reaching
tions based on co-optimized n- and p-type tunnel field-effect acceptable ION levels; 2) suppressing ambipolar effects affect-
transistors (TFETs) integrated on the same InAs/Al0.05 Ga0.95 Sb ing the off-state performance; 3) dealing with the superlinear
platform. Based on 3-D full-quantum simulations, the consid-
ered devices feature steep subthreshold slopes and relatively onset and high saturation voltage of device output charac-
high ON -currents and are combined into two inverter designs. teristics [10]; 4) reducing Miller effects associated with the
Benchmarking against aggressively scaled CMOS logic based typically high gate–drain capacitances Cgd [11]; and 5) cointe-
on multigate architectures highlights potential of the proposed grating simultaneously optimized n- and p-type devices. There
TFET implementations to perform up to 10× and 100× faster is wide consensus on the use of heterostructures with staggered
in low operating power and low standby power environments,
respectively. The comparison is conducted at low supply voltages or broken-gap lineups to boost the ON-state current, whereas
(VDD = 0.25 V) and for equal levels of static power consumption. a careful optimization of the device geometry, doping levels,
The proposed TFET-based platform is thus expected to be a good and gate-stack is required to improve output performance.
candidate for low-voltage/low-power applications in near-future Circuit-level evaluation is often conducted with HSPICE or
technology generations. Verilog-A behavioral models [5], [8], [9] exploiting lookup
Index Terms— III–V materials, heterojunction, subthreshold tables based on simplified TCAD simulations, whose accuracy
slope, tunnel-field-effect transistor (TFET). may be in question when aggressively scaled devices need to
I. I NTRODUCTION be investigated. To mitigate this issue, TCAD models could
be calibrated against atomistic simulations [7].
A LTERNATIVES to the conventional CMOS technology
need to be introduced to enable continued miniatur-
ization of integrated circuits (ICs) while keeping the short-
In contrast with the majority of literature, a full-band
quantum simulation approach is adopted in this paper to
channel effects under control. Aggressive scaling of device properly account for quantum effects, which strongly influence
dimensions is currently being pursued by multigate field-effect TFET device, and hence circuit, performance. Device- and
transistors [1], whereas transistors exploiting different oper- circuit-level design is presented for the TFET inverters real-
ating principles are required to further reduce the supply ized on a recently proposed InAs/Al0.05 Ga0.95 Sb technology
voltage VDD . Tunnel-FETs (TFETs) are especially promising platform [12]. Performance of the considered circuit blocks
candidates [2] to overcome the intrinsic 60-mV/decade limita- is compared with the best-case predictions for aggressively
tion to the MOSFET subthreshold slope (SS), thus potentially scaled CMOS logic based on multigate architectures. The
providing transition from very low OFF-currents (IOFF ) to comparison is conducted for equal static power consump-
sufficiently high ON-currents (ION ) within the increasingly tion, exploiting predictive technology models (PTM-MG) for
small VDD window required to contain IC power consumption. CMOS simulation [13], and allows identifying favorable VDD
Boosted by recent experimental advances leading to successful windows where the TFET has a potential to outperform the
demonstration of functional inverter stages [3], [4], consider- traditional technology.
able effort is being placed in the TCAD-assisted evaluation of The rest of this paper is described as follows. The paper
TFET-based digital circuits, to predict their potential bene- is organized as follows. The adopted TFET-based platform
fits over traditional CMOS logics [5]–[9]. Major challenges and the proposed inverted implementations are described in
Section II and III, respectively. Comparison with the CMOS
Manuscript received October 18, 2013; accepted December 6, 2013. Date logic is conducted in Section IV. The concluding remarks are
of publication January 2, 2014; date of current version January 20, 2014. This
work was supported by the EU under Grant 257267, in part by the Italian given in Section V.
Ministry of University and Research through the “Futuro in Ricerca” Project
FIRB 2010. The review of this paper was arranged by Editor H. Jaouen. II. T ECHNOLOGY P LATFORM A SSESSMENT
The authors are with the Department of Electronics, Advanced
Research Center for Electronic Systems, University of Bologna, Bologna Heterostructures are exploited to achieve satisfactory
40136, Italy (e-mail: [email protected]; [email protected]; ION levels with the TFET architecture, and promising
[email protected]; [email protected]; [email protected]). experimental studies have been reported on III–V antimonide
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. compounds [14]. Baravelli et al. [12] have indicated
Digital Object Identifier 10.1109/TED.2013.2294792 InAs/Al0.05 Ga0.95 Sb as a suitable material pair for cointe-
0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 474 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 2, FEBRUARY 2014

Fig. 3. Inverter designs I1 (Tn+Tp) and I2 (Tn+4 Tp instances with modified

WF), with indication of the switching behavior. A two-stage inverter chain
is shown on the right, which is used for transient performance estimation
under self-loading. The schematic illustrates device input capacitances Cg,n
Fig. 1. Considered n-type (Tn) and p-type (Tp) heterojunction TFETs based and Cg,p as well as the gate–drain capacitance Cgd , which is responsible for
on the same InAs/Al0.05 Ga0.95 Sb material pair. Doping concentrations are Miller effects.
indicated in cm−3 and abrupt profiles are assumed. A nonuniform drain
doping is used to reduce ambipolarity in Tn. The gate dielectric is Al2 O3
with an equivalent oxide thickness EOT = 1 nm. (ITRS) requirements [2] on the off-state current for the LSTP
(IOFF = 10 pA/µm) and the LOP (IOFF = 5 nA/µm)
applications are also indicated in the figure. Both the
n-type (Tn) and p-type (Tp) devices comply with the LOP
specifications at VDD = 0.4 V, and the curves are shifted by
the VGS value (VOFF ) at which the corresponding IOFF level is
reached, to compare the device performance for equal static
power consumption. A nonuniform drain doping is required
in the n-TFET to reduce ambipolarity and hence meet this
standard, although the doping configuration in Fig. 1 has been
modified compared with that presented in [12] to trade-off
the leakage and output performance. Both devices exhibit sub-
40 mV/decade minimum SS [Fig. 2(b)] and sub-60 mV/decade
average subthreshold slopes (SSav ) [Fig. 2(c)], which are
Fig. 2. (a) Simulated I D –VGS curves at |VDS | = 0.4 V for the TFETs in sustained for about three decades of drain current [Fig. 2(d)].
Fig. 1 (normalized by device side for consistency with quantization-induced This is combined with relatively high ION levels at 0.4 V
charge distribution). LSTP (10 pA/µm) and LOP (5 nA/µm) specs on IOFF supply voltage, especially for the n-TFET [Fig. 2(e)].
are indicated. Curves are shifted by the respective VOFF , i.e., the VGS at which
ID = 5 nA/µm (= IOFF ,LOP ). Corresponding device performance is evaluated
in terms of (b) minimum SS, (c) average subthreshold slope, SSav , (d) number III. TFET-BASED I NVERTER D ESIGN
of current decades over which SSav is computed, and (e) ION at VDD = 0.4 V.
Two inverter designs are considered as potential competitors
gration of n- and p-type devices with similar dimensions and of a conventional CMOS logic in an LOP scenario with
opposite choices for the source and channel+drain materials. VDD = 0.4 V. The configurations are indicated as I1 and I2
The TFETs considered here are a modified version of the in Fig. 3 and are built exploiting the platform presented in
7-nm-side platform described in [12]: the devices are shown Section II. Specifically, I1 is composed by one Tp and one Tn
in Fig. 1 and feature a gate-all-around nanowire geometry device, whereas I2 has a pull-up network (PUN) with four Tp
with square cross section. Numerical simulations are carried FETs in parallel to compensate for the lower ON-current of
out in a fully 3-D framework. Quantum ballistic transport the p-TFET compared with its n-type counterpart [Fig. 2(e)].
is modeled within the NEGF formalism [15], based on a However, different work-functions (WFs) have been used to
four-band k·p Hamiltonian with accurate choice of material ensure equal OFF-current dissipation for the PUNs of I1 and I2.
parameters, including bowing effects [16]. The NEGF module I D –VDS families computed for the PUN and pull-down
is self-consistently coupled with a 3-D Poisson solver. network (PDN) of I1 and I2 are shown in Fig. 4(a) and (b),
Validation of the software against atomistic tight-binding respectively, as a function of the inverter output
calculations [17] has demonstrated a good agreement of the Vo = VDS,n = VDD + VDS, p (Fig. 3). Voltage transfer
two simulation approaches [12], thus boosting confidence on characteristics (VTCs) of I1 and I2 are computed by
the predictive capabilities of the results presented in this paper. intersection of these curves (black dots in Fig. 4) and
Turn-on curves computed for the TFETs in Fig. 1 are shown nonlinear interpolation, and are shown in Fig. 5(a). The
in Fig. 2(a), where currents are normalized by the device side. strong drive current unbalance between Tn and Tp leads to an
The International Technology Roadmap for Semiconductors asymmetric VTC for I1, whereas symmetry is considerably

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 BARAVELLI et al.: TFET INVERTERS WITH n-/p-DEVICES 475

Fig. 6. (a) Gate capacitance computed through (1) for TFETs Tn and Tp and
normalized by device side. (b) Total input capacitance of the two inverters,
used to compute tr and t f in a self-loading configuration.

Fig. 4. Simulated I D –VDS families in 0.05 V VGS steps for Tn and Tp.
Additional curves at intermediate VGS values are obtained through nonlinear
interpolation between these characteristics. Curves are combined exploiting
Vo = VDS,n = VDD + VDS, p (Fig. 3) to compute VTCs in Fig. 5(a) for
inverters (a) I1 and (b) I2.

Fig. 5. (a) VTCs of inverters I1 and I2 in Fig. 3, computed exploiting Fig. 7. Rise and fall times computed for inverters I1 and I2 in (a) self-
nonlinear interpolation between simulated I D –VDS families, as described in loading (with Miller effects included) and (b) constant-loading. I2 provides
Fig. 4. (b) Voltage gain and (c) current consumption during switching of the more balanced and overall faster performance than I1.
two inverters.
characteristics at VGS = 0 V or |VGS | = VDD from Fig. 4
enhanced with I2. As can be seen from Fig. 5(b) and (c), both  0.9VDD
designs feature voltage gains greater than 10, and I2 exhibits d Vo
tr, f = C L . (2)
a larger switching current than I1 due to the stronger PUN. 0.1VDD |I D, p o − I D,n (Vo )|
(V )
In order to evaluate transient performance of the proposed
The considered load is either a fixed capacitance C L
inverter designs, total gate capacitances of Tn and Tp have
(constant loading condition), or an equal inverter stage in a
been estimated as
chain configuration like the one illustrated in Fig. 3 (self-
Q ON − Q OFF
Cg = (1) loading). In the latter case, Miller effects are accounted for
VDD through an additional load C M = 2 × Cgd , with the estimate
where Q ON − Q OFF is the net charge difference between the on Cgd ≈ 0.8 × C g , which is a reasonable assumption for III–V
and off states of transistor operation and are integrated over TFETs [11]. This leads to an effective load C L = 2.6 × Cin
the whole device domain. The extracted capacitance values are for self-loading transient estimation. The Cgd component is
reported in Fig. 6(a) and lead to the total input capacitance Cin instead neglected in the constant loading condition because
in Fig. 6(b) for inverters I1 and I2. The latter has a higher Cin values C L  C M are considered.
due to the four p-TFETs in its PUN. Transient performance Transient performance obtained with this approach for
is estimated in terms of the 10% to 90% rise and fall times inverters I1 and I2 are reported in Fig. 7: I2 exhibits fairly
tr, f of an inverter in response to an instantaneous voltage balanced rise and fall times and is considerably faster than I1
step. tr and t f are computed by integrating device output under constant loading. Overall, design I2 provides a better

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 476 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 2, FEBRUARY 2014

TABLE I
F IN FET D IMENSIONS U SED IN CMOS S IMULATIONS

Fig. 9. Rise and fall times of TFET-based inverter I2 and of a 10-nm CMOS-
Fig. 8. Unnormalized I D –VGS curves associated with the PUN (4× Tp) and based inverter, operating at LOP-compatible IOFF . CMOS logic is faster than
PDN (Tn) of I2 are compared with those of FinFET-based 10-nm-node CMOS TFET in both (a) self-loading and (b) constant loading, because it provides
computed with PTM-MG SPICE models [13]. The WFs in PTM model cards higher drive current at 0.4 V VDD and is not significantly affected by Miller
are adjusted to make the IOFF , and hence static power dissipation, of FinFETs effects.
equal to that of their TFET counterparts. The subthreshold slope of FinFET
characteristics is about 75 mV/decade. Dashed vertical lines: advantage of
TFETs when reducing VDD from 0.4 to 0.25 V.

combination of static and dynamic performance in an LOP

scenario with VDD = 0.4 V.

IV. TFET V ERSUS CMOS L OGIC

The TFET-based inverter designs presented above are here
benchmarked against the best, FinFET-based CMOS logic
projected to the 10-nm technology node. The considered
FinFET devices have dimensions reported in Table I and are
simulated in SPICE using PTM-MG [13]. The WFs in PTM
model cards have been adjusted to make the IOFF , and hence
static power dissipation, of FinFETs equal to that of their
TFET counterparts.

A. LOP Case
A scenario with the LOP-compatible IOFF and VDD = 0.4 V
is first considered, where I2 is selected as the TFET-based Fig. 10. Same analysis as in Fig. 9, but with VDD = 0.25 V. In this case,
inverter. Turn-on curves associated with its PUN and PDN TFET logic is substantially faster than CMOS in both (a) self-loading and
are compared in Fig. 8 with those obtained from n- and (b) constant loading.
p-type FinFET simulation. The TFETs are seen to provide
considerably improved subthreshold performance, and the two As demonstrated in Fig. 10, in such a situation, the TFET logic
architectures exhibit a break-even point for current drive at is predicted to be about 10× and 7× faster than CMOS under
|VGS − VOFF,LOP |  0.35 V, so that FinFETs have some ION self-loading and constant loading conditions, respectively.
advantage at 0.4 V VDD . As a consequence, the CMOS logic
is faster than its TFET counterpart in these conditions, both B. LSTP Case
considering a self-loading or a constant loading situation, as Shrinking the supply voltage is also beneficial to n-TFET
demonstrated in Fig. 9(a) and (b), respectively. Results for the ambipolarity, so that LSTP requirements on IOFF can be met
self-loading case are further motivated by the higher effective even by Tn at VDS = 0.25 V. This is shown in Fig. 11, where
load of TFET inverters due to the Miller contribution, which turn-on curves of TFET and CMOS technologies are compared
is instead assumed to be negligible for the CMOS logic. in an LSTP scenario with VDD = 0.25 V. In this case the
On the other hand, Fig. 8 indicates potential advan- ON -current of Tn is well balanced by that of a single p-TFET,
tage of TFET at sub-0.35 V supply voltage. Especially, at so inverter configuration I1 in Fig. 3 with one device in both its
VDD = 0.25 V, the advantage in current drive is over 10×. PUN and its PDN is expected to be convenient. The associated

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 BARAVELLI et al.: TFET INVERTERS WITH n-/p-DEVICES 477

Fig. 11. Unnormalized I D –VGS curves obtained for TFETs Tn and Tp Fig. 13. Rise and fall times of TFET-based inverter I1 and of a 10-nm
at |VDS | = 0.25 V are compared with those of 10-nm-node CMOS. WFs CMOS-based inverter, both operating at LSTP-compatible IOFF and VDD =
of all devices are adjusted to provide equal static power dissipation with 0.25 V. In this situation, TFET technology provides a strong advantage over
LSTP-compatible IOFF . Curves obtained for n- and p-TFETs with longer CMOS under both (a) self-loading and (b) constant loading.
channels (L g = 40 nm) are also shown to illustrate potential ways to improve
TFET subthreshold behavior. TABLE II
P ERFORMANCE C OMPARISON OF TFET AND CMOS L OGIC

which act as free carriers in the n-type device. The channel

Fig. 12. (a) VTCs of TFET-based inverter I1 and of a 10-nm CMOS-based length could therefore be considered as a further design para-
inverter, under LSTP-compatible operation at VDD = 0.25 V. (b) Voltage gain
and (c) current consumption during switching of the two inverters.
meter for a more complex optimization, leading to different
L g choices for n- and p-type devices and for different supply
voltages, in order to balance the on-state performance. This
VTC in Fig. 12(a) still exhibits some asymmetry due to the will be the object of future studies, but is not considered in
different subthreshold behavior of Tn and Tp, but it features this paper, whose focus is on a highly symmetric platform that
a steeper transition compared with that of an LSTP-CMOS can be used in various VDD regimes.
implementation. This is confirmed by the higher voltage gain Results of the comparison conducted in this section between
extracted for the TFET logic and shown in Fig. 12(b), although TFET and CMOS technology is quantitatively summarized in
the better current drive of this technology is also reflected in a Table II in terms of static power dissipation, TFET to CMOS
higher switching current compared with CMOS [Fig. 12(c)]. In ION ratio for the PUN and PDN of the compared inverters,
terms of transient performance, TFET-based logic is predicted as well as the speedup in self-loading [Speedup (Cin )] and
to be over two orders of magnitude faster than a 10-nm CMOS constant loading [Speedup (C L )] conditions. Static power
inverter in LSTP applications with 0.25 V supply voltage. This consumption is equal for the two technologies as a design
is shown in Fig. 13 for both loading conditions considered in constraint, whereas other figures of merit are defined so that
this paper. values greater than 1 indicate advantage of TFET over CMOS
It is worth noting that the subthreshold behavior of the 
n-type TFET could be greatly improved by suppressing direct ION, TFET 
ION ratio = (3)
source–drain tunneling through a longer channel. For example, ION, CMOS same IOFF

Fig. 11 shows the impact of increasing the channel length L g (tr + t f )CMOS 
Speedup (C x ) = . (4)
of Tn from 20 to 40 nm. On the other hand, only a modest (tr + t f )TFET Load=C x
improvement is observed when the same L g modification is
applied to the p-TFET Tp. This is attributed to the higher Table II clearly shows the potential of the TFET technol-
effective mass of holes in Tp compared with that of electrons, ogy to perform substantially faster than a best-case CMOS

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 478 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 2, FEBRUARY 2014

implementation at 0.25 V supply voltage, for equal levels [14] G. Zhou, R. Li, T. Vasen, M. Qi, S. Chae, Y. Lu, et al., “Novel
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with ITRS requirements on the off-state leakage for the LOP Emanuele Baravelli received the Ph.D. degree
or low LSTP applications. Results are compared with the best- in electrical engineering from the University of
Bologna, Bologna, Italy, in 2008.
case predictions for aggressively scaled CMOS logic based on He was a Post-Doctoral Researcher with the
multigate architectures. It is found that the TFET implementa- University of Bologna and the Georgia Institute
tions have potential to perform up to 10× and 100× faster than of Technology, Atlanta, GA, USA. His current
research interests include nanoelectronics and signal
the CMOS in the LOP and LSTP environments, respectively, processing.
at very low supply voltages VDD = 0.25 V, for equal levels
of static power dissipation.

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