A B C D E

1 1

LCFC Confidential
2

BE560 Rev1.0 Schematic 2

Intel SkyLake Processor with DDRIIIL + PCH-LP

AMD Litho XT GDDR5 2GB
2015-07-28 Rev1.0
3 3

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/11/04 Deciphered Date 2014/09/07 COVER PAGE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 1 of 99

A B C D E
 A B C D E

SkyLake
Memory BUS (DDRIII)
1
USB 2.0 Port 7 1DPC (Interleaved) DDR3L-SO-DIMM X2 1

eDP Conn. BANK 0, 1, 2, 3

USB Port 7 DP Port0 1.35V DDRIIIL 1333/1600 MT/s
DP Port 0 UP TO 16G Page 18~19
Page 38
Intel 20141227_S
USB 2.0 Port 2 & 3 5V 480MHz
SkyLake-U 2+2 type Litho XT 2GB GDDR5
Processor PCIE Port 9-12
OneLink board 128M*32bit *4pcs
Page 60 USB 3.0 Port 3& 4 5V 5GT/s
Sub/B PCIe port 9-12
BGA1356 Page 27~36
40mm*24mm
NGFF Card
DP Repeater DDI1 HDMI PCIe Gen1 Port 3 NGFF Card WLAN
On OneLink board PCIe Port 3
DDI1 USB 2.0 port6
MUX USB 2.0 port 6 page 50

HDMI Conn. DDI2 DP DDI1

Page 37 Page 42
USB Left
2
+ 2

USB 3.0 , Port 1,2 5V 5GT/s JUSB1 JUSB2 AOU

USB 3.0 Port 2 USB 3.0 Port 1
VGA Conn DP to CRT DDI2
USB 2.0 , port 1,2 5V 480MHz USB 2.0 Port 2 USB 2.0 Port 1
Converter TPS2546RTER
Page 40 Page 41 Page 45 USB charger Page 45

20141227_S Intel PCH-LP

Intel USB 2.0 x 2 Int. Camera
RJ45 Conn WGI219V-QQJZ Non Vpro PCIe Gen1 Port 4 USB 2.0 Port 7
WGI219LM QQJY Vpro Page 38
Page 49
QFN48_6X6
PCIe port 4
Page 47
Touch Panel
USB 2.0 Port 5
Page 64

Card Reader
Realtek RTS5227S PCIe Gen1 Port 6
Power Circuit DC/DC SD/MMC/XD Conn
USB 2.0 Port 5 Finger printer
Page 73~88 USB 2.0 Port Page
9 65
Page 51
3 3

One-Link Docking Board

SATA Gen3 Port 0 SATA HDD
SATA Port 0
page 43
&
USB3.0 Port3 SPI ROM
4MB+8MB/TPM
SPI BUS SATA Gen2 Port 1 SATA ODD
3.3V 33MHz SATA Port 1
(NPCT652LAAWX) Page 5~20
page 44

Page 23,69

Combon Jack Board LPC BUS HD Audio

3.3V 33MHz 3.3V 24MHz

Codec
Mirror function EC CX11852-11z
SP_OUTR/L
SPK Conn.
ITE IT8586E/FX Page 55
Power Board Page 54
Page 61

HP_R/L_JACK
SMB BUS Ext Mic

Thermal Sensor Int.KBD G-Sensor

4 Fintek F75303M LIS3DHTR Combo Jack 4

Page 66 Page 64 Page 68 Page 55

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 BLOCK DIAGRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 2 of 99

A B C D E
 A B C D E

1 1

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
STATE SLP_A# SLP_S3# SLP_S4# SLP_S5# EC_ON2 EC_ON SUSP#
+5VS
Power Plane +3VS
Full ON HIGH HIGH HIGH HIGH ON ON ON

+VCC_CORE S1(Power On Suspend) HIGH HIGH HIGH HIGH ON ON ON

+VCC_IO
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF
+VCC_SA
+3VALW
+VCC_ST S4 (Suspend to Disk) LOW LOW LOW HIGH ON ON OFF
B+ +5VALW +1.35V +VCC_STG
S5 (Soft OFF) LOW LOW LOW LOW ON ON OFF
+1.8VALW +VGA_CORE
+3VS_VGA
State +1VALW +1.8VS_VGA
+1.35VS_VGA
SMBUS Control Table
+0.675VS
Main WLAN Thermal CP Security G
SOURCE VGA BATT SODIMM WiMAX Sensor PCH Module ROM LAN PHY sensor
2 2

S0 O O O O EC_SMB_CK1 IT8580F
X V X X X X X X X X
EC_SMB_DA1 +3VL
+3VALW

S3 O O O X EC_SMB_CK3 IT8580F
V X X X V V
EC_SMB_DA3 +3VS +3VS_VGA +3VS +3V_PCH
X X X V
+3VALW_GS

S5 S4/AC Only O O X X PCH_SMB_CLK PCH

X X V X X X V X X
PCH_SMB_DATA
+3V_PCH +3VS +5VS
V
+3VS
S5 S4
Battery only O X X X PCH_SML0_CLK
PCH_SML0_DAT
PCH
X X X X X X X X V X
+3V_PCH +3VALW

S5 S4
AC & Battery X X X X
don't exist USB2 Port USB3 Port PCIE Port SATA Port
3 3
Port Device Port Device Port Device Port Device

1 JUSB2 1 JUSB2 1 3D CCD(USB3) 1 HDD

2 JUSB3 2 JUSB3 2 X 2 ODD
3 Sub Board 3 Sub Board 3 WLAN 3 X
4 Docking 4 Docking 4 LAN 4 X
5 Touch Panel 5 3D CCD(PCIE1) 5 X
6 BT 6 CardReader
7 CMOS 7 X
8 FP/Smart 8 X
9 GPU
10 GPU
11 GPU
12 GPU

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/11/04 Deciphered Date 2014/09/07 NOTE LIST
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 3 of 99

A B C D E
 5 4 3 2 1

VGA and DDR3 Voltage Rails (Litho XT 2GB DDR3) 20141227_S

BOM Structure Table
GPIO I/O ACTIVE Function Description
BOM Structure NOTE
D GPIO0 OUT N/A D

PCB@ For PCB load BOM

GPIO5 IN - GPIO5_AC_BATT
XDP@ Debug port
GPIO6 IN - GPIO6
UMA@ UMA SKU ID
GPIO7 OUT N/A
DIS@ Optimus SKU ID
GPIO8 OUT - GPIO8_ROMSO
DIMM2@ For DIMM2 function
GPIO9 OUT - GPIO9_ROMSI

-
DIMM1@ For DIMM1 function
GPIO10 OUT GPIO10_ROMSCK
VPRO@ For VPRO function
GPIO11 OUT N/A
ME@ ME Connector
GPIO12 OUT N/A
EMC@ For EMC function
GPIO13 OUT N/A
EMC_2D@ For EMC function
GPIO15 IN N/A SVI2_SVD
EMC_NS@ For EMC function
GPIO16 OUT N/A
C C
RF_NS@ For RF function
GPIO17 OUT N/A
S2G@ For VRAM Strap
GPIO19 OUT N/A GPIO19_CTF
CHA@ For VRAMA function
GPIO20 IN IN GPIO20
CHB@ For VRAMB function
GPIO21 OUT N/A
RANKA@ GPU DDR5 Setting
GPIO22 OUT N/A GPIO22_ROMCSB
X76@ GPU VRAM Setting
GPIO29 OUT N/A
3DCCD@ 3D Camera Setting
GPIO30 OUT N/A
VGA@ VGA Setting
+3VS_VGA MUX@ MUX Setting

+1VS_VGA ODD@ ODD Setting

TPM@ Trusted Platform Module (TPM)
+1.8VS_VGA
B
NVPRO@ For Non-VPRO function B

+VGA_CORE MIRROR@ For mirror function

+1.35VS_VGA 10us

RESET
GPU Litho XT 2GB DDR3

FB Memory (DDR3L) PS_3 (RV114) PS_3 (RV117)

1. all power rail ramp up time should be within 20ms

Samsung K4W4G1646D-BC1A
1000MHz
Device ID setting I2C Slave addrees ID 256Mx16 PH 3.4K PD 10K

JET-XT 0xFFFF SMB_ALT_ADDR Hynix H5TC4G63AFR-11C

0 0xFF
(ROM_SO Bit 1) 1000MHz
256Mx16 PH 4.75K NC
1 0xFF
Micro MT41J256M16HA-093G
1000MHz
256Mx16 PH 3.24K PD 5.62K
A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/11/04 Deciphered Date 2014/09/07 VGA NOTE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 4 of 99

5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1A
DDI1_MUX_TX0- E55 C47 CPU_EDP_TX0-
[42] DDI1_MUX_TX0- DDI1_MUX_TX0+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- [38]
F55 C46
[42] DDI1_MUX_TX0+ DDI1_MUX_TX1- DDI1_TXP[0] EDP_TXP[0] CPU_EDP_TX1- CPU_EDP_TX0+ [38]
E58 D46
[42] DDI1_MUX_TX1- DDI1_MUX_TX1+ F58 DDI1_TXN[1] EDP_TXN[1] C45 CPU_EDP_TX1+ CPU_EDP_TX1- [38] EDP
[42] DDI1_MUX_TX1+ DDI1_MUX_TX2- DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ [38]
F53 EDP A45
HDMI & DOCKING [42] DDI1_MUX_TX2- DDI1_MUX_TX2+ G53 DDI1_TXN[2] HDMI EDP_TXN[2] B45
[42] DDI1_MUX_TX2+ DDI1_MUX_TX3- DDI1_TXP[2] EDP_TXP[2]
F56 A47
[42] DDI1_MUX_TX3- DDI1_MUX_TX3+ DDI1_TXN[3] EDP_TXN[3]
G56 B47
[42] DDI1_MUX_TX3+ DDI1_TXP[3] EDP_TXP[3]
DDI2_VGA_TX0- C50 E45 CPU_EDP_AUX#
[41] DDI2_VGA_TX0- DDI2_VGA_TX0+ DDI2_TXN[0] DDI EDP EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# [38]
D50 F45
VGA [41] DDI2_VGA_TX0+ DDI2_VGA_TX1- C52 DDI2_TXP[0] DP EDP_AUXP CPU_EDP_AUX [38]
[41] DDI2_VGA_TX1- DDI2_VGA_TX1+ DDI2_TXN[1]
D52 B52
[41] DDI2_VGA_TX1+ DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50 PCH_MUX_AUX#
DDI2_TXP[2] DDI1_AUXN PCH_MUX_AUX PCH_MUX_AUX# [42]
D51 F50
DDI2_TXN[3] DDI1_AUXP PCH_VGA_AUX# PCH_MUX_AUX [42]
C51 E48
DDI2_TXP[3] DDI2_AUXN PCH_VGA_AUX PCH_VGA_AUX# [41]
F48
DDI2_AUXP PCH_VGA_AUX [41]
G46
DISPLAY SIDEBANDS DDI3_AUXN F46
PCH_MUX_CLK L13 DDI3_AUXP
[42] PCH_MUX_CLK PCH_MUX_DAT GPP_E18/DDPB_CTRLCLK PCH_MUX_HPD
L12 L9 PCH_MUX_HPD [42]
[42] PCH_MUX_DAT GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 PCH_VGA_HPD
L7 PCH_VGA_HPD [41]
DP_DDC_CLK N7 GPP_E14/DDPC_HPD1 L6
DP_DDC_DAT N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD [38]
N11
N12 GPP_E22/DDPD_CTRLCLK R12 ENBKL
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_EDP_PWM ENBKL [61]
R11
EDP_COMP E52 EDP_BKLTCTL PCH_ENVDD PCH_EDP_PWM [38]
+VCC_IO RC344 1 2 24.9_0402_1% U13
EDP_RCOMP EDP_VDDEN PCH_ENVDD [38]
C C
[SKL PDG]EDP_RCOMP Pull up to VCCIO via 24.9 ohm resistor SKYLAKE-U_BGA1356
REV = 1
1 OF 20 ??

[SKL PDG]EDP_RCOMP @
1. Trace width=20 mils, Spacing=25mil, Max length=100mils
2. RC1 close to MCP

DDPB_CTRLDATA, DDPC_CTRLDATA Internal PD 20K

+3VS

ENBKL RC209 1 2 100K_0402_5%

RC277 1 @ 2 2.2K_0402_5% PCH_MUX_CLK CPU_EDP_HPD RC159 1 2 100K_0402_5%

RC287 1 2 2.2K_0402_5% PCH_MUX_DAT

[SKL PDG]EDP_HPD Pull down to ground via
RC1 1 @ 2 2.2K_0402_5% DP_DDC_CLK 100k ohm resistor
PCH_MUX_HPD RC288 1 @ 2 100K_0402_5%
RC2 1 2 2.2K_0402_5% DP_DDC_DAT

[SKL PDG]For DP required

PCH_VGA_HPD RC204 1 2 100K_0402_5%
B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(1/16):DDI/EDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 5 of 99

5 4 3 2 1
 5 4 3 2 1

D D

+VCC_ST

+VCC_STG [SKL PDG]1 K pull- up t o

1
VCCST
RC53
1K_0402_1%

2
1
RC294 THRMTRIP#
1K_0402_5% [SKL PDG]Refer Figure 45-1
C C

2
UC1D SKL_ULT

TC119 1 D63 +VCC_ST

H_PECI CATERR#
[61] H_PECI VR_HOT# VR_HOT#_R
A54
PECI 15/0526
RC5 1 2 499_0402_1% C65
[61,75,79] VR_HOT# PROCHOT# JTAG
1 2 THRMTRIP# C63
[28] H_THERMTRIP# THERMTRIP# XDP_TCLK XDP_TDI
RC54 @ 0_0402_5% A65 B61 RC31 1 XDP@ 2 51_0201_5%
SKTOCC# PROC_TCK D60 XDP_TDI
CPU MISC PROC_TDI
1 XDP_BPM#0 C55 A61 XDP_TDO XDP_TMS RC34 1 XDP@ 2 51_0201_5%
TC1 XDP_BPM#1 BPM#[0] PROC_TDO XDP_TMS
1 D55 C60
TC2 XDP_BPM#2 BPM#[1] PROC_TMS XDP_TRST#
1 B54 B59
TC7 XDP_BPM#3 BPM#[2] PROC_TRST#
1 C56
TC9 BPM#[3] PCH_JTAG_TCK XDP_TCLK
B56 1 TC10 RC4 1 2 51_0201_5%
EC_WAKE# RC40 1 2 0_0402_5% EC_WAKE#_L A6 PCH_JTAG_TCK D59 PCH_JTAG_TDI
[61] EC_WAKE# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI A56 PCH_JTAG_TDO XDP_TRST# RC6 1 2 51_0201_5%
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 PCH_JTAG_TMS
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TMS C61 PCH_JTAG_TRST# PCH_JTAG_TCK RC352 1 2 51_0201_5%
GPP_B4/CPU_GP3 PCH_TRST# A59 PCH_JTAGX
RC151 1 2 49.9_0402_1% PROC_POPIRCOMP AT16 JTAGX
1 2 PCH_OPIRCOMP AU16 PROC_POPIRCOMP
[SKL PDG]If THERMTRIP# goes active, the CPU is indicating an overheat
RC55
RC200 1 2
49.9_0402_1%
49.9_0402_1% OPCE_RCOMP H66 PCH_OPIRCOMP 20141229
condition, and the PCH will immediately transition to an S5 state. CPU_GP can RC56 1 2 49.9_0402_1% OPC_RCOMP H65 OPCE_RCOMP
be used from external sensors for the thermal management. OPC_RCOMP

SKYLAKE-U_BGA1356 ? 4 OF 20 ?
REV = 1
[SKL PDG]PROC_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm
[SKL PDG]Refer Figure 45-1 +1VALW_PCH
@
∮ 1 %.
[SKL PDG]PCH_OPI_RCOMP: Signal should be pulled down to ground with a resistance of 50 ohm
∮ 1 %.
[SKL PDG]On Package Interface Compensation (OPI) Guidelines PCH_JTAG_TDI RC354 1 XDP@ 2 51_0201_5%
 Should be referenced to VSS plane only. VSS reference planes must be continuous
 Require low DC resistance routing <0.2 ohm 15/0526 PCH_JTAG_TMS RC353 1 XDP@ 2 51_0201_5%
 Avoid routing next to clock pins or noisy signals. XDP_TCLK PCH_JTAGX
RC415 1 DCI@ 2 0_0201_5%
B
XDP_TDI RC422 1 DCI@ 2 0_0201_5% PCH_JTAG_TDI B
XDP_TDO RC423 1 DCI@ 2 0_0201_5% PCH_JTAG_TDO
XDP_TMS RC424 1 DCI@ 2 0_0201_5% PCH_JTAG_TMS
XDP_TRST# RC425 1 DCI@ 2 0_0201_5% PCH_JTAG_TRST#

+VCC_ST +VCC_STG

@
XDP_TDO RC3 1 2 51_0201_5%
XDP_TDO RC426 1 2 51_0201_5%

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(2/16):MISC/JTAG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 6 of 99

5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1B

AU53 SA_CLK_DDR#0
DDR_A_D0 DDR0_CKN[0] SA_CLK_DDR0 SA_CLK_DDR#0 [25]
AL71 AT53
[25] DDR_A_D[0..63] DDR_A_D1 DDR0_DQ[0] DDR0_CKP[0] SA_CLK_DDR#1 SA_CLK_DDR0 [25]
AL68 AU55
[25] DDR_A_DQS#[0..7] DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] SA_CLK_DDR1 SA_CLK_DDR#1 [25]
AN68 AT55
[25] DDR_A_DQS[0..7] DDR_A_D3 DDR0_DQ[2] DDR0_CKP[1] SA_CLK_DDR1 [25]
AN69
[25] DDR_A_MA[0..15] DDR_A_D4 DDR0_DQ[3] DDRA_CKE0_DIMMA
AL70 BA56
DDR_A_D5 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE1_DIMMA DDRA_CKE0_DIMMA [25]
AL69 BB56
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] DDRA_CKE1_DIMMA [25]
AN70 AW56
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[3]
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDRA_CS0_DIMMA#
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS1_DIMMA# DDRA_CS0_DIMMA# [25]
AU71 AU43
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[1] DDRA_ODT0_DIMMA# DDRA_CS1_DIMMA# [25]
AU68 AT45
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDRA_ODT1_DIMMA# DDRA_ODT0_DIMMA# [25]
AR71 AT43
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[1] DDRA_ODT1_DIMMA# [25]
AR69
DDR_A_D14 AU70 DDR0_DQ[13] BA51 DDR_A_MA5
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9
DDR_A_D16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDR_A_MA6
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7
C DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BS2 C
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BS2 [25]
BA65 AW54
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_MA15
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA14
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13
DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CAS#
DDR_A_D27 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_WE# DDR_A_CAS# [25]
AW59 AT46
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_RAS# DDR_A_WE# [25]
BB61 AU50
DDR_A_D29 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BS0 DDR_A_RAS# [25]
AY61 AU52
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BS0 [25]
BA59 AY51
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
? AT48 DDR_A_BS1
DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BS1 [25]
AY39 AT50
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4]
DDR_A_D38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDR_A_DQS#0
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDR_A_DQS#1
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDR_A_DQS#2
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4
DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7
B B
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR_A_D55 DDR0_DQ[54]/DDR1_DQ[38]
DDR_A_D56
BB29
AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT#
AW50
AT52
20141201
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 SM_DIMM_VREFCA
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA SA_DIMM_VREFDQ SM_DIMM_VREFCA [25]
AW25 AY68
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ [25]
BB27 DDR CH - A BA67
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ SB_DIMM_VREFDQ [26]
BA27
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL
DDR_A_D63 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_PG_CTRL [25]
BB25
DDR0_DQ[63]/DDR1_DQ[47]

SKYLAKE-U_BGA1356 2 OF 20 ?
REV = 1
@

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(3/16):DDR3L CH.A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 7 of 99

5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1C

DDR_B_D0 AF65 AN45 SB_CLK_DDR#0

[26] DDR_B_D[0..63] DDR_B_D1 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] SB_CLK_DDR#1 SB_CLK_DDR#0 [26]
AF64 AN46
[26] DDR_B_DQS#[0..7] DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] SB_CLK_DDR0 SB_CLK_DDR#1 [26]
AK65 AP45
[26] DDR_B_DQS[0..7] DDR_B_D3 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] SB_CLK_DDR1 SB_CLK_DDR0 [26]
AK64 AP46
[26] DDR_B_MA[0..15] DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] SB_CLK_DDR1 [26]
AF66
DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDRB_CKE0_DIMMB
DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDRB_CKE1_DIMMB DDRB_CKE0_DIMMB [26]
AK67 AP55
DDR_B_D7 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] DDRB_CKE1_DIMMB [26]
AK66 AN55
DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_B_D10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDRB_CS0_DIMMB#
DDR_B_D11 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] DDRB_CS1_DIMMB# DDRB_CS0_DIMMB# [26]
AH68 AY42
DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDRB_ODT0_DIMMB# DDRB_CS1_DIMMB# [26]
AF71 BA42
DDR_B_D13 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] DDRB_ODT1_DIMMB# DDRB_ODT0_DIMMB# [26]
AF69 AW42
DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1_DIMMB# [26]
AH70
DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
DDR_B_D16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDR_B_MA9
DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDR_B_MA8
C DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7 C
DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDR_B_BS2
DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR_B_MA12 DDR_B_BS2 [26]
AP66 AN50
DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDR_B_MA11
DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_MA15
DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDR_B_MA14
DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43 DDR_B_MA13
DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS#
DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_WE# DDR_B_CAS# [26]
AN61 AY44
DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_RAS# DDR_B_WE# [26]
AP61 AW44
DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BS0 DDR_B_RAS# [26]
AT60 BB44
DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BS0 [26]
AU60 ? AY47
DDR_B_D32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDR_B_BS1
DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10 DDR_B_BS1 [26]
AT40 AW46
DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDR_B_MA3
DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1
DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDR_B_DQS1
DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_B_D44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDR_B_DQS2
DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_B_D46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDR_B_DQS3
DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
DDR_B_D48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4
DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR_B_D50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_B_D52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDR_B_DQS6
DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
B B
DDR_B_D54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDR_B_DQS7
DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR_B_D57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43
DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR3_DRAMRST#
DDR_B_D59 DDR1_DQ[58] DRAM_RESET# SM_RCOMP0 DDR3_DRAMRST# [25,26]
AT21 AR18 RC8 1 2 121_0402_1%
DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1 RC9 1 2 80.6_0402_1%
DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP2 RC10 1 2 100_0402_1%
DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDR_B_D63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 3 OF 20 ?
REV = 1
[SKL PDG]for DDR3L
@ DDR_RCOMP[0] Pull down 121 ohm resistor
DDR_RCOMP[1] Pull down 80.6 ohm resistor
DDR_RCOMP[2] Pull down 100 ohm resistor

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(4/16):DDR3L CH.B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 8 of 99

5 4 3 2 1
 5 4 3 2 1

D D

[SKL PDG]Manufacturing Mode Jumper

1. If strap is sampled low, the security measures def i ned i n t he Fl asDescri
h pt orwill be i n ef f ect ( def ault )
2. If sampled high, the Flash Descriptor Security will be overridden.

RPC2
PCH_HDA_RST# 1 8 HDA_RST#
[54] PCH_HDA_RST# PCH_HDA_BCLK HDA_BCLK
2 7
[54] PCH_HDA_BCLK PCH_HDA_SDOUT HDA_SDOUT
3 6
[54] PCH_HDA_SDOUT PCH_HDA_SYNC HDA_SYNC
4 5
[54] PCH_HDA_SYNC
33_0804_8P4R_5%
SD30000370T

RC21 1 2 0_0402_5%
[61] ME_FLASH

UC1G SKL_ULT

AUDIO
Check RC377 to remove HDA_SYNC
GPP_B14, Internal PD 20K by 7/20 HDA_BCLK
BA22
AY22 HDA_SYNC/I2S0_SFRM
C
No Reboot on TCO HDA_SDOUT
PCH_HDA_SDIN0
BB22 HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
SDIO/SDXC
C
BA21
Timer expiration [54] PCH_HDA_SDIN0
AY21 HDA_SDI0/I2S0_RXD AB11
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD
pull-up to VCC3_3 through a 18.2  K ∮∮ 5 % HDA_RST# AW22
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
AB13
AB12
resistor to disable this capability AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
+3VALW_PCH AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
PCH_BEEP 1 @ 2 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
RC95 8.2K_0402_5% GPP_A16/SD_1P8_SEL
1 2 H5 AB7 1 2
RC300 @ 20K_0402_5% D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0 RC378
Internal PD already   D8 AF13 200_0402_1%
C8 GPP_D17/DMIC_CLK1 GPP_F23
Un-mout RC300 by 7/20 GPP_D18/DMIC_DATA1
Processor Strapping PCH_BEEP AW5
[55] PCH_BEEP
543016_543016_SKL_PDG_UY_1_0_pub GPP_B14/SPKR
+VCC_IO
P780
SKYLAKE-U_BGA1356 7 OF 20 ? ?
REV = 1
PCH_HDA_SDIN0 1 @ 2
RC297 1K_0402_5%
@ [SKL PDG] internal SD Card
1 2
RC301 @ 20K_0402_5%

B B

+VCC_HDA

HDA_SDOUT 1 @ 2
RC299 1K_0402_5%
1 2
RC302 @ 20K_0402_5%

+3VALW_PCH

HDA_SYNC 1 @ 2
RC356 1K_0402_5%
Default 15/0519
Un-mout RC356
by 7/20

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(5/16):HDA/SDIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 9 of 99

5 4 3 2 1
 5 4 3 2 1

20150514

RTC External Circuit JCMOS, JME Setting, Need Under DDR Door

+RTCBATT +RTCVCC +RTCVCC

JCMOS1 @
RC12 PCH_RTCRST#
RC11 1 2 0_0402_5% 1 2 1 2

D 1 1 20K_0402_5% CC1 1 2 1U_0402_10V6K D

C8542
CC2
1U_0402_10V6-K 0.1U_0402_10V6-K JME1 @
2 2 RC14 PCH_SRTCRST#
1 2 1 2
20K_0402_5%
CC5 1 2 1U_0402_10V6K

+RTCBATT, +RTCVCC
Trace width = 20mils

UC1J SKL_ULT

+3VS CLOCK SIGNALS

+3VS
RC29 1 DIS@ 2 10K_0402_5% D42
C42 CLKOUT_PCIE_N0
RC32 1 UMA@ 2 10K_0402_5% DISCRETE_PRESENCE AR10 CLKOUT_PCIE_P0
UMA@ GPP_B5/SRCCLKREQ0#
RC165 1 2 10K_0402_5% CLKREQ_PCIE4_VGA# B42
A42 CLKOUT_PCIE_N1 F43
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
C
DIS@ GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P C
RC166 1 2 10K_0402_5% CLK_PCIE_WLAN# D41 BA17 SUSCLK_32K
[50] CLK_PCIE_WLAN# CLK_PCIE_WLAN CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK_32K [50]
C41
[50] CLK_PCIE_WLAN CLKREQ_PCIE2_WLAN# CLKOUT_PCIE_P2 PCH_XTAL24_IN
20141220 WLAN [50] CLKREQ_PCIE2_WLAN# AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 PCH_XTAL24_OUT +1VALW
CLK_PCIE_LAN# D40 XTAL24_OUT
[47] CLK_PCIE_LAN# CLK_PCIE_LAN CLKOUT_PCIE_N3 DIFFCLK_BIASREF
C40 E42 1 2
[47] CLK_PCIE_LAN CLKREQ_PCIE3_LAN# CLKOUT_PCIE_P3 XCLK_BIASREF
LAN [47] CLKREQ_PCIE3_LAN# AT10
GPP_B8/SRCCLKREQ3# PCH_RTCX1
AM18 RC379
CLK_PCIE_VGA# B40 RTCX1 AM20 PCH_RTCX2 2.7K_0402_1%
[27] CLK_PCIE_VGA# CLK_PCIE_VGA CLKOUT_PCIE_N4 RTCX2
+3VS A40
[27] CLK_PCIE_VGA CLKREQ_PCIE4_VGA# CLKOUT_PCIE_P4 PCH_SRTCRST#
RPC200
CLKREQ_PCIE2_WLAN#
VGA [27] CLKREQ_PCIE4_VGA# AU8
GPP_B9/SRCCLKREQ4# SRTCRST#
AN18
PCH_RTCRST#
1 8 AM16
2 7 CLKREQ_PCIE3_LAN# CLK_PCIE_CR# E40 RTCRST#
[51] CLK_PCIE_CR# CLK_PCIE_CR CLKOUT_PCIE_N5
3 6
CLKREQ_PCIE5_CR#
CR [51] CLK_PCIE_CR CLKREQ_PCIE5_CR#
E38
CLKOUT_PCIE_P5
4 5 AU7
[51] CLKREQ_PCIE5_CR# GPP_B10/SRCCLKREQ5#
10K_0804_8P4R_5% [SKL PDG]External pull-up resistor required if
15/0519 used for CLKREQ# functionality.
SKYLAKE-U_BGA1356 10 OF 20 ? ?
REV = 1
@

[SKL PDG]Used to set BIAS reference

for differential clocks. Connect to a [RC379]
2.71K ∮∮ 0.5% precision resistor to 1.0v.

B B

[SKL PDG]
1.Space > 15mils
2.No trace under crystal [SKL PDG]
3.Place on oppsosit side of MCP for temp inf l uence 1.A 24 MHz crystal with crystal frequency tolerance and stability of +/-30 ppm
4.The exact capacitor values forC1 and C2 must be based on the crystal maker recommendat ions. 2.Two External Load Capacitors (Ce1 and Ce2)
Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF. 3.A 1-Mohm bias resistor (Rf)
PCH_XTAL24_IN
RTC Crystal PCH_RTCX1
PCH_XTAL24_OUT RC30
1 2
RC13 PCH_RTCX2
1 2
1M_0402_5%
10M_0402_5%
YC2
YC1
1 2 1 3
[SKL PDG]Max Crystal ESR = 50k Ohm. 1 3
32.768KHZ_12.5PF_9H03200042 GND1 GND2
1 1 1 1
CC3 CC4 CC6 2 4 CC7
5.6P_0402_50V8-D 5.6P_0402_50V8-D 12P_0402_50V8-J 12P_0402_50V8-J
2 2 2 2
24MHZ_10PF_8Y24000011

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(6/16):CLOCK SIGNALS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 10 of 99

5 4 3 2 1
 5 4 3 2 1

Functional Strap Definitions

L:Disable Intel ME Crypto TLS cipher suite (no confidentiality).

*H:Enable Intel ME Crypto Transport Layer Security (TLS) cipher
suite (with confidentiality).Support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
D D

+3VALW_PCH

GPP_C2 1 2
RC306 1K_0402_5%
1 2
GPP_C2, Internal PD 20K RC307 @ 20K_0402_5%

SKL_ULT
UC1E
close to CPU RC380
0_0402_5% SPI - FLASH
SMBUS, SMLINK
SPI_CLK 1 2 SPI_CLK_R AV2 R7 PCH_SMB_CLK
[23,69] SPI_CLK SPI_SO SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
AW3 R8 DIMM1, DIMM2, Security EEPROM, Click Pad
[23,69] SPI_SO SPI_SI SPI0_MISO GPP_C1/SMBDATA GPP_C2
JTAG ODT [23,69] SPI_SI
AV3
SPI0_MOSI GPP_C2/SMBALERT#
R10
SPI_IO2 AW2
[23] SPI_IO2 SPI_IO3 SPI0_IO2 PCH_SML0_CLK
+3VALW_PCH AU4 R9
[23] SPI_IO3 SPI_CS0#_8MB SPI0_IO3 GPP_C3/SML0CLK PCH_SML0_DAT PCH_SML0_CLK [47]
AU3 W2
[23] SPI_CS0#_8MB SPI_CS1#_4MB AU2 SPI0_CS0# GPP_C4/SML0DATA W1 GPP_C5 PCH_SML0_DAT [47] LAN
[23] SPI_CS1#_4MB SPI_CS2#_TPM SPI0_CS1# GPP_C5/SML0ALERT#
[69] SPI_CS2#_TPM AU1
SPI_SI SPI0_CS2# PCH_SML1CLK
SPI0_MOSI 1 @ 2
GPP_C6/SML1CLK
W3
RC298 8.2K_0402_5% V3 PCH_SML1DATA
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 EC,dGPU,Thermal Sensor
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
V2 GPP_D21/SPI1_IO2
EC_SCI# M1 GPP_D22/SPI1_IO3 AY13
[61] EC_SCI# LPC
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_AD0 [61]
BA13
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 [61]
BB13
C C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 [61] C
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 [61]
+3VALW_PCH G3 BA12
[50] CL_CLK_WLAN CL_CLK GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# [61]
G2 BA11 SUS_STAT# RC47 1 @ 2 0_0402_5% 1
[50] CL_DATA_WLAN CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC18
[50] CL_RST_WLAN# G1
CL_RST#
SPI_SO 1 @ 2 AW9 PCH_PCI_CLK_R RC24 1 EMC@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_EC [61]
RC308 8.2K_0402_5% KBRST# AW13 AY9
[61] KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 AW11CLKRUN#
SERIRQ AY11 GPP_A8/CLKRUN#
[61,69] SERIRQ GPP_A6/SERIRQ +3VS

SKYLAKE-U_BGA1356 5 OF 20 ? ? 1 2
REV = 1 RC52 8.2K_0402_5%
@

GPP_C5, Internal PD 20K

*L: LPC
H: eSPI +3VALW_PCH

GPP_C5 2 @ 1
RC83 1K_0402_5%
1 @ 2
RC350 20K_0402_5%

B B

SB00000EO1J
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
QC1A QC2A SB00000EO1J
+3VS +3VALW_PCH PCH_SMB_CLK 6 1 +3VS PCH_SML1CLK 6 1

D
PM_SMB_CLK [23,25,26,67] EC_SMB_CK3 [28,60,61,66,68]

S
RPC22
8 1 SERIRQ PCH_SML0_CLK RC92 1 2 499_0402_1% +3VS
7 2 EC_SCI# PCH_SML0_DAT RC93 1 2 499_0402_1%
G

G
2

2
6 3 +3VS
5 4 KBRST# RC106 1 2 4.7K_0402_5%
PCH_SMB_CLK RC395 1 2 2.2K_0402_1%
10K_0804_8P4R_5% PCH_SMB_DATA RC396 1 2 2.2K_0402_1%
PCH_SML1CLK RC397 1 2 2.2K_0402_1% RC107 1 2 4.7K_0402_5%
PCH_SML1DATA
5

5
RC398 1 2 2.2K_0402_1%
G

G
PCH_SMB_DATA 3 4 PCH_SML1DATA 3 4
PM_SMB_DAT [23,25,26,67] EC_SMB_DA3 [28,60,61,66,68]
S

S
GPP_B23 RC101 2 1 150K_0402_5%
D

D
QC1B QC2B SB00000EO1J
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6
SB00000EO1J

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(7/16):LPC/SPI/SMBUS/CL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 11 of 99

5 4 3 2 1
 5 4 3 2 1

D D
SKL_ULT
UC1K
SYSTEM POWER MANAGEMENT
+3VS AT11 PM_SLP_S0# 1 PM_SLP_S3# 1 TP125
GPP_B12/SLP_S0# PM_SLP_S3# TC20 PM_SLP_S4#
AP15 1 TP126
GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# [61] PM_SLP_S5#
PLTRST# AN10 BA16 1 TP127
[27] PLTRST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# [61]
1 2 B5 AY16
EC_RSMRST# SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# [61]
RC108 10K_0402_5% AY17
[61] EC_RSMRST# RSMRST# PCH_SLP_SUS#
AN15 1
H_CPUPWRGD SLP_SUS# PCH_SLP_LAN# TC21
1 A68 AW15
T59 VCCST_PWRGD PROCPWRGD SLP_LAN# PCH_SLP_WLAN# PCH_SLP_LAN# [47,61] PM_SLP_A#
B65 BB17 1 TP128
VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# PCH_SLP_WLAN# [61]
AN16
PCH_SYSPWROK GPD6/SLP_A# PM_SLP_A# [61] PBTN_OUT#
B6 1 TP129
[61] PCH_SYSPWROK SYS_PWROK PBTN_OUT#
RC41 1 2 0_0402_5% PWROK BA20 BA15
[61] PCH_PWROK EC_DPWROK_R PCH_PWROK GPD3/PWRBTN# AC_PRESENT PBTN_OUT# [61]
RC286 1 @ 2 0_0402_5% BB20 AY15
EC_RSMRST# [61] EC_DPWROK DSW_PWROK GPD1/ACPRESENT AC_PRESENT [61]
RC373 1 2 0_0402_5% AU13 BATLOW#
RC109 1 2 0_0402_5% SUSWARN# AR13 GPD0/BATLOW#
SUSACK# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +RTCVCC
GPP_A15/SUSACK# AU11 PME# 1
PCIE_WAKE# GPP_A11/PME# PCH_INTRUDER# TC120
BB15 AP16 2 1
1 AM15 WAKE# INTRUDER# RC16 1M_0402_5%
T21 GPD2/LAN_WAKE# EXT_PWR_GATE#
LANPHYPC AW17 AM10 1
[47] LANPHYPC GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# TC121
GPD7 AT15 AM11 VRALERT# 1
GPD7/RSVD GPP_B2/VRALERT# TC24
Connect to Power
SKYLAKE-U_BGA1356 11 OF 20 ? ?
REV = 1
@
PWROK

2
RC403
C C
10K_0402_5%

20150514 @ +VCC_STG

1
RC123
@ 10K_0402_5%

RC436

2
+3VALW 1 2VCCST_PWRGD_GD
[61] VCCST_PG_EC
RPC18
1 8 AC_PRESENT 0_0402_5%
2 7 BATLOW#
3 6 PCIE_WAKE#
4 5 PCH_SLP_LAN# +3VALW
UC3
10K_0804_8P4R_5% 1 5
NC VCC RC348 1 2 33_0402_5%
PBTN_OUT# PLTRST_NEAR# [23,47,51]
1 @ 2 PLTRST# 2
RC399 10K_0402_5% IN_A
+VCC_STG 3 4 RC48 1 2 33_0402_5%
GND OUT_Y PLTRST_FAR# [50,61,69]

1
1 2 PCH_SLP_WLAN#
1 1
RC393 10K_0402_5% RC26 TC7SG17FE_SON5

1
100K_0402_5% CC9 CC102
RC401 100P_0402_25V8J 100P_0402_25V8J

2
2 2
1 @ 2 GPD7 1K_0402_5% 15/0519
RC351 10K_0402_5%
RC410

2
VCCST_PWRGD_GD 1 2 VCCST_PWRGD
1 @ 2 EC_DPWROK
RC392 10K_0402_5%
60.4_0402_1%
B B

EC_RSMRST# PCH_SYSPWROK PCH_PWROK EC_DPWROK

2

1
RC27
10K_0402_5% RC381 RC382 RC383
5P_0402_50V8-C 5P_0402_50V8-C 5P_0402_50V8-C
2

2
EMC_NS@ EMC_NS@ EMC_NS@
1

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(8/16):SYSTEM PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 12 of 99

5 4 3 2 1
 D

0.1
Re v

99
of
13
Sheet
Wednesday, September 23, 2015
SKL(9/16):Decoupling
1

1
BE560
Size Document Number
Custom
Title

Date:

1U_0201_6.3V6-M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1

2015/05/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

CC159
1U_0201_6.3V6-M
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1

CC158
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

1U_0201_6.3V6-M
LC Future Center Secret Data
1

CC157
1U_0201_6.3V6-M
1

Deciphered Date

CC156
1U_0201_6.3V6-M
2

2
1

CC155
1U_0201_6.3V6-M
1

CC154
1U_0201_6.3V6-M
1

https://dr-bios.com
CC153
1U_0201_6.3V6-M
1

2014/05/07
CC152
1U_0201_6.3V6-M
1

2
[SKL PDG]10uF x10,1uF x12,47uF x6,22uFx12

CC151
1U_0201_6.3V6-M
1

CC150
10U_0603_6.3V6-M 1U_0201_6.3V6-M
1

Security Classification
1 2
CC133 CC149
10U_0603_6.3V6-M 1U_0201_6.3V6-M

Issued Date
1

1 2
CC131 CC148
[SKL PDG]VCCGT

10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M

1

1 2
CC130 CC147 CC161
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

1 2
CC129 CC146 CC160
+VCC_GT
3

3
1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

CC145 CC179 CC199

1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
10U_0603_6.3V6-M
1

CC144 CC178 CC198 CC208 1 2

1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M CC225
10U_0603_6.3V6-M
1

CC143 CC177 CC197 CC207 1 2

1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M CC224
10U_0603_6.3V6-M
[SKL PDG]22uF x9,10uF x7,1uF x15,47uF x8,10uFx8

2
CC142 CC176 CC196 CC206 1 2
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M CC223
10U_0603_6.3V6-M
1

2
1 2
CC141 CC175 CC195 CC205 1 2
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M CC222
10U_0603_6.3V6-M
1

2
1 2
4

4
CC140 CC174 CC194 CC204 1 2
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M CC221
1

2
1 2 10U_0603_6.3V6-M
CC139 CC173 CC193 CC203
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1 2
CC123
1

2
1 2
[SKL PDG]VCC

CC138 CC172 CC192 CC202 10U_0603_6.3V6-M

10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1 2
1

2
1 2 CC218
CC137 CC171 CC191 CC201
10U_0603_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M 1U_0201_6.3V6-M
1

2
+VCC_CORE

1 2
CC136 CC170 CC190 CC200 CC209
5

5
D

A
 5 4 3 2 1

D D

GPP_B18, Internal PD 20K GPP_B22, Internal PD 20K Project ID

15/0714
*L: Disable ¨ No Reboot〃 mode *L: SPI PLANARID0 (GPP_B5) PLANARID2 DGPU_PWROK
(GPP_C8) (GPP_C10) (GPP_A7)
H: Enable ¨ No Reboot〃 mode +3VALW_PCH H: LPC +3VALW_PCH
L 14" UMA 1(X)
@
GPP_B18 2 1 GPP_B22 2 @ 1 H 15" DIS 1(X)
RC98 1K_0402_5% RC99 1K_0402_5% * *
2 @ 1 1 2 +3VS +3VS
RC97 20K_0402_5% RC100 20K_0402_5%
@ 15/0603

1
@

10K_0402_5%

RC67

10K_0402_5%

RC70

10K_0402_5%

RC434
2

2
PLANARID0
PLANARID1

DGPU_PWROK

1
@ @ @

10K_0402_5%

RC71

10K_0402_5%

RC74

10K_0402_5%

RC435
C C

2
? SKL_ULT
UC1F
LPSS ISH
+3VALW_PCH

RC376 RF_OFF# AN8 P2 RC427

RF_OFF# [50] RF_OFF# GPP_B15/GSPI0_CS# GPP_D9
1 2 AP7 P3 CP_RESET#_R 1 2 CP_RESET#
GPP_B16/GSPI0_CLK GPP_D10 CP_RESET# [61,67]
AP8 P4
GPP_B18 GPP_B17/GSPI0_MISO GPP_D11
10K_0402_5% AR7
GPP_B18/GSPI0_MOSI GPP_D12
P1 0_0402_5% 15/0708
PCH_CMOS_ON AM5 M4
[38] PCH_CMOS_ON GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA
AN7 N3
BT_ON AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
[50] BT_ON GPP_B22 GPP_B21/GSPI1_MISO
AN5 N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
15/0708 GPP_D8/ISH_I2C1_SCL
N2
PLANARID0 AB1
CP_BYPASS RC428 1 2 0_0402_5% CP_BYPASS_R AB2 GPP_C8/UART0_RXD AD11
[61,67] CP_BYPASS TP_REST GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
+3VS RC429 1 2 0_0402_5% TP_REST_R W4 AD12
[61,67] TP_REST GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
B [15,36,83] DGPU_PWROK RC411 1 2 0_0402_5% AB3 B
GPP_C11/UART0_CTS#
1 UART2_RX AD1 U1
TP941 UART2_TX GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
TP942 1 AD2 U2
F4_LED# AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
[64] F4_LED# PCH_TSOFF# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
15/0519 [64] PCH_TSOFF#
AD4
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
U4

AC1 FN_LED#
GPP_C12/UART1_RXD/ISH_UART1_RXD F1_LED# FN_LED# [64]
PLANARID1 U7 AC2
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD F1_LED# [64]
RPC9 U6 AC3
8 1 PCH_TSOFF# GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
7 2 VGA_ON VGA_ON U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
DGPU_HOLD_RST# [27,36,83] VGA_ON DGPU_HOLD_RST# GPP_C18/I2C1_SDA
6 3 U9 AY8
BT_ON [27] DGPU_HOLD_RST# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
5 4 BA8
AH9 GPP_A19/ISH_GP1 BB7 FW_GPIO
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 FW_GPIO [38]
10K_0804_8P4R_5% AH10 BA7
GPP_F5/I2C2_SCL 6 OF 20 GPP_A21/ISH_GP3
SKYLAKE-U_BGA1356 AY7
MIC_HW_EN AH11 REV = 1 ? GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 1
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 TC118
2

AF11
RC355 AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
0_0402_5%
1

15/0519

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(10/16):GPIO/CPU/MISC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 14 of 99

5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1H

D D
SSIC / USB3
PCIE/USB3/SATA
H8 USB3P1_RXN
USB3_1_RXN USB3P1_RXP USB3P1_RXN [45]
G8
USB3P5_RXN USB3_1_RXP USB3P1_TXN USB3P1_RXP [45]
[38] USB3P5_RXN H13 C13
USB3P5_RXP PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3P1_TXP USB3P1_TXN [45]
[38] USB3P5_RXP
G13
PCIE1_RXP/USB3_5_RXP
3D camera USB3.0 on board USB3_1_TXP
D13
USB3P1_TXP [45] On Board (Right-Front)
USB3P5_TXN B17
3D CCD [38] USB3P5_TXN USB3P5_TXP A17 PCIE1_TXN/USB3_5_TXN J6 USB3P2_RXN
[38] USB3P5_TXP PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3P2_RXP USB3P2_RXN [45]
H6
USB3_2_RXP/SSIC_1_RXP USB3P2_TXN USB3P2_RXP [45]
G11 B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB3P2_TXP USB3P2_TXN [45] On Board (AOU Port)
PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3P2_TXP [45]
D16
C16 PCIE2_TXN/USB3_6_TXN J10 USB3P3_RXN
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB3P3_RXP USB3P3_RXN [60]
H10
PCIE3_CRX_DTX_N USB3_3_RXP/SSIC_2_RXP USB3P3_TXN USB3P3_RXP [60]
[50] PCIE3_CRX_DTX_N H16
PCIE3_RXN
ChargerPort USB3_3_TXN/SSIC_2_TXN
B15
USB3P3_TXN [60] S/B (Sub board)
PCIE3_CRX_DTX_P G16 A15 USB3P3_TXP
WLAN [50] PCIE3_CRX_DTX_P
1 2 PCIE3_CTX_DRX_N D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3P3_TXP [60] 20141024
[50] PCIE3_CTX_C_DRX_N PCIE3_CTX_DRX_P PCIE3_TXN USB3P4_RXN
CC18 1 2 0.1U_0402_10V7-K C17 E10
[50] PCIE3_CTX_C_DRX_P PCIE3_TXP USB3_4_RXN USB3P4_RXP USB3P4_RXN [60]
CC19 0.1U_0402_10V7-K Docking USB3_4_RXP
F10
USB3P4_RXP [60]
PCIE4_CRX_DTX_N G15 C15 USB3P4_TXN
[47] PCIE4_CRX_DTX_N PCIE4_CRX_DTX_P F15 PCIE4_RXN USB3_4_TXN D15 USB3P4_TXP USB3P4_TXN [60] Docking
[47] PCIE4_CRX_DTX_P PCIE4_CTX_DRX_N PCIE4_RXP USB3_4_TXP USB3P4_TXP [60]
LAN 1 2 B19 20141024
[47] PCIE4_CTX_C_DRX_N PCIE4_CTX_DRX_P PCIE4_TXN
CC92 1 2 0.1U_0402_10V7-K A19 AB9 USB20_N1
[47] PCIE4_CTX_C_DRX_P PCIE4_TXP USB2N_1 USB20_N1 [45]
CC93 0.1U_0402_10V7-K AB10 USB20_P1
F16 USB2P_1 USB20_P1 [45] On Board (Right-Front)
E16 PCIE5_RXN AD6 USB20_N2
PCIE5_RXP USB2N_2 USB20_N2 [45]
C19 AD7 USB20_P2
D19 PCIE5_TXN USB2P_2 USB20_P2 [45] On Board (Right-Back)(AOU Port)
PCIE5_TXP AH3 USB20_N3
USB2N_3 USB20_N3 [60]
G18 Sub/B Charger Port AJ3 USB20_P3
[51] PCIE6_CRX_DTX_N
F18 PCIE6_RXN USB2P_3 USB20_P3 [60] S/B
[51] PCIE6_CRX_DTX_P PCIE6_CTX_DRX_N PCIE6_RXP
1 2 D20 CR AD9 USB20_N4 USB Port Number
Card Reader [51] PCIE6_CTX_C_DRX_N
CC20 1 2 0.1U_0402_10V7-K PCIE6_CTX_DRX_P C20 PCIE6_TXN ONE DOCK USB2N_4 AD10 USB20_P4
USB20_N4 [60]
DOCKING
[51] PCIE6_CTX_C_DRX_P PCIE6_TXP USB2P_4 USB20_P4 [60]
CC21 0.1U_0402_10V7-K
SATA_PRX_DTX_N0 USB20_N5
USB_OC0# Port 1, Port2
[43] SATA_PRX_DTX_N0 F20 AJ1
C SATA_PRX_DTX_P0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 [64] C
[43] SATA_PRX_DTX_P0
E20
PCIE7_RXP/SATA0_RXP
Touch Panel USB2P_5
AJ2
USB20_P5 [64] Touch Panel USB_OC1# Port 3, Port4
SATA_PTX_DRX_N0 HDD
HDD [43]
[43]
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_P0
B21
A21 PCIE7_TXN/SATA0_TXN
USB2
AF6 USB20_N6 USB_OC2# Port 5, Port6
PCIE7_TXP/SATA0_TXP USB2N_6 USB20_N6 [50]
BT AF7 USB20_P6
SATA_PRX_DTX_N1 USB2P_6 USB20_P6 [50] BT
[44] SATA_PRX_DTX_N1 SATA_PRX_DTX_P1
G21
PCIE8_RXN/SATA1A_RXN
USB_OC3# Port 7, Port8
F21 AH1 USB20_N7
[44] SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 [38]
ODD(NGFF) Camera AH2 USB20_P7
ODD, only for 15" [44] SATA_PTX_DRX_N1 SATA_PTX_DRX_P1
D21
C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 [38] CAMERA
[44] SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8 USB20_N9
PCIE_CRX_GTX_N0 USB2N_8 USB20_N9 [65]
E22 WWAN AF9 USB20_P9
[27] PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 E23 PCIE9_RXN USB2P_8 USB20_P9 [65] FPR
[27] PCIE_CRX_GTX_P0 PCIE1_PTX_DRX_N0 PCIE9_RXP
GPU [27] PCIE_CTX_C_GRX_N0
1
CC86 DIS@ 1
2
2 0.1U_0402_10V7-K PCIE1_PTX_DRX_P0
B23
A23 PCIE9_TXN FPR USB2N_9
AG1
AG2
[27] PCIE_CTX_C_GRX_P0 PCIE9_TXP USB2P_9
CC87 DIS@ 0.1U_0402_10V7-K
PCIE_CRX_GTX_N1 F25 AH7
[27] PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 PCIE10_RXN USB2N_10
[27] PCIE_CRX_GTX_P1
E25
PCIE10_RXP
Smart Card USB2P_10
AH8
1 2 PCIE2_PTX_DRX_N1 D23
[27] PCIE_CTX_C_GRX_N1 PCIE2_PTX_DRX_P1 PCIE10_TXN
CC88 DIS@ 1 2 0.1U_0402_10V7-K C23 AB6 USBCOMP 1 2
[27] PCIE_CTX_C_GRX_P1 PCIE10_TXP USB2_COMP USB2_ID
CC89 DIS@ 0.1U_0402_10V7-K AG3 RC384 113_0402_1%
1 2 PCIE_RCOMP F5 GPU USB2_ID AG4 USB2_VBUSSENSE
RC385 100_0402_1% E5 PCIE_RCOMPN USB2_VBUSSENSE
20141124 PCIE_RCOMPP A9 USB_OC0#
XDP_PRDY_N GPP_E9/USB2_OC0# USB_OC1# USB_OC0# [45]
15/0603 TC25 1 D56
PROC_PRDY# GPP_E10/USB2_OC1#
C9
USB_OC1# [45]
@ TC26 1 XDP_PREQ_N D61 D9 USB_OC2#
DGPU_PWROK DGPU_PWROK_R PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# [60]
[14,36,83] DGPU_PWROK 1 2 BB11 B9
RC402 0_0402_5% GPP_A7/PIRQA# GPP_E12/USB2_OC3# +3VALW_PCH
PCIE_CRX_GTX_N2 E28 J1 HDD_DEVSLP0 RPC15
[27] PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 SSD_DEVSLP1 HDD_DEVSLP0 [43] USB_OC0#
[27] PCIE_CRX_GTX_P2 E27 J2 1 8 1
PCIE3_PTX_DRX_N2 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 ODD_EN TC27 USB_OC1#
1 2 D24 J3 7 2
[27] PCIE_CTX_C_GRX_N2 PCIE3_PTX_DRX_P2 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 ODD_EN [44] USB_OC2#
CC90 DIS@ 1 2 0.1U_0402_10V7-K C24 6 3
[27] PCIE_CTX_C_GRX_P2 PCIE_CRX_GTX_N3 PCIE11_TXP/SATA1B_TXP ODD_DA# USB_OC3#
CC23 DIS@ 0.1U_0402_10V7-K E30 H2 5 4
[27] PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 ODD_DETEC# ODD_DA# [44]
[27] PCIE_CRX_GTX_P3 F30 H3
PCIE4_PTX_DRX_N3 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 ONEDOCK_DET# ODD_DETEC# [44]
1 2 A25 G4 10K_0804_8P4R_5%
[27] PCIE_CTX_C_GRX_N3 PCIE4_PTX_DRX_P3 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 ONEDOCK_DET# [60]
CC24 DIS@ 1 2 0.1U_0402_10V7-K B25
[27] PCIE_CTX_C_GRX_P3 PCIE12_TXP/SATA2_TXP
B CC91 DIS@ 0.1U_0402_10V7-K H1 B
GPP_E8/SATALED#
ONEDOCK_DET# 1 2
SKYLAKE-U_BGA1356 8 OF 20 ? ? RC372 10K_0402_5%
REV = 1
@

USB2_ID
USB2_VBUSSENSE

2
RC406 RC407
1K_0402_5% 1K_0402_5%

+3VS
1

1
ODD_DETEC#
HDD_DEVSLP0 RC88 2 1 10K_0402_5%
ODD_DETEC# RC86 2 1 10K_0402_5%

1
RC386
15/05/18 5P_0402_50V8-C ODD_DA# RC409 2 1 10K_0402_5%

2
EMC_NS@

15/0519

A 15/0714 A

DGPU_PWROK_R RC433 2 1 10K_0402_5%

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(11/16):PCIE/USB/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 15 of 99

5 4 3 2 1
 5 4 3 2 1

SKL_ULT
UC1L
+VCC_CORE CPU POWER 1 OF 4
+VCC_CORE

A30 G32
A34 VCC_A30 VCC_G32 G33
A39 VCC_A34 VCC_G33 G35
A44 VCC_A39 VCC_G35 G37
AK33 VCC_A44 VCC_G37 G38
D D
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
AK38 VCC_AK37 VCC_G42 J30
AK40 VCC_AK38 VCC_J30 J33
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40 +VCC_CORE +VCC_ST [SKL PDG]VIDSOUT
AL40 VCC_AL37 VCC_J40 K33
VCC_AL40 VCC_K33
AM32
VCC_AM32 VCC_K35
K35 Rpu2

1
AM33 K37
AM35 VCC_AM33 VCC_K37 K38 RC120 RC388
AM37 VCC_AM35 VCC_K38 K40 100_0402_1% 100_0402_1%
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43

2
VR_SVID_DAT
VR_SVID_DAT [79]
K32 E32 RC121 1 2 0_0402_5%
RSVD_K32 VCC_SENSE VCC_SENSE [79]
E33 RC142 1 2 0_0402_5%
VSS_SENSE VSS_SENSE [79]
AK32
RSVD_AK32 B63 VR_SVID_ALRT#_R

1
+VCC_ST [SKL PDG]VIDSCK
AB62 VIDALERT# A63 VR_SVID_CLK
VCCOPC_AB62 VIDSCK D64 VR_SVID_DAT
P62
VCCOPC_P62 VIDSOUT
RC143 Rpu1

1
V62 100_0402_1%
VCCOPC_V62 G20 RC387
VCCSTG_G20 +VCC_STG

2
H63 @ 100_0402_1%
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61

2
VR_SVID_CLK
VR_SVID_CLK [79]
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE
AE62 +VCC_ST [SKL PDG]VIDALERT#
AG62 VCCEOPIO_AE62
VCCEOPIO_AG62
Rpu1

1
AL63
AJ62 VCCEOPIO_SENSE RC20
C VSSEOPIO_SENSE 56_0402_1% C

Rs1
SKYLAKE-U_BGA1356 12 OF 20 ? ?

2
REV = 1 VR_SVID_ALRT#_R 1 2 VR_SVID_ALRT#
VR_SVID_ALRT# [79]
@ RC19 220_0402_1%

+VCC_GT
SKL_ULT
+VCC_GT UC1M
+1.35V
CPU POWER 2 OF 4
Primary side cap
N70 +VCC_IO
A48 VCCGT_N70 N71 [SKL PDG]VCCIO
A53 VCCGT_A48 VCCGT_N71 R63 [SKL PDG]VDDQ [SKL PDG]10uF x2, 1uF x8

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
A58 VCCGT_A53 VCCGT_R63 R64 [SKL PDG]10uF x6, 1uF x4
VCCGT_A58 VCCGT_R64

1
A62 R65

CC226

CC227

CC228

CC229

CC230

10U_0603_6.3V6-M

10U_0603_6.3V6-M
A66 VCCGT_A62 VCCGT_R65 R66

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
VCCGT_A66 VCCGT_R66 1 1 1 1

1
AA63 R67

CC104

CC105

CC106

CC107

CC108

CC109
VCCGT_AA63 VCCGT_R67

2
AA64 R68
AA66 VCCGT_AA64 VCCGT_R68 R69 UC1N SKL_ULT
VCCGT_AA66 VCCGT_R69

2
+VCC_STG +VCC_ST +VCC_ST +VCC_SFR AA67 R70 2 2 2 2
VCCGT_AA67 VCCGT_R70 CPU POWER 3 OF 4
RC197 AA69 R71
1 2 AA70 VCCGT_AA69 VCCGT_R71 T62 AU23 AK28
AA71 VCCGT_AA70 VCCGT_T62 U65 AU28 VDDQ_AU23 VCCIO_AK28 AK30
0_0603_5% AC64 VCCGT_AA71 VCCGT_U65 U68 AU35 VDDQ_AU28 VCCIO_AK30 AL30 +VCC_SA
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

10U_0603_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1 1 1 VCCGT_AC64 VCCGT_U68 1 1 1 1 VDDQ_AU35 VCCIO_AL30

1
AC65 U71 AU42 AL42 [SKL PDG]VCCSA
CC68

CC69

CC70

CC232

CC233

CC231

CC234

CC235
AC66 VCCGT_AC65 VCCGT_U71 W63 BB23 VDDQ_AU42 VCCIO_AL42 AM28 [SKL PDG]10uF x13, 1uF x7
AC67 VCCGT_AC66 VCCGT_W63 W64 BB32 VDDQ_BB23 VCCIO_AM28 AM30

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
VCCGT_AC67 VCCGT_W64 VDDQ_BB32 VCCIO_AM30

2
2 2 2 AC68 W65 2 2 2 2 BB41 AM42
VCCGT_AC68 VCCGT_W65 VDDQ_BB41 VCCIO_AM42

1
AC69 W66 BB47

CC236

CC237

CC239

CC241

CC244

CC245
AC70 VCCGT_AC69 VCCGT_W66 W67 BB51 VDDQ_BB47 AK23
VCCGT_AC70 VCCGT_W67 VDDQ_BB51 VCCSA_AK23
Primary side cap Primary side cap AC71
VCCGT_AC71 VCCGT_W68
W68
VCCSA_AK25
AK25

2
J43 W69 G23
[SKL PDG]VCCSTG [SKL PDG]VCCST [SKL PDG]VCCPLL J45 VCCGT_J43 VCCGT_W69 W70 AM40 VCCSA_G23 G25
VCCGT_J45 VCCGT_W70 +1.35V VDDQC VCCSA_G25
[SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 J46 W71 G27
J48 VCCGT_J46 VCCGT_W71 Y62 A18 VCCSA_G27 G28
B +VCC_ST B
J50 VCCGT_J48 VCCGT_Y62 VCCST VCCSA_G28 J22

10U_0603_6.3V6-M
+1.35V +1.35V +VCC_SFROC J52 VCCGT_J50 A22 VCCSA_J22 J23

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
VCCGT_J52 +VCC_STG VCCSTG_A22 VCCSA_J23 1 1 1 1 1 1 1

1
J53 AK42 J27

CC247

CC249

CC250

CC251

CC252

CC253

CC254

CC255
RC293
1 2 J55 VCCGT_J53 VCCGTX_AK42 AK43 AL23 VCCSA_J27 K23
VCCGT_J55 VCCGTX_AK43 +VCC_SFROC VCCPLL_OC VCCSA_K23
J56 AK45 K25
VCCGT_J56 VCCGTX_AK45 VCCSA_K25

2
J58 AK46 K20 K27 2 2 2 2 2 2 2
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K

1 1 0_0603_5% 1 +VCC_SFR
J60 VCCGT_J58 VCCGTX_AK46 AK48 K21 VCCPLL_K20 VCCSA_K27 K28
CC94

CC256

CC257

K48 VCCGT_J60 VCCGTX_AK48 AK50 VCCPLL_K21 VCCSA_K28 K30

K50 VCCGT_K48 VCCGTX_AK50 AK52 VCCSA_K30
2 2 2 K52 VCCGT_K50 VCCGTX_AK52 AK53 AM23 VCCIO_SENSE RC192 1 2 100_0402_1%
VCCGT_K52 VCCGTX_AK53 VCCIO_SENSE VSSIO_SENSE +VCC_IO
K53 AK55 AM22 RC189 1 2 100_0402_1%
K55 VCCGT_K53 VCCGTX_AK55 AK56 VSSIO_SENSE
VCCGT_K55 VCCGTX_AK56
Primary side cap K56
VCCGT_K56 VCCGTX_AK58
AK58
VSSSA_SENSE
H21 RC185 1 2 0_0402_5%
K58 AK60 H20 RC126 1 2 0_0402_5% +VCC_SA
[SKL PDG]VDDQC [SKL PDG]VCCPLL K60 VCCGT_K58 VCCGTX_AK60 AK70 VCCSA_SENSE
[SKL PDG]1uF x1 [SKL PDG]1uF x1 L62 VCCGT_K60 VCCGTX_AK70 AL43
VCCGT_L62 VCCGTX_AL43

1
L63 AL46 SKYLAKE-U_BGA1356 14 OF 20 ? ?
L64 VCCGT_L63 VCCGTX_AL46 AL50 REV = 1 RC375
L65 VCCGT_L64 VCCGTX_AL50 AL53 100_0402_1%
VCCGT_L65 VCCGTX_AL53 @
L66 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
VCCGT_L67 VCCGTX_AL60

2
L68 AM48
L69 VCCGT_L68 VCCGTX_AM48 AM50
VCCGT_L69 VCCGTX_AM50 VSSSA_SENSE [79]
+VCC_GT L70 AM52
VCCGT_L70 VCCGTX_AM52 VCCSA_SENSE [79]
L71 AM53
M62 VCCGT_L71 VCCGTX_AM53 AM56
VCCGT_M62 VCCGTX_AM56
1

N63 AM58
VCCGT_N63 VCCGTX_AM58

1
RC125 N64 AU58
100_0402_1% N66 VCCGT_N64 VCCGTX_AU58 AU63
N67 VCCGT_N66 VCCGTX_AU63 BB57 RC374
N69 VCCGT_N67 VCCGTX_BB57 BB66 100_0402_1%
VCCGT_N69 VCCGTX_BB66
2

2
RC124 1 2 0_0402_5% J70 AK62
[79] VCCGT_SENSE VCCGT_SENSE VCCGTX_SENSE
RC183 1 2 0_0402_5% J69 AL61
A [79] VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE A
1

SKYLAKE-U_BGA1356 13 OF 20 ??
RC184 REV = 1
100_0402_1% @
2

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(12/16):POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 16 of 99

5 4 3 2 1
 5 4 3 2 1

+1VALW _PCH

D D
15/0520 85mA
VccMPHYGT(Mod PHY Externally Gated Primary 1.0 V: Externally gated +3VALW _PCH
Reserve for Sense Resistor primary supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic.)
1 SKL_ULT
UC1O
+VCC_MPHYGT +VCC_MPHYGT CC272
+1.8VALW +1.8VALW _PCH CPU POWER 4 OF 4
47U_0805_6.3V6-M
RC173 0_0603_5% 2 AB19 161mA
+PCH_CORE VCCPRIM_1P0_AB19 1100mA +1.8VALW _PCH
1 2 CC52 please close to N18 AB20
VCCPRIM_1P0_AB20 VCCPGPPA
AK15
CC50 & CC258 please close to N15 P18
VCCPRIM_1P0_P18 VCCPGPPB
AG15
+3VALW +3VALW _PCH

1U_0402_10V6K
1 Y16
RC341 0_0805_5% AF18 VCCPGPPC Y15
1 2 VCCPRIM_CORE_AF18 VCCPGPPD +3VALW _PRIM

CC52

1U_0402_10V6K
1 AF19 T16
VCCPRIM_CORE_AF19 VCCPGPPE
2
[SKL PDG]VccMPHYGT
1 15/0520 1 V20
VCCPRIM_CORE_V20
600mA
VCCPGPPF
AF16
[SKL PDG]1uF x1 135mA

CC50
V21 AD15
+1VALW RC176 +1VALW _PCH [SKL PDG]Close N15, CC258 CC271 VCCPRIM_CORE_V21 VCCPGPPG +1VALW _PCH
0_0805_5% [SKL PDG]VccAPLLEBB Placement type:Edge<3mm(118mil) 2 47U_0805_6.3V6-M 47U_0805_6.3V6-M +DCPDSW AL1 V19
1 2 [SKL PDG]1uF x1 [SKL PDG]47uF x1 2 2 DCPDSW_1P0 22mA VCCPRIM_3P3_V19
[SKL PDG]Close N18, [SKL PDG]Close N15, K17 T1 +1.8VALW _PCH
Placement type:Edge<3mm(118mil) Placement type:Edge<10mm(394mil) +VCC_MPHYGT L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1
+1VALW +VCC_MPHYGT VCCMPHYAON_1P0_L1 AA1 +3VALW _RTCPRIM
JC5 SRAM Primary Well 1.0 V. Dedicated SRAM rail and can Mod PHY Always On Primary 1.0 V: Always on primary N15 VCCATS_1P8
1 2 have on board power down gate control. supply for PCIe/DMI/USB3/SATA/MIPI MPHY logic N16 VCCMPHYGT_1P0_N15 AK17 +RTCVCC
1 2 N17 VCCMPHYGT_1P0_N16 1500mA VCCRTCPRIM_3P3
+VCC_MPHYGT +1VALW _PCH P15 VCCMPHYGT_1P0_N17 AK19
JUMP_43X118 P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14
@ CC47 please close to AF20 +VCC_AMPHYPLL
CC49 please close to K17 K15
VCCAMPHYPLL_1P0_K15 DCPRTC
BB10 +DCPRTC
88mA

1U_0402_10V6K
1 L15
@ VCCAMPHYPLL_1P0_L15 A14
+1VALW _PLL VCCCLK1
20150308 15/0526

CC47

1U_0402_10V6K
1 V15
VCCAPLL_1P0 26mA K19 +1VALW _CLK2 1 2 0_0805_5%
1 VCCCLK2
2

CC49
CC273 AB17 LC3
+VCC_DSW 3P3 Y18 VCCPRIM_1P0_AB17 L21
2 0.1U_0402_10V6-K VCCPRIM_1P0_Y18 VCCCLK3
[SKL PDG]VccSRAM [SKL PDG]VccMPHYAON RF@ 2 AD17 N20 +1VALW _CLK4 1 2 0_0805_5%
[SKL PDG]1uF x1 [SKL PDG]1uF x1 AD18 VCCDSW_3P3_AD17 118mA VCCCLK4 LC4
[SKL PDG]Close AF20, [SKL PDG]Close K17, AJ17 VCCDSW_3P3_AD18 L19 +1VALW _CLK5 1 2 0_0805_5%
Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil) +VCC_HDA VCCDSW_3P3_AJ17 VCCCLK5
15/0520 LC5
AJ19 A10
Primary Well 1.0 V: For I/O blocks, ungated ISH SRAM VCCHDA 68mA VCCCLK6
C +VCC_MPHYGT power, USB AFE Digital Logic, JTAG, Thermal Sensor and AJ16 AN11 1 C
MIPI DPHY. 1 +3V_SPI VCCSPI GPP_B0/CORE_VID0 T56
+3VALW _PCH CC274 AN13 1 15/0520
1 2 0_0805_5% +VCC_AMPHYPLL AF20 GPP_B1/CORE_VID1 T57
LC1 +1VALW _PCH
0.1U_0402_10V6-K AF21 VCCSRAM_1P0_AF20
RF@ 2 T19 VCCSRAM_1P0_AF21 565mA
+1VALW _PCH +3VALW _PRIM VCCSRAM_1P0_T19
please close to AG15 , Y16 & T16 CC95 please close to AB19 T20
VCCSRAM_1P0_T20
2 0_0805_5% +1VALW _PLL
1U_0402_10V6K

1U_0402_10V6K

1U_0402_10V6K
LC2 1 1 1 1 AJ21
VCCPRIM_3P3_AJ21 75mA

1U_0402_10V6K
1
CC262

CC263

CC264
AK20
VCCPRIM_1P0_AK20 33mA

CC95
2 2 2 N18
2 VCCAPLLEBB 33mA
[SKL PDG]VCCPRIM
[SKL PDG]1uF x1 SKYLAKE-U_BGA1356 15 OF 20 ? ?
[SKL PDG]Close AB19, REV = 1
Placement type:Edge<10mm(394mil)
@
+VCC_AMPHYPLL
1U_0402_10V6K

1
@
CC46

Primary Well 3.3 V HD Audio Power 3.3 V, 1.8 V, 1.5 V. For Intel High Thermal Sensor Primary Well 1.8 V Deep Sx Well 1.0 V: This rail is generated by on die DSW RTC de-coupling capacitor only. This rail should NOT
Definition Audio. +1.8VALW _PCH low dropout (LDO) linear voltage regulator to supply DSW be driven.
GPIOs, DSW core logic and DSW USB2 logic. Board needs to
connect 1 uF capacitor to this rail and power should NOT
B +3VALW _PCH +3VALW _PRIM +3VALW _PCH +VCC_HDA be driven from the board. When primary well power is up, +DCPRTC B
this rail is bypassed from VCCPRIM_1p0.

1U_0402_10V6K
1
RC326 1 2 0_0402_5% RC330 1 2 0_0402_5% 1
1U_0402_10V6K

CC61
1 +DCPDSW
1U_0402_10V6K

1U_0402_10V6K
1 1 CC259
[SKL PDG]VCCPRIM [SKL PDG]VccHDA [SKL PDG]VccATS 2 [SKL PDG]DcpDSW [SKL PDG]DcpRTC
CC97

0.1U_0402_10V6-K
[SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]1uF x1 [SKL PDG]0.1uF x1 2
CC99

CC60
[SKL PDG]Close V19, 2 [SKL PDG]Close AJ19, [SKL PDG]Close AA1, [SKL PDG]Close AL1, [SKL PDG]Close BB10,
Placement type:Edge<3mm(118mil) Placement type:Edge<10mm(394mil) 2 Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil) 2 Placement type:Edge<3mm(118mil)

Deep Sx Well for GPD GPIOs and USB2 RTC Logic Primary Well 3.3 V. This power supplies the RTC RTC Logic Primary Well 3.3 V. This power supplies
Core Logic Primary Well: This rail scales from 0.85 V internal VRM. It will be off during Deep Sx mode. the RTC internal VRM. It will be off during Deep
to 1.0 V. +3VALW _PCH Sx mode.
+3VALW _RTCPRIM
+PCH_CORE
+1VALW +RTCVCC
+3VL RC127 1 @ 2 0_0402_5%
+VCC_DSW 3P3 RC333 1 2 0_0402_5%

1 2 0_0805_5%

1U_0402_10V6K

0.1U_0402_10V6-K

0.1U_0402_10V6-K

1U_0402_10V6K
RC304 1 1 1 1
1 +3VALW _PCH RC132 1 2 0_0402_5%
[SKL PDG]VccRTC
1U_0402_10V6K

CC58

CC260

CC261

CC59
[SKL PDG]VccPRIM_Core [SKL PDG]VccRTCPRIM [SKL PDG]1uF x1
CC96

[SKL PDG]1uF x1 [SKL PDG]1uF x1,0.1uF x2 2 2 2 [SKL PDG]Close AK19, 2

[SKL PDG]Close AF18, 2 [SKL PDG]VccDSW [SKL PDG]Close AK17, Placement type:Edge<3mm(118mil)
Placement type:Edge<10mm(394mil) Placement type:Edge<3mm(118mil)

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(13/16):POWER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 17 of 99

5 4 3 2 1
 5 4 3 2 1

D D

UC1P UC1Q UC1R

SKL_ULT SKL_ULT
SKL_ULT
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT68 VSS_AT63 VSS_BA49 BA53 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AT71 VSS_AT68 VSS_BA53 BA57 G22 VSS_G10 VSS_L2 L20
AA2 VSS_A70 VSS_AM13 AM21 AU10 VSS_AT71 VSS_BA57 BA6 G43 VSS_G22 VSS_L20 L4
AA4 VSS_AA2 VSS_AM21 AM25 AU15 VSS_AU10 VSS_BA6 BA62 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU20 VSS_AU15 VSS_BA62 BA66 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU32 VSS_AU20 VSS_BA66 BA71 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AU38 VSS_AU32 VSS_BA71 BB18 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV1 VSS_AU38 VSS_BB18 BB26 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV68 VSS_AV1 VSS_BB26 BB30 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV69 VSS_AV68 VSS_BB30 BB34 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV70 VSS_AV69 VSS_BB34 BB38 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AV71 VSS_AV70 VSS_BB38 BB43 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW10 VSS_AV71 VSS_BB43 BB55 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW12 VSS_AW10 VSS_BB55 BB6 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW14 VSS_AW12 VSS_BB6 BB60 H18 VSS_H15 VSS_P20 P21
C AD21 VSS_AD20 VSS_AN20 AN23 AW16 VSS_AW14 VSS_BB60 BB64 H71 VSS_H18 VSS_P21 R13 C
AD62 VSS_AD21 VSS_AN23 AN28 AW18 VSS_AW16 VSS_BB64 BB67 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW21 VSS_AW18 VSS_BB67 BB70 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW23 VSS_AW21 VSS_BB70 C1 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW26 VSS_AW23 VSS_C1 C25 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW28 VSS_AW26 VSS_C25 C5 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW30 VSS_AW28 VSS_C5 D10 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW32 VSS_AW30 VSS_D10 D11 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW34 VSS_AW32 VSS_D11 D14 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW36 VSS_AW34 VSS_D14 D18 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW38 VSS_AW36 VSS_D18 D22 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW41 VSS_AW38 VSS_D22 D25 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW43 VSS_AW41 VSS_D25 D26 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW45 VSS_AW43 VSS_D26 D30 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW47 VSS_AW45 VSS_D30 D34 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW49 VSS_AW47 VSS_D34 D39 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW51 VSS_AW49 VSS_D39 D44 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW53 VSS_AW51 VSS_D44 D45 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW55 VSS_AW53 VSS_D45 D47 K67 VSS_K66 VSS_V18 W13
AG19 VSS_AG18 VSS_AP35 AP38 AW57 VSS_AW55 VSS_D47 D48 K68 VSS_K67 VSS_W13 W6
AG20 VSS_AG19 VSS_AP38 AP42 AW6 VSS_AW57 VSS_D48 D53 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW60 VSS_AW6 VSS_D53 D58 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW62 VSS_AW60 VSS_D58 D6 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW64 VSS_AW62 VSS_D6 D62 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW66 VSS_AW64 VSS_D62 D66 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AW8 VSS_AW66 VSS_D66 D69 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 AY66 VSS_AW8 VSS_D69 E11
AH67 VSS_AH64 VSS_AR15 AR16 B10 VSS_AY66 VSS_E11 E15
AJ15 VSS_AH67 VSS_AR16 AR20 B14 VSS_B10 VSS_E15 E18
AJ18 VSS_AJ15 VSS_AR20 AR23 B18 VSS_B14 VSS_E18 E21 SKYLAKE-U_BGA1356 18 OF 20
AJ20 VSS_AJ18 VSS_AR23 AR28 B22 VSS_B18 VSS_E21 E46 REV = 1 ? ?
AJ4 VSS_AJ20 VSS_AR28 AR35 B30 VSS_B22 VSS_E46 E50
AK11 VSS_AJ4 VSS_AR35 AR42 B34 VSS_B30 VSS_E50 E53
AK16 VSS_AK11 VSS_AR42 AR43 B39 VSS_B34 VSS_E53 E56
AK18 VSS_AK16 VSS_AR43 AR45 B44 VSS_B39 VSS_E56 E6
B B
AK21 VSS_AK18 VSS_AR45 AR46 B48 VSS_B44 VSS_E6 E65
AK22 VSS_AK21 VSS_AR46 AR48 B53 VSS_B48 VSS_E65 E71
AK27 VSS_AK22 VSS_AR48 AR5 B58 VSS_B53 VSS_E71 F1
AK63 VSS_AK27 VSS_AR5 AR50 B62 VSS_B58 VSS_F1 F13
AK68 VSS_AK63 VSS_AR50 AR52 B66 VSS_B62 VSS_F13 F2
AK69 VSS_AK68 VSS_AR52 AR53 B71 VSS_B66 VSS_F2 F22
AK8 VSS_AK69 VSS_AR53 AR55 BA1 VSS_B71 VSS_F22 F23
AL2 VSS_AK8 VSS_AR55 AR58 BA10 VSS_BA1 VSS_F23 F27
AL28 VSS_AL2 VSS_AR58 AR63 BA14 VSS_BA10 VSS_F27 F28
AL32 VSS_AL28 VSS_AR63 AR8 BA18 VSS_BA14 VSS_F28 F32
AL35 VSS_AL32 VSS_AR8 AT2 BA2 VSS_BA18 VSS_F32 F33
AL38 VSS_AL35 VSS_AT2 AT20 BA23 VSS_BA2 VSS_F33 F35
AL4 VSS_AL38 VSS_AT20 AT23 BA28 VSS_BA23 VSS_F35 F37
AL45 VSS_AL4 VSS_AT23 AT28 BA32 VSS_BA28 VSS_F37 F38
AL48 VSS_AL45 VSS_AT28 AT35 BA36 VSS_BA32 VSS_F38 F4
AL52 VSS_AL48 VSS_AT35 AT4 F68 VSS_BA36 VSS_F4 F40
AL55 VSS_AL52 VSS_AT4 AT42 BA45 VSS_F68 VSS_F40 F42
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA45 VSS_F42 BA41
AL64 VSS_AL58 VSS_AT56 AT58 VSS_BA41
VSS_AL64 VSS_AT58

SKYLAKE-U_BGA1356 16 OF 20 SKYLAKE-U_BGA1356 17 OF 20
REV = 1 ?? REV = 1 ??

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(14/16):GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 18 of 99

5 4 3 2 1
 5 4 3 2 1

D D

SKL_ULT
UC1I

CSI-2

C C
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2

A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 1 2
EMMC_RCOMP
SKYLAKE-U_BGA1356 9 OF 20 ? ? RC389
REV = 1 200_0402_1%
@ @

B B

15/0521

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(15/16):CSI-2/EMMC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 19 of 99

5 4 3 2 1
 5 4 3 2 1

[SKL EDS]
D D

CFG0 +VCC_IO

SKL_ULT
UC1S CFG0 RC105 2 @ 1 1K_0402_5%

RESERVED SIGNALS-1 RC201 2 @ 1 1K_0402_1%

TC30 1 CFG0 E68 BB68 1 TC31

TC43 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC32 L:Stall.
TC44 1 CFG2 D65 CFG[1] RSVD_TP_BB69
CFG[2] *H:(Default) Normal Operation; No stall.
TC33 1 CFG3 D67 AK13 1 TC45
TC34 1 CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 1 TC46
TC35 1 CFG5 C68 CFG[4] RSVD_TP_AK12
TC36 1 CFG6 D68 CFG[5] BB2 1 TC37
CFG[6] RSVD_BB2
TC47 1 CFG7 C67
CFG[7] RSVD_BA3
BA3 1 TC38 CFG4 +VCC_IO
TC48 1 CFG8 F71
TC39 1 CFG9 G69 CFG[8]
TC49 1 CFG10 F70 CFG[9] AU5 1 TC50 CFG4 RC104 2 @ 1 1K_0402_5%
TC40 1 CFG11 G68 CFG[10] TP5 AT5 1 TC51
TC41 1 CFG12 H70 CFG[11] TP6 RC144 2 1 1K_0402_1%
TC42 1 CFG13 G71 CFG[12]
TC52 1 CFG14 H69 CFG[13] D5 1 TC53
TC54 1 CFG15 G70 CFG[14] RSVD_D5 D4 1 TC55 *L: Embedded DisplayPort Enabled
CFG[15] RSVD_D4 B2 1 TC56
RSVD_B2 H: Embedded DisplayPort Disabled
TC57 1 CFG16 E63 C2 1 TC58
CFG[16] RSVD_C2
[SKL CRB] TC59 1 CFG17 F63
CFG[17] B3 1 TC60
TC61 1 CFG18 E66 RSVD_B3 A3 1 TC62
TC63 1 CFG19 F66 CFG[18] RSVD_A3
CFG[19] AW1 1 TABLE
CFG_RCOMP RSVD_AW1 TC64
RC152 2 1 49.9_0402_1% E60
CFG_RCOMP E1 1 TC65
RC390 2 1 1.5K_0402_5% ITP_PMODE E8 RSVD_E1 E2 1 TC66
C +1VALW_PCH ITP_PMODE RSVD_E2 CFG0 : Stall Reset Sequence C
TC67 1 AY2
RSVD_AY2 RSVD_BA4
BA4 1
TC68 after PCU PLL Lock until de-asserted
TC69 1 AY1 BB4 1
RSVD_AY1 RSVD_BB4 TC70 1 : No Stall
TC71 1 D1
RSVD_D1 RSVD_A4
A4 1 TC72 0 : Stall
TC73 1 D3 C4 1 TC74
RSVD_D3 RSVD_C4
TC75 1 K46 BB5 1 TC76
TC77 1 K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC78 CFG4 : eDP Enable
RSVD_A69
TC79 1 AL25
RSVD_AL25 RSVD_B69
B69 1 TC80 1 : Disabled
TC81 1 AL27
RSVD_AL27 AY3 RC296 1 2 0_0402_5% 0 : Enabled
TC82 1 C71 RSVD_AY3
TC83 1 B70 RSVD_C71 D71 1 TC84
RSVD_B70 RSVD_D71 C70 1 TC85
1 F60 RSVD_C70 CFG9 : SVID Bus Communication
RSVD_F60
TC86
RSVD_C54
C54 1 TC87 1 : Enabled
TC88 1 A52 D54 1 TC89
RSVD_A52 RSVD_D54 0 : Disabled
TP92 1 BA70 AY4 1
RSVD_TP_BA70 TP1 TC91
TP93 1 BA68 BB3 1
RSVD_TP_BA68 TP2 TC93
TC94 1 J71 AY71 RC295 1 2 0_0402_5% +VCC_ST
TC95 1 J68 RSVD_J71 VSS_AY71 AR56 1 TC96
RSVD_J68 ZVM#
F65 AW71 1
VSS_F65 RSVD_TP_AW71 TC97
G65 AW70 1
VSS_G65 RSVD_TP_AW70 TC98
TC99 1 F61 AP56 1 TC100 @
E61 RSVD_F61 MSM# C64 2 1
RSVD_E61 PROC_SELECT# RC391 100K_0402_1% ZVM# state VCCOPC

B
15/0522 SKYLAKE-U_BGA1356 19 OF 20 ? ? 0V 0V B
REV = 1 [SKL CRB]
@
1V 1V

UC1T SKL_ULT

SPARE

TC103 1 AW69 F6 1 TC104

TC102 1 AW68 RSVD_AW69 RSVD_F6 E3 1 TC105
TC106 1 AU56 RSVD_AW68 RSVD_E3 C11 1 TC107
TC108 1 AW48 RSVD_AU56 RSVD_C11 B11 1 TC109
TC110 1 C7 RSVD_AW48 RSVD_B11 A11 1 TC111
TC112 1 U12 RSVD_C7 RSVD_A11 D12 1 TC113
TC114 1 U11 RSVD_U12 RSVD_D12 C12 1 TC115
RSVD_U11 RSVD_C12
TC116 1 H11
RSVD_H11 RSVD_F52
F52 1 TC117 ZVM# state MSM# state VCCEOPIO

0V X 0V
SKYLAKE-U_BGA1356 20 OF 20 ? ?
REV = 1
@ 1V 0V 0.8V

1V 1V 1V

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2014/05/07 Deciphered Date 2015/05/07 SKL(16/16):CFG/RESERVED
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 20 of 99

5 4 3 2 1
 5 4 3 2 1

D D

Security ROM M3 Support + Intel LAN PHY / Wireless LAN Solut i on

+3VS
USROM1
1 8
2 NC_1 VCC 7 +3VALW +3V_SPI
PLTRST_NEAR# 3 NC_2 WP 6 PM_SMB_CLK
[12,47,51] PLTRST_NEAR# PROT# SCL PM_SMB_DAT PM_SMB_CLK [11,25,26,67] 1 +3V_SPI
4 5 CC22 RC310 1 2 0_0402_5%
GND SDA PM_SMB_DAT [11,25,26,67]
0.1U_0402_10V6-K
PCA24S08AD_SO8
2
@ 0.085 A
SA00004MK00/SA00004ML00
@

20141220

SPI_IO3 1 @ 2
RC394 1K_0402_5%

4MB(32Mb) for VPRO SKU

+3V_SPI
[SKL]SPI0_CS0#: SPI FLASH
SPI0_CS1#: SPI FLASH RC117 1 2 1K_0402_5% SPI_IO2
C
SPI0_CS2#: SPI TPM 8MB(64Mb) RC118 1 2 1K_0402_5% SPI_IO3 C

feedback to SDV rev..

15/0522 15/0525

+3V_SPI
+3V_SPI
UC8M1 UC4M1
SPI_CS0#_8MB 1 8 +3V_SPI SPI_CS1#_4MB 1 8 +3V_SPI
[11] SPI_CS0#_8MB CS# VCC [11] SPI_CS1#_4MB SPI_SO_4MB CS# VCC SPI_IO3_4MB
2 7
SPI_SO_8MB 2 7 SPI_IO3_8MB SPI_IO2_4MB 3 DO HOLD# 6 SPI_CLK_4MB
DO HOLD# 1 WP# CLK SPI_SI_4MB 1
4 5 CC26
SPI_IO2_8MB 3 6 SPI_CLK_8MB CC25 GND DI 0.1U_0402_10V7-K
WP# CLK 0.1U_0402_10V7-K W25Q32FVSSIQ_SO8 VPRO@
4 5 SPI_SI_8MB 2 2
GND DI VPRO@

W25Q64FVSSIQ_SO8
2nd = SA00005VN00

RPC23 RPC24
SPI_IO3_8MB 1 8 SPI_IO3 SPI_IO3_4MB 1 8 SPI_IO3
SPI_CLK_8MB SPI_CLK SPI_IO3 [11] SPI_CLK_4MB SPI_CLK
2 7 2 7
SPI_SI_8MB SPI_SI SPI_CLK [11,69] SPI_SI_4MB SPI_SI
3 6 3 6
SPI_IO2_8MB SPI_IO2 SPI_SI [11,69] SPI_IO2_4MB SPI_IO2
4 5 4 5
SPI_IO2 [11]
B 33_0804_8P4R_5% 33_0804_8P4R_5% B
SD30000370T Near SPI ROM SD30000370T
VPRO@

Near SPI ROM

SPI_SO_8MB 1 2 SPI_SO SPI_SO_4MB 1 VPRO@ 2 SPI_SO
SPI_SO [11,69]
RC103 33_0402_5% RC102 33_0402_5%

Mirror Code
RC311 1 2 0_0402_5% SPI_CS0#_8MB
[61] FSCE# SPI_SI_8MB
RC312 1 2 0_0402_5%
[61] SPI_FMOSI# SPI_SO_8MB
RC313 1 2 0_0402_5%
[61] SPI_FMISO SPI_CLK_8MB
RC314 1 2 0_0402_5%
[61] SPI_FSCK

Close to SPI ROM (UC8M1).

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 SPI ROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 23 of 99

5 4 3 2 1
 5 4 3 2 1

+1.35V DDR_A_DQS#[0..7] [7]

+1.35V +1.35V Layout Note:
JDIMM1 ME@
DDR_A_DQS[0..7] [7] Place near JDIMM1
+V_DDR_REFA

1
1 2
VREF_DQ VSS1 DDR_A_D4 DDR_A_D[0..31] [7]
RD1 3 4
DDR_A_D0 5 VSS2 DQ4 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5 DDR_A_MA[0..15] [7]
1.8K_0402_1% 7 8
9 DQ1 VSS3 10 DDR_A_DQS#0 +1.35V
RD2 VSS4 DQS#0 DDR_A_D[32..63] [7]

2
D 1 2 11 12 DDR_A_DQS0 D
[7] SA_DIMM_VREFDQ DM0 DQS0 +1.35V
13 14

2.2U_0402_6.3V6-K
1 CD13 CD14 CD15 CD16 CD19 CD20 CD21 CD22
2_0402_1% DDR_A_D2 VSS5 VSS6 DDR_A_D6

1
15 16

1.8K_0402_1%

0.1U_0402_10V7-K
CD2 1 1 DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

330U_D2_2V_Y
DQ3 DQ7 1

1
19 20

RD3

CD3

CD1
0.022U_0402_25V7-K 1 1 1 1 1 1 1
2 @ DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12 RD21 +
2 2 DDR_A_D9 DQ8 DQ12 DDR_A_D13
1

23 24 470_0402_5%
DQ9 DQ13

2
RD4 25 26
DDR_A_DQS#1 27 VSS9 VSS10 28 2 2 2 2 2 2 2 2
DQS#1 DM1

2
24.9_0402_1% DDR_A_DQS1 29 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# [8,26]
31 32
VSS11 VSS12
2

DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15 1
Close to JDIMM1 35 36 CD59
37 DQ11 DQ15 38 0.1U_0402_10V7-K
DDR_A_D16 VSS13 VSS14 DDR_A_D20
DDR_A_D17
39
DQ16 DQ20
40
DDR_A_D21 2
EMC_NS@ For RF solution.
41 42
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS15 VSS16 46 CD8 CD9 CD10 CD11 CRF1 CRF2
DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D22

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
@ @ RF_NS@ RF_NS@
DDR_A_D18 51 VSS18 DQ22 52 DDR_A_D23
DDR_A_D19 DQ18 DQ23 1 1 1 1 1 1
53 54
55 DQ19 VSS19 56 DDR_A_D28
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29
DDR_A_D25 59 DQ24 DQ29 60 2 2 2 2 2 2
61 DQ25 VSS21 62 DDR_A_DQS#3
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D26 67 VSS23 VSS24 68 DDR_A_D30
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31
71 DQ27 DQ31 72
VSS25 VSS26

DDRA_CKE0_DIMMA 73 74 DDRA_CKE1_DIMMA
C [7] DDRA_CKE0_DIMMA
75 CKE0 CKE1 76
DDRA_CKE1_DIMMA [7] Layout Note: C
77 VDD1 VDD2 78 DDR_A_MA15 Place near JDIMM1.203,204
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
[7] DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11 +0.675VS
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88 CD23 CD24 CD25 CD26
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K
@ @
93 A5 A4 94
DDR_A_MA3 VDD7 VDD8 DDR_A_MA2 1 1 1 1
95 96
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
SA_CLK_DDR0 101 VDD9 VDD10 102 SA_CLK_DDR1 2 2 2 2
[7] SA_CLK_DDR0 SA_CLK_DDR#0 CK0 CK1 SA_CLK_DDR#1 SA_CLK_DDR1 [7]
[7] SA_CLK_DDR#0 103 104 SA_CLK_DDR#1 [7]
105 CK0# CK1# 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 [7] +1.35V
109 110
[7] DDR_A_BS0 BA0 RAS# DDR_A_RAS# [7]
111 112
DDR_A_WE# 113 VDD13 VDD14 114 DDRA_CS0_DIMMA#
[7] DDR_A_WE# DDR_A_CAS# WE# S0# DDRA_ODT0_DIMMA# DDRA_CS0_DIMMA# [7] All VREF traces should

1
115 116
[7] DDR_A_CAS#
117 CAS# ODT0 118
DDRA_ODT0_DIMMA# [7]
RD9 have 10 mil trace width
DDR_A_MA13 119 VDD15 VDD16 120 DDRA_ODT1_DIMMA# 1.8K_0402_1%
DDRA_CS1_DIMMA# A13 ODT1 DDRA_ODT1_DIMMA# [7]
[7] DDRA_CS1_DIMMA# 121 122
123 S1# NC2 124
VDD17 VDD18 RD10

2
125 126 +VREF_CA 1 2
NCTEST VREF_CA SM_DIMM_VREFCA [7]
127 128 1
DDR_A_D32 VSS27 VSS28 DDR_A_D36 2_0402_1%

1
129 130 CD12

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37 RD11 0.022U_0402_25V7-K
DQ33 DQ37 1 1
133 134 1.8K_0402_1%
DDR_A_DQS#4 135 VSS29 VSS30 136 2

CD17

CD18
DDR_A_DQS4 DQS#4 DM4

1
137 138 @
DQS4 VSS31

2
139 140 DDR_A_D38 2 2 RD12
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 24.9_0402_1%
DDR_A_D35 143 DQ34 DQ39 144
B B
145 DQ35 VSS33 146 DDR_A_D44
VSS34 DQ44

2
DDR_A_D40 147 148 DDR_A_D45 +3V_DDR +3VS
DDR_A_D41 DQ40 DQ45 +VREF_CA [26]
149 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS#5 154 DDR_A_DQS5
DM5 DQS5 close to JDDR3L.126

2
155 156 @
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46 RD23 RD25
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47 100K_0402_5%
DQ43 DQ47 100K_0402_5%
161 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DQ48 DQ52

1
DDR_A_D49 165 166 DDR_A_D53
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170
DDR_A_DQS6 171 DQS#6 DM6 172 +1.35V SM_PG_CTRL
DQS6 VSS43 DDR_A_D54 SM_PG_CTRL [86]
173 174
DDR_A_D50 175 VSS44 DQ54 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55

1
177 178
179 DQ51 VSS45 180 DDR_A_D60 QD1
DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61 2 DTC115TMT2L_VMT3
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48
DM7
DQS#7
DQS7
188 DDR_A_DQS7 take care the BOM P/N

3
189 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62 DDR_PG_CTRL
DDR_A_D59 DQ58 DQ62 DDR_A_D63 [7] DDR_PG_CTRL
193 194
195 DQ59 DQ63 196
VSS51 VSS52

1
197 198
199 SA0 EVENT# 200 RD24
+3VS VDDSPD SDA PM_SMB_DAT [11,23,26,67]
201 202 10K_0402_5%
SA1 SCL PM_SMB_CLK [11,23,26,67]
+0.675VS 203 204 +0.675VS @
VTT1 VTT2

2
205 206
G1 G2
2

1 1
RC316 RC315 LCN_DAN06-K4406-0102
A A
CD29 @ CD30
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

0_0402_5%

0_0402_5%

2 2

Channel A
1

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DDR3L DIMM1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 25 of 99

5 4 3 2 1
 5 4 3 2 1

+1.35V
+1.35V +1.35V
[7] SB_DIMM_VREFDQ
JDIMM2 ME@
+V_DDR_REFB DDR_B_DQS#[0..3] [8]

1
1 2
RD15 3 VREF_DQ VSS_2 4 DDR_B_D12
DDR_B_D8 VSS_1 DQ4 DDR_B_D13 DDR_B_DQS[0..3] [8]
5 6
1.8K_0402_1% DDR_B_D9 7 DQ0 DQ5 8
DQ1 VSS_4 DDR_B_DQS#1 DDR_B_D[0..31] [8]
9 10
RD17 VSS_3 DQS0#

2
1 2 11 12 DDR_B_DQS1
13 DM0 DQS0 14
DDR_B_MA[0..15] [8] Layout Note:
1 2_0402_1% DDR_B_D10 VSS_5 VSS_6 DDR_B_D14 Place near JDIMM2

1
15 16

2.2U_0402_6.3V6-K
DDR_B_D11 DQ2 DQ6 DDR_B_D15 DDR_B_D[32..63] [8]
17 18

CD32
0.022U_0402_25V7-K CD31 RD16 1 1
19 DQ3 DQ7 20

0.1U_0402_10V7-K
D D
2 DDR_B_D0 VSS_7 VSS_8 DDR_B_D4 DDR_B_DQS#[4..7] [8] +1.35V
21 22

CD33
1.8K_0402_1%
DDR_B_D1 DQ8 DQ12 DDR_B_D5

1
@ 23 24
2 2 DQ9 DQ13 DDR_B_DQS[4..7] [8]

2
25 26
24.9_0402_1% RD18 DDR_B_DQS#0 27 VSS_9 VSS_10 28 CD42 CD43 CD44 CD45 CD46 CD47 CD48
DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# [8,25]
31 32
VSS_11 VSS_12
2
DDR_B_D2 33 34 DDR_B_D6

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
DDR_B_D3 DQ10 DQ14 DDR_B_D7 1 1 1 1 1 1 1 1
35 36
37 DQ11 DQ15 38
Close to JDIMM2 DDR_B_D16 39 VSS_13 VSS_14 40 DDR_B_D20
CD60 EMC_NS@
0.1U_0402_10V7-K
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D21 2 2 2 2 2 2 2 2
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS_15 VSS_16 46
DDR_B_DQS2 47 DQS2# DM2 48
49 DQS2 VSS_18 50 DDR_B_D22
DDR_B_D18 51 VSS_17 DQ22 52 DDR_B_D23
DDR_B_D19 53 DQ18 DQ23 54
55 DQ19 VSS_20 56 DDR_B_D28
DDR_B_D24 VSS_19 DQ28 DDR_B_D29
DDR_B_D25
57
DQ24 DQ29
58 For RF solution.
59 60
61 DQ25 VSS_22 62 DDR_B_DQS#3 CD38 CD39 CD40 CD41 CRF3 CRF4
63 VSS_21 DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D26 67 VSS_23 VSS_24 68 DDR_B_D30
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

2200P_0402_50V7-K

47P_0402_50V8-J
@ @ RF_NS@ RF_NS@
71 DQ27 DQ31 72
VSS_25 VSS_26 1 1 1 1 1 1

DDRB_CKE0_DIMMB 73 74 DDRB_CKE1_DIMMB
[8] DDRB_CKE0_DIMMB CKE0 CKE1 DDRB_CKE1_DIMMB [8] 2 2 2 2 2 2
75 76
77 VDD_1 VDD_2 78 DDR_B_MA15
DDR_B_BS2 79 NC_1 A15 80 DDR_B_MA14
[8] DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD_3 VDD_4 84 DDR_B_MA11
C DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7 C
87 A9 A7 88
DDR_B_MA8 89 VDD_5 VDD_6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD_7 VDD_8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
Layout Note:
SB_CLK_DDR0 101 VDD_9 VDD_10 102 SB_CLK_DDR1 Place near JDIMM2.203,204
[8] SB_CLK_DDR0 SB_CLK_DDR#0 CK0 CK1 SB_CLK_DDR#1 SB_CLK_DDR1 [8]
[8] SB_CLK_DDR#0 103 104 SB_CLK_DDR#1 [8]
105 CK0# CK1# 106 +0.675VS
DDR_B_MA10 107 VDD_11 VDD_12 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 [8]
[8] DDR_B_BS0 109 110 DDR_B_RAS# [8]
111 BA0 RAS# 112 CD51 CD52 CD53 CD54 CD55 CD56
DDR_B_WE# 113 VDD_13 VDD_14 114 DDRB_CS0_DIMMB#
[8] DDR_B_WE# DDR_B_CAS# WE# S0# DDRB_ODT0_DIMMB# DDRB_CS0_DIMMB# [8]
115 116

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

1U_0402_6.3VA-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M
[8] DDR_B_CAS# CAS# ODT0 DDRB_ODT0_DIMMB# [8]
117 118 1 1 1 1 1 1
DDR_B_MA13 119 VDD_15 VDD_16 120 DDRB_ODT1_DIMMB#
DDRB_CS1_DIMMB# A13 ODT1 DDRB_ODT1_DIMMB# [8]
[8] DDRB_CS1_DIMMB# 121 122
123 S1# NC_2 124
125 VDD_17 VDD_18 126 +VREF_CA 2 2 2 2 2 2
TEST VREF_CA +VREF_CA [25]
127 128
DDR_B_D32 129 VSS_27 VSS_28 130 DDR_B_D36
DDR_B_D33 131 DQ32 DQ36 132 DDR_B_D37
133 DQ33 DQ37 134
DDR_B_DQS#4 VSS_29 VSS_30 1
135 136 CD49
DDR_B_DQS4 137 DQS4# DM4 138
139 DQS4 VSS_32 140 DDR_B_D38 0.1U_0402_10V7-K
All VREF traces should
DDR_B_D34 141 VSS_31 DQ38 142 DDR_B_D39 2 have 10 mil trace width
DDR_B_D35 143 DQ34 DQ39 144
145 DQ35 VSS_34 146 DDR_B_D44
DDR_B_D40 147 VSS_33 DQ44 148 DDR_B_D45
DDR_B_D41 149 DQ40 DQ45 150
151 DQ41 VSS_35 152 DDR_B_DQS#5
153 VSS_36 DQS5# 154 DDR_B_DQS5
B B
155 DM5 DQS5 156
DDR_B_D42 157 VSS_37 VSS_38 158 DDR_B_D46
DDR_B_D43 159 DQ42 DQ46 160 DDR_B_D47
161 DQ43 DQ47 162
DDR_B_D48 163 VSS_39 VSS_40 164 DDR_B_D52
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS_41 VSS_42 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS_44 174 DDR_B_D54
DDR_B_D50 175 VSS_43 DQ54 176 DDR_B_D55
DDR_B_D51 177 DQ50 DQ55 178
179 DQ51 VSS_46 180 DDR_B_D60
+3VS DDR_B_D56 181 VSS_45 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS_48 186 DDR_B_DQS#7
VSS_47 DQS7# DDR_B_DQS7
1

187 188
RD19 189 DM7 DQS7 190
DDR_B_D58 191 VSS_49 VSS_50 192 DDR_B_D62
10K_0402_5% DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D63
195 DQ59 DQ63 196
VSS_51 VSS_52
2

197 198
199 SA0 EVENT# 200
+3VS VDDSPD SDA PM_SMB_DAT [11,23,25,67]
201 202
SA1 SCL PM_SMB_CLK [11,23,25,67]
+0.675VS 203 204 +0.675VS
VTT_1 VTT_2
205 206
207 GND1 GND2 208
2.2U_0402_6.3V6-K

0.1U_0402_10V6-K

CD58

@
BOSS1 BOSS2
2

1 1
RC317
CD57

LCN_DAN06-K4406-0103
0_0402_5%
2 2
Channel B
1

A A

<Address: SA1:SA0=10>

DIMM_2 STD H:4mm

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DDR3L DIMM2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 26 of 99

5 4 3 2 1
 1 2 3 4 5

UV1A @

PART 1 0F 9

PCIE_CTX_C_GRX_P0 AA38 Y33 PCIE_CRX_C_GTX_P0 CV1 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P0

[15] PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_CRX_C_GTX_N0 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P0 [15]
CTX0 [15] PCIE_CTX_C_GRX_N0 Y37
PCIE_RX0N PCIE_TX0N
Y32 CV2 DIS@ 1 2 0.1U_0402_10V7-K
PCIE_CRX_GTX_N0 [15] CRX0

PCIE_CTX_C_GRX_P1 Y35 W33 PCIE_CRX_C_GTX_P1 CV3 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P1

[15] PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_CRX_C_GTX_N1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P1 [15]
CTX1 [15] PCIE_CTX_C_GRX_N1 W36
PCIE_RX1N PCIE_TX1N
W32 CV4 DIS@ 1 2 0.1U_0402_10V7-K
PCIE_CRX_GTX_N1 [15] CRX1
A A
PCIE_CTX_C_GRX_P2 W38 U33 PCIE_CRX_C_GTX_P2 CV5 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P2
[15] PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 [15]
CTX2 [15] PCIE_CTX_C_GRX_N2
V37
PCIE_RX2N PCIE_TX2N
U32 CV6 DIS@ 1 2 0.1U_0402_10V7-K
PCIE_CRX_GTX_N2 [15] CRX2

PCIE_CTX_C_GRX_P3 V35 U30 PCIE_CRX_C_GTX_P3 CV7 DIS@ 1 2 0.1U_0402_10V7-K PCIE_CRX_GTX_P3 UV1C

[15] PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_CRX_C_GTX_N3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P3 [15]
CTX3 [15] PCIE_CTX_C_GRX_N3 U36
PCIE_RX3N PCIE_TX3N
U29 CV8 DIS@ 1 2 0.1U_0402_10V7-K
PCIE_CRX_GTX_N3 [15] CRX3

U38 T33 PART 3 0F 9

T37 PCIE_RX4P PCIE_TX4P T32
PCIE_RX4N PCIE_TX4N

T35 T30
R36 PCIE_RX5P PCIE_TX5P T29 AV33 XTALIN
PCIE_RX5N PCIE_TX5N XTALIN

R38 P33
PCIE_RX6P PCIE_TX6P
P37
PCIE_RX6N PCIE_TX6N
P32
160mA
P35 P30 AU34 XTALOUT
N36 PCIE_RX7P PCIE_TX7P P29 +1.8VS_VGA MPLL_PVDD XTALOUT
PCIE_RX7N PCIE_TX7N
LV3 DIS@
N38 N33 1 2 CV220 CV219 CV218 H7
M37 PCIE_RX8P PCIE_TX8P N32 H8 MPLL_PVDD_1
PCIE_RX8N PCIE_TX8N MPLL_PVDD_2

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
BLM18PG221SN1D_2P

PCI EXPRESS INTERFACE

1 1 1 AW34
M35 N30 XO_IN
L36 PCIE_RX9P PCIE_TX9P N29 AM10
PCIE_RX9N PCIE_TX9N SPLL_PVDD

DIS@

DIS@

DIS@

PLLS/XTAL
2 2 2
L38 L33
K37 PCIE_RX10P PCIE_TX10P L32 AN9 AW35
B PCIE_RX10N PCIE_TX10N SPLL_VDDC XO_IN2 B

K35 L30
75mA
J36 PCIE_RX11P PCIE_TX11P L29 AN10
PCIE_RX11N PCIE_TX11N +1.8VS_VGA SPLL_PVDD SPLL_PVSS
LV4 DIS@
J38 K33 1 2 CV222 CV221 CV225
H37 PCIE_RX12P PCIE_TX12P K32 AK10
PCIE_RX12N PCIE_TX12N AF30 CLKTESTA AL10

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
BLM18PG121SN1D_2P
AF31 NC_XTAL_PVDD CLKTESTB
1 1 1 NC_XTAL_PVSS
H35 J33
G36 PCIE_RX13P PCIE_TX13P J32
PCIE_RX13N PCIE_TX13N

DIS@

DIS@

DIS@
2 2 2
G38
F37 PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
K30
K29 100mA
216-0855000_A0_FCBGA962
F35 H33 +0.95VS_VGA
E37 PCIE_RX15P PCIE_TX15P H32 SPLL_VDDC
PCIE_RX15N PCIE_TX15N LV5 DIS@
1 2 CV226 CV223 CV224
CLOCK
BLM18PG121SN1D_2P

10U_0603_6.3V6-M

1U_0402_10V6-K

0.1U_0402_10V7-K
CLK_PCIE_VGA RV4 1 DIS@ 2 0_0402_5% AB35
[10] CLK_PCIE_VGA CLK_PCIE_VGA# PCIE_REFCLKP 1 1 1
RV5 1 DIS@ 2 0_0402_5% AA36
[10] CLK_PCIE_VGA# PCIE_REFCLKN +0.95VS_VGA

DIS@

DIS@

DIS@
CALIBRATION 2 2 2
Y30 RV6 1 DIS@ 2 1.69K_0402_1%
PCIE_CALR_TX
RV7 1 DIS@ 2 1K_0402_5% AH16 Y29 RV8 1 DIS@ 2 1K_0402_5%
TEST_PG PCIE_CALR_RX

C
PLT_RST_VGA# AA30 C
PERSTB

216-0855000_A0_FCBGA962

+3VS_VGA
1

RV11 RV10 DIS@

@ RV207 1 @ 2 0_0402_5%
10K_0402_5% 1 2
+3VS_VGA
2

RV13 @ L->H 1M_0402_5%

2 1 +3VS
[14,36,83] VGA_ON

1
YV1 DIS@
10K_0402_5% RV9 4 3 XTALOUT
CV19

0.1U_0402_10V7-K

NC2 OSC2
5

+3VS_VGA 10K_0402_5%
1
@ XTALIN 1 2
VCC

PLTRST# 1 OSC1 NC1

[12] PLTRST# IN1

2
1

4
@

1 27MHZ_16PF_7V27000011 1
2 DGPU_HOLD_RST# OUT PLT_RST_VGA# [28,83]
RV14 [14] DGPU_HOLD_RST# 2 CV17 CV18
GND

IN2

1
@ DIS@ DIS@
10K_0402_5% RV167 22P_0402_50V8-J 22P_0402_50V8-J
2 2
2

QV1 UV15 100K_0402_5%

G

@ MC74VHC1G08DFT2G_SC70-5 DIS@
1 3 CLK_REQ_GPU# DIS@
[10] CLKREQ_PCIE4_VGA# CLK_REQ_GPU# [28]
2
D

S
CV20

0.1U_0402_10V7-K

D D
2

1 2N7002WT1G_1N_SC-70-3
SB00000YY00 RV15
10K_0402_5%
1 @ 2 @
@

2
1

RV16 0_0402_5%

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Graphic
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 27 of 99

1 2 3 4 5
 5 4 3 2 1

After check with AE, can leave NC for GPIO17. RV110 @

1 2
H_THERMTRIP# [6]
@
GPIO17_THERMAL_INT 1 2 47K_0402_5%
RV104 0_0402_5%
RV105 @

1
C
GPIO19_CTF 1 @ 2 47K_0402_5% 1 2 2
RV102 QV4
B S TR TTC4116FU NPN SC-70-3
+3VS_VGA

0.1U_0402_25V6-K
D 2 @ 1 2.2K_0402_5% E SB000010U00 D

3
1

CV209 @
RV118 10K_0402_5% 1 @
RV103 @
UV1B 10K_0402_5%

DV4 @ 2
PART 2 0F 9 PLT_RST_VGA#

2
1 2
[27,83] PLT_RST_VGA#
MUTI GFX

2
AD29 AU24 RB751V-40_SOD323-2

G
AC29 GENLK_CLK TXCAP_DPA3P AV23 SCS00006S00
GENLK_VSYNC TXCAM_DPA3N
AT25
6 1 SMBCLK AJ21 TX0P_DPA2P AR24
[11,60,61,66,68] EC_SMB_CK3

S
AK21 SWAPLOCKA DPA TX0M_DPA2N

D
DIS@ QV5A SWAPLOCKB AU26
2N7002KDWH_SOT363-6 TX1P_DPA1P AV25
TX1M_DPA1N
2 @ 1 RV144 AR8 AT27
AU8 DVPCNTL_MVP_0 TX2P_DPA0P AR26
0_0402_5% AP8 DVPCNTL_MVP_1 TX2M_DPA0N
DVPCNTL_0

5
AW8 AR30

G
AR3 DVPCNTL_1 TXCBP_DPB3P AT29
AR1 DVPCNTL_2 TXCBM_DPB3N
AU1 DVPCLK AV31
3 4 SMBDAT AU3 DVPDATA_0 TX3P_DPB2P AU30
[11,60,61,66,68] EC_SMB_DA3

S
AW3 DVPDATA_1 DPB TX3M_DPB2N

D
DVPDATA_2
DIS@ QV5B AP6
DVPDATA_3 TX4P_DPB1P
AR32
VID CODES Add Optional Bypass resistor
2N7002KDWH_SOT363-6 AW5 AT31
AU5 DVPDATA_4 TX4M_DPB1N
0_0402_5% 2 @ 1 RV142 AR6 DVPDATA_5 AT33 1 DI S@ 2 0_0402_5%
DVPDATA_6 TX5P_DPB0P SVC SVD Boot Voltage RV180
PU AT EC SIDE, +3VS AND 4.7K AW6 AU32
AU6 DVPDATA_7 TX5M_DPB0N RV181 1 DI S@ 2 0_0402_5%
AT7 DVPDATA_8 AU14 0 0 1.1V
AV7 DVPDATA_9 TXCCP_DPC3P AV13
AN7 DVPDATA_10 TXCCM_DPC3N 0 1 1.0V
AV9 DVPDATA_11 AT15
AT9 DVPDATA_12 TX0P_DPC2P AR14 1 0 0.9V(Default) +3VS_VGA +1.8VS_VGA
AR10 DVPDATA_13 TX0M_DPC2N +3VS_VGA
AW10 DVPDATA_14 DPC AU16 1 1 0.8V
AU10 DVPDATA_15 TX1P_DPC1P AV15
AP10 DVPDATA_16 TX1M_DPC1N
AV11 DVPDATA_17 AT17

CV205

0.1U_0402_10V7-K

CV207

0.1U_0402_10V7-K
+3VS_VGA AT11 DVPDATA_18 TX2P_DPC0P AR16
DVPDATA_19 TX2M_DPC0N 1 1
AR12
DVPDATA_20

1
AW12 AU20
DVPDATA_21 TXCDP_DPD3P

@
RV99 1 DIS@ 2 4.7K_0402_5% AU12 AT19 RV91 RV92
AP12 DVPDATA_22 TXCDM_DPD3N 10K_0402_5% 10K_0402_5% 2 2
RV98 1 DIS@ 2 4.7K_0402_5% DVPDATA_23 AT21 @ DIS@ UV14 @
TX3P_DPD2P AR20
TX3M_DPD2N
SVD

2
1 8
C SMBCLK AJ23 DPD AU22 VCC(A) VCC(B) C
AH23 SMBCLK SMBus TX4P_DPD1P AV21 GPIO15_PWRCNTL_0 SVI2_SVD
SMBDAT RV178 1 DIS@ 2 0_0402_5% 2 7 RV96 1 @ 2 33_0402_5%
SMBDATA TX4M_DPD1N 1A 1B SVI2_SVD [83]
AT23 GPIO20_PWRCNTL_1 SVI2_SVC
RV179 1 DIS@ 2 0_0402_5% 3 6 RV97 1 @ 2 33_0402_5%
TX5P_DPD0P AR22 2A 2B SVI2_SVC [83]
Test_Point_20MIL 1 TPV13 I2CS_SCL
I2CS_SDA
AK26
SCL
TX5M_DPD0N SVC 5
DIR GND
4

1
1 TPV14 AJ26 I2C
Test_Point_20MIL
SDA RV127 RV133
AD39 10K_0402_5% 10K_0402_5% 74AVCH2T45GD_XSON8_3X2
R AD37 DIS@ @
GENERAL PURPOSE I/O
@ 2 10K_0402_5% AVSSN_1
+3VS_VGA RV138 1 AH20
RV134
+3VS_VGA
GPIO_0

2
+3VS_VGA RV139 1 @ 2 10K_0402_5% AH18 AE36
GPIO_1 G
NC but reserved PU resistor RV140 1 @ 2 10K_0402_5% AN16 AD35 1 2
GPIO_2 AVSSN_2

0.1U_0402_10V7-K

10U_0603_6.3V6-M
AF37 10K_0402_5%
GPIO5_AC_BATT B
1

CV206 @

CV208 @
AH17 AE38 1 1 @
AJ17 GPIO_5_AC_BATT AVSSN_3
RV117
DIS@ AK17 GPIO_6 DAC1 AC36
Keep voltage level.
1 TPV3 GPIO8_ROMSO AJ13 GPIO_7_BLON HSYNC AC38
2.2K_0402_5% Test_Point_20MIL
1 TPV4 GPIO9_ROMSI AH15 GPIO_8_ROMSO VSYNC 2 2
Test_Point_20MIL
GPIO10_ROMSCK
2

GPIO_9_ROMSI

1
Test_Point_20MIL 1 TPV5 AJ16 +1.8VS_VGA
AK16 GPIO_10_ROMSCK AB34 RV145 RV146
DV5 AL16 GPIO_11 RSET 10K_0402_5% 10K_0402_5%
VGA_AC_DC# 1 2 GPIO5_AC_BATT AM16 GPIO_12 AD34 DIS@ DIS@
[61] VGA_AC_DC# 1 TPV15 GPIO10_ROMSCK AM14 GPIO_13 AVDD AE34
Test_Point_20MIL
GPIO15_PWRCNTL_0 GPIO_14_HPD2 AVSSQ

2
RB751V-40_SOD323-2 AM13
GPIO_15_PWRCNTL_0

1
SCS00006S00 AK14 AC33
GPIO17_THERMAL_INT AG30 GPIO_16 VDD1DI AC34
DIS@ RV148
AN14 GPIO_17_THERMAL_INT VSS1DI DIS@
1 2 GPIO19_CTF AM17 GPIO_18_HPD3
RV149 @ 0_0402_5% 499_0402_1%
[61,83] GPU_VR_HOT# GPIO20_PWRCNTL_1 GPIO_19_CTF
AL13 V13
GPIO_20_PWRCNTL_1 NC_1

2
AJ14 U13
1 TPV6 GPIO22_ROMCSB AK13 GPIO_21 NC_2 AF33
Test_Point_20MIL
RV129 1 @ 2 0_0402_5% AN13 GPIO_22_ROMCSB NC_TSVSSQ AF32
[27] CLK_REQ_GPU# RV130 1 @ 2 100_0402_5% CLKREQB NC_7 AA29
NC_8 AG21
AG32 NC_9 AC32
GPIO_29 NC_5
AG33
GPIO_30 AC31
MLPS Recommend setting Value
AJ19 NC_3 AD30
AK19 GENERICA NC_4 AD32
+1.8VS_VGA GENERICB NC_6
AJ20
AK20 GENERICC RV112 = 8.45K ohm
11001 RV113 = 2K ohm
GENERICD
AJ24
AH26 GENERICE_HPD4 PS_0 PS0[5..1] =
AH24 GENERICF_HPD5 CV213 = NC
GENERICG_HPD6
AM34 PS_0
2

PS_0 +1.8VS_VGA +1.8VS_VGA

RV128 Test_Point_20MIL 1 TPV16 CEC AC30
RV106 = NC
11000 RV109 = 4.75K ohm
CEC_1
B 499_0402_1%
PS_1 PS_1 PS1[5..1] = B

1
DI S@ Test_Point_20MIL 1 TPV17 HPD AK24 AD31
HPD1 MLPS PS_1 RV112 RV108 CV212 = NC
1

DIS@ @
8.45K_0402_1% 4.99K_0402_1%
PS_2
CV214 VREFG AH13
VREFG PS_2
AG31
PS_0 PS_2 RV108 = NC

2
PX5.0 doesn't need this function. Leave as NC.
PS_2 PS2[5..1] = 11000 RV111 = 4.75K ohm
0.1U_0402_10V7-K

1 BACO PS_3 CV210 = NC

1
Test_Point_20MIL 1 TPV12 RV101 1 @ 2 0_0402_5% AL21 AD33 1 1
+3VS_VGA PX_EN PS_3 RV113 CV213 RV111 CV210
2

+3VS_VGA DIS@ DIS@

2
RV114 =

0.1U_0402_10V7-K

0.082U_0402_50V7-K
RV160 2K_0402_1% 4.75K_0402_1%
1 @ 2 2 2
249_0402_1% RV93 5.11K_0402_1%
11xxx RV107 =

2
DEBUG DDC/AUX
DI S@ DDC1CLK
AM26
PS_3 PS3[5..1] =
1

AN26
RV94 1 DIS@ 2 1K_0402_5% CV211 = NC
1

RV131 RV132 RV135 RV136 AD28 DDC1DATA

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% TESTEN AM27
@ @ @ @ AUX1P AL27
AUX1N
JTAG_TRSTB
2

Tes t_Point_20MIL 1 TPV7 AM23 AM19

JTAG_TRSTB 1 TPV8 JTAG_TDI AN23 JTAG_TRSTB DDC2CLK AL19 +1.8VS_VGA +1.8VS_VGA
Tes t_Point_20MIL
JTAG_TMS 1 TPV9 JTAG_TCK AK23 JTAG_TDI DDC2DATA
Tes t_Point_20MIL
JTAG_TDI 1 TPV10 JTAG_TMS AL24 JTAG_TCK AN20
Tes t_Point_20MIL
JTAG_TDO JTAG_TDO JTAG_TMS AUX2P

1
Tes t_Point_20MIL 1 TPV11 AM24
JTAG_TDO AUX2N
AM20 RV114 RV107 Strap PS_3[3..1]
RV106 RV114
AL30 @ S2G@
DDCCLK_AUX3P
1

DDCDATA_AUX3N
AM30 8.45K_0402_1% 3.4K_0402_1% FB Memory (DDR3L)
RV137
PS_1 PS_3

2
10K_0402_5% THERMAL AL29
DDCCLK_AUX4P
@ Test_Point_20MIL 1 DPLS AF29
DPLUS DDCDATA_AUX4N
AM29 1G PU 8.45K PD 2K 001
Test_Point_20MIL
TPV18 1 DMINUS AG29 Samsung
DMINUS
2

1
TPV20 AN21 1 1
DDCCLK_AUX5P AM21
DDCDATA_AUX5N
RV109 CV212 RV107 CV211 2G PU 3.4K PD 10K 110
13mA 1 DIS@ 2 FDO AK32
GPIO_28_FDO
DIS@ S2G@

0.1U_0402_10V7-K

0.1U_0402_10V7-K
RV147 10K_0402_5% AK30 4.75K_0402_1% 10K_0402_1%
AL31 DDCCLK_AUX6P AK29 2 2
TS_A DDCDATA_AUX6N 1G PU 4.53K PD 2K 010

2
+1.8VS_VGA
LV6 Hynix
AJ30
DDCVGACLK
1 2 CV216 CV217 CV215 AJ32
TSVDD DDCVGADATA
AJ31 2G PU 4.75K NC 111
AJ33
TSVSS
10U_0603_6.3V6-M

0.1U_0402_10V7-K

BLM15PX121SN1D_2P
1G NC PD 4.75K 000
1U_0402_10V6-K

DIS@ 1 1 1
Micron
E450 unused. 216-0855000_A0_FCBGA962
2G PU 3.24K PD 5.62K 101
DIS@

DIS@

DIS@

2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2012/07/01 Deciphered Date 2014/07/01 Graphic

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF LC FUTURE CENTER.
D
BE560 0.1

Date: W ednesday , S eptem ber 23, 2015

Sheet 28 of 99
5 4 3 2 1

https://dr-bios.com
 1 2 3 4 5

100mA
+1.8VS_VGA

1.5A UV1E TPV1

Test_Point_32MIL CV21 CV24 CV25

PART 5 0F 9

10U_0603_6.3V6-M
+1.35VS_VGA

1U_0402_10V6-K

1U_0402_10V6-K
MEM I/O 1 1 1

1
CV22 CV26 CV27 CV28 CV23 CV29 CV30 CV31 AC7 AA31
AD11 VDDR1_1 NC_PCIE_VDDR_1 AA32
AF7 VDDR1_2 NC_PCIE_VDDR_2 AA33

.01U_0402_16V7-K

0.1U_0402_10V7-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

DIS@

DIS@

DIS@
VDDR1_3 NC_PCIE_VDDR_3 2 2 2

A
1 1 1 1 1 1 1 1 AG10
AJ7
AK8
VDDR1_4
VDDR1_5
NC_PCIE_VDDR_4
NC_PCIE_VDDR_5
AA34
W30
Y31
1A A
AL9 VDDR1_6 NC_PCIE_VDDR_6 V28

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
+0.95VS_VGA
2 2 2 2 2 2 2 2 G11 VDDR1_7 NC_BIF_VDDC_1 W29
VDDR1_8 NC_BIF_VDDC_2
G14
G17 VDDR1_9 PCIE_PVDD
AB37
0.8A

PCIE
G20 VDDR1_10 G30 CV32 CV33 CV34 CV35 CV36 CV37 CV38
G23 VDDR1_11 PCIE_VDDC_1 G31
G26 VDDR1_12 PCIE_VDDC_2 H29 +0.95VS_VGA

10U_0603_6.3V6-M
G29 VDDR1_13 PCIE_VDDC_3 H30

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VDDR1_14 PCIE_VDDC_4 1 1 1 1 1 1 1
H10 J29
J7 VDDR1_15 PCIE_VDDC_5 J30 CV227
J9 VDDR1_16 PCIE_VDDC_6 L28

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
K11 VDDR1_17 PCIE_VDDC_7 M28 2 2 2 2 2 2 2

1U_0402_10V6-K
K13 VDDR1_18 PCIE_VDDC_8 N28
VDDR1_19 PCIE_VDDC_9 1
K8 R28
L12 VDDR1_20 PCIE_VDDC_10 T28
VDDR1_21 PCIE_VDDC_11
L16 U28
37A

DIS@
L21 VDDR1_22 PCIE_VDDC_12 2
L23 VDDR1_23
L26 VDDR1_24 N27
L7 VDDR1_25 BACO BIF_VDDC_1 T27 +VGA_CORE
M11 VDDR1_26 BIF_VDDC_2
VDDR1_27
13mA N11
P7
R11
VDDR1_28
VDDR1_29 CORE VDDC_1
AA15
AA17
CV39 CV40 CV41 CV42 CV43 CV44 CV45 CV46 CV47 CV48 CV49 CV50 CV51 CV52

U11 VDDR1_30 VDDC_2 AA20

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M

10U_0603_6.3V6-M
+1.8VS_VGA
U7 VDDR1_31 VDDC_3 AA22
VDDR1_32 VDDC_4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Y11 AA24
CV53 Y7 VDDR1_33 VDDC_5 AA27
VDDR1_34 VDDC_6 AB16

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

@
VDDC_7 AB18 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDDC_8 AB21
1U_0402_10V6-K

1 VDDC_9
+1.8VS_VGA AB23
VDDC_10 AB26
LEVEL VDDC_11 AB28
DIS@

TRANSLATION
B 2 AF26 VDDC_12 AC17 B
VDD_CT_1 VDDC_13
25mA AF27
AG26
AG27
VDD_CT_2
VDD_CT_3
VDDC_14
VDDC_15
AC20
AC22
AC24
CV54 CV55 CV56 CV57 CV58 CV59 CV60 CV61

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K

2.2U_0402_6.3V6-K
+3VS_VGA +3VS_VGA VDD_CT_4 VDDC_16 AC27
VDDC_17 1 1 1 1 1 1 1 1
AD18
VDDC_18 AD21
I/O VDDC_19
CV62 AF23 AD23

DIS@

DIS@

DIS@

DIS@

DIS@

@
AF24 VDDR3_1 VDDC_20 AD26 2 2 2 2 2 2 2 2
AG23 VDDR3_2 VDDC_21 AF17
AG24 VDDR3_3 VDDC_22 AF20
1U_0402_10V6-K

1 VDDR3_4 VDDC_23 AF22

VDDC_24 AG16
DVP VDDC_25
AD12 AG18
@

2 AF11 VDDR4_1 VDDC_26

AF12 VDDR4_2 AH22
VDDR4_3 VDDC_28
30mA AF13
VDDR4_4 VDDC_29
VDDC_30
AH27
AH28
M26
+1.8VS_VGA AF15 VDDC_31 N24
AG11 VDDR4_5 VDDC_32 R18
AG13 VDDR4_6 VDDC_33 R21
CV63 AG15 VDDR4_7 VDDC_34 R23
VDDR4_8 VDDC_35 R26
VDDC_36 T17
1U_0402_10V6-K

VDDC_37 T20
1 VDDC_38 T22
VDDC_39 T24
VDDC_40 U16
DIS@

2 VDDC_41 U18
VDDC_42 U21
VDDC_43 U23
VDDC_44 U26
VDDC_45 V17
VDDC_46 V20
C C
VDDC_47 V22
VDDC_48 V24
VDDC_49 V27
VDDC_50
VDDC_51
VDDC_52
Y16
Y18
Y21
37A
VDDC_53 Y23
VDDC_54 Y26 +VGA_CORE
VDDC_55 Y28
VDDC_56
AA13 CV64 CV65 CV66 CV67 CV68 CV69 CV70
VDDCI_1 AB13
VDDCI_2 AC12

10U_0603_6.3V6-M

10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K
VDDCI_3 AC15

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VDDCI_4 1 1 1 1 1 1 1
AD13
VDDCI_5 AD16
VDDCI_6 M15

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
VDDCI_7 M16 2 2 2 2 2 2 2
VDDCI_8 M18
VOLTAGE VDDCI_9 M23
VDDCI_10
CORE I/O

SENESE N13
ISOLATED

AF28 VDDCI_11 N15

[83] VDDC_SEN FB_VDDC VDDCI_12 N17
VDDCI_13 N20
AG28 VDDCI_14 N22
FB_VDDCI VDDCI_15 R12
VDDCI_16 R13
AH29 VDDCI_17 R16
[83] VDDC_RTN FB_GND VDDCI_18 T12
VDDCI_19 T15
VDDCI_20 V15
VDDCI_21 Y13
VDDCI_22

D D

216-0855000_A0_FCBGA962

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 Graphic
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 29 of 99

1 2 3 4 5
 5 4 3 2 1

UV1G

AB39
PART 7 0F 9

A3 UV1F
280mA
E39 GND_176 GND_1 A37 UV1D
F34 GND_177 GND_2 AA16 +0.95VS_VGA
F39 GND_178 GND_3 AA18 PART 6 0F 9
G33 GND_179 GND_4 AA2 PART 4 0F 9
G34 GND_180 GND_5 AA21 DP_VDDR DP_VDDC
H31 GND_181 GND_6 AA23 AP31 AK27
H34 GND_182 GND_7 AA26 DP_VDDC_1 AP32 VARY_BL AJ27
D D
H39 GND_183 GND_8 AA28 DP_VDDC_2 AN33 DIGON
J31 GND_184 GND_9 AA6 DP_VDDC_3 AP33 LVDS CONTROL
J34 GND_185 GND_10 AB12 AN24 DP_VDDC_4 AL33
K31 GND_186 GND_11 AB15 AP24 NC_DP_VDDR_1 DP_VDDC_5 AM33
K34 GND_187 GND_12 AB17 AP25 NC_DP_VDDR_6 DP_VDDC_6 AK33 AK35
K39 GND_188 GND_13 AB20 AP26 NC_DP_VDDR_7 DP_VDDC_7 AK34 TXCLK_UP_DPF3P AL36
L31 GND_189 GND_14 AB22 AU28 NC_DP_VDDR_8 DP_VDDC_8 AN31 TXCLK_UN_DPF3N
L34 GND_190 GND_15 AB24 AV29 NC_DP_VDDR_10 DP_VDDC_9 AJ38
M34 GND_191 GND_16 AB27 NC_DP_VDDR_12 TXOUT_U0P_DPF2P AK37
M39 GND_192 GND_17 AC11 TXOUT_U0N_DPF2N
N31 GND_193 GND_18 AC13 AP20 AP13 AH35
N34 GND_194 GND_19 AC16 AP21 NC_DP_VDDR_2 NC_DP_VDDC_1 AT13 TXOUT_U1P_DPF1P AJ36
GND_195 GND_20 NC_DP_VDDR_3 NC_DP_VDDC_4 TXOUT_U1N_DPF1N
P31
P34
P39
GND_196
GND_197
GND_21
GND_22
AC18
AC2
AC21
237mA AP22
AP23
AU18
NC_DP_VDDR_4
NC_DP_VDDR_5
NC_DP_VDDC_2
NC_DP_VDDC_3
AP14
AP15
TXOUT_U2P_DPF0P
AG38
AH37
R34 GND_198 GND_23 AC23 AV19 NC_DP_VDDR_9 TXOUT_U2N_DPF0N
T31 GND_199 GND_24 AC26 +1.8VS_VGA NC_DP_VDDR_11 DP GND AF35
T34 GND_200 GND_25 AC28 AN27 TXOUT_U3P AG36
GND_201 GND_26 DP_VSSR_1 TXOUT_U3N

LVTMDP
T39 AC6 CV71 CV72 AH34 AP27
U31 GND_202 GND_27 AD15 AJ34 DP_VDDR_13 DP_VSSR_2 AP28
U34 GND_203 GND_28 AD17 AF34 DP_VDDR_14 DP_VSSR_3 AW24

10U_0603_6.3V6-M
V34 GND_204 GND_29 AD20 AG34 DP_VDDR_15 DP_VSSR_4 AW26

1U_0402_10V6-K
GND_205 GND_30 1 1 DP_VDDR_16 DP_VSSR_5
V39 AD22 AM37 AN29 AP34
W31 GND_206 GND_31 AD24 AL38 DP_VDDR_17 DP_VSSR_6 AP29 TXCLK_LP_DPE3P AR34
W34 GND_207 GND_32 AD27 AM32 DP_VDDR_18 DP_VSSR_7 AP30 TXCLK_LN_DPE3N

@
Y34 GND_208 GND_33 AD9 2 2 DP_VDDR_19 DP_VSSR_8 AW30 AW37
Y39 GND_209 GND_34 AE2 DP_VSSR_9 AW32 TXOUT_L0P_DPE2P AU35
GND_210 GND_35 AE6 DP_VSSR_10 AN17 TXOUT_L0N_DPE2N
GND_36 AF10 DP_VSSR_11 AP16 AR37
GND_37 AF16 DP_VSSR_12 AP17 TXOUT_L1P_DPE1P AU39
GND_38 AF18 DP_VSSR_13 AW14 TXOUT_L1N_DPE1N
GND_39 AF21 DP_VSSR_14 AW16 AP35
GND GND_40 DP_VSSR_15 TXOUT_L2P_DPE0P
AG17 AN19 AR35
F15 GND_41 AG2 DP_VSSR_16 AP18 TXOUT_L2N_DPE0N
C F17 GND_100 GND_42 AG20 DP_VSSR_17 AP19 AN36 C
F19 GND_101 GND_43 DP_VSSR_18 AW20 TXOUT_L3P AP37
F21 GND_102 AG6 CALIBRATION DP_VSSR_19 AW22 TXOUT_L3N
F23 GND_103 GND_45 AG9 DP_VSSR_20 AN34
F25 GND_104 GND_46 AH21 DP_VSSR_21 AP39
F27 GND_105 GND_47 AJ10 Test_Point_20MIL 1 DPAB AW28 DP_VSSR_22 AR39
F29 GND_106 GND_48 AJ11 TPV21 DPAB_CALR DP_VSSR_23 AU37
F31 GND_107 GND_49 AJ2 DP_VSSR_24 AF39 216-0855000_A0_FCBGA962
F33 GND_108 GND_50 AJ28 DP_VSSR_25 AH39
F7 GND_109 GND_51 AJ6 Test_Point_20MIL 1 DPCD AW18 DP_VSSR_26 AK39
F9 GND_110 GND_52 AK11 TPV22 DPCD_CALR DP_VSSR_27 AL34
G2 GND_111 GND_53 AK31 DP_VSSR_28 AV27
G6 GND_112 GND_54 AK7 DP_VSSR_29 AR28
H9 GND_113 GND_55 AL11 RV17 1 DIS@ 2 150_0402_1% AM39 DP_VSSR_30 AV17
J2 GND_114 GND_56 AL14 DPEF_CALR DP_VSSR_31 AR18
J27 GND_115 GND_57 AL17 DP_VSSR_32 AN38
J6 GND_116 GND_58 AL2 DP_VSSR_33 AM35
J8 GND_117 GND_59 AL20 DP_VSSR_34 AN32
K14 GND_118 GND_60 DP_VSSR_35
K7 GND_119 AL23
L11 GND_120 GND_61 AL26
L17 GND_121 GND_62 AL32
L2 GND_122 GND_63 AL6
L22 GND_123 GND_64 AL8
L24 GND_124 GND_65 AM11
L6 GND_125 GND_66 AM31 216-0855000_A0_FCBGA962
M17 GND_126 GND_67 AM9
M22 GND_127 GND_68 AN11
M24 GND_128 GND_69 AN2
N16 GND_129 GND_70 AN30
N18 GND_130 GND_71 AN6
N2 GND_131 GND_72 AN8
N21 GND_132 GND_73 AP11
N23 GND_133 GND_74 AP7
N26 GND_134 GND_75 AP9
B B
N6 GND_135 GND_76 AR5
R15 GND_136 GND_77 B11
R17 GND_137 GND_78 B13
R2 GND_138 GND_79 B15
R20 GND_139 GND_80 B17
R22 GND_140 GND_81 B19
R24 GND_141 GND_82 B21
R27 GND_142 GND_83 B23
R6 GND_143 GND_84 B25
T11 GND_144 GND_85 B27
T13 GND_145 GND_86 B29
T16 GND_146 GND_87 B31
T18 GND_147 GND_88 B33
T21 GND_148 GND_89 B7
T23 GND_149 GND_90 B9
T26 GND_150 GND_91 C1
U15 GND_151 GND_92 C39
U17 GND_153 GND_93 E35
U2 GND_154 GND_94 E5
U20 GND_155 GND_95 F11
U22 GND_156 GND_96 F13
U24 GND_157 GND_97
U27 GND_158
U6 GND_159
V11 GND_160 AG22
V16 GND_161 GND_44
V18 GND_163
V21 GND_164
V23 GND_165
V26 GND_166
W2 GND_167
W6 GND_168
Y15 GND_169
Y17 GND_170
A
Y20 GND_171 A
Y22 GND_172 A39
Y24 GND_173 VSS_MECH_1 AW1
Y27 GND_174 VSS_MECH_2 AW39
GND_175 VSS_MECH_3

216-0855000_A0_FCBGA962 Security Classification LC Future Center Secret Data Title

Issued Date 2014/07/01 Graphic

https://dr-bios.com
2012/07/01 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 30 of 99

5 4 3 2 1
 1 2 3 4 5

FBB_MAB0_[0..8] [34]
FBA_MAA0_[0..8] [32]
FBB_MAB1_[0..8] [35]
FBA_MAA1_[0..8] [33]
[34] FBB0_EDC[0..3]

[32] FBA0_EDC[3..0] [35] FBB1_EDC[0..3]

[33] FBA1_EDC[3..0]

A A
UV1H UV1I

PART 8 0F 9 PART 9 0F 9
[32] FBA_D[0..31] FBA_D0 GDDR5/DDR3 FBA_MAA0_0 [34] FBB_D[0..31] FBB_D0 GDDR5/DDR3 FBB_MAB0_0
C37 G24 C5 P8
FBA_D1 C35 DQA0_0 MAA0_0/MAA_0 J23 FBA_MAA0_1 FBB_D1 C3 DQB0_0 MAB0_0 T9 FBB_MAB0_1
FBA_D2 A35 DQA0_1 MAA0_1/MAA_1 H24 FBA_MAA0_2 FBB_D2 E3 DQB0_1 MAB0_1 P9 FBB_MAB0_2
FBA_D3 E34 DQA0_2 MAA0_2/MAA_2 J24 FBA_MAA0_3 FBB_D3 E1 DQB0_2 MAB0_2 N7 FBB_MAB0_3
FBA_D4 G32 DQA0_3 MAA0_3/MAA_3 H26 FBA_MAA0_4 FBB_D4 F1 DQB0_3 MAB0_3 N8 FBB_MAB0_4
FBA_D5 D33 DQA0_4 MAA0_4/MAA_4 J26 FBA_MAA0_5 FBB_D5 F3 DQB0_4 MAB0_4 N9 FBB_MAB0_5
FBA_D6 F32 DQA0_5 MAA0_5/MAA_5 H21 FBA_MAA0_6 FBB_D6 F5 DQB0_5 MAB0_5 U9 FBB_MAB0_6
FBA_D7 E32 DQA0_6 MAA0_6/MAA_6 G21 FBA_MAA0_7 FBB_D7 G4 DQB0_6 MAB0_6 U8 FBB_MAB0_7
FBA_D8 DQA0_7 MAA0_7/MAA_7 FBA_MAA1_0 FBB_D8 DQB0_7 MAB0_7 FBB_MAB1_0

MEMORY INTERFACE A
D31 H19 H5 Y9
FBA_D9 F30 DQA0_8 MAA1_0/MAA_8 H20 FBA_MAA1_1 FBB_D9 H6 DQB0_8 MAB1_0 W9 FBB_MAB1_1
FBA_D10 C30 DQA0_9 MAA1_1/MAA_9 L13 FBA_MAA1_2 FBB_D10 J4 DQB0_9 MAB1_1 AC8 FBB_MAB1_2
FBA_D11 A30 DQA0_10 MAA1_2/MAA_10 G16 FBA_MAA1_3 FBB_D11 K6 DQB0_10 MAB1_2 AC9 FBB_MAB1_3
FBA_D12 F28 DQA0_11 MAA1_3/MAA_11 J16 FBA_MAA1_4 FBB_D12 K5 DQB0_11 MAB1_3 AA7 FBB_MAB1_4
FBA_D13 C28 DQA0_12 MAA1_4/MAA_12 H16 FBA_MAA1_5 FBB_D13 L4 DQB0_12 MAB1_4 AA8 FBB_MAB1_5
FBA_D14 A28 DQA0_13 MAA1_5/MAA_0 J17 FBA_MAA1_6 FBB_D14 M6 DQB0_13 MAB1_5 Y8 FBB_MAB1_6
FBA_D15 E28 DQA0_14 MAA1_6/MAA_1 H17 FBA_MAA1_7 FBB_D15 M1 DQB0_14 MAB1_6 AA9 FBB_MAB1_7
FBA_D16 D27 DQA0_15 MAA1_7/MAA_2 FBB_D16 M3 DQB0_15 MAB1_7

MEMORY INTERFACE B
FBA_D17 F26 DQA0_16 A32 FBA_W CKA0_0 FBB_D17 M5 DQB0_16 H3 FBB_W CKB0_0
FBA_D18 DQA0_17 WCKA0_0/DQMA0_0 FBA_W CKA0B_0 FBA_WCKA0_0 [32] FBB_D18 DQB0_17 WCKB0_0 FBB_W CKB0B_0 FBB_WCKB0_0 [34]
C26 C32 N4 H1
FBA_D19 DQA0_18 WCKA0B_0/DQMA0_1 FBA_W CKA0_1 FBA_WCKA0B_0 [32] FBB_D19 DQB0_18 WCKB0B_0 FBB_W CKB0_1 FBB_WCKB0B_0 [34]
A26 D23 P6 T3
FBA_D20 DQA0_19 WCKA0_1/DQMA0_2 FBA_W CKA0B_1 FBA_WCKA0_1 [32] FBB_D20 DQB0_19 WCKB0_1 FBB_W CKB0B_1 FBB_WCKB0_1 [34]
F24 E22 P5 T5
FBA_D21 DQA0_20 WCKA0B_1/DQMA0_3 FBA_W CKA1_0 FBA_WCKA0B_1 [32] FBB_D21 DQB0_20 WCKB0B_1 FBB_W CKB1_0 FBB_WCKB0B_1 [34]
C24 C14 R4 AE4
+1.35VS_VGA FBA_D22 DQA0_21 WCKA1_0/DQMA1_0 FBA_W CKA1B_0 FBA_WCKA1_0 [33] +1.35VS_VGA FBB_D22 DQB0_21 WCKB1_0 FBB_W CKB1B_0 FBB_WCKB1_0 [35]
A24 A14 T6 AF5
FBA_D23 DQA0_22 WCKA1B_0/DQMA1_1 FBA_W CKA1_1 FBA_WCKA1B_0 [33] FBB_D23 DQB0_22 WCKB1B_0 FBB_W CKB1_1 FBB_WCKB1B_0 [35]
E24 E10 T1 AK6
FBA_D24 DQA0_23 WCKA1_1/DQMA1_2 FBA_W CKA1B_1 FBA_WCKA1_1 [33] FBB_D24 DQB0_23 WCKB1_1 FBB_W CKB1B_1 FBB_WCKB1_1 [35]
C22 D9 U4 AK5
FBA_D25 DQA0_24 WCKA1B_1/DQMA1_3 FBA_WCKA1B_1 [33] FBB_D25 DQB0_24 WCKB1B_1 FBB_WCKB1B_1 [35]
A22 V6
FBA_D26 F22 DQA0_25 C34 FBA0_EDC0 FBB_D26 V1 DQB0_25 F6 FBB0_EDC0
FBA_D27 DQA0_26 EDCA0_0/QSA0_0 FBA0_EDC1 FBB_D27 DQB0_26 EDCB0_0 FBB0_EDC1
1

1
DIS@ D21 D29 DIS@ V3 K3
RV18 FBA_D28 A20 DQA0_27 EDCA0_1/QSA0_1 D25 FBA0_EDC2 RV19 FBB_D28 Y6 DQB0_27 EDCB0_1 P3 FBB0_EDC2
B
40.2_0402_1% FBA_D29 F20 DQA0_28 EDCA0_2/QSA0_2 E20 FBA0_EDC3 40.2_0402_1% FBB_D29 Y1 DQB0_28 EDCB0_2 V5 FBB0_EDC3 B
FBA_D30 D19 DQA0_29 EDCA0_3/QSA0_3 E16 FBA1_EDC0 FBB_D30 Y3 DQB0_29 EDCB0_3 AB5 FBB1_EDC0
FBA_D31 E18 DQA0_30 EDCA1_0/QSA1_0 E12 FBA1_EDC1 FBB_D31 Y5 DQB0_30 EDCB1_0 AH1 FBB1_EDC1
[33] FBA1_D[0..31] DQA0_31 EDCA1_1/QSA1_1 [35] FBB1_D[0..31] DQB0_31 EDCB1_1
2

2
FBA1_D0 C18 J10 FBA1_EDC2 FBB1_D0 AA4 AJ9 FBB1_EDC2
CV73 FBA1_D1 A18 DQA1_0 EDCA1_2/QSA1_2 D7 FBA1_EDC3 CV74 FBB1_D1 AB6 DQB1_0 EDCB1_2 AM5 FBB1_EDC3
FBA1_D2 F18 DQA1_1 EDCA1_3/QSA1_3 FBB1_D2 AB1 DQB1_1 EDCB1_3
FBA1_D3 D17 DQA1_2 A34 FBA0_DBI0# FBB1_D3 AB3 DQB1_2 G7 FBB0_DBI0#
FBA1_D4 DQA1_3 DDBIA0_0/QSA0_0B FBA0_DBI1# FBA0_DBI0# [32] FBB1_D4 DQB1_3 DDBIB0_0 FBB0_DBI1# FBB0_DBI0# [34]
1

1
DIS@ DIS@ A16 E30 DIS@ DIS@ AD6 K1
1U_0402_10V6-K

1U_0402_10V6-K
1 FBA1_D5 DQA1_4 DDBIA0_1/QSA0_1B FBA0_DBI2# FBA0_DBI1# [32] 1 FBB1_D5 DQB1_4 DDBIB0_1 FBB0_DBI2# FBB0_DBI1# [34]
RV20 F16 E26 RV21 AD1 P1
FBA1_D6 DQA1_5 DDBIA0_2/QSA0_2B FBA0_DBI3# FBA0_DBI2# [32] FBB1_D6 DQB1_5 DDBIB0_2 FBB0_DBI3# FBB0_DBI2# [34]
100_0402_5% D15 C20 100_0402_5% AD3 W4
FBA1_D7 DQA1_6 DDBIA0_3/QSA0_3B FBA1_DBI0# FBA0_DBI3# [32] FBB1_D7 DQB1_6 DDBIB0_3 FBB1_DBI0# FBB0_DBI3# [34]
E14 C16 AD5 AC4
2 FBA1_D8 DQA1_7 DDBIA1_0/QSA1_0B FBA1_DBI1# FBA1_DBI0# [33] 2 FBB1_D8 DQB1_7 DDBIB1_0 FBB1_DBI1# FBB1_DBI0# [35]
F14 C12 AF1 AH3
DQA1_8 DDBIA1_1/QSA1_1B FBA1_DBI1# [33] DQB1_8 DDBIB1_1 FBB1_DBI1# [35]
2

2
FBA1_D9 D13 J11 FBA1_DBI2# FBB1_D9 AF3 AJ8 FBB1_DBI2#
FBA1_D10 DQA1_9 DDBIA1_2/QSA1_2B FBA1_DBI3# FBA1_DBI2# [33] FBB1_D10 DQB1_9 DDBIB1_2 FBB1_DBI3# FBB1_DBI2# [35]
F12 F8 AF6 AM3
FBA1_D11 DQA1_10 DDBIA1_3/QSA1_3B FBA1_DBI3# [33] FBB1_D11 DQB1_10 DDBIB1_3 FBB1_DBI3# [35]
A12 AG4
FBA1_D12 D11 DQA1_11 J21 FBA_ADBIA0 FBB1_D12 AH5 DQB1_11 T7 FBB_ADBIB0
FBA1_D13 DQA1_12 ADBIA0/ODTA0 FBA_ADBIA1 FBA_ADBIA0 [32] FBB1_D13 DQB1_12 ADBIB0 FBB_ADBIB1 FBB_ADBIB0 [34]
F10 G19 AH6 W7
FBA1_D14 DQA1_13 ADBIA1/ODTA1 FBA_ADBIA1 [33] FBB1_D14 DQB1_13 ADBIB1 FBB_ADBIB1 [35]
A10 AJ4
+1.35VS_VGA FBA1_D15 C10 DQA1_14 H27 FBA_CLKA0 +1.35VS_VGA FBB1_D15 AK3 DQB1_14 L9 FBB_CLKB0
FBA1_D16 DQA1_15 CLKA0 FBA_CLKA0# FBA_CLKA0 [32] FBB1_D16 DQB1_15 CLKB0 FBB_CLKB0# FBB_CLKB0 [34]
G13 G27 AF8 L8
FBA1_D17 DQA1_16 CLKA0B FBA_CLKA0# [32] FBB1_D17 DQB1_16 CLKB0B FBB_CLKB0# [34]
H13 AF9
FBA1_D18 J13 DQA1_17 J14 FBA_CLKA1 FBB1_D18 AG8 DQB1_17 AD8 FBB_CLKB1
FBA1_D19 DQA1_18 CLKA1 FBA_CLKA1# FBA_CLKA1 [33] FBB1_D19 DQB1_18 CLKB1 FBB_CLKB1# FBB_CLKB1 [35]
H11 H14 AG7 AD7
FBA1_D20 DQA1_19 CLKA1B FBA_CLKA1# [33] FBB1_D20 DQB1_19 CLKB1B FBB_CLKB1# [35]
1

1
DIS@ G10 DIS@ AK9
RV22 FBA1_D21 G8 DQA1_20 K23 FBA_RASA0# RV23 FBB1_D21 AL7 DQB1_20 T10 FBB_RASB0#
FBA1_D22 DQA1_21 RASA0B FBA_RASA1# FBA_RASA0# [32] FBB1_D22 DQB1_21 RASB0B FBB_RASB1# FBB_RASB0# [34]
40.2_0402_1% K9 K19 40.2_0402_1% AM8 Y10
FBA1_D23 DQA1_22 RASA1B FBA_RASA1# [33] FBB1_D23 DQB1_22 RASB1B FBB_RASB1# [35]
K10 AM7
FBA1_D24 G9 DQA1_23 K20 FBA_CASA0# FBB1_D24 AK1 DQB1_23 W10 FBB_CASB0#
DQA1_24 CASA0B FBA_CASA0# [32] DQB1_24 CASB0B FBB_CASB0# [34]
2

2
FBA1_D25 A8 K17 FBA_CASA1# FBB1_D25 AL4 AA10 FBB_CASB1#
FBA1_D26 DQA1_25 CASA1B FBA_CASA1# [33] FBB1_D26 DQB1_25 CASB1B FBB_CASB1# [35]
CV75 C8 CV76 AM6
FBA1_D27 E8 DQA1_26 K24 FBA_CSA0# FBB1_D27 AM1 DQB1_26 P10 FBB_CSB0#
FBA1_D28 DQA1_27 CSA0B_0 FBA_CSA0# [32] FBB1_D28 DQB1_27 CSB0B_0 FBB_CSB0# [34]
A6 K27 AN4 L10
FBA1_D29 DQA1_28 CSA0B_1 FBB1_D29 DQB1_28 CSB0B_1
1

1
DIS@ DIS@ C6 DIS@ DIS@ AP3
1U_0402_10V6-K

1U_0402_10V6-K
1 FBA1_D30 DQA1_29 FBA_CSA1# 1 FBB1_D30 DQB1_29 FBB_CSB1#
RV24 E6 M13 RV25 AP1 AD10
FBA1_D31 DQA1_30 CSA1B_0 FBA_CSA1# [33] FBB1_D31 DQB1_30 CSB1B_0 FBB_CSB1# [35]
C 100_0402_5% A5 K16 100_0402_5% AP5 AC10 C
DQA1_31 CSA1B_1 DQB1_31 CSB1B_1
2 MVREFDA L18 K21 FBA_CKEA0 2 U10 FBB_CKEB0
MVREFDA CKEA0 FBA_CKEA0 [32] CKEB0 FBB_CKEB0 [34]
2

2
MVREFSA L20 J20 FBA_CKEA1 MVREFDB Y12 AA11 FBB_CKEB1
MVREFSA CKEA1 FBA_CKEA1 [33] MVREFDB CKEB1 FBB_CKEB1 [35]
MVREFSB AA12
L27 K26 FBA_WEA0# MVREFSB N10 FBB_WEB0#
NC_MEM_CALRN0 WEA0B FBA_WEA1# FBA_WEA0# [32] WEB0B FBB_WEB1# FBB_WEB0# [34]
N12 L15 AB11
NC_MEM_CALRN1 WEA1B FBA_WEA1# [33] WEB1B FBB_WEB1# [35]
AG12
NC_MEM_CALRN2
H23 FBA_MAA0_8 T8 FBB_MAB0_8
1 DIS@ 2 M27 MAA0_8/MAA_13 J19 FBA_MAA1_8 MAB0_8 W8 FBB_MAB1_8
MEM_CALRP0 MAA1_8/MAA_14 M21 MAB1_8 U12
RV26 M12 MAA0_9/MAA_15 M20 MAB0_9 V12
243_0402_1% AH12 NC_MEM_CALRP1 MAA1_9/NC MAB1_9
NC_MEM_CALRP2 AH11 DRAM_RST
DRAM_RST

216-0855000_A0_FCBGA962
216-0855000_A0_FCBGA962

RV27 RV28
FBA_RST# 1 DIS@ 2 1 DIS@ 2 DRAM_RST
[32,33,34,35] FBA_RST#
49.9_0402_1% 10_0402_5%

1
1 1
CV77 RV29 CV78
120P_0402_50V8-J 5.1K_0402_5% 68P_0402_50V8-J
DIS@ DIS@ @
2 2

2
D D

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 GDDR5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 31 of 99

1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits

FBA_MAA0_[0..8] [31]

FBA0_EDC[3..0] [31]

UV6

MF=0 MF=1 MF=1 MF=0

A A
FBA_D5 FBA_D[0..31] [31]
A4
FBA0_EDC0 C2 DQ24 DQ0 A2 FBA_D2
FBA0_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA_D7
FBA0_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA_D1
FBA0_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA_D4 +1.35VS_VGA +1.35VS_VGA
EDC3 EDC0 DQ28 DQ4 E2 FBA_D3
DQ29 DQ5 F4 FBA_D6
FBA0_DBI0# DQ30 DQ6 FBA_D0

1
D2 F2
[31] FBA0_DBI0# FBA0_DBI1# DBI0# DBI3# DQ31 DQ7 FBA_D10
D13 A11 RV30 RV31
[31] FBA0_DBI1# FBA0_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_D8 2.1K_0402_1% 2.1K_0402_1%
P13 A13
[31] FBA0_DBI2# FBA0_DBI3# DBI2# DBI1# DQ17 DQ9 FBA_D9
P2 B11 Litho@ Litho@
[31] FBA0_DBI3# DBI3# DBI0# DQ18 DQ10 FBA_D11
B13
DQ19 DQ11

2
FBA_CLKA0 J12 E11 FBA_D14 CV79 +FBA_VREFC0 CV80 +FBA_VREFD0
[31] FBA_CLKA0 FBA_CLKA0# CK DQ20 DQ12 FBA_D12
J11 E13
[31] FBA_CLKA0# FBA_CKEA0 CK# DQ21 DQ13 FBA_D13
J3 F11

0.1U_0402_10V7-K

0.1U_0402_10V7-K
[31] FBA_CKEA0 CKE# DQ22 DQ14 FBA_D15

1
F13 1 1
DQ23 DQ15 U11 FBA_D23 RV32 DIS@ RV33 DIS@
FBA_MAA0_2 H11 DQ8 DQ16 U13 FBA_D21 4.99K_0402_1% 4.99K_0402_1%
FBA_MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBA_D20 Litho@ Litho@
FBA_MAA0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA_D22 2 2
BA2/A4 BA0/A2 DQ11 DQ19

2
FBA_MAA0_3 H10 N11 FBA_D19
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA_D17
DQ13 DQ21 M11 FBA_D18
FBA_MAA0_7 K4 DQ14 DQ22 M13 FBA_D16
FBA_MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA_D25
FBA_MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA_D27
FBA_MAA0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA_D26
FBA_MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA_D24
A12/RFU/NC DQ3 DQ27 N4 FBA_D28
2 Litho@ 1 A5 DQ4 DQ28 N2 FBA_D29
RV195 1K_0402_1% U5 VPP/NC1 DQ5 DQ29 M4 FBA_D30
VPP/NC2 DQ6 DQ30 M2 FBA_D31
2 Litho@ 1 DQ7 DQ31
RV197 1K_0402_1% J1 +1.35VS_VGA
B J10 MF B
2 Litho@ 1 J13 SEN B1
RV194 121_0402_1% ZQ VDDQ1 D1
VDDQ2
PASS F1
FBA_ADBIA0 J4 VDDQ3 M1
[31] FBA_ADBIA0 FBA_RASA0# ABI# VDDQ4
G3 P1
[31] FBA_RASA0# FBA_CSA0# RAS# CAS# VDDQ5 FBA_CLKA0
G12 T1
[31] FBA_CSA0# FBA_CASA0# CS# WE# VDDQ6
L3 G2
[31] FBA_CASA0# FBA_W EA0# CAS# RAS# VDDQ7
L12 L2
[31] FBA_WEA0# WE# CS# VDDQ8 B3
VDDQ9

1
D3
VDDQ10 F3 RV41 +1.35VS_VGA
FBA_W CKA0B_0 D5 VDDQ11 H3 DIS@ 60.4_0402_1%
[31] FBA_WCKA0B_0 FBA_W CKA0_0 WCK01# WCK23# VDDQ12
D4 K3
[31] FBA_WCKA0_0 WCK01 WCK23 VDDQ13 M3
VDDQ14

2
FBA_W CKA0B_1 P5 P3
[31] FBA_WCKA0B_1 FBA_W CKA0_1 WCK23# WCK01# VDDQ15
P4 T3
[31] FBA_WCKA0_1 WCK23 WCK01 VDDQ16 E5
VDDQ17

1
N5
+FBA_VREFD0 A10 VDDQ18 E10 RV42
U10 VREFD1 VDDQ19 N10 DIS@ 60.4_0402_1%
+FBA_VREFC0 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
VDDQ22

2
F12
VDDQ23 H12 FBA_CLKA0#
FBA_RST# J2 VDDQ24 K12
PASS[31,33,34,35] FBA_RST# RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14
L5 VSS4 VDDQ33 M14
C C
T5 VSS5 VDDQ34 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36
VSS8
G10
VSS9
+1.35VS_VGA UV6 SIDE
L10 A1
P10 VSS10 VSSQ1 C1 CV83 CV84 CV85 CV86 CV87 CV88
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1

10U_0603_6.3V6-M
K14 VSS13 VSSQ4 R1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VSS14 VSSQ5 1 1 1 1 1 1
+1.35VS_VGA U1
VSSQ6 H2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
G1 VSSQ7 K2
L1 VDD1 VSSQ8 A3 2 2 2 2 2 2
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3
VDD7 VSSQ14
R10
VDD8 VSSQ15
C4 +1.35VS_VGA UV6 SIDE
D11 R4
G11 VDD9 VSSQ16 F5 CV96 CV97 CV98 CV99 CV100
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
G14 VDD12 VSSQ19 M10
VDD13 VSSQ20 1 1 1 1 1
L14 C11
VDD14 VSSQ21 R11 DIS@ DIS@ DIS@ DIS@ DIS@
VSSQ22 A12
VSSQ23 C12 2 2 2 2 2
VSSQ24 E12
VSSQ25 N12
VSSQ26 R12
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
D VSSQ30 A14 D
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
X76@ H5GC2H24BFR-T2C_BGA170
H5GC2H24BFR-T2C Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 GDDR5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 32 of 99

1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Upper 32 bits FBA_MAA1_[0..8]

FBA1_EDC[3..0]
[31]

[31]

UV5

MF=0 MF=1 MF=1 MF=0

FBA1_D4 FBA1_D[0..31] [31]

A A4 A
FBA1_EDC0 C2 DQ24 DQ0 A2 FBA1_D0
FBA1_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBA1_D7
FBA1_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBA1_D1
FBA1_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBA1_D5
EDC3 EDC0 DQ28 DQ4 E2 FBA1_D2
DQ29 DQ5 F4 FBA1_D6
FBA1_DBI0# D2 DQ30 DQ6 F2 FBA1_D3 +1.35VS_VGA +1.35VS_VGA
[31] FBA1_DBI0# FBA1_DBI1# DBI0# DBI3# DQ31 DQ7 FBA1_D8
D13 A11
[31] FBA1_DBI1# FBA1_DBI2# DBI1# DBI2# DQ16 DQ8 FBA1_D9
P13 A13
[31] FBA1_DBI2# FBA1_DBI3# DBI2# DBI1# DQ17 DQ9 FBA1_D10

1
P2 B11
[31] FBA1_DBI3# DBI3# DBI0# DQ18 DQ10 FBA1_D11
B13 RV43 RV44
FBA_CLKA1 J12 DQ19 DQ11 E11 FBA1_D15 2.1K_0402_1% 2.1K_0402_1%
[31] FBA_CLKA1 FBA_CLKA1# CK DQ20 DQ12 FBA1_D12
J11 E13 Litho@ Litho@
[31] FBA_CLKA1# FBA_CKEA1 CK# DQ21 DQ13 FBA1_D13
J3 F11
[31] FBA_CKEA1 CKE# DQ22 DQ14

2
F13 FBA1_D14 CV106 +FBA_VREFC1 CV107 +FBA_VREFD1
DQ23 DQ15 U11 FBA1_D23
FBA_MAA1_4 H11 DQ8 DQ16 U13 FBA1_D20

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBA_MAA1_3 BA0/A2 BA2/A4 DQ9 DQ17 FBA1_D22

1
K10 T11 1 1
FBA_MAA1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBA1_D21 RV45 RV46
FBA_MAA1_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 FBA1_D19 4.99K_0402_1% DIS@ 4.99K_0402_1% DIS@
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBA1_D17 Litho@ Litho@
DQ13 DQ21 M11 FBA1_D18 2 2
DQ14 DQ22

2
FBA_MAA1_0 K4 M13 FBA1_D16
FBA_MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBA1_D25
FBA_MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBA1_D27
+1.35VS_VGA FBA_MAA1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBA1_D24
FBA_MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBA1_D26
A12/RFU/NC DQ3 DQ27 N4 FBA1_D28
2 Litho@ 1 A5 DQ4 DQ28 N2 FBA1_D29
RV199 1K_0402_1% U5 VPP/NC1 DQ5 DQ29 M4 FBA1_D30
VPP/NC2 DQ6 DQ30 M2 FBA1_D31
2 Litho@ 1 DQ7 DQ31
RV200 1K_0402_1% J1 +1.35VS_VGA
J10 MF
B 2 Litho@ 1 J13 SEN B1 FBA_CLKA1 B
RV198 121_0402_1% ZQ VDDQ1 D1
VDDQ2
PASS F1
FBA_ADBIA1 VDDQ3

1
J4 M1
[31] FBA_ADBIA1 FBA_CASA1# ABI# VDDQ4
G3 P1 RV53
[31] FBA_CASA1# FBA_WEA1# RAS# CAS# VDDQ5 +1.35VS_VGA
G12 T1 DIS@ 60.4_0402_1%
[31] FBA_WEA1# FBA_RASA1# CS# WE# VDDQ6
L3 G2
[31] FBA_RASA1# FBA_CSA1# CAS# RAS# VDDQ7
L12 L2
[31] FBA_CSA1# WE# CS# VDDQ8

2
B3
VDDQ9 D3
VDDQ10 F3
FBA_WCKA1B_0 D5 VDDQ11 H3
[31] FBA_WCKA1B_0 FBA_WCKA1_0 WCK01# WCK23# VDDQ12

1
D4 K3
[31] FBA_WCKA1_0 WCK01 WCK23 VDDQ13 M3 RV54
FBA_WCKA1B_1 P5 VDDQ14 P3 DIS@ 60.4_0402_1%
[31] FBA_WCKA1B_1 FBA_WCKA1_1 WCK23# WCK01# VDDQ15
P4 T3
[31] FBA_WCKA1_1 WCK23 WCK01 VDDQ16 E5
VDDQ17

2
N5
+FBA_VREFD1 A10 VDDQ18 E10 FBA_CLKA1#
U10 VREFD1 VDDQ19 N10
+FBA_VREFC1 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12
VDDQ22 F12
VDDQ23 H12
FBA_RST# VDDQ24
PASS[31,32,34,35] FBA_RST#
J2 K12
RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28
VDDQ29
G13 +1.35VS_VGA UV5 SIDE
H1 L13
VSS1 VDDQ30
K1
VSS2 VDDQ31
B14 CV111 CV112 CV113 CV114 CV115 CV116 +1.35VS_VGA UV5 SIDE
B5 D14
G5 VSS3 VDDQ32 F14 CV117 CV118 CV119 CV120 CV121 CV122

10U_0603_6.3V6-M
L5 VSS4 VDDQ33 M14

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VSS5 VDDQ34 1 1 1 1 1 1
T5 P14

10U_0603_6.3V6-M
C C
B10 VSS6 VDDQ35 T14 DIS@

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
DIS@ DIS@ DIS@ DIS@ DIS@ 1 1 1 1 1 1
D10 VSS7 VDDQ36
G10 VSS8 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
L10 VSS9 A1
P10 VSS10 VSSQ1 C1 2 2 2 2 2 2
T10 VSS11 VSSQ2 E1
H14 VSS12 VSSQ3 N1
VSS13 VSSQ4
+1.35VS_VGA
K14
VSS14 VSSQ5
R1 +1.35VS_VGA UV5 SIDE
U1
VSSQ6
VSSQ7
H2 CV123 CV124 CV125 CV126 CV127 +1.35VS_VGA UV5 SIDE
G1 K2
L1 VDD1 VSSQ8 A3 CV128 CV129 CV130 CV131 CV132

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
G4 VDD2 VSSQ9 C3
VDD3 VSSQ10 1 1 1 1 1
L4 E3

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
C5 VDD4 VSSQ11 N3 DIS@ DIS@ DIS@ DIS@ DIS@
VDD5 VSSQ12 1 1 1 1 1
R5 R3
C10 VDD6 VSSQ13 U3 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@
R10 VDD7 VSSQ14 C4
D11 VDD8 VSSQ15 R4 2 2 2 2 2
G11 VDD9 VSSQ16 F5
L11 VDD10 VSSQ17 M5
P11 VDD11 VSSQ18 F10
G14 VDD12 VSSQ19 M10
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11
VSSQ22 A12
VSSQ23 C12
VSSQ24 E12
VSSQ25 N12
VSSQ26 R12
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
D VSSQ31 C14 D
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
X76@ H5GC2H24BFR-T2C_BGA170
H5GC2H24BFR-T2C
Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 GDDR5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 33 of 99

1 2 3 4 5
 1 2 3 4 5

Memory Partition A - Lower 32 bits

UV7

MF=0 MF=1 MF=1 MF=0

FBB_MAB0_[0..8] [31]
A A
FBB_D4 FBB_D[0..31] [31]
A4
FBB0_EDC0 DQ24 DQ0 FBB_D3 FBB0_EDC[3..0] [31]
C2 A2
FBB0_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB_D5
FBB0_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB_D2
FBB0_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBB_D6
EDC3 EDC0 DQ28 DQ4 E2 FBB_D1
DQ29 DQ5 F4 FBB_D7
FBB0_DBI0# D2 DQ30 DQ6 F2 FBB_D0
[31] FBB0_DBI0# FBB0_DBI1# DBI0# DBI3# DQ31 DQ7 FBB_D8
D13 A11
[31] FBB0_DBI1# FBB0_DBI2# DBI1# DBI2# DQ16 DQ8 FBB_D9
P13 A13
[31] FBB0_DBI2# FBB0_DBI3# DBI2# DBI1# DQ17 DQ9 FBB_D10
P2 B11
[31] FBB0_DBI3# DBI3# DBI0# DQ18 DQ10 FBB_D11
B13
FBB_CLKB0 J12 DQ19 DQ11 E11 FBB_D14 +1.35VS_VGA +1.35VS_VGA
[31] FBB_CLKB0 FBB_CLKB0# CK DQ20 DQ12 FBB_D12
J11 E13
[31] FBB_CLKB0# FBB_CKEB0 CK# DQ21 DQ13 FBB_D15
J3 F11
[31] FBB_CKEB0 CKE# DQ22 DQ14 FBB_D13

1
F13
DQ23 DQ15 U11 FBB_D22 RV55 RV56
FBB_MAB0_2 H11 DQ8 DQ16 U13 FBB_D20 2.1K_0402_1% 2.1K_0402_1%
FBB_MAB0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBB_D23 Litho@ Litho@
FBB_MAB0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBB_D21
BA2/A4 BA0/A2 DQ11 DQ19

2
FBB_MAB0_3 H10 N11 FBB_D19 CV133 +FBB_VREFC0 CV134 +FBB_VREFD0
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBB_D17
DQ13 DQ21 M11 FBB_D16

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBB_MAB0_7 DQ14 DQ22 FBB_D18

1
K4 M13 1 1
FBB_MAB0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBB_D27 RV57 RV58
FBB_MAB0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 FBB_D28 4.99K_0402_1% DIS@ 4.99K_0402_1% DIS@
FBB_MAB0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBB_D26 Litho@ Litho@
FBB_MAB0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBB_D30 2 2
A12/RFU/NC DQ3 DQ27

2
N4 FBB_D25
2 Litho@ 1 A5 DQ4 DQ28 N2 FBB_D29
RV202 1K_0402_1% U5 VPP/NC1 DQ5 DQ29 M4 FBB_D24
VPP/NC2 DQ6 DQ30 M2 FBB_D31
2 Litho@ 1 DQ7 DQ31
RV203 1K_0402_1% J1 +1.35VS_VGA
B J10 MF B
2 Litho@ 1 J13 SEN B1
RV201 121_0402_1% ZQ VDDQ1 D1
VDDQ2
PASS F1
FBB_ADBIB0 J4 VDDQ3 M1
[31] FBB_ADBIB0 FBB_RASB0# ABI# VDDQ4
G3 P1
[31] FBB_RASB0# FBB_CSB0# RAS# CAS# VDDQ5
G12 T1
[31] FBB_CSB0# FBB_CASB0# CS# W E# VDDQ6
L3 G2
[31] FBB_CASB0# FBB_W EB0# CAS# RAS# VDDQ7
L12 L2
[31] FBB_WEB0# W E# CS# VDDQ8 FBB_CLKB0
B3
VDDQ9 D3 2015-0120-S
VDDQ10 F3
FBB_W CKB0B_0 VDDQ11

1
D5 H3
[31] FBB_WCKB0B_0 FBB_W CKB0_0 W CK01# WCK23# VDDQ12
D4 K3 RV66
[31] FBB_WCKB0_0 W CK01 WCK23 VDDQ13 +1.35VS_VGA
M3 DIS@ 60.4_0402_1%
FBB_W CKB0B_1 P5 VDDQ14 P3
[31] FBB_WCKB0B_1 FBB_W CKB0_1 W CK23# WCK01# VDDQ15
P4 T3
[31] FBB_WCKB0_1 W CK23 WCK01 VDDQ16

2
E5
VDDQ17 N5
+FBB_VREFD0 A10 VDDQ18 E10
U10 VREFD1 VDDQ19 N10
+FBB_VREFC0 VREFD2 VDDQ20

1
J14 B12
VREFC VDDQ21 D12 RV67
VDDQ22 F12 DIS@ 60.4_0402_1% 2015-0120-S
VDDQ23 H12
FBA_RST# J2 VDDQ24 K12
PASS[31,32,33,35] FBA_RST# RESET# VDDQ25

2
M12
VDDQ26 P12 FBB_CLKB0#
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14
L5 VSS4 VDDQ33 M14
C C
T5 VSS5 VDDQ34 P14
B10 VSS6 VDDQ35 T14
D10 VSS7 VDDQ36
G10 VSS8
VSS9
L10
VSS10 VSSQ1
A1 +1.35VS_VGA UV7 SIDE
P10 C1
T10 VSS11 VSSQ2 E1 CV137 CV138 CV139 CV140 CV141 CV142
H14 VSS12 VSSQ3 N1
K14 VSS13 VSSQ4 R1

10U_0603_6.3V6-M
+1.35VS_VGA VSS14 VSSQ5 U1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VSSQ6 1 1 1 1 1 1
H2
G1 VSSQ7 K2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3 2 2 2 2 2 2
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
R5 VDD5 VSSQ12 R3
C10 VDD6 VSSQ13 U3
R10 VDD7 VSSQ14 C4
VDD8 VSSQ15
D11
VDD9 VSSQ16
R4 +1.35VS_VGA UV7 SIDE
G11 F5
L11 VDD10 VSSQ17 M5 CV150 CV151 CV152 CV153 CV154
P11 VDD11 VSSQ18 F10
G14 VDD12 VSSQ19 M10

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 1 1 1 1 1
R11
VSSQ22 A12 DIS@ DIS@ DIS@ DIS@ DIS@
VSSQ23 C12
VSSQ24 E12 2 2 2 2 2
VSSQ25 N12
VSSQ26 R12
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
D VSSQ30 A14 D
VSSQ31 C14
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
X76@ H5GC2H24BFR-T2C_BGA170
H5GC2H24BFR-T2C Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/07/01 Deciphered Date 2014/07/01 GDDR5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 34 of 99

1 2 3 4 5
 5 4 3 2 1

Memory Partition A - Upper 32 bits

FBB_MAB1_[0..8] [31]

FBB1_EDC[3..0] [31]
UV8

MF=0 MF=1 MF=1 MF=0

FBB1_D7 FBB1_D[0..31] [31]

D A4 D
FBB1_EDC0 C2 DQ24 DQ0 A2 FBB1_D2
FBB1_EDC1 C13 EDC0 EDC3 DQ25 DQ1 B4 FBB1_D6
FBB1_EDC2 R13 EDC1 EDC2 DQ26 DQ2 B2 FBB1_D0
FBB1_EDC3 R2 EDC2 EDC1 DQ27 DQ3 E4 FBB1_D5
EDC3 EDC0 DQ28 DQ4 E2 FBB1_D3
DQ29 DQ5 F4 FBB1_D4
FBB1_DBI0# D2 DQ30 DQ6 F2 FBB1_D1
[31] FBB1_DBI0# FBB1_DBI1# DBI0# DBI3# DQ31 DQ7 FBB1_D10
D13 A11
[31] FBB1_DBI1# FBB1_DBI2# DBI1# DBI2# DQ16 DQ8 FBB1_D8 +1.35VS_VGA +1.35VS_VGA
P13 A13
[31] FBB1_DBI2# FBB1_DBI3# DBI2# DBI1# DQ17 DQ9 FBB1_D9
P2 B11
[31] FBB1_DBI3# DBI3# DBI0# DQ18 DQ10 FBB1_D11
B13
FBB_CLKB1 DQ19 DQ11 FBB1_D14

1
J12 E11
[31] FBB_CLKB1 FBB_CLKB1# CK DQ20 DQ12 FBB1_D12
J11 E13 RV68 RV69
[31] FBB_CLKB1# FBB_CKEB1 CK# DQ21 DQ13 FBB1_D13 2.1K_0402_1% 2.1K_0402_1%
J3 F11
[31] FBB_CKEB1 CKE# DQ22 DQ14 FBB1_D15
F13 Litho@ Litho@
DQ23 DQ15 U11 FBB1_D22
DQ8 DQ16

2
FBB_MAB1_4 H11 U13 FBB1_D21 CV160 +FBB_VREFC1 CV161 +FBB_VREFD1
FBB_MAB1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 FBB1_D20
FBB_MAB1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 FBB1_D23

0.1U_0402_10V7-K

0.1U_0402_10V7-K
FBB_MAB1_5 BA2/A4 BA0/A2 DQ11 DQ19 FBB1_D19

1
H10 N11 1 1
BA3/A3 BA1/A5 DQ12 DQ20 N13 FBB1_D17 RV70 RV71
DQ13 DQ21 M11 FBB1_D18 4.99K_0402_1% DIS@ 4.99K_0402_1% DIS@
FBB_MAB1_0 K4 DQ14 DQ22 M13 FBB1_D16 Litho@ Litho@
FBB_MAB1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 FBB1_D26 2 2
A9/A1 A11/A6 DQ0 DQ24

2
FBB_MAB1_7 H4 U2 FBB1_D28
+1.35VS_VGA FBB_MAB1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 FBB1_D27
FBB_MAB1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 FBB1_D30
A12/RFU/NC DQ3 DQ27 N4 FBB1_D25
2 Litho@ 1 A5 DQ4 DQ28 N2 FBB1_D29
RV206 1K_0402_1% U5 VPP/NC1 DQ5 DQ29 M4 FBB1_D24
VPP/NC2 DQ6 DQ30 M2 FBB1_D31
2 Litho@ 1 DQ7 DQ31
RV205 1K_0402_1% J1 +1.35VS_VGA
J10 MF
C 2 Litho@ 1 J13 SEN B1 C
RV204 121_0402_1% ZQ VDDQ1 D1
VDDQ2
PASS F1
FBB_ADBIB1 J4 VDDQ3 M1
[31] FBB_ADBIB1 FBB_CASB1# ABI# VDDQ4
G3 P1
[31] FBB_CASB1# FBB_W EB1# RAS# CAS# VDDQ5 FBB_CLKB1
G12 T1
[31] FBB_WEB1# FBB_RASB1# CS# W E# VDDQ6
L3 G2
[31] FBB_RASB1# FBB_CSB1# CAS# RAS# VDDQ7
L12 L2 2015-0120-S
[31] FBB_CSB1# W E# CS# VDDQ8

1
B3
VDDQ9 D3 RV78
VDDQ10 F3 DIS@ 60.4_0402_1% +1.35VS_VGA
FBB_W CKB1B_0 D5 VDDQ11 H3
[31] FBB_WCKB1B_0 FBB_W CKB1_0 W CK01# WCK23# VDDQ12
D4 K3
[31] FBB_WCKB1_0 W CK01 W CK23 VDDQ13

2
M3
FBB_W CKB1B_1 P5 VDDQ14 P3
[31] FBB_WCKB1B_1 FBB_W CKB1_1 W CK23# WCK01# VDDQ15
P4 T3
[31] FBB_WCKB1_1 W CK23 W CK01 VDDQ16 E5
VDDQ17

1
N5
+FBB_VREFD1 A10 VDDQ18 E10 RV79
U10 VREFD1 VDDQ19 N10 DIS@ 60.4_0402_1%
+FBB_VREFC1 J14 VREFD2 VDDQ20 B12
VREFC VDDQ21 D12 2015-0120-S
VDDQ22

2
F12
VDDQ23 H12 FBB_CLKB1#
FBA_RST# VDDQ24
PASS[31,32,33,34] FBA_RST#
J2 K12
RESET# VDDQ25 M12
VDDQ26 P12
VDDQ27 T12
VDDQ28 G13
H1 VDDQ29 L13
K1 VSS1 VDDQ30 B14
B5 VSS2 VDDQ31 D14
G5 VSS3 VDDQ32 F14
L5 VSS4 VDDQ33 M14
T5 VSS5 VDDQ34 P14
B B
B10 VSS6 VDDQ35 T14
VSS7 VDDQ36
D10
VSS8
+1.35VS_VGA UV8 SIDE
G10
L10 VSS9 A1 CV165 CV166 CV167 CV168 CV169 CV170
P10 VSS10 VSSQ1 C1
T10 VSS11 VSSQ2 E1

10U_0603_6.3V6-M
H14 VSS12 VSSQ3 N1

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K

1U_0402_10V6-K
VSS13 VSSQ4 1 1 1 1 1 1
K14 R1
+1.35VS_VGA VSS14 VSSQ5 U1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
VSSQ6 H2
G1 VSSQ7 K2 2 2 2 2 2 2
L1 VDD1 VSSQ8 A3
G4 VDD2 VSSQ9 C3
L4 VDD3 VSSQ10 E3
C5 VDD4 VSSQ11 N3
VDD5 VSSQ12
R5
VDD6 VSSQ13
R3 +1.35VS_VGA UV8 SIDE
C10 U3
R10 VDD7 VSSQ14 C4 CV177 CV178 CV179 CV180 CV181
D11 VDD8 VSSQ15 R4
G11 VDD9 VSSQ16 F5

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K
L11 VDD10 VSSQ17 M5
VDD11 VSSQ18 1 1 1 1 1
P11 F10
G14 VDD12 VSSQ19 M10 DIS@ DIS@ DIS@ DIS@ DIS@
L14 VDD13 VSSQ20 C11
VDD14 VSSQ21 R11 2 2 2 2 2
VSSQ22 A12
VSSQ23 C12
VSSQ24 E12
VSSQ25 N12
VSSQ26 R12
170-BALL VSSQ27 U12
VSSQ28 H13
SGRAM GDDR5 VSSQ29 K13
VSSQ30 A14
A VSSQ31 C14 A
VSSQ32 E14
VSSQ33 N14
VSSQ34 R14
VSSQ35 U14
VSSQ36
X76@ H5GC2H24BFR-T2C_BGA170
H5GC2H24BFR-T2C
Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/12/05 Deciphered Date 2014/12/05 GDDR5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 35 of 99

5 4 3 2 1
 5 4 3 2 1

+1.35V to +1.35VS_VGA

+1.0VALW to +0.95VS_VGA +1.35V

QV24
+1.35VS_VGA

TPCA8057-H
1
2
Rds(on) < 7.5mohm (Vgs = 4.5V) 5 3

+5VS +1VALW +1VS_VGA

1 1
DIS@

4
D QV9 DIS@ CV232 CV233 D
AO4430L_SO8 1U_0402_6.3V6-K 0.1U_0402_10V7-K
8 1 2@ 2@
7 2 +1.35VS_VGA_EN

1
+5VALW 6 3
RV152 5
10K_0402_5% 1 1
DIS@ CV163 CV187

2
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K

2
RV143 DIS@ @
2 2
1

300_0402_5% +5VALW +5VALW

2
RV151 DIS@
100K_0402_5% RV185

1
DIS@ DIS@ 0_0402_5%
2

1
+0.95VS_VGA_GATE

1
RV209 RV208
D

1
RV150 100K_0402_5% 10K_0402_5%
+0.95VS_VGA_EN#
3

D QV18B QV17 2 2 1 DIS@ DIS@

+0.95VS_VGA_EN# 5 2N7002KDWH_SOT363-6 2N7002WT1G_1N_SC-70-3 G
1

2
G SB00000EO1J CV229 SB00000YY00 S 10K_0402_5%

3
DIS@ 0.22U_0402_10V6-K DIS@ +1.35VS_VGA_EN
DIS@
S DIS@
4

2
6

D
VGA_ON

3
2 QV18A D QV23B
G 2N7002KDWH_SOT363-6 +1.35VS_VGA_EN# 5 2N7002KDWH_SOT363-6
SB00000EO1J G DIS@
S DIS@ SB00000EO1J
1

S
RV210

4
6
D QV23A
DGPU_PWROK 2 1 2 2N7002KDWH_SOT363-6
[14,15,83] DGPU_PWROK G DIS@
JV1 @ 1 SB00000EO1J
1 2 0_0402_5% CV241 S
+1VS_VGA 1 2 +0.95VS_VGA

1
C DIS@ 0.1U_0402_10V7-K C
JUMP_43X118 @
2

+3VS to +3VS_VGA +1.8VALW to +1.8VS_VGA

+1.8VALW
VIN 1.8V (VBIAS=5V), IMAX=6A, Rds=15mohm
+5VALW +3VS +3VS_VGA
DIS@
UV12 Bit
QV6
1 5
MLPS
AO3413_SOT23-3
VIN1 GND +1.8VS_VGA
DIS@ 5 4 3 2 1
JV4 @ 1 2 6 CV239 1DIS@ 2820P_0402_50V7-K
VIN2 CT
1

3 1 1 2 +5VALW
S

1 2 18PWRON_R 3 +1.8VS_VGA
B RV161 CV237
ON VOUT1
7 PS_0[5:1] 1 1 0 0 1 B
DIS@ JUMP_43X39 1U_0402_6.3V6-K
47K_0402_5% 2@ 4 8 1
G

VBIAS VOUT2
2

PS_1[5:1] 1 1 0 0 0
2

RV162 1 9 CV238
DIS@ THERMALPAD 0.1U_0402_10V7-K
2@
2

470_0402_5% CV236
0.1U_0402_10V7-K
PS_2[5:1] 1 1 0 0 0
RV163
2 DIS@
1

DIS@
TPS22965DSGR_WSON8_2X2
10K_0402_5% PS_3[5:1] 1 1 X X X
1

DGPU_PWREN#
6

D RV164
2 2 1 DGPU_PWREN#
RV183 G SCS00006S00
3

0_0402_5% D QV19B 1 10K_0402_5% RB751V-40_SOD323-2

VGA_ON 1 DIS@ 2 5 2N7002KDWH_SOT363-6 CV228 S DV7 1 2 DIS@
[14,27,83] VGA_ON DIS@
1

G SB00000EO1J DIS@ QV19A

1

DIS@ .01U_0402_16V7-K 2N7002KDWH_SOT363-6

RV166 S 2 SB00000EO1J RV153
4

@ DIS@ VGA_ON 1 2 18PWRON_R

100K_0402_5%
22K_0402_5% 1
2

1
DIS@ CV240
RV188 0.22U_0402_10V6-K
100K_0402_5% DIS@
@ 2

2
A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2012/12/05 Deciphered Date 2014/12/05 Litho swich power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 36 of 99

5 4 3 2 1
 5 4 3 2 1

D D

EXC24CH900U_4P EXC24CH900U_4P
H_HDMI_TX0- 4 3 HDMI_TX0-_CON H_HDMI_TX2- 4 3 HDMI_TX2-_CON
[42] H_HDMI_TX0- 4 3 [42] H_HDMI_TX2- 4 3

H_HDMI_TX0+ 1 2 HDMI_TX0+_CON H_HDMI_TX2+ 1 2 HDMI_TX2+_CON

[42] H_HDMI_TX0+ 1 2 [42] H_HDMI_TX2+ 1 2
L1 EMC@ L3 EMC@

EXC24CH900U_4P EXC24CH900U_4P
H_HDMI_TX1- 4 3 HDMI_TX1-_CON H_HDMI_TXC- 4 3 HDMI_TXC-_CON
[42] H_HDMI_TX1- 4 3 [42] H_HDMI_TXC- 4 3

H_HDMI_TX1+ 1 2 HDMI_TX1+_CON H_HDMI_TXC+ 1 2 HDMI_TXC+_CON

[42] H_HDMI_TX1+ 1 2 [42] H_HDMI_TXC+ 1 2
L2 EMC@ L4 EMC@

C C

D12 RCLAMP0524PATCT_SLP2510P8-10-9

+5VS_HDMI 9 1 +5VS_HDMI
HDMI_HPD 8 2 HDMI_HPD
HDMI_DAT 7 4 HDMI_DAT
HDMI_CLK 6 5 HDMI_CLK
+5VS +5VS_HDMI_F +5VS_HDMI
D5
2 F2
1 1 2
3
HDMI CONN.
EMC@
3

0.5A_8V_KMC3S050RY
RB491D_SOT23-3
AO3401A_SOT23-3 JHDMI ME@
HDMI_HPD 19
[42] HDMI_HPD HP_DET
@ 1 3 Q22 18

S
+5VS_HDMI +5V
17
HDMI_DAT 16 DDC/CEC_GND
[42] HDMI_DAT HDMI_CLK SDA
[42] HDMI_CLK 15

G
SCL

2
D14 RCLAMP0524PATCT_SLP2510P8-10-9 14
[70] SUSP Reserved
13
HDMI_TXC-_CON 12 CEC 20
11 CK- GND1 21
HDMI_TXC-_CON 9 1 HDMI_TXC-_CON HDMI_TXC+_CON 10 CK_shield GND2 22
HDMI_TXC+_CON 8 2 HDMI_TXC+_CON HDMI_TX0-_CON 9 CK+ GND3 23
B B
HDMI_TX0-_CON 7 4 HDMI_TX0-_CON 8 D0- GND4
HDMI_TX0+_CON 6 5 HDMI_TX0+_CON HDMI_TX0+_CON 7 D0_shield
HDMI_TX1-_CON 6 D0+
5 D1-
HDMI_TX1+_CON 4 D1_shield
HDMI_TX2-_CON 3 D1+
EMC@ 2 D2-
D2_shield
3

+5VS_HDMI HDMI_TX2+_CON 1
D2+
CONCR_099ATAC19NBLCNF

R224 1 2 2.2K_0402_5% HDMI_CLK

R225 1 2 2.2K_0402_5% HDMI_DAT

D13 RCLAMP0524PATCT_SLP2510P8-10-9

HDMI_TX1-_CON 9 1 HDMI_TX1-_CON
HDMI_TX1+_CON 8 2 HDMI_TX1+_CON
HDMI_TX2-_CON 7 4 HDMI_TX2-_CON
HDMI_TX2+_CON 6 5 HDMI_TX2+_CON

EMC@
3

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 HDMI CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 37 of 99

5 4 3 2 1
 5 4 3 2 1

CMOS Camera For 2D CCD

+3VS +3VS_CMOS
2DCCD@
LCDVDD Circuit R17 1 2 0_0402_5% 2W
0.4A
+LCDVDD_CON For RF solution. +5VS +5VS_CMOS For RF solution.
D +3VS For 3D CCD D
U3
W= 60 mil 5 1
W= 60 mil
+LCDVDD_CON CRF7 CRF8 5
U4 3DCCD@
1 +5VS_CMOS C11 CRF9 CRF10
IN OUT IN2 OUT
1 2 1 2
GND GND
C8 PCH_ENVDD 4 3 EMC_NS@ RF_NS@ @ C10 4 3 PCH_CMOS_ON From PCH @ RF_NS@ RF_NS@

4.7U_0603_6.3V6-K

2200P_0402_50V7-K

47P_0402_50V8-J

4.7U_0603_6.3V6-K

2200P_0402_50V7-K

47P_0402_50V8-J
[5] PCH_ENVDD EN OC IN1 EN PCH_CMOS_ON [14]
1U_0402_6.3VA-K 1 1 1 1U_0402_6.3VA-K 1 1 1
2 2 G5243AT11U_SOT23-5
From PCH

1
G524B1T11U_SOT23-5 C9 SA00005XJ00

1
R18 2 2 2 R2 2 2 2
@ 100K_0402_5%
100K_0402_5%

2
2
20141231

For RF solution.
C C
B+
For RF solution. +3VALW_LOGO
R9474
2A 80 mil 0_0805_5% 2A 80 mil
1 2 C12 CRF11 CRF12 +LEDVDD CRF13 CRF14

RF_NS@ EMC_NS@ RF_NS@ RF_NS@

4.7U_0805_25V6-K

2200P_0402_50V7-K

47P_0402_50V8-J

2200P_0402_50V7-K

47P_0402_50V8-J
1 1 1 1 1
1
eDP CONN.
C8533 EMC_NS@
2 2 2 2 2 2200P_0402_50V7-K
2 JLCD ME@
+LEDVDD W= 80 mil 1
1
2
3 2
FW _GPIO BKOFF# R21 1 2 100K_0402_5% 4 3
1 2 +3VDMIC W= 40 mil 5 4
+3VS 5
+3VS_CMOS R9475 0_0402_5% 6
6

1
+LCDVDD_CON W= 60 mil 7
7
8
R9449 R26 R25 1 2 2.2K_0402_1% +3VALW_LOGO 9 8
100K_0402_5% 100K_0402_5% LOGO_LED# 10 9
1 [61,72] LOGO_LED# 10
+3VALW [61] BKOFF# BKOFF# 11
11

2
EMC_NS@ C8534 PCH_EDP_PWM 12
[5] PCH_EDP_PWM 12
2200P_0402_50V7-K 13
2 DMIC_DATA 14 13
[54] DMIC_DATA DMIC_CLK 14
15
CMOS USB Port 2 [54] DMIC_CLK
USB20_N7_CMOS
16 15
16
17
USB20_P7_CMOS 18 17
EMC_2D@ 18
19
EXC24CH900U_4P CPU_EDP_AUX# C17 1 2 0.1U_0402_10V7-K CPU_EDP_AUX#_CON 20 19
USB20_N7 USB20_N7_CMOS [5] CPU_EDP_AUX# CPU_EDP_AUX C18 20
[15] USB20_N7 4 3 1 2 0.1U_0402_10V7-K CPU_EDP_AUX_CON 21
4 3 [5] CPU_EDP_AUX CPU_EDP_HPD 21
B 22 B
[5] CPU_EDP_HPD 22
23
USB20_P7 1 2 USB20_P7_CMOS 24 23
[15] USB20_P7 1 2 CPU_EDP_TX1- 24
C13 1 2 0.1U_0402_10V7-K CPU_EDP_TX1-_CON 25
[5] CPU_EDP_TX1- CPU_EDP_TX1+ 25
L15 C14 1 2 0.1U_0402_10V7-K CPU_EDP_TX1+_CON 26
[5] CPU_EDP_TX1+ 26
27
CPU_EDP_TX0- 1 2 0.1U_0402_10V7-K CPU_EDP_TX0-_CON 28 27
ESD request [5] CPU_EDP_TX0- CPU_EDP_TX0+
C15
C16 1 2 0.1U_0402_10V7-K CPU_EDP_TX0+_CON 29 28
[5] CPU_EDP_TX0+ 29
30
31 30
USB3P5_RXN_CON 32 31
+3VALW_LOGO USB3P5_RXP_CON 33 32
33
EMC_NS@
R165 1 2 0_0402_5% LOGO_LED# For 3D CCD USB3P5_TXN_CON
34
35 34
USB3P5_TXP_CON 36 35
37 36 41
EMC_3D@ FW_GPIO 37 GND1
3

2 38 42
EXC24CH900U_4P [14] FW_GPIO 38 GND2
D1 39 43
USB3P5_RXN USB3P5_RXN_CON 39 GND3
[15] USB3P5_RXN
4
4 3
3 EMC@ +5VS_CMOS W= 50 mil 40
40 GND4
44
PESD5V0U2BT_SOT23-3
I-PEX_20474-040E-12
USB3P5_RXP 1 2 USB3P5_RXP_CON
[15] USB3P5_RXP 1 2
1

L16

EMC_NS@
R166 1 2 0_0402_5%

EMC_NS@
R167 1 2 0_0402_5%

EMC_3D@
A EXC24CH900U_4P A
3DCCD@
C28 1 2 0.1U_0402_10V7-K USB3P5_TXN_C 4 3 USB3P5_TXN_CON
[15] USB3P5_TXN 4 3

C29 1 2 0.1U_0402_10V7-K USB3P5_TXP_C 1 2 USB3P5_TXP_CON

[15] USB3P5_TXP 1 2
3DCCD@ L17

EMC_NS@ Title
R168 1 2 0_0402_5% Security Classification LC Future Center Secret Data

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 eDP CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 38 of 99

5 4 3 2 1
 5 4 3 2 1

EMC@
LT3 SM01000L40J
R229 1 2 0_0402_5% VGA_RED_R 1 2 VGA_RED_CON
[41] VGA_RED
BLM15BB220SN1D_2P

EMC@
LT2 SM01000L40J
R230 1 2 0_0402_5% VGA_GREEN_R 1 2 VGA_GREEN_CON
[41] VGA_GREEN
BLM15BB220SN1D_2P
D D
EMC@
LT1 SM01000L40J
R231 1 2 0_0402_5% VGA_BLUE_R 1 2 VGA_BLUE_CON
[41] VGA_BLUE
BLM15BB220SN1D_2P

75_0402_1%

75_0402_1%

75_0402_1%
1

3P_0402_50V8-C

3P_0402_50V8-C

3P_0402_50V8-C

3P_0402_50V8-C

3P_0402_50V8-C

3P_0402_50V8-C
1 1 1 1 1 1
RT21 RT22 RT23 CT29 CT26 CT24 CT25 CT27 CT28
EMC@ EMC@ EMC@ EMC@ EMC@ EMC@
2 2 2 2 2 2

2
Please Close CRT Connector

RT34 1 2 0_0402_5%

+5VS_HDMI DT1 EMC@

VGA_RED_CON 1 6 VGA_BLUE_CON

+5VS_HDMI

1
2 5 +5VS_HDMI

OE#
C VGA_HSYNC 2 4 VGA_HSYNC_1 RT20 1 2 0_0402_5% VGA_HSYNC_CON C
[41] VGA_HSYNC A Y

G
UT3
SN74AHCT1G125DCKR_SC70-5 VGA_GREEN_CON 3 4

3
@
CM1293A-04SO_SC-74-6

+5VS_HDMI

Traslater VGA@ DT2 EMC@

CT31 1 2 0.1U_0402_10V6-K VGA_VSYNC_CON 1 6 VGA_HSYNC_CON

+5VS_HDMI
5

1
2 5 +5VS_HDMI
P

OE#
VGA_VSYNC 2 4 VGA_VSYNC_1 RT27 1 2 0_0402_5% VGA_VSYNC_CON
[41] VGA_VSYNC A Y
G

UT4
SN74AHCT1G125DCKR_SC70-5 VGA_DDC_SCL_CON 3 4 VGA_DDC_SDA_CON
3

@
CM1293A-04SO_SC-74-6

RT35 1 2 0_0402_5%

+3VS +3VS +5VS_HDMI

B
Only for 15' B
1

RT36
CRT Connector

1
@ RT14
2

2.2K_0402_5% QT1A
G

JCRT ME@
2N7002KDWH_SOT363-6 2.2K_0402_5%
2

SB00000EO1J 6

2
1 11
VGA_DDC_SCL VGA_DDC_SCL_CON VGA_RED_CON T25
[41] VGA_DDC_SCL 1 6 1
S

7
D

@ VGA_DDC_SDA_CON 12
VGA_GREEN_CON 2
1

8
VGA_HSYNC_CON
1
RT37 @ RT28 1 2 0_0402_5% 13
RT13 VGA_BLUE_CON 3
2.2K_0402_5% +5VS_HDMI 9
VGA_VSYNC_CON
5

QT1B 2.2K_0402_5% 14 16
G
2

2N7002KDWH_SOT363-6 1 4 17
T26
2

SB00000EO1J 10
VGA_DDC_SCL_CON 15
VGA_DDC_SDA 4 3 VGA_DDC_SDA_CON 5
S

[41] VGA_DDC_SDA
D

@ SUYIN_070546HR015S21BZR

RT29 1 2 0_0402_5%

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 CRT CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 40 of 99

5 4 3 2 1
 2 1

+3VS +3VS_DP
+3VS_DP VBUCK_1V5
RVG130
0_0805_5%
1 2
1 1 1 1 1 1 1 1
1
20141222

0.1U_0402_10V6-K
CVG34

0.1U_0402_10V6-K
CVG35

0.1U_0402_10V6-K
CVG36

0.1U_0402_10V6-K
CVG37

0.1U_0402_10V6-K
CVG38

0.1U_0402_10V6-K
CVG39

0.1U_0402_10V6-K
CVG40

0.1U_0402_10V6-K
CVG41
CVG42
2.2U_0603_6.3V6-K 2 2 2 2 2 2 2 2
2

17

27
30

28
1

6
UVG2
B B

PVDD33

VDDD15
VDDA15_DP

VDDA15_DAC
VDDE33_IO1

VDDE33_IO2
VDDA33_DNW
DP_HPD_R 11 25 XTLI
HPD OSC_IN
26 XTLO
29 OSC_OUT
TESTMODE

CVG15 1 2 0.1U_0402_10V6-K ML0N

[5] DDI2_VGA_TX0- VGA_RED
CVG16 1 2 0.1U_0402_10V6-K ML0P 24
[5] DDI2_VGA_TX0+ RED VGA_RED [40]
[5] DDI2_VGA_TX1- CVG17 1 2 0.1U_0402_10V6-K ML1N AUXP 2
CVG18 1 2 0.1U_0402_10V6-K ML1P AUXN 3 AUX_P
[5] DDI2_VGA_TX1+ AUX_N VGA_GREEN
CVG19 1 2 0.1U_0402_10V6-K AUXN 22
[5] PCH_VGA_AUX# GRN VGA_GREEN [40]
[5] PCH_VGA_AUX CVG20 1 2 0.1U_0402_10V6-K AUXP ML0P 4
ML0N 5 ML0_P
ML0_N 21 VGA_BLUE
DP_HPD_R BLU VGA_BLUE [40]
RVG129 1 2 0_0402_5% ML1P 7
[5] PCH_VGA_HPD ML1_P
ML1N 8
ML1_N RVG18
VGA_HSYNC_L 1
20141225_S @ HSYNC
20 2
36_0402_5%
VGA_HSYNC [40] 20141225_S
CVG43 1 2 10
1U_0402_10V6K RST_N RVG19
VGA_VSYNC_L 1
RVG131 1 2 RST# 23 VSYNC
19 2
36_0402_5%
VGA_VSYNC [40] 20141225_S
1.2K_0402_1% RSET

16 VGA_DDC_SCL
CFG1_DP DDC_SCL VGA_DDC_SCL [40]
12
CFG2_DP 15 CFG1
14 CFG2 18 VGA_DDC_SDA
CFG3 DDC_SDA VGA_DDC_SDA [40]
RVG16 1 2 1M_0402_5% 13
CFG5
L21
4.7UH_TLPC4012C-4R7M_1.25A_20%
YVG1 31 1 2 VBUCK_1V5
32 SWOUT

GND
XTLI 1 4 PGND
OSC1 GND2 1
2
GND1 OSC2
3 XTLO PTN3356R1BS_HVQFN32_5X5
Ready On 1229 CVG44

33
4.7U_0402_6.3V6-M
2
27MHZ_10PF_7V27000050
1

CVG32 CVG33
12P_0402_50V8-J 12P_0402_50V8-J
2

+3VS +3VS
1

RVG132 RVG133
10K_0402_5% @ 10K_0402_5%
2

A A
CFG1_DP CFG2_DP
1

RVG134 RVG135
@ 10K_0402_5% 10K_0402_5%
2

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DP to VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 41 of 99

2 1
 A B C D E F G H

1 1

UX1 MUX@

+3VS_DDIMUX 14 8 MUX_PEQ
28 VDD33_1 PEQ
VDD33_2 PCH_MUX_HPD
To MCP
41 5
56 VDD33_3 Out IN_HPD 11
PCH_MUX_HPD [5]
VDD33_4 IN_CA_DET
DDI1_MUX_TX0+ CX4 MUX@1 2 0.1U_0402_10V7-K DDI1_MUX_TX0+_R 3 40 DOCK_TX0+
[5] DDI1_MUX_TX0+ DDI1_MUX_TX0- DDI1_MUX_TX0-_R IN_D0p DP_D0p DOCK_TX0- DOCK_TX0+ [60]
CX3 MUX@1 2 0.1U_0402_10V7-K 4 39
[5] DDI1_MUX_TX0- DDI1_MUX_TX1+ DDI1_MUX_TX1+_R IN_D0n DP_D0n DOCK_TX1+ DOCK_TX0- [60]
CX6 MUX@1 2 0.1U_0402_10V7-K 6 37
[5] DDI1_MUX_TX1+ DDI1_MUX_TX1- DDI1_MUX_TX1-_R IN_D1p DP_D1p DOCK_TX1- DOCK_TX1+ [60]
+3VS RX1 +3VS_DDIMUX CX5 MUX@1 2 0.1U_0402_10V7-K 7 36
[5] DDI1_MUX_TX1- DDI1_MUX_TX2+ DDI1_MUX_TX2+_R IN_D1n DP_D1n DOCK_TX1- [60]
0_0805_5% CX8 MUX@1 2 0.1U_0402_10V7-K 9 34
[5] DDI1_MUX_TX2+ DDI1_MUX_TX2- DDI1_MUX_TX2-_R IN_D2P DP_D2p
1 2 CX7 MUX@1 2 0.1U_0402_10V7-K 10 33
[5] DDI1_MUX_TX2- DDI1_MUX_TX3+ DDI1_MUX_TX3+_R IN_D2n DP_D2n
CX10MUX@1 2 0.1U_0402_10V7-K 12 31
[5] DDI1_MUX_TX3+ DDI1_MUX_TX3- DDI1_MUX_TX3-_R IN_D3p DP_D3p
CX9 MUX@1 2 0.1U_0402_10V7-K 13 30
[5] DDI1_MUX_TX3- IN_D3n DP_D3n
PCH_MUX_CLK 50 55 DOCK_AUX
[5] PCH_MUX_CLK PCH_MUX_DAT IN_DDC_SCL DP_AUXp_SCL DOCK_AUX# DOCK_AUX [60]
[5] PCH_MUX_DAT 49 54
IN_DDC_SDA DP_AUXn_SDA DOCK_AUX# [60]
MUX_SW 45 16 H_HDMI_TXC+
SW/SDA_CTL TMDS_CLKp H_HDMI_TXC- H_HDMI_TXC+ [37]
TP939 1 46 15
PD TMDS_CLKn H_HDMI_TXC- [37]
MUX@
PCH_MUX_AUX CX15 1 2 0.1U_0402_10V7-K PCH_MUX_AUX_C 52 19 H_HDMI_TX0+
[5] PCH_MUX_AUX PCH_MUX_AUX# PCH_MUX_AUX#_C IN_AUXp TMDS_CH0p H_HDMI_TX0- H_HDMI_TX0+ [37]
+3VS_DDIMUX CX16 1 2 0.1U_0402_10V7-K 51 18
[5] PCH_MUX_AUX# IN_AUXn TMDS_CH0n H_HDMI_TX1+ H_HDMI_TX0- [37]
22
MUX_I2C_CTL_EN TMDS_CH1p H_HDMI_TX1- H_HDMI_TX1+ [37]
MUX@ MUX@ MUX@ MUX@ MUX@ 38 21
+3VS_DDIMUX I2C_CTL_EN TMDS_CH1n H_HDMI_TX2+ H_HDMI_TX1- [37]
CX11 CX13 CX12 CX14 25
MUX_MODE TMDS_CH2p H_HDMI_TX2- H_HDMI_TX2+ [37]
53 24
MODE TMDS_CH2n H_HDMI_TX2- [37]
MUX@
0.1U_0402_10V7-K

0.1U_0402_10V7-K

.01U_0402_16V7-K

.01U_0402_16V7-K
1 1 1 1 HDMI_CLK
CX2 1 2 2.2U_0402_6.3V6-K 1 48
CEXT TMDS_SCL HDMI_DAT HDMI_CLK [37]
RX2 1 2 4.99K_0402_1% 27 47
2 REXT TMDS_SDA HDMI_DAT [37] 2
MUX@
2 2 2 2 DOCKDP_HPD 32 20 MUX_PRE
[60] DOCKDP_HPD MUX_CAD DP_HPD 3V, Int. PD 150K TMDS_PRE
42
DP_CA_DET 23 MUX_RT
MUX_DDCBUF 2 TMDS_RT
HDMI_HPD 17 TMDS_DDCBUF 26
[37] HDMI_HPD TMDS_HPD 5V, Int. PD 150K GND1 35
MUX_CFG0 44 GND2 43
MUX_CFG1 29 DP_CFG0/SCL_CTL GND3 57
DP_CFG1 EPAD

PS8339BQFN56GTR2-A1_QFN56_7X7

15/0528 Auto Mode 15/0528

DP Higher Priolity Pass Through Mode
+3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX +3VS_DDIMUX
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
3 3
1

1
RX19 RX17 RX16 RX11 RX14 RX9 RX8 RX6 RX3
@ MUX@ @ MUX@ @ @ @ @ MUX@
2

2
MUX_CFG1 MUX_CFG0 MUX_CAD MUX_SW MUX_MODE MUX_I2C_CTL_EN MUX_DDCBUF MUX_RT MUX_PRE MUX_PEQ
4.7K_0402_5%

4.7K_0402_5%

1M_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
1

1
RX20 RX18 RX21 RX15 RX10 RX13 RX12 RX7 RX5 RX4
@ MUX@ MUX@ MUX@ MUX@ @ MUX@ @ @ MUX@
2

2
4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 Mux IC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 42 of 99

A B C D E F G H
 5 4 3 2 1

D D

SATA HDD CONN.

Close to JHDD
+3VS

C 1
RF_NS@
1
RF_NS@
SATA HDD CONN. JHDD ME@
C
C204 C205 1
2200P_0402_50V7-K 47P_0402_50V8-J SATA_PTX_DRX_P0 C24 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P0 2 GND1
2 2 [15] SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 A+
[15] SATA_PTX_DRX_N0 C25 1 2 .01U_0402_16V7-K 3
4 A-
SATA_PRX_DTX_N0 C26 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N0 5 GND2
[15] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C27 1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P0 6 B-
[15] SATA_PRX_DTX_P0 7 B+
GND3

8
+3VS VCC_3V3_1
9
HDD_DEVSLP0 10 VCC_3V3_2
[15] HDD_DEVSLP0 VCC_3V3_3
11
HDD_DETECT# 12 GND4
[61] HDD_DETECT# 13 GND5
14 GND6
+5VS VCC5_1
15
16 VCC5_2
17 VCC5_3
18 GND7
Pin18 connect to GND for SATA Gen3 19 RESERVED
+5VS 20 GND8 23
VCC12_1 GND9
Close to JHDD 21
22 VCC12_2 GND10
24
VCC12_3

1 1 1 1 1 1 1
C19 C20 C21 C22 C23 RF_NS@ RF_NS@ ACES_50812-0227P-001
@ @ @ @ C202 C203
10U_0805_10V6-K 10U_0805_10V6-K 1U_0402_10V6-K 0.1U_0402_25V6-K 1000P_0402_50V7-K 2200P_0402_50V7-K 47P_0402_50V8-J
2 2 2 2 2 2 2
B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 SATA HDD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 43 of 99

5 4 3 2 1
 5 4 3 2 1

D D

+5VS TO +5VS_ODD

R154 1 @ 2 0_0805_5%

+5VS +5VS_ODD
80 mils 5
U150 ODD@
1 +5VS_ODD 80 mils
IN2 OUT
1 2 1
C132 GND
C 4 3 ODD_EN From PCH C131
C

SATA ODD CONN

ODD@ ODD@
IN1 EN ODD_EN [15]
1U_0402_6.3VA-K 4.7U_0603_6.3V6-K
2 G5243AT11U_SOT23-5 2

1
SA00005XJ00
R153
ODD@
100K_0402_5% JODD ME@
1
1

2
SATA_PTX_DRX_P1 C164 ODD@ 1 2 .01U_0402_16V7-K SATA_PTX_C_DRX_P1 2
[15] SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1 2
[15] SATA_PTX_DRX_N1 C165 ODD@ 1 2 .01U_0402_16V7-K 3
4 3
SATA_PRX_DTX_N1 C129 ODD@1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_N1 5 4
[15] SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 C130 ODD@1 2 .01U_0402_16V7-K SATA_PRX_C_DTX_P1 6 5
[15] SATA_PRX_DTX_P1 7 6 14
ODD_DETEC# 8 7 GND1
[15] ODD_DETEC# 8
9 15
+5VS_ODD 9 GND2
10
1 2 ODD_DA#_R 11 10
MCP [15] ODD_DA#
R150 0_0402_5% 12 11
13 12
+5VS_ODD 13
For RF solution. 20141204 ACES_50885-0137P-001
Close to JODD connector.

CRF5 CRF6

RF_NS@ RF_NS@
2200P_0402_50V7-K

47P_0402_50V8-J

1 1

2 2

B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 ODD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 44 of 99

5 4 3 2 1
 5 4 3 2 1

+USB_VCCA
USB3 PORT1 POWER SWITCH
+5VALW
1
C8545
+USB_VCCA
W=80mils U15
EMC@

5 1
W=80mils 2
0.1U_0402_10V6-K
IN OUT
2 D8 RCLAMP0524PATCT_SLP2510P8-10-9 1
GND
USB_ON# USB_OC0# 1
4 3 + C122 C123
[60,61] USB_ON# EN OC USB_OC0# [15]
1 USB3P1_TXP_CON USB3P1_TXP_CON
C119 G524B2T11U_SOT23-5 9 1 150U_B2_6.3VM_R35M 470P_0402_50V7-K
EMC@ USB3P1_TXN_CON 8 2 USB3P1_TXN_CON 2 2
D 0.1U_0402_10V6-K USB3P1_RXP_CON 7 4 USB3P1_RXP_CON D
2 USB3P1_RXN_CON 6 5 USB3P1_RXN_CON
Low Act i ve 2. 5A

EXC24CH900U_4P EMC@

3
USB3P1_TXP C121 1 2 0.1U_0402_10V7-K USB3P1_TXP_C 4 3 USB3P1_TXP_CON
[15] USB3P1_TXP 4 3

USB3P1_TXN C124 1 2 0.1U_0402_10V7-K USB3P1_TXN_C 1 2 USB3P1_TXN_CON

[15] USB3P1_TXN 1 2
L9 EMC@ +USB_VCCA

JUSB1 ME@
EXC24CH900U_4P USB3P1_TXP_CON 9
USB3P1_RXP 4 3 USB3P1_RXP_CON D7 EMC@ 1 StdA_SSTX+
[15] USB3P1_RXP 4 3 USB20_N1_CON USB20_P1_CON USB3P1_TXN_CON VBUS
1 6 8
USB20_P1_CON 3 StdA_SSTX-
USB3P1_RXN 1 2 USB3P1_RXN_CON +USB_VCCA 7 D+
[15] USB3P1_RXN 1 2 USB20_N1_CON GND_DRAIN
2 10
L10 EMC@ 2 5 USB3P1_RXP_CON 6 D- GND_1 11
4 StdA_SSRX+ GND_2 12
USB3P1_RXN_CON 5 GND_5 GND_3 13
StdA_SSRX- GND_4
EXC24CH900U_4P 3 4 TAITW_PUBAU1-09FNLSCNN4H0
USB20_P1 4 3 USB20_P1_CON
[15] USB20_P1 4 3 CM1293A-04SO_SC-74-6
USB20_N1 1 2 USB20_N1_CON
[15] USB20_N1 1 2
L11 EMC@

C C

PORT2(AOU)
EXC24CH900U_4P
USB3P2_TXP C8529 1 2 0.1U_0402_10V7-K USB3P2_TXP_C 4 3 USB3P2_TXP_CON
[15] USB3P2_TXP 4 3
+5VALW +5VALW_CHGUSB
USB3P2_TXN C8530 1 2 0.1U_0402_10V7-K USB3P2_TXN_C 1 2 USB3P2_TXN_CON
[15] USB3P2_TXN 1 2
L19 EMC@
AOU1
1 12
IN OUT 10 USB20P2
USB20_P2 3 DP_IN 11 USB20N2
[15] USB20_P2 USB20_N2 DP_OUT DM_IN
2 14
[15] USB20_N2 DM_OUT GND
EXC24CH900U_4P EXC24CH900U_4P
9 AOU_IFG# USB3P2_RXP 4 3 USB3P2_RXP_CON USB20P2 4 3 USB20_P2_CON
STATUS# AOU_IFG# [61] [15] USB3P2_RXP 4 3 4 3
4
USB_OC1# 13 ILIM_SEL USB3P2_RXN 1 2 USB3P2_RXN_CON USB20N2 1 2 USB20_N2_CON
[15] USB_OC1# AOU_EN FAULT# [15] USB3P2_RXN 1 2 1 2
[61] AOU_EN 5
EN 15 ILIM_LO R484 1 @ 2 20K_0402_1% L18 EMC@ L20 EMC@
AOU_CTL1 6 ILIM_LO 16 ILIM_HI R9476 1 2 20K_0402_1%
[61] AOU_CTL1 CLT1 ILIM_HI
7
AOU_CTL3 8 CLT2 17
[61] AOU_CTL3 CLT3 GND_Pad
B 1 TPS2546RTER_QFN16_4X4 B
@ +5VALW_CHGUSB
C8532
0.1U_0402_10V7-K
TI TPS2546 D16 RCLAMP0524PATCT_SLP2510P8-10-9
2

USB3P2_TXP_CON USB3P2_TXP_CON 1
9 1 1
USB3P2_TXN_CON 8 2 USB3P2_TXN_CON + C8531 C8528
USB3P2_RXP_CON 7 4 USB3P2_RXP_CON
USB3P2_RXN_CON 6 5 USB3P2_RXN_CON 150U_B2_6.3VM_R35M 470P_0402_50V7-K
CLT1 CLT2 CLT3 ILIM_SEL MOD 2 2

0 0 0 X DCH OUT held low

EMC@

3
1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active
*
* 1 1 1 0 SDP2 Data Connected

+5VALW_CHGUSB
* 1 1 0 X SDP1 Data Connected

JUSB2 ME@
* 0 1 0 X SDP1 Data Connected
D17 EMC@
USB3P2_TXP_CON 9
1 StdA_SSTX+
USB20_N2_CON 1 6 USB20_P2_CON USB3P2_TXN_CON 8 VBUS
USB20_P2_CON StdA_SSTX-
1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode 3
D+
+5VALW_CHGUSB 7
USB20_N2_CON 2 GND_DRAIN 10
2 5 USB3P2_RXP_CON 6 D- GND_1 11
1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode
StdA_SSRX+ GND_2
4 12
USB3P2_RXN_CON 5 GND_5 GND_3 13
StdA_SSRX- GND_4
0 1 1 DCP_Auto Data Disconnected and Port Power Mgt. Function Active
*
X
A A
3 4 TAITW_PUBAU1-09FNLSCNN4H0

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active CM1293A-04SO_SC-74-6

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 USB3 PORT1/PORT2(AOU)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 45 of 99

5 4 3 2 1
 5 4 3 2 1

VPRO SKU : RL2 (@), RL25(VPRO@)

+5VALW +3VALW +3VALW_LAN

40 mils 40 mils

1
3 1

D
RL22 VPRO@ QL2 VPRO@
+3VALW +3VALW_LAN 47K_0402_5% AO3413_SOT23-3

G
2
D RL24 VPRO@ D

2
RL19 LAN_PWRON# 1 2
1 2 1
D

1
RL25 10K_0402_5%
0_0603_5% LAN_PWRON 1 VPRO@ 2 LAN_PWRON_R 2 QL3 VPRO@ CL17 VPRO@
[61] LAN_PWRON
For Non-Vpro NVPRO@ G 2N7002WT1G_1N_SC-70-3
2
.01U_0402_16V7-K

1
0_0402_5% S SB00000YY00

3
RL23 VPRO@
100K_0402_5%

2
UL1
CLKREQ_PCIE3_LAN# 48 13 MDI_0+
[10] CLKREQ_PCIE3_LAN# PLTRST_NEAR# CLK_REQ_N MDI_PLUS[0] MDI_0- MDI_0+ [49]
36 14
[12,23,51] PLTRST_NEAR# PE_RST_N MDI_MINUS[0] MDI_0- [49]
CLK_PCIE_LAN 44 17 MDI_1+
[10] CLK_PCIE_LAN CLK_PCIE_LAN# PE_CLKP MDI_PLUS[1] MDI_1- MDI_1+ [49]
45 18
[10] CLK_PCIE_LAN# PE_CLKN MDI_MINUS[1] MDI_1- [49]

PCIE
PCIE4_CRX_DTX_P PCIE4_CRX_DTX_P_C MDI_2+

MDI
CL1 1 2 0.1U_0402_10V7-K 38 20
[15] PCIE4_CRX_DTX_P PCIE4_CRX_DTX_N PCIE4_CRX_DTX_N_C PETp MDI_PLUS[2] MDI_2- MDI_2+ [49]
CL2 1 2 0.1U_0402_10V7-K 39 21
[15] PCIE4_CRX_DTX_N PETn MDI_MINUS[2] MDI_2- [49]
PCIE4_CTX_C_DRX_P 41 23 MDI_3+
[15] PCIE4_CTX_C_DRX_P PCIE4_CTX_C_DRX_N PERp MDI_PLUS[3] MDI_3- MDI_3+ [49]
42 24
C [15] PCIE4_CTX_C_DRX_N PERn MDI_MINUS[3] MDI_3- [49] +3VALW_LAN C

PCH_SML0_CLK 28 6
[11] PCH_SML0_CLK PCH_SML0_DAT SMB_CLK SVR_EN_N
[11] PCH_SML0_DAT 31

SMBUS
SMB_DATA 1 1 2
RSVD1_VCC3P3 RL4 4.7K_0402_5%
RL18 1 2 0_0402_5% LAN_WAKE#_R 2 5
[61] LAN_WAKE# LANWAKE_N VDD3P3_IN
RL17 1 @ 2 0_0402_5% LANPHYPC 3
[12,61] PCH_SLP_LAN# LAN_DISABLE_N 4
VDD3P3_4
15 1 2 CL3
RJ45_LINKUP# 26 VDD3P3_15 19
[49] RJ45_LINKUP# RJ45_ACTIVITY# LED0 VDD3P3_19
20141209 [49] RJ45_ACTIVITY#
27
25 LED1 VDD3P3_29
29
1U_0402_6.3VA-K

LED
LED2
47 VCC0R9GBE
VDD0P9_47 46
+3VALW_LAN 1 32 VDD0P9_46 37
T23 JTAG_TDI VDD0P9_37
1 34
T24 JTAG_TDO
RL5 1 2 10K_0402_5% 33 43
JTAG_TMS

JTAG
RL6 1 2 10K_0402_5% 35 VDD0P9_43
JTAG_TCK 11
VDD0P9_11
LAN_XTALO LAN_XTALO 9 40
LAN_XTALI 10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
LAN_XTALI VDD0P9_16 8
YL1 25MHZ_10PF_8Y25000010 VDD0P9_8
30
TEST_EN
1 3 12 7 VCC0R9GBE_L LL1 1 2 4.7UH_ LQH32PN4R7NN0L_30% CL4 CL5 CL6 VCC0R9GBE
1 3 RBIAS CTRL0P9
GND1 GND2 49
GND

0.1U_0402_10V7-K

0.1U_0402_10V7-K

22U_0805_6.3V6-M
1 2 4 1
15P_0402_50V8-J

15P_0402_50V8-J

RL7 RL8 WGI219LM-QREF-A0_QFN48_6X6 1 @ 1 2

B CL7 CL8 1K_0402_5% 3.01K_0402_1% B

2 2 20150526
Close to FL1
2

2
2 2 1
SA00007H610 15/0526
UL1 GBE PHY

vPro Model Non-vPro Model

I219LM I219V
+3VALW_LAN

ST-1_SWG_SDV-SWG_EC062
Add vPro/Non-vPro table.
1

RL9
10K_0402_5%
2

LANPHYPC
[12] LANPHYPC

When use Native function, intel recommend pull high 10K ohm
This part is un-mount in Sting.
A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 47 of 99

5 4 3 2 1
 5 4 3 2 1

TL1 EMC@
MDI_0+ 1 1:1
[47] MDI_0+ TD1+ T1/B RJ45_TXD0P
24
TX1+

MDI_0- 2
[47] MDI_0- TD1-
D D
23 RJ45_TXD0N
TX1-
3 22 MCT1 RL10 2 1 75_0805_5% RJ45_GND DL3 SURGE@
TDCT1 T1/A TXCT1 MCT1 2 1

4 21 MCT2 RL11 2 1 75_0805_5%

MDI_1+ TDCT2 1:1 TXCT2
5 T1/B LSE-200NX3216TRLF_1206-2
[47] MDI_1+ TD2+ RJ45_TXD1P
20
TX2+ SURGE@
DL4
MCT2 2 1
MDI_1- 6
[47] MDI_1- TD2- RJ45_TXD1N
19 LSE-200NX3216TRLF_1206-2
TX2-
DL5 SURGE@
T1/A MCT3 2 1
MDI_2+ 7 1:1
[47] MDI_2+ TD3+ T1/B RJ45_TXD2P
18 LSE-200NX3216TRLF_1206-2
TX3+
DL6 SURGE@
MDI_2- 8 MCT4 2 1
[47] MDI_2- TD3-
17 RJ45_TXD2N
TX3- LSE-200NX3216TRLF_1206-2
9 16 MCT3 RL12 2 1 75_0805_5%
TDCT3 T1/A TXCT3
15/0526
10 15 MCT4 RL13 2 1 75_0805_5%
MDI_3+ TDCT4 1:1 TXCT4
11 T1/B
[47] MDI_3+ TD4+ RJ45_TXD3P
14
TX4+
1U_0402_10V6K

1 1
CL13

PATTERN MUST BE
CL9
C
0.1U_0402_25V6-K MDI_3- 12 SHORT AND WIDE. C
2 2 [47] MDI_3- TD4- RJ45_TXD3N
13
TX4-

T1/A
CL9 CL13 close to LAN Chip BOTHHAND_NA69LF

ME will change CONN on SDV phase.

RJ-45 Conn.
DL1 RCLAMP0524PATCT_SLP2510P8-10-9

RL16 JRJ452 ME@

MDI_0+ 9 1 MDI_0+ 1 2 9
MDI_0- MDI_0- +3VALW_LAN YellowLED+
8 2
MDI_1+ 7 4 MDI_1+ 510_0402_1% RJ45_ACTIVITY# 10
MDI_1- MDI_1- [47] RJ45_ACTIVITY# YellowLED-
6 5 For RF solution. RJ45_TXD3N 8
PR4-
B +3VALW_LAN RJ45_TXD3P 7 B
PR4+
EMC@ RJ45_TXD1N 6
PR2-
3

CRF15 CRF16
RJ45_TXD2N 5
PR3-
2200P_0402_50V7-K

47P_0402_50V8-J

RF_NS@ RF_NS@
RJ45_TXD2P 4
1 1 PR3+
RJ45_TXD1P 3
PR2+ 14
2 2 RJ45_TXD0N 2 GND2
PR1- 13
RJ45_TXD0P 1 GND1
RL15 PR1+
DL2 RCLAMP0524PATCT_SLP2510P8-10-9 1 2 11
+3VALW_LAN GreenLED+
510_0402_1% RJ45_LINKUP# 12
[47] RJ45_LINKUP# GreenLED-
MDI_2+ 9 1 MDI_2+ FOX_JM3611-RS800013-7H
MDI_2- 8 2 MDI_2-
MDI_3+ 7 4 MDI_3+ EMC@
MDI_3- 6 5 MDI_3-
RJ45_GND CL10 1 2 1000P_1808_3KV7k~D LANGND
1 1
CL11 CL12
EMC_NS@ EMC@
EMC@ 0.1U_0402_10V6-K .01U_0402_16V7-K
3

2 2

LANGND

20141231
A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 RJ45 CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 49 of 99

5 4 3 2 1
 +3V_WLAN

TYPE-A NGFF SLOT FOR WLAN +3VALW R236 1

@
2 0_0805_5%

3.2H CONNECTOR R237 1 @ 2 0_0805_5%

+3VS

+3V_WLAN

15/0708 JWLBT ME@

1 2
USB20_P6 3 GND1 3.3VAUX1 4
[15] USB20_P6 USB20_N6 USB_D+ 3.3VAUX2
5 6
[15] USB20_N6 USB_D- LED#1
7 8
GND2 NC
9 NC NC 10
11 NC NC 12
For RF solution. 13 NC NC 14
15
16
NC LED#2
17 18
+3V_WLAN 19 MLDIR_SENSE GND16 20 1 R151 2 0_0402_5% BT_ON_R
21 DP_ML3N DP_AUXN 22 @
CRF21 CRF22 23 DP_ML3P DP_AUXP 24
RF_NS@ RF_NS@ 25 GND3 GND13 26 1 R152 2 0_0402_5% EC_TX_R
27 DP_ML2N DP_ML1N 28 @
2200P_0402_50V7-K

47P_0402_50V8-J

29 DP_ML2P DP_ML1P 30
1 1 GND4 GND14
31 32
33 DP_HPD DP_ML0N 34
PCIE3_CTX_C_DRX_P 35 GND5 DP_ML0P 36
2 2 [15] PCIE3_CTX_C_DRX_P PCIE3_CTX_C_DRX_N PETP0 GND15 CL_RST_WLAN#
37 38
[15] PCIE3_CTX_C_DRX_N PETN0 RESERVED1 CL_DATA_WLAN CL_RST_WLAN# [11]
39 40
PCIE3_CRX_DTX_P GND6 RESERVED2 CL_CLK_WLAN CL_DATA_WLAN [11]
41 42
[15] PCIE3_CRX_DTX_P PCIE3_CRX_DTX_N PERP0 RESERVED3 CL_CLK_WLAN [11]
43 44
[15] PCIE3_CRX_DTX_N PERN0 COEX3
45 46
CLK_PCIE_WLAN 47 GND7 COEX2 48
[10] CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX1 SUSCLK_32K
49 50
[10] CLK_PCIE_WLAN# REFCLKN0 SUSCLK PLTRST_FAR# SUSCLK_32K [10]
51 52
CLKREQ_PCIE2_WLAN# GND8 PERST0# BT_ON_R PLTRST_FAR# [12,61,69]
53 54
[10] CLKREQ_PCIE2_WLAN# EC_WLAN_WAKE# CLKREQ0# RESERVED/W_DISABLE#2 RF_OFF#
55 56
[61] EC_WLAN_WAKE# PEWAKE0# W_DISABLE#1 RF_OFF# [14]
57 58
59 GND9 I2C_DATA 60
To EC 61 PETP1 I2C_CLK 62 R90 1 2 100_0402_1% EC_RX
PETN1 I2C_ALERT# EC_TX_R EC_TX EC_RX [61]
63 64 R89 1 2 100_0402_1%
GND10 RESERVED4 EC_TX [61]
65 66
67 PERP1 PERST1# 68
69 PERN1 CLKREQ1# 70
GND11 PEWAKE1#

1
71 72
73 REFCLKP1 3.3VAUX4 74
VPRO SKU : R48(@), R70(VPRO@) 75 REFCLKN1
GND12
3.3VAUX5 R91
100K_0402_5%
77 76
PEG1 PEG2

2
79 78 BT_ON_R R239 1 2 1K_0402_5%
+5VALW +3VALW +3V_WLAN NPTH1 NPTH2 BT_ON [14]
TYCO_2199230-8
1

3 1
S

R28
47K_0402_5% Q26
G
2

NVPRO@ R51 AO3413_SOT23-3

2

WLAN_PWRON# 1 2 NVPRO@

10K_0402_5% 1
D
1

R9460 NVPRO@
WLAN_PWRON 1 2 WLAN_PWRON_R 2 Q5 C75
[61] WLAN_PWRON
G 2N7002WT1G_1N_SC-70-3 .01U_0402_16V7-K
2 NVPRO@
1

0_0402_5% S SB00000YY00
3

NVPRO@
R69
100K_0402_5%
NVPRO@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 WWAN/WLAN NGFF CONN.

https://dr-bios.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom

Date:
BE560
Wednesday, September 23, 2015 Sheet 50 of 99
Re v
0.1
 5 4 3 2 1

UW1
40 mils 11 30 SD_CD#
+3VS 3V3_IN SD_CD#
D 18 31 D
+DV33_18 DV33_18 MS_INS#
AV12 10 32 RW20 2 1 10K_0402_5%
AV12 WAKE# +3VS
RW3
1 2
0_0603_5%
DV12 14
20141231
DV12S
DV12 connects with AV12, due
to DV12 need a external input. 15 SD_DATA1_R RW4 2 1 0_0402_5% SD_DATA1
SP1
12 16 SD_DATA0_MS_DATA1_R RW21 2 1 0_0402_5% SD_DATA0_MS_DATA1
+CRD_POWER Card_3V3 SP2 EMC@
RW18 0_0402_5% 17 SD_CLK_MS_DATA0_R RW22 2 1 0_0402_5% SD_CLK_MS_DATA0 CW11 1 2 5P_0402_50V9-C
2 1 +3V3_AUX 27 SP3
+3VS 3V3aux SD_CMD_MS_DATA2_R SD_CMD_MS_DATA2
375mA SP4
19 RW23 2 1 0_0402_5%

RW8 1 2 6.2K_0402_1% 9 20 SD_MS_DATA3_R RW24 2 1 0_0402_5% SD_MS_DATA3

RREF SP5
Close to chip 12mils, lengths < 200mils
21 SD_DATA2_MS_CLK_R RW25 2 1 0_0402_5% SD_DATA2_MS_CLK
SP6
PCIE6_CTX_C_DRX_P 3 29 SD_WP For EMI, please close to the chip
[15] PCIE6_CTX_C_DRX_P HSIP SP7
Close to chip
PCIE6_CTX_C_DRX_N 4
[15] PCIE6_CTX_C_DRX_N HSIN
CW9 1 2 0.1U_0402_10V7-K PCIE6_CRX_C_DTX_P 7
[15] PCIE6_CRX_DTX_P HSOP
CW10 1 2 0.1U_0402_10V7-K PCIE6_CRX_C_DTX_N 8 13
[15] PCIE6_CRX_DTX_N HSON NC_1
22
NC_2
CLK_PCIE_CR 5 23
[10] CLK_PCIE_CR REFCLKP NC_3
CLK_PCIE_CR# 6 24
[10] CLK_PCIE_CR# REFCLKN NC_4
25
NC_5
C PLTRST_NEAR# 1 26 C
[12,23,47] PLTRST_NEAR# PERST# NC_6

CLKREQ_PCIE5_CR# 2
[10] CLKREQ_PCIE5_CR# CLK_REQ#

+3VS RW11 1 2 10K_0402_5% 28 33 GND

GPIO GND

RTS5227S-GRT_QFN32_4X4

DV12 +DV33_18 AV12

20 mils 20 mils 20 mils +3VS +3VS

CW1 CW2 CW3 CW4

+CRD_POWER for Edge 15''
1

1
@ @
4.7U_0603_6.3V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

1 1 1 1 JREAD2
RW13 RW12 40 mils ME@
1U_0402_10V6-K

100K_0402_5% 100K_0402_5%
B
SD_CMD_MS_DATA2 2 B
2 2 2 2 3 CMD
VSS1
2

2
RW14 0_0402_5% 4
RW15 0_0402_5% SD_CLK_MS_DATA0 5 VDD
SD_CD#_R 2 1 SD_CD# SD_WP_R 2 1 SD_WP 6 CLK
VSS2

10U_0603_6.3V6-M
0.1U_0402_10V7-K
SD_DATA0_MS_DATA1 7
1 1 SD_DATA1 DAT0
8

CW13
SD_DATA2_MS_CLK DAT1
All of cap. close to chip 9

CW12
SD_MS_DATA3 1 DAT2
2 2 CD/DAT3

SD_WP_R 10
SD_CD#_R 11 W/P
+3VS +3V3_AUX C/D
40 mils 40 mils 12
13 GND1
CW5 CW6 CW7 CW8 GND2
EMC_NS@ EMC_NS@ Close to JREAD1.
SD_CLK_MS_DATA0 RW16 1 2 10_0402_5% CW14 1 2 10P_0402_50V8-J
10U_0603_6.3V6-M

0.1U_0402_10V7-K

0.1U_0402_10V7-K

4.7U_0603_6.3V6-K

1 1 1 1 SUYIN_250312HB011M106ZL

RW16 and CW14reserved for EMI.

2 2 2 2
Please close to conn.

20141231
Close to pin 11 Close to pin 27

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 Card Reader
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 51 of 99

5 4 3 2 1
 A B C D E

+5VS +1.8V_LDO +1.65V_LDO +3V_LDO

RA1
LDO 1V8 VREF 1V65 LDO 3V3
1 0_0805_5% +3VS 1
1 2 CA2 CA3 CA4 CA5 +5VS_CLASSD

1
C3505 close Pin7

4.7U_0603_10V6-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

0.1U_0402_10V7-K

CA6

CA7

CA8

CA9

CA10
1 1 1 1 CA1
2 1 1 1 1 1 0.1U_0402_10V7-K
CA11
2
2 2 2 2 2.2U_0402_6.3V6-M

0.1U_0402_10V7-K

4.7U_0603_10V6-K

0.1U_0402_10V7-K

1U_0402_6.3VA-K

0.1U_0402_10V7-K
1 2 2 2 2 2

X5R CAP X5R CAP

+3VS
Close to Pin13,16 RA28 1 2 0_0402_5% +3VS_VDDO

1
CA12
0.1U_0402_10V7-K
UA1
2 CA12 close Pin2
PCH_HDA_RST# 9 3
[9] PCH_HDA_RST# RESET# FILT_1.8V +1.8V_LDO
7
VDD_IO +3VS_VDDIO +3VL
2 RA30 0_0805_5%
PCH_HDA_BCLK VDDO_3.3 +3VS_VDDO
5 18 1 2
[9] PCH_HDA_BCLK BIT_CLK DVDD_3.3 +3VS_DVDD
PCH_HDA_SYNC +3V_AVDD_HP
[9] PCH_HDA_SYNC
8
SYNC AVDD_3.3
27 +3V_LDO 20141204 +3VALW
[9] PCH_HDA_SDIN0
PCH_HDA_SDIN0 RA5 1 2 33_0402_5% PCH_HDA_SDIN0_R 6 CX11852 VREF_1.65V
29
28
+1.65V_LDO
+5VS_AVDD
12/3 For PH noise
RA2 1 @ 2 0_0805_5%
PCH_HDA_SDOUT 4 SDATA_IN AVDD_5V
[9] PCH_HDA_SDOUT SDATA_OUT 1
PC_BEEP 10 12 SPK_L2+ CA13 +3VS
2 [55] PC_BEEP SPKR_MUTE# PC_BEEP LEFT+ SPK_L1- SPK_L2+ [55] 2
39 14 1U_0402_6.3VA-K RA3 2 @ 1 0_0805_5%
SPKR_MUTE# LEFT- SPK_L1- [55] 2
SPK_R2+
[55] JSENSE
JSENSE 38
37 JSENSE RIGHT+
17
15 SPK_R1- SPK_R2+ [55] C3537 close Pin24
GPIO1/PORTC_R_MIC RIGHT- SPK_R1- [55]
36 35
DMIC_CLK RA31 1 2 33_0402_5% MIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
[38] DMIC_CLK DMIC_DATA DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB +MICBIASB +3VS_DVDD +3VS
1 RA4
[38] DMIC_DATA DMIC_DAT/GPIO1 PORTB_R
33 0_0805_5%
PORTB_R_LINE PORTB_L PORTB_R [55]
32 1 2
PORTB_L_LINE PORTB_L [55]
CA16 1 2 0.1U_0402_10V7-K 11
+5VS_CLASSD CLASS-D_REF EXT_MIC_A
13 PORTD_A_MIC
30
31 EXT_MIC_B EXT_MIC_A [55] X5R CAP, Please Close Pin18
LPWR_5.0 PORTD_B_MIC EXT_MIC_B [55]
W= 80mils 16
RPWR_5.0 25 HGNDA
HGNDA HGNDA [55,72] 1
CA17 1 2 1U_0402_6.3V6-K 19 26 HGNDB
FLY_P HGNDB HGNDB [55,72]
20 CA14
FLY_N 24 1U_0402_6.3VA-K
AVDD_HP +3V_AVDD_HP 2
+AVEE +AVEE 21
CA18 AVEE 23 HP_OUTR
PORTA_R HP_OUTL HP_OUTR [55]
41 22
2.2U_0402_6.3V6-M

HP indicate 1 GND PORTA_L HP_OUTL [55]

Should be Apple --> EXT_MIC_A, HGNDB

2 connect to CX11852-11Z_QFN40_5X5 Nokia --> EXT_MIC_B, HGNDA
GNDA +5VS_AVDD RA32 +5VS
0_0805_5%
1 2

38 31
1 AGND 1
CA15
1U_0402_6.3VA-K
3 DGND 2 3
21
11
Please Close Pin28

RF, close to RA7

+3VS_VDDO

DMIC_CLK
+3VALW_PCH +3VS
1
CA40
1

EMC@ +3VS_VDDIO
150P_0402_50V8-J RA29 RA25 1 2 0_0402_5%
2 W= 300mils @
15/0519 47K_0402_5%
+3VS_VDDIO
EMC_NS@ RA27 1 2 0_0402_5%
CA19 1 2 0.1U_0402_10V7-K
2

DMIC_DATA 1

1 CA42
CA43 DA5 4.7U_0603_10V6-K
RF_NS@ EC_MUTE# 1 2 SPKR_MUTE# 2
47P_0402_50V8-J
[61] EC_MUTE# GND GNDA
2 RB751V-40_SOD323-2
SCS00006S00
CA42 close Pin7

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 Audio Codec
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 54 of 99

A B C D E
 5 4 3 2 1

D D

PC Beep
+3VS
CA22 1 @ 2 0.1U_0402_10V7-K

1
EC Beep 2
DA1 RA18
5.11K_0402_1%
[61] BEEP#
CA24
RA11

2
1 1 2 1 2 PC_BEEP
PC_BEEP [54] JSENSE_CON
PCH Beep JSENSE RA20 2 1 20K_0402_1% JSENSE_CON [72]
33_0402_5% [54] JSENSE
3 0.1U_0402_10V7-K
[9] PCH_BEEP
RA21 2 1 39.2K_0402_1%
BAT54CW_SOT323-3

1
CA23 1 @ 2 0.1U_0402_10V7-K

RA13
10K_0402_5%

2
C C

Apple --> EXT_MIC_A, HGNDB

EXT. MIC/LINE IN Nokia --> EXT_MIC_B, HGNDA

[54] EXT_MIC_A
EXT_MIC_A RA14 1 2 100_0402_5% CA29 1 2 2.2U_0402_6.3V6-K HGNDB
HGNDB [54,72]
Speaker OUT SPK CONN.
EXT_MIC_B RA15 1 2 100_0402_5% CA30 1 2 2.2U_0402_6.3V6-K HGNDA
[54] EXT_MIC_B HGNDA [54,72]
15/0519 Need Lenght Match ME update PN
Changed CA29 & CA30 from 1uF to 2.2uF/X5R SPK_L1- RA8 1
EMC@
2 BLM18PG221SN1D_2P SPK_L1-_CON SPK_R2+_CON 1
JSPK ME@
[54] SPK_L1-
to meet Port-D(headset-Mic) THD+N <= -65 dB SPK_L2+ RA9 1
EMC@
2 BLM18PG221SN1D_2P SPK_L2+_CON
SPK_R1-_CON
SPK_L2+_CON
2
3
1
2
[54] SPK_L2+ SPK_L1-_CON 3
EMC@ 4
SPK_R1- RA10 1 2 BLM18PG221SN1D_2P SPK_R1-_CON 4
[54] SPK_R1-
EMC@ 5
SPK_R2+ RA12 1 2 BLM18PG221SN1D_2P SPK_R2+_CON 6 GND1
[54] SPK_R2+ GND2

HeadPhone/LINE OUT RB751V-40_SOD323-2

TYCO_2041180-4

RA16 1 2 3K_0402_5% 1 2 DA6 +MICBIASB

B 15/0519 B
SCS00006S00
HP_OUTL RA17 1 2 75_0402_5% HP_OUTL_CON EMC@
[54] HP_OUTL HP_OUTL_CON [72] SPK_L1-_CON
CA25 1 2 470P_0402_50V7-K
CA31 EMC@
PORTB_L RA19 SPK_L2+_CON
[54] PORTB_L 1 2 1 2 CA26 1 2 470P_0402_50V7-K
EMC@
100_0402_5% SPK_R1-_CON
10U_0603_6.3V6-M CA27 1 2 470P_0402_50V7-K
EMC@
CA28 1 2 470P_0402_50V7-K SPK_R2+_CON
RB751V-40_SOD323-2
RA22 1 2 3K_0402_5% 1 2 DA7
+MICBIASB
EMI parts
SCS00006S00
HP_OUTR RA23 1 2 75_0402_5% HP_OUTR_CON
[54] HP_OUTR HP_OUTR_CON [72]
CA32
PORTB_R RA24
[54] PORTB_R 1 2 1 2
100_0402_5%
10U_0603_6.3V6-M

CA31, CA32 change to 4.7U for Quality requirement

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 HP/MIC JACK/Speaker
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 55 of 99

5 4 3 2 1
 5 4 3 2 1

D
CABLE D

JU3LC
24
23 G4
EMC_NS@ +3VS 22 G3
R163 1 2 0_0402_5% 21 G2
USB3P4_RXN_COAX_CON 20 G1
EMC@ DOCK_AUX# USB3P4_RXP_COAX_CON 20
R106 1 2 100K_0402_5% 19
EXC24CH900U_4P DOCKING 18 19
USB20_N3 4 3 USB20_N3_FFC_CON R107 1 2 100K_0402_5% DOCK_AUX USB3P4_TXN_COAX_CON 17 18
[15] USB20_N3 4 3 USB3P4_TXP_COAX_CON 17
16
15 16
USB20_P3 1 2 USB20_P3_FFC_CON USB3P3_RXN_COAX_CON 14 15
[15] USB20_P3 1 2 USB3P3_RXP_COAX_CON 14
13
L5 12 13
EMC_NS@
SUB/B USB3P3_TXN_COAX_CON 11 12
R164 1 2 0_0402_5% USB3P3_TXP_COAX_CON 10 11
9 10
DOCK_TX1- 8 9
[42] DOCK_TX1- DOCK_TX1+ 8
7
[42] DOCK_TX1+ 7
EMC_NS@ 6
R177 1 2 0_0402_5% +5VALW DOCK_TX0- 5 6
[42] DOCK_TX0- DOCK_TX0+ 5
4
EMC@ [42] DOCK_TX0+ 4
3
EXC24CH900U_4P DOCK_AUX# 2 3
USB20_N4 USB20_N4_FFC_CON [42] DOCK_AUX# DOCK_AUX 2
4 3 1
[15] USB20_N4 4 3 [42] DOCK_AUX 1
1 1 ACES_50406-02071-001
USB20_P4 1 2 USB20_P4_FFC_CON C171 C172 ME@
[15] USB20_P4 1 2 @ @
L13 .01U_0402_16V7-K 1U_0402_6.3VA-K
EMC_NS@ 2 2
R178 1 2 0_0402_5%
C C

EMC_NS@
R169 1 2 0_0402_5%
EMC@
EXC24CH900U_4P
USB3P3_RXN 4 3 USB3P3_RXN_COAX_CON
[15] USB3P3_RXN 4 3

USB3P3_RXP 1 2 USB3P3_RXP_COAX_CON
[15] USB3P3_RXP 1 2
L6

R170 1 2 0_0402_5% +3VALW +5VALW

EMC_NS@

1
EMC_NS@
R176 1 2 0_0402_5% R233 R234
100K_0402_5% 100K_0402_5%
EMC@
@ @
EXC24CH900U_4P

2
USB3P3_TXN 4 3 USB3P3_TXN_COAX_CON
[15] USB3P3_TXN 4 3
ONEDOCK_DET#
FFC
USB3P3_TXP USB3P3_TXP_COAX_CON ONEDOCK_DET# [15]
1 2
[15] USB3P3_TXP 1 2 JU3LF

2
L12 1
EMC_NS@ R235 USB_OC2# 2 1
[15] USB_OC2# USB_ON# 2
R175 1 2 0_0402_5% 0_0402_5% 3
[45,61] USB_ON# 3
@ 4
EC_SMB_DA3 5 4
[11,28,61,66,68] EC_SMB_DA3 5

1
EC_SMB_CK3 6
[11,28,61,66,68] EC_SMB_CK3 6
B EMC_NS@ 7 B
R172 1 2 0_0402_5% DOCKDP_HPD 8 7
[42] DOCKDP_HPD DOCK_CONSUMP 8
9
EMC@ [75] DOCK_CONSUMP ONEDOCK_DET# 9
10
EXC24CH900U_4P LID_SW# 11 10
USB3P4_RXN USB3P4_RXN_COAX_CON [61,64] LID_SW# 11
4 3 ON/OFF# 12
[15] USB3P4_RXN 4 3 [61,65] ON/OFF# 12
13
14 13
USB3P4_RXP 1 2 USB3P4_RXP_COAX_CON 15 14
[15] USB3P4_RXP 1 2 +5VALW 15
16
L7 DOCKDP_HPD 17 16
18 17
+5VS 18
R171 1 2 0_0402_5% +3VS 19
EMC_NS@ 20 19
+3VL 20
21
USB20_N3_FFC_CON 21

1
22
R108 USB20_P3_FFC_CON 23 22
EMC_NS@ 24 23
100K_0402_5% 24
R174 1 2 0_0402_5% USB20_N4_FFC_CON 25 27
@ USB20_P4_FFC_CON 25 GND1
26 28
EMC@ 26 GND2

2
EXC24CH900U_4P
USB3P4_TXN 4 3 USB3P4_TXN_COAX_CON
[15] USB3P4_TXN 4 3 HIGHS_FC5AF261-1151H
USB3P4_TXP USB3P4_TXP_COAX_CON ME@
1 2
[15] USB3P4_TXP 1 2
L8

R173 1 2 0_0402_5%
1. AC Capacitor place on Sub/B
2. Need to check with MUX IC vendor
EMC_NS@ whether st ill need AC cap bet weenMUX I C and devi ce.

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DOCKING/ DCIN CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 60 of 99

5 4 3 2 1
 5 4 3 2 1

1 RE1 2 PECI
[6] H_PECI
43_0402_5%
1
@
CE1
47P_0402_50V8-J
2

Intel recommend +3VL

Vcc 3.3V +/- 5%

+3VL
RE3 100K +/- 1%
All capacitors close to EC

2
+3VL RE3
Board ID RE7 VAD_BID min V AD_BID typ VAD_BID max Phase
D
+3VL CE4 CE5 CE8 CE6 CE9 CE10
100K_0402_1%
0 0K +/- 5% 0 V 0 V 0 V SDV D
RE4
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V FVT

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K

0.1U_0402_25V6-K
1 2 W RST#

1
100K_0402_5% 1 1 1 1 1 1 Board_ID
1
CE11 Close to EC +3VS +3VL_AVCC
@ @ 2 18K +/- 5% 0.436 V 0.503 V 0.538 V SIT
CE7 3 33K +/- 5% 0.712 V 0.819 V 0.875 V SVT

1
1U_0402_10V6-K 1 2 +VCOREVCC 2 2 2 2 2 2
2
0.1U_0402_25V6-K
RE7 4 4.7K +/- 5% 0.141 V 0.148 V 0.155 V
33K_0402_5%
5 24K +/- 5% 0.612 V 0.638 V 0.664 V

2
114
121
127
minimum trace width 12 mil

11

74
12

26
50
92
3
+3VALW UE1

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VCC

VSTBY5
VSTBY(PLL)
VBAT

VCORE

AVCC
RE15 1 2 100K_0402_5% HDD_DETECT#

15/05/19
KBRST# 4 24 LOGO_LED#
[11] KBRST# SERIRQ 5 KBRST#/GPB6 PWM0/GPA0 25 AOU_IFG# LOGO_LED# [38,72]
[11,69] SERIRQ LPC_FRAME# SERIRQ/GPM6 PWM1/GPA1 EC_ON2_R AOU_IFG# [45]EC_ON2
+3VALW [11] LPC_FRAME# LPC_AD3
6
7 LFRAME#/GPM5 PWM2/GPA2
28
29 ALL_PW RGD
RE42 1 2
0_0402_5%
EC_ON2 [87,88] 20141226 RE41
10K_0402_5%
+3VS
[11] LPC_AD3 LPC_AD2 LAD3/GPM3 PWM3/GPA3 VR_ON_EC ALL_PW RGD
[11] LPC_AD2 LPC_AD1
8
LAD2/GPM2
PWM PWM4/GPA4
30
EC_FAN_PW M
RE56 1 2 0_0402_5%
VR_ON [12,79]
1 2
RPE1 9 31
1 8 [11] LPC_AD1 LPC_AD0 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PW M [65]
BEEP#
2 7 AOU_IFG# [11] LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 VCCST_PG_EC BEEP# [55]
KB_FN [11] CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7
34
VCCST_PG_EC [12]
3 6 W RST# 14 120
4 5 EC_W LAN_W AKE# HDD_DETECT# 15 WRST# TMRI0/GPC4 124 SUSP#_EC
[43] HDD_DETECT# EC_RX ECSMI#/GPD4 TMRI1/GPC6 +3VL +3VL_AVCC
16
[50] EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66 GPU_VR_HOT#
10K_0804_8P4R_5% GPU_VR_HOT# [28,83] RC431 LE1
[50] EC_TX PLTRST_FAR# 22 LPCPD#/GPE6 ADC0/GPI0 67 CP_BYPASS_EC 1 0_0402_5%
2 CP_BYPASS 1 2 +3VL_AVCC
[12,50,69] PLTRST_FAR# EC_SCI# 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP CP_BYPASS [14,67]
BATT_TEMP [74,75] @
[11] EC_SCI# VGA_AC_DC# ECSCI#/GPD3 ADC2/GPI2 Board_ID
RPE2
[28] VGA_AC_DC#
126
GA20/GPB5 ADC ADC3/GPI3
69
FAN_ID
BLM18PG121SN1D_2P
1
2
3
8
7
6
KSO1
KSO2
FAN_ID
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
70
71
72
ADP_I
TP_REST_EC
FAN_ID
ADP_I [75]
[65]
RC432
1 0_0402_5%
2 TP_REST
15/0708 1

CE2
1

CE3
4 5 LAN_W AKE#
KSI[0..7] KSI0 58
LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 ADP_ID
ADP_ID [73] @
TP_REST [14,67]
2
0.1U_0402_25V6-K
2
1000P_0402_50V7-K
[64] KSI[0..7] KSI1 59 KSI0/STB# 78 VGATE
10K_0804_8P4R_5% VGATE [79] LE2
KSO[0..17] KSI2 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPW ON_EC EC_AGND 1 2
[64] KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT_EC MAINPW ON_EC [73,74,78]
C KSI3 61
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
80 C
KSI4 62 81 ENBKL ENBKL [5] BLM18PG121SN1D_2P
RE40 1 2 10K_0402_5% EC_W AKE# KSI5 63 KSI4 DAC5/RIG0#/GPJ5
KSI6 64 KSI5 85 AOU_EN
20150105 KSI7 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 PBTN_OUT# AOU_EN [45]
KSO0 36 KSI7 PS2DAT0/TMB1/GPF1 87 PCH_SLP_LAN# PBTN_OUT# [12]
KSO0/PD0 GPF2 PCH_SLP_W LAN# PCH_SLP_LAN# [12,47]
KSO1 37 Int. K/B PS2 88 +5VALW
KSO1/PD1 GPF3 CP_CLK PCH_SLP_W LAN# [12]
KSO2 38 89 RE2
+3VS KSO3 39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 CP_DATA CP_CLK [67]
10K_0402_5%
40 KSO3/PD3 PS2DAT2/GPF5 CP_DATA [67] USB_ON# 1 2
RPE3 KSO4
1 8 LPC_FRAME# 41 KSO4/PD4 EC_DPW ROK
EC_FAN_SPEED
KSO5
KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3
96
LAN_PW RON EC_DPW ROK [12]
+3VL 2 7 KSO6 42 97
3 6 KSO7 43 KSO6/PD6 GPH4/ID4 98 ACOFF LAN_PW RON [47]
4 5 LID_SW # KSO8 44 KSO7/PD7 GPH5/ID5 99 PCH_PW ROK ACOFF [75] +5VS
45 KSO8/ACK# GPH6/ID6 PCH_PW ROK [12]
KSO9
10K_0804_8P4R_5% KSO10 46 KSO9/BUSY 101 FSCE# CP_CLK RE5 1 2 4.7K_0402_5%
51 KSO10/PE NC1 102 SPI_FMOSI# FSCE# [23]
KSO11
KSO11/ERR# NC2 SPI_FMISO SPI_FMOSI# [23]
KSO12 52
KSO12/SLCT SPI Flash ROM NC3
103
SPI_FSCK SPI_FMISO [23] CP_DATA
KSO13 53 105 RE6 1 2 4.7K_0402_5%
54 KSO13 NC4 SPI_FSCK [23]
KSO14
RPE4 KSO15 55 KSO14
1 8 SUSP#_EC KSO16 56 KSO15 108 ACIN +3VS
KSO16/SMOSI/GPC3 AC_IN# LID_SW #
2 7 KSO17 57
KSO17/SMISO/GPC5 UART LID_SW#
109
LID_SW # [60,64] EC_FAN_PW M
3 6 RE8 1 @ 2 10K_0402_5%
4 5 SYSON_EC
PCH_SYSPW ROK
15/0708 [60,65] ON/OFF# ON/OFF# 110
PWRSW# EGAD/GPE1
82
EC_ON PCH_SYSPW ROK [12] GPU_VR_HOT#
100K_0804_8P4R_5% 111 SM Bus 83 RE9 1 2 10K_0402_5%
EC_SMB_CK1 XLP_OUT EGCS#/GPE2 AOU_CTL1 EC_ON [78]
115 84
[74,75] EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 AOU_CTL1 [45]
@
[74,75] EC_SMB_DA1 SMDAT1/GPC2 PM_SLP_S5#
CE14 2 1 0.1U_0402_25V6-K PECI 117
ADAPTER_ID_ON# 118 SMCLK2/PECI/GPF6 GPIO GPJ1
77
EC_MUTE# PM_SLP_S5# [12] Un-stuff if not necessary.
For EMC [73] ADAPTER_ID_ON# EC_SMB_CK3 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
100
106 EC_GS_ON# EC_MUTE# [54]
[11,28,60,66,68] EC_SMB_CK3 EC_SMB_DA3 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 104 ME_FLASH EC_GS_ON# [68]
[11,28,60,66,68] EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON_EC ME_FLASH [9]
DTR1#/SBUSY/GPG1/ID7 119 BKOFF#
CRX0/GPC0 123 W LAN_PW RON BKOFF# [38]
112 CTX0/TMA0/GPB2 18 PM_SLP_S3# W LAN_PW RON [50]
+3VL +3VL LAN_W AKE# VSTBY0 RI1#/GPD0 PM_SLP_S4# PM_SLP_S3# [12] +3VL
125 21
[47] LAN_W AKE# GPE4 RI2#/GPD1 PM_SLP_A# PM_SLP_S4# [12]
RPE5 W AKE UP 76 MIRROR@
EC_SMB_CK1 TACH2/GPJ0 AOU_CTL3 PM_SLP_A# [12]
1 8
EC_SMB_DA1
15/0708 TACH1A/TMA1/GPD7
48
EC_FAN_SPEED AOU_CTL3 [45] EC_ON
+3VS 2 7 47 RE39 1 2 10K_0402_5%
EC_SMB_DA3 USB_ON# TACH0A/GPD6 EC_W LAN_W AKE# EC_FAN_SPEED [65]
B 3 6 33 19 B
EC_SMB_CK3 [45,60] USB_ON# CP_RESET# 1 RC430 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 EC_W LAN_W AKE# [50]
4 5 2 0_0402_5% CP_RESET#_EC 35 GPIO 20 KB_FN
[14,67] CP_RESET# EC_RSMRST# RTS1#/GPE5 L80LLAT/GPE7 KB_FN [64] +3VL
@ 93
[12] EC_RSMRST# CLKRUN#/GPH0/ID0
2.2K_0804_8P4R_5%
20150105 EC_W AKE# 2
Please don't place any PU Resistor on GPG[7:2] +3VALW
EC_MUTE# RE31 1
MIRROR@
2 10K_0402_5%
[6] EC_W AKE# AC_PRESENT 128 CK32KE/GPJ7
Clock
(Reserve hardware strapping) 15/0714 RE52
[12] AC_PRESENT CK32K/GPJ6 1 2 1 2
RE32 @ 10K_0402_5%
5.1K_0402_1%
RE54
SYSON_EC 1 2 SYSON
SYSON [70,71,86] 1. Version CX : Don't Support Mirror Code
Version DX/EX/FX : Support Mirror Code
AVSS

0_0402_5% D64 @
VSS1

VSS2
VSS3
VSS4
VSS5
VSS6

2 1 PM_SLP_S4#
2. For Mirror Code
+3VS IT8586E-AX_LQFP128_14X14 IT8586E/FX LQFP RB521CM_30 "H" --> Enable
1

27
49
91
113
122

75

SA00005W940 15/0522 +3VALW

RE53 @ "L" --> Disable (Default)
EC_AGND
10K_0402_5%
1 2 *
2

RE51 @ RE55
SUSP#_EC 1 2 SUSP#
10K_0402_5% SUSP# [70,71,86]
0_0402_5% D65 @
PM_SLP_S3#
1

@ 2 1
D59 +3VL
PM_SLP_S3# 1 2 VR_ON
RB521CM_30 ACIN RE33 1 2 10K_0402_5%
RB521CM_30 AC IN, need to conf i r m t hepi n i sHi gh or Lo wac t i ve RE43 1 2 0_0402_5%
while pulg ACIN ACPRN [75]

DEV1 @ 2 1 RB751V-40_SOD323-2

For ESD
PROCHOT# For factory EC f l as h CE12 1 2 100P_0402_50V8-J
(EC asserts PROCHOT# signal by driving high, 1 EC_SMB_CK1
EMC_NS@
CE13 1 2 220P_0402_50V7-K PLTRST_FAR# the level shif t er must i nvert it and dri ve t hepr ocess or si dePROCHOT# l o w.) IT1
IT2
@1 EC_SMB_DA1
A A
@1
IT3
For EMI IT4
@1
RE38 @1
VR_HOT# IT5
EMC_NS@ 10_0402_5% @
CE15 1 2 10P_0402_50V8-J 1 2 CLK_PCI_EC [6,75,79] VR_HOT#
EMC_NS@ 1
D
1

CE17 1 KSI7
H_PROCHOT_EC 2 IT6
@1 KSI6
2 1 BATT_TEMP IT7
CE16 100P_0402_50V8-J G 47P_0402_50V8-J @1 W RST#
2 IT8
QE1 S @
3

EMC@
BATT_TEMP 璶  璶E C   ADC p i n 2N7002W T1G_1N_SC-70-3

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 EC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 61 of 99

5 4 3 2 1
 5 4 3 2 1

D D

TOUCH PANEL CONN. +3VS

+3VS

1 1
C115 C116
@ @

1
0.1U_0402_10V6-K 0.1U_0402_10V6-K
EMC_NS@ R217 2 2
R9472 1 2 0_0402_5% TS@
LID_SW# 100K_0402_5%
[60,61] LID_SW#
D11

2
TS@ JTOUCH ME@
L22 RB521CS-30GT2RA_VMN2-2 1
USB20_N5 1 2 USB20_N5_CON 1 2 TS_OFF# 2 1
[15] USB20_N5 1 2 2
1 2 3
[14] PCH_TSOFF# USB20_N5_CON 3
4
USB20_P5 USB20_P5_CON USB20_P5_CON 4
[15] USB20_P5
4
4 3
3 D60
TS@
5
6 5 20141231
EXC24CH900U_4P RB521CS-30GT2RA_VMN2-2 7 6
8 7
EMC@ 8
R9473 1 2 0_0402_5%
20150105 9
10 9
EMC_NS@ 10
11
12 GND1
GND2
ACES_50463-0104A-P01
C C

RTC CONN. KB CONN

JKB ME@

KSI[0..7] KSI1 1
[61] KSI[0..7] 1
KSI7 2
KSO[0..17] KSI6 3 2
R112 [61] KSO[0..17] 3
D6 JRTC ME@ KSO9 4
1 2 1 2 1 KSI4 5 4
+RTCBATT 1 5
2 KSI5 6
RB751V-40_SOD323-2 1K_0603_5% 2 KSO0 7 6
SCS00006S00 3 KSI2 8 7
4 GND1 KSI3 9 8
GND2 KSO5 10 9
TE_2041180-2 KSO1 11 10
KSI0 12 11
B B
KSO2 13 12
KSO4 14 13
KSO7 15 14
KSO8 16 15
KSO6 17 16
KSO3 18 17
KSO12 19 18
KSO13 20 19
KSO14 21 20
KSO11 22 21
R111 KSO10 23 22
300_0402_5% KSO15 24 23
1 2 25 24
+3VS FN_LED# 25
26
[14] FN_LED# F1_LED# 26
[14] F1_LED# F4_LED#
27
28 27 20141231
[14] F4_LED# KB_FN 28
29
[61] KB_FN 29
30
KSO16 31 30 33
KSO17 32 31 GND1 34
32 GND2

JAE_FL10F032HA2R3000

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 KB/RTC/TOUCH PAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 64 of 99

5 4 3 2 1
 5 4 3 2 1

D D

FAN CONN.
PWR BTN/LID SW CONN.
+5VS
40mil
R68 0_0603_5%
+VCC_FAN1
2 1
For 14" on board
For 15" on Sub/B
JFAN ME@
1
[61] EC_FAN_PWM 1
2
3 2
[61] EC_FAN_SPEED 3
4 6
5 4 G1 7
C [61] FAN_ID 5 G2 C
ACES_85205-05001 ON/OFF Switch --> 簿 簿Sub/ B
For RF solution.

惠 AMD
惠惠惠T 惠絋HERM
惠 PI絋AL
絋 N絋 絋 d e fi e
n +VCC_FAN1

+3VL
CRF17 CRF18 SW1 DEBUG@
1 3

2200P_0402_50V7-K

47P_0402_50V8-J
RF_NS@ RF_NS@

1
1 1 Power Button 2 4

NTC010-AK1G-B160T_4P R71
100K_0402_5%
2 2

2
J1
Bottom Side 1 2 ON/OFF#
ON/OFF# [60,61]
SHORT PADS
@

FingerPrint CONN.
B B

+3VS

R70
Lid Switch --> 簿 簿Sub/B
0_0402_5% JFPB ME@
2 1 +3VS_FP 1
USB20_P9 2 1
[15] USB20_P9 USB20_N9 2
20141126[15] USB20_N9
3
4 3
4
3

1 5
C52 6 5
3

D4 EMC_NS@ FPR@ 6
AZC199-02SPR7G_SOT23-3 0.1U_0402_10V6-K 7
2 8 GND1
1

GND2
1

ACES_88514-0060N-071

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 PBTN/LID/FP/FAN CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 65 of 99

5 4 3 2 1
Thermal Sensor
Thermal Sensor
placed near by VRAM
U1
+3VS

1 10 EC_SMB_CK3
VCC SCL EC_SMB_CK3 [11,28,60,61,68]
REMOTE1+ 2 9 EC_SMB_DA3
DP1 SDA EC_SMB_DA3 [11,28,60,61,68]
1
C1 REMOTE1- 3 8
DN1 ALERT#
0.1U_0402_10V6-K REMOTE2+ 4 7 R3 1 @ 2 10K_0402_5% +3VS
2 DP2 THERM#
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10

Address 1001_101xb
Internal pull up 1.2K to 1.5V
R for init i al t her mal s hut do wn t e mp

Close to U1 Close to +VCC_CORE Close JDIMM1&JDIMM2

REMOTE1+ REMOTE2+ REMOTE1+ REMOTE2+ REMOTE2+/-:
Trace width/space:10/10 mil
1 1 1 1
Trace length:<8"

1
C C
C2 C3 C4 @ 2 Q1 C5 @ 2 Q2
2200P_0402_50V7-K 2200P_0402_50V7-K 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3 100P_0402_50V8-J B S TR TTC4116FU NPN SC-70-3
2 2 2 E SB000010U00 2 E SB000010U00

3
REMOTE1- REMOTE2- REMOTE1- REMOTE2-

Security Classification LC Future Center Secret Data Title

Issued Date 2013/09/07 Deciphered Date 2014/09/07 Thermal Sensor

https://dr-bios.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom

Date:
BE560
Wednesday, September 23, 2015 Sheet 66 of 99
Re v
0.1
 5 4 3 2 1

D D

+3VS
Track point
R60
1 2

4.7K_0402_5%
+5VS JTP
R59 @ TP_DATA2 1
20141231
1 2 TP_RESET 2 1
3 2
4.7K_0402_5% 4 3
5 4
TP_CLK2 6 5
7 6
8 7
9 8
+5VS 10 9
11 10 13
12 11 GND1 14
12 GND2
R63 1 2 4.7K_0402_5% TP_CLK2

TP_DATA2 JAE_FL10F012HA1R3000
R65 1 2 4.7K_0402_5%
C ME@ C

AMD TP_REST has PU

+3VS
CP_RESET#
15/0525 R67 1 2 100K_0402_5%
2

RC413
10K_0402_5%
TP_REST 1 2 TP_RESET

Click Pad
R64 0_0402_5%
+5VS
1

R66 1 @ 2 0_0402_5% BYPASS_PAD

2
RL20
0_0603_5%
R105 1 2 0_0402_5%
[14,61] CP_BYPASS

1
JCP ME@
1
PM_SMB_CLK 2 1
[11,23,25,26] PM_SMB_CLK 2
3
TP_DATA2 4 3
TP_CLK2 5 4
PM_SMB_DAT 6 5
[11,23,25,26] PM_SMB_DAT 6
7
CP_RESET# 8 7
[14,61] CP_RESET# CP_CLK 8
9 13
[61] CP_CLK CP_DATA 9 GND1
B 10 B
[61] CP_DATA TP_REST 10
11 14
[14,61] TP_REST BYPASS_PAD 11 GND2
12
12
1 1

2
R61 C44 @ @ C45
4.7K_0402_5% @ 100P_0402_50V8J 100P_0402_50V8J ACES_50506-01201-AT1
2 2

1
A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 CP/TPOINTCONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 67 of 99

5 4 3 2 1
 A B C D E

1 1

+3VALW +3VALW_GS

RG1 1 @ 2 0_0402_5%

3 1 +3VALW _GS

D
1 QG1 1 1
CG1 AO3413_SOT23-3 CG3

G
2
W=40 mils @
0.1U_0402_10V6-K @
CG2
.01U_0402_16V7-K
10U_0603_6.3V6-M
@
2 2 2

RG4 TABLE
1 2
[61] EC_GS_ON#
100K_0402_5% 1
CG4
P/N Mode Selection
.01U_0402_16V7-K
2
+3VALW_GS
H I2C Mode

2 L SPI Mode 2

APS G-Sensor
+3VS +3VALW_GS
TABLE

1U_0402_10V6K

10U_0603_6.3V6-M
1 1
P/N ADDR_SEL Address

CG5

CG6
RG5 RG6
2 2
10K_0402_5% 10K_0402_5%
H 32h (W) & 33h (R)
LIS3DH

14
1

1
L 30h (W) & 31h (R) UGSEN1

Vdd
Vdd_IO
8
I2C_CLK_GSENSE 4 CS
I2C_DATA_GSENSE 6 SCL/SPC
H 3Eh (W) & 3Fh (R) ADDR_SEL 7 SDA/SDI/SDO
KX023-1025 SDO/SA0 11 GSENSE_INT
L 3Ch (W) & 3Dh (R) 16 INT1 9 GSENSE_INT2 1
ADC1 INT2 TG1
15
13 ADC2 10
ADC3 RES

2
2

GND_1

GND_2
RG8 3 NC_1
NC_2
10K_0402_5%
+3VALW_GS

12
LIS3DHTR_LGA16_3x3
3 3

RG7 1 @ 2 0_0402_5% GSENSE_INT

2
G

I2C_CLK_GSENSE 1 6
S

EC_SMB_CK3 [11,28,60,61,66]
D

QG2A
5

2N7002KDWH_SOT363-6
G

I2C_DATA_GSENSE 4 3
S

EC_SMB_DA3 [11,28,60,61,66]
D

QG2B
2N7002KDWH_SOT363-6 PU AT EC SIDE, +3VS AND 4.7K

20141204

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 G SENSOR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 68 of 99

A B C D E
 A B C D E

5 ms < t
NOTE:
1) It is recommended to connect the TPM to the system's
standby voltage to improve performance.
2) SPI_RST# must be asserted for at least 5 msec after
1 0 < t VSB power-up. 1
VSB 3) VSB may come up anytime before VDD power-up,
but not after VDD power-up.
4) SPI_RST# may be asserted together with VDD power
VDD negation, but should not at any point exceed 0.5V
above the VDD power level.
1 ms < t

SPI_RST#

+3VS
TPM IC
1 1
C50
TPM@ C51 TPM@
0.1U_0402_10V6-K 10U_0603_6.3V6-M
2 2

+3V_SPI
2 2

NOTE:
Place 0.1 uF capacitors as close as
possible to the device power pins. 1 1 1 1
C8499 C8498 C8497 C8496 +3V_SPI +3VS
TPM@ TPM@ TPM@ TPM@

2
10U_0603_6.3V6-M

0.1U_0402_10V6-K

0.1U_0402_10V6-K

0.1U_0402_10V6-K
2 2 2 2 R9477
10K_0402_5% +3V_SPI

2
TPM@
R9480

22

14
UTPM1

1
TPM@ @ 10K_0402_5%

VSB
VDD2

VDD1
VDD3

1
15 4 PP 1 TP940
SERIRQ R9478 1 @ 2 0_0402_5% SERIRQ_R 18 LAD3 PP 3 GPIO2 1 3

S
[11,61] SERIRQ SPI_SI SPI_SI_R LAD2/SPI_IRQ GPX/GPIO2
R9479 1 TPM@ 2 33_0402_5% 21 30 GPIO01 1
[11,23] SPI_SI SPI_SO SPI_SO_R LAD1/MOSI SCL/GPIO1
R9481 1 TPM@ 2 33_0402_5% 24 TP120 Q27
[11,23] SPI_SO SPI_CS2#_TPM SPI_CS2_R LAD0/MISO
R9482 1 TPM@ 2 33_0402_5% 20 AO3413_SOT23-3

G
[11] SPI_CS2#_TPM LFRAME/SCS

2
2
27 TPM@
SPI_CLK R9483 1 TPM@ 2 33_0402_5% SPI_CLK_L 19 SERIRQ 29 R9489
[11,23] SPI_CLK LCLK/SCLK XOR_OUT/SDA/GPIO0 6 GPIO03 1 TP121 TPM@ 10K_0402_5%
TP124 1 GPIO04 13 GPIO3/BADD 5
PLTRST_FAR# 17 CLKRUN/GPIO04/SINT TEST Q27_G 1 TPM@ 2 SPI_CS2_R
[12,50,61] PLTRST_FAR# LRESET/SPI_RST/SRESET

1
R9491
NOTE: 28 2 100_0402_5%
Follow the SPI topology layout guidelines LPCPD NC1 7
in the relevant Intel Platform Design Guide. NC2 10
NC3 11
NC4
12
Reserved NC5
25 15/0519
3 26 3
NC6

2
31
R9484 NC7
10K_0402_5% 33
Q27 R9480 R9489 R9491

GND4
GND1

GND2

GND3
TPM@ EX-PAD

New silicon
1

NPCT650LA0YX_QFN32_5X5
NPCT650LB0YX X O X X

16

23

32
Current silicon
NPCT650LA0YX O X O O

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 69 of 99

A B C D E
 5 4 3 2 1

15/0519
+1VALW +VCC_ST

+1VALW to +VCC_IO_AP
3A
D D
+5VS +1VALW +VCC_IO_AP

Q23
AO4430L_SO8 U148
8 1
7 2 15/0522

1
+5VALW 6 3 A1 A2
R9485 5 IN OUT
10K_0402_5% 1 1 R9492 1
C8536 C8537 1 2 B1 B2
[61,71,86] SYSON EN GND

4
4.7U_0603_6.3V6-K 0.1U_0402_10V7-K C8544

2
@ 0_0402_5% 0.1U_0402_10V7-K
2 2 2
1

SIP32451DB-T2-GE1_WCSP4

2
R9486
100K_0402_5% R9487

2
0_0402_5%
15/0714 R9493 1
2

10K_0402_5%

1
+VCC_IO_AP_GATE C8543
10U_0402_6.3V6-M

1
2
3 D
20141204
1
5 Q24B C8540
G 2N7002KDWH_SOT363-6 0.22U_0402_10V6-K
<BOM Structure>
S 2
4
6

D
[61,71,86] SUSP# SUSP# 2 Q24A
G 2N7002KDWH_SOT363-6
<BOM Structure>
S
1

C C

+VCC_IO
+VCC_IO_AP

JC1 @
1 2
1 2 +VCC_IO +VCC_STG
JUMP_43X79

1 2

15/0522 R9490
0_0805_5%
+5VLP +5VALW
+0.675VS
1

@ +3VALW
R157 R156 R159
100K_0402_5% 100K_0402_5% 47_0603_5%
@
15/0520
2

@
SUSP
[37] SUSP
3

D Q6B +3VALW +1VALW +VCC_STG

5 SUSP

1
G
B C8541 B
6

Q6A D S 2N7002KDWH_SOT363-6 0.1U_0402_6.3V7-K

4

2
SUSP# 2
G @

20121218 2N7002KDWH_SOT363-6 S
1

U149

1
R9488 SLG5NT1533VTR_STDFN8-6_1X1P6
10K_0402_1%

VDD
3 4
D S Slew Rate=10uS<TR<65us

1
@
20121219 2 5
ON CAP

D15

GND
SUSP# 1 2

6
RB521CM_30

2
@ C749 C747
@
10U_0402_6.3V 2200P_0402_25V7-K

1
@ @

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 VCC_IO and VCC_ST LSW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 70 of 99

5 4 3 2 1
 5 4 3 2 1

D D

+5VALW VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=18mohm +5VS

U11 J5 @
1 14 +5VS_LS 1 2
2 VIN1_1 VOUT1_2 13 1 2
VIN1_2 VOUT1_1 JUMP_43X118
1 1
SUSP# 3 12 C71 1 2 1000P_0402_25V7-K
Load Switch @ C69
1U_0402_6.3VA-K
[61,70,86] SUSP#
4
ON1 CT1
11
@ C70
0.1U_0402_10V7-K
+5VALW To +5VS 2 +5VALW
SUSP# 5
VBIAS GND
10 C72 1 2 100P_0402_50V8-J
2

+3VALW To +3VS +3VALW

6
ON2 CT2
9 J6 @
+3VS

7 VIN2_1 VOUT2_2 8 +3VS_LS 1 2

VIN2_2 VOUT2_1 1 2
C C
1 15 JUMP_43X118 1
GPAD
@ C73 TPS22966DPUR_WSON14_2X3 @ C74
1U_0402_6.3VA-K 0.1U_0402_10V7-K
2 2

+5VS, C159 --> 1.5ms

+3VS, C160 --> 2.5ms

+3VALW to +3V_DDR

+3VALW +3V_DDR
U7
5 1 +3V_DDR
IN OUT
2
1 From PCH GND 1
C751
B B
C750 SYSON 4 3 4.7U_0603_10V6-K
[61,70,86] SYSON EN OC
2 1U_0402_6.3V6-K 2
G524B1T11U_SOT23-5

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 DC V TO VS/ V-PCH/VM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 71 of 99

5 4 3 2 1
 5 4 3 2 1

D D

For Edge 15'' Audio board CONNECTOR

+3VALW

C C

1
R238

1K_0402_5%
FFC

2
JAUF ME@
12 14
LOGO_LED# 11 12 GND2 13
[38,61] LOGO_LED# 11 GND1
10
JSENSE_CON 9 10
[55] JSENSE_CON HP_OUTR_CON 9
8
[55] HP_OUTR_CON HP_OUTL_CON 8
7
[55] HP_OUTL_CON 7
HGNDA 6
[54,55] HGNDA 6
5
4 5
HGNDB 3 4
[54,55] HGNDB 3
2
1 2
1
ACES_50506-01201-001

GNDA

B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 SUB-AUDIO JACK CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 72 of 99

5 4 3 2 1
 5 4 3 2 1

D D

+3VALW

2
VSYSTEM
PR4
750_0402_1%

1
PD4 @ PR5
RB751V-40_SOD323-2 1M_0402_5%

2
2N7002KDWH 2N SOT363-6

D
2

@ PR6 2 ADAPTER_ID_ON
PQ4A

0_0402_5% G

2N7002KDWH 2N SOT363-6
S
1

D
1

3
PR7
10K_0402_1% PR8 5 PD1

PQ4B
ADAPTER_ID_ON# [61]
1 2 1M_0402_5% G RB751V-40
ADP_ID [61] PD2
S

4
C C
1 2
1SS355 PR1 PR2
VSYSTEM PRT2A

2
100K_0402_1% 10K_0402_1%
680P_0402_50V7-K

A/D [61,74,78] MAINPWON_EC

2 1 1 2 1 2
0.1U_0402_6.3V

1 1 2
B+
1
1
PC2

PC3

2
PD5 PD3
2

2 AZ5425-01F_DFN1006P2E2 RB751V-40 0_0402_5%

3
2

PQ1 UMA@
2 E PR3
2

B MMBT3906_SOT23-3 750K_0402_5%

1
1
EMC@
C VCCGT 1.35VS VCCSA
PL1
MURATA BLM18KG300TN1D 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%

1
C PRT1 PRT3 PRT4
1 2 2 2 1 2 1 2 1
EMC@ PQ2
JDCIN1
APDIN PF1
PL2
MURATA BLM18KG300TN1D
VSYSTEM MMBT3904_SOT23-3
E
B
2

3
1 7A_32V_0437007.WR
1 2 2 1 1 2 PC1
2 3
3 4 EMC@ EMC@ EMC@ EMC@ 1U_0603_25V7K
1
1000P_0402_50V7-K

4 5

100P_0402_50V8J
5
100P_0402_50V8-J

1000P_0402_50V7-K
8 6 2 1 2 1 2 1
GND1 6
1

1
9 7
GND2 7 PRT6 PRT2 PRT5
ACES_50271-00701-001 540_0402NEW_30% 540_0402NEW_30% 540_0402NEW_30%
2

2
ME@
PC4

PC5

PC6

PC7 Charger VGA DIS@ VCORE

B B

+3VL
2

PR18
1.5K_0402_5%

+RTCBATT
1

<10,50> 1 2

PD6
2

RB751V-40
PR19

RTC Battery 45.3K_0402_1%

1

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 DCIN / Vin Detector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 73 of 99

5 4 3 2 1
 5 4 3 2 1

D D

PRT7 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
PL3 EMC@ Recovery at 56 +-3 degree C
MURATA BLM18KG300TN1D
C VMB2 VMB 1 2 C

JBATT1 PF2
12A_32V_0501012.WRS PL4 EMC@
1 2 1 MURATA BLM18KG300TN1D
1 BATT+
2
2 3 EC_SMCA 1 2
3 4 EC_SMDA +5VLP
4
+3VL +3VALW
5
5
EMC@ EMC@
1

2
6
6

1
7 PC9 PC10
7

2
8 1000P_0402_50V 0.01U_0402_25V PC8

47K_0402_1%
12.7K_0402_1%
G1
2

1
2

1
9 0.1U_0603_16V7K PR9

@ PR10

@ PR11
G2

2
10
PESD5V0U2BT_SOT23-3

G3 16.5K_0402_1%
1

11
G4 PR15

1
PR14 PU1

2
1 8 NTC_V_1
EMC_NS@

PD7

ME@ 100_0402_1%
VCC TMSNS1
1

100_0402_1%
2

SUYIN_200082GR007M211ZR @ PR13 2 7 OTP_N_002 2 1

100K_0402_1%_NCP15WF104F03RC
0_0402_5% GND RHYST1
OTP_N_003

1
1 2 3 6 PR12
[61,73,78] MAINPWON_EC OT1 TMSNS2 20K_0402_1%
20141231 4 5

PRT7
EC_SMB_CK1 [61,75] OT2 RHYST2
G718TM1U_SOT23-8

2
EC_SMB_DA1 [61,75]
PR16
100K_0402_1%
2 1 +3VALW

1 2
A/D
BATT_TEMP [61,75]
B B
PR17
10K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 74 of 99

5 4 3 2 1
 5 4 3 2 1

D D

PQ101
P2 PQ102 EMC@
VSYSTEM AON7466 AON7466 P3 PL101
3 3 1UH_PCMB053T-1R0MS_20% PR101
2 2 0.01_1206_1%
5 1 1 5 1 2 1 2
B+
EMC@ EMC@

10U_0805_25V6-K

10U_0805_25V6-K
1

2
PC104
1

1
PC102

PC103
PC101 PR102 0.022U_0402_25V

1
4.7_0603_5%
470P_0402_50V 2
PC105
PQ104

2
0.1U_0402_25V7K

5
AON7466
2 1
PQ103
2N7002WT1G BQ24780_BATDRV 4

1
3 1 PC107

1
2
3
1U_0603_25V7-K PC106

499K_0402_1%

0.01U_0603_50V7K
2

1
0.1U_0402_25V7K 2

PR103
G
2

1
PR106

PC108
2 1 2 1 10_0402_1%
1

1
PD101 PR107

2
RB751V-40 PR104 PR105 VSYSTEM B+ 10_0402_1%
1M_0402_5% 1M_0402_5%

2
1 2 PR108
1K_0402_1%

2
C C

2
1 2

RB751V-40
PD102

RB751V-40
PD103
DOCK_CONSUMP [60]
1 2 EMC@ RF_NS@ RF_NS@ B+
PR109
2N7002WT1G

D
1

@ 0_0402_5% @ PC109

10U_0805_25V6K

10U_0805_25V6K
1

1
1 2 2 100P_0402_50V8-J
PQ105

2200P_0402_25V7-K
[61] ACOFF

47P_0402_50V8-J
G VSYSTEM 1 1
4.02K_0603_1%

4.02K_0603_1%

68P_0402_50V8-J
1

1
S

PC113

PC114
PC111

PC112
PC110
3
2

ACN
ACP
PR110
PR111

PR112

2
2 2

2
10K_0402_1%

5
PR114
2

1
PR115 PR113 10_1206_5% BQ24780_VDD
1

68K_0402_1% 432K_0402_1% PC115 PC116

ACN
ACP
1 2 1U_0603_25V 4.7U_0603_10V6-M

1
2 1 28 24 1 2
VCC REGN

2
4 PQ106
1 2 6 PR116 PC118 AON7408L
ACDET 2.2_0603_5% 0.047U_0603_25V
PC117 0.1U_0402_25V7K 25 BST_CHG1 2 2 1
BTST

3
2
1
PL102 PR117
3 26 DH_CHG 4.7UH_PCMB104T-4R7MS 0.01_1206_1%

4
CMSRC HIDRV 1 2 CHG 1 2 BATT+
ACDRV
LX_CHG EMC@

5
27
@ PHASE

2
PR118 1 2 0_0402_5% 5

4.7_0603_5%
[61] ACPRN ACOK
@
PR120 1 2 0_0402_5% 11 PQ107

PR119
SDA

10U_0805_25V6-K

10U_0805_25V6-K
[61,74] EC_SMB_DA1 PU101 23 DL_CHG 4 AON7408L
@ LODRV

2
[61,74] EC_SMB_CK1
PR121 1 2 0_0402_5% 12
SCL
BQ24780SRUYR
GND
22
EMC@

PC119

PC120
B B

1
680P_0402_50V7K
@

3
2
1

1
PR122 1 2 0_0402_5% 7 29
[61] ADP_I IADP PAD

PC121
@

2
BQ24780_BATDRV

1
PR123 1 2 0_0402_5% 8 18
@ IDCHG BATDRV PC122
PR124 1 2 0_0402_5% 9 0.1U_0402_25V7K PC123
[79] PSYS PMON

2
17 0.1U_0402_25V7K
PR126 BATSRC PR125 10_0603_5%
PC127
PC125

PC126

@ 0_0402_5% 20 SRP 2 1
VR_HOT# 1 2VR_HOT_R# 10 SRP
[6,61,79] VR_HOT# PROCHOT#

1
2

13 PC124
100P_0402_50V8J
100P_0402_50V8J

100P_0402_50V8J

CMPIN
0.1U_0402_25V7K

2
BATPRES#
14 PR128 10_0603_5%
TB_STAT#

CMPOUT
1

19 SRN 2 1
21 SRN
ILIM
2

PR129
15
16

0_0402_5%
@
PR130 PR131
1

316K_0402_1% 18.2K_0402_1%
+3VALW 1 2 1 2 BATT_TEMP [61,74]
1
1

PR132
PC128 100K_0402_1%
0.1U_0402_25V6
2

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 75 of 99

5 4 3 2 1
 5 4 3 2 1

D D

+3VALW
FSW=750 KHz
B+ @
PU201
SYX198BQNC_QFN10_3X3
TDC:8A
2
PJ201
1 EMC@ RF_NS@ +3V_VIN 7 2 +3V_PWRGD
OCP:11A
2 1 EN2 PG @ PR202 PC203

1
1 0_0603_5% 0.1U_0603_25V7-M
+3VALW

47P_0402_50V8-J

10U_0805_25V6-K
0.1U_0402_25V6-K
1

1
JUMP_43X79 PR201 8 6 +3VBS 1 2 1 2
IN BS

PC201
1M_0402_5% PL201
8A

PC202
PC230
2.2UH_PCMB063T-2R2MS_8A_20%
EMC@ EMC@ PJ202

2
2 9 10 +3VLX 1 2 +3VALW_P 2 1
GND LX 2 1

2
PR203
3V5V_ON +3VALW_OUT
@ 0_0402_5%
2 +3VALW_P EMC_NS@ @ JUMP_43X118

2
1 4 1

2200P_0402_25V7-K
EN1 OUT PR205 PR204

0.1U_0402_25V6
22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M
+3VALW_FB 100mA @ 0_0402_5% 4.7_0603_5% 1 1 1 1

1
PR206 3 5 1 2

PC206

PC207

PC210
PC204

PC205

PC211
2.2K_0402_1% FB LDO +3VL

2 1
EC_ON
[61] EC_ON 1 2 1 EMC_NS@

2
PC208 2 2 2 2
4.7U_0603_6.3V6-K PC209
680P_0402_50V7K
+3VL

1
2

1
47K_0402_1%
1

2
@ PC213 PR208
PR216

0.1U_0402_25V6-K 1M_0402_5%
47K_0402_1%
1

PR217

1
PC212 PR207

2
0.01U_0402_25V7-K 1K_0402_1%
D
2

1 2 1 2
C C
2
2

G
D
3

S
1

[61,73,74] MAINPWON_EC 5 2N7002KDWH 2N

G
S PQ201A
4

2N7002KDWH 2N

PQ201B

+3VALW

1
@ PR209
100K_0402_5%
@ PR210
0_0402_5% +5VALW

2
+3V_PWRGD 1 2
FSW=750 KHz
B+ @
PU202
SYX198CQNC_QFN10_3X3 @ PR211
TDC:8A
2
PJ203
RF_NS@
1 EMC@ +5V_VIN 8 2 +5V_PWRGD
0_0402_5%
1 2
OCP:11A
2 1 IN PG @ PR212 PC217
47P_0402_50V8-J

1 0_0603_5% 0.1U_0603_25V7-M
+5VALW
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6-K
1

JUMP_43X79 9 6 +5VBS 1 2 1 2
PC231

PC215

PC216
PC214

GND BS PL202
8A
PC218 2.2UH_PCMB063T-2R2MS_8A_20%
EMC@ EMC@ 2 PJ204
2

2 1 2+5V_VCC 5 10 +5VLX 1 2 +5VALW_P 1

VCC LX PR213 2 1
B B

2
3V5V_ON
1U_0603_25V6M
1 4 +5VALW_OUT1
@ 0_0402_5%
2 +5VALW_P EMC_NS@ @ JUMP_43X118
EN OUT

2200P_0402_25V7-K
PR214

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
100mA 4.7_0603_5% 1 1 1 1

1
+5VFB 3 7

PC221

PC222

PC223

PC224

PC228
PC219

PC220

PC227
FB LDO +5VLP

1
1 EMC_NS@ 2 2 2 2

2
2
PC225
4.7U_0603_6.3V6-K PC226
680P_0402_50V7K

1
2

PC229 PR215
6800P_0402_25V7-K 1K_0402_1%
1 2 1 2

6800pf soft start 2ms

47nf soft start 7ms

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/08 Deciphered Date 2013/08/05 3VALWP/5VALWP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 78 of 99

5 4 3 2 1
 5 4 3 2 1

D D

B+ +5VALW

+VCC_ST

1
1 +3VS

1
PC401 PR401 PR402 PC402
0.01U_0402_25V7-K 1K_0402_5% 2_0402_5% 1U_0402_6.3V6-K
1

2
PC403 2

2
0.1U_0402_6.3V6-K

1
PR403 PR404 2
100_0402_5% 47_0402_5%

2
12

13
PR406

2
10K_0402_1%

VRMP

VCC

1
PR407
@ 0_0402_5%
VR_ON 1 2 37 38
[12,61] VR_ON VGATE VGATE [61]
PR408 EN VR_RDY PR409
@ 0_0402_5% 75_0402_5%
VR_SVID_ALRT# VR_HOT# VR_HOT# [6,61,75]
[16] VR_SVID_ALRT# 1 2 33 31 1 2
PR410 ALERT# VR_HOT#
51_0402_5%
VR_SVID_CLK
[16] VR_SVID_CLK 1 2 34 35 DRVON DRVON [80,81,85]
PR411 SCLK DRVON
10_0402_5%
VR_SVID_DAT 1 2 32 22 PWM_1A
[16] VR_SVID_DAT SDIO PWM_1A PWM_1A [80]

46 29 SW_1A
[75] PSYS PSYS PR412 1 2 7.5K_0603_1% SW_1A [80]
PSYS CSP_1A

1
2 1 PC441 PR405
PR413 1U_0402_6.3V6-K 12K_0402_1%
PC404 16.5K_0402_1% 1 2

2
1000P_0402_25V7-K
VCC_SENSE
1 2 1 2
[16] VCC_SENSE

1
PR414
3.24K_0402_1% PU401 1 PRT401

1
MURAT_NCP15WF104F03RC
1 2 24 NCP81208MNTXG_QFN48_6X6 PC440
PR415 VSP_1A 1000P_0402_50V7-K
PLACE CLOSE TO

2
3.24K_0402_1% PC405 2

2
PC406
0.033U_0402_25V7K VCCCPUCORE PL403
28 CSN_1A
1000P_0402_25V7-K CSN_1A CSN_1A [80]

1
C PR416 PR417 C
910_0402_1% @ 0_0402_5%
1 2 25 23 1 2
VSN_1A TSENSE_1PH
PC407
3300P_0402_50V7-K
VSS_SENSE

1
[16] VSS_SENSE 1 2

2
PRT402
PC408 PR418 MURAT_NCP15WF104F03RC
PC409 1 2 15P_0402_50V8-J 26 0.1U_0402_25V6-K 61.9K_0402_1%
COMP_1A

2
PLACE CLOSE TO

2
PR419

1
1 2
2.49K_0402_1%
1 2 VCCCPUCORE PU402
PR420 PC410
48.7K_0402_1% 1500P_0402_50V7-K
1 2 27
ILI M_1A
PWM1_2PH
PR421 16 PWM1_2PH [81]
107K_0402_1% PWM1_2PH
2 1 30
IOUT_1A 17
PC411 1 2 270P_0402_50V7-M PWM2_2PH

PR422
PC412 1 21000P_0402_50V7-K 2.05K_0402_1%
10 1 2 CSP1 CSP1 [81]
VCCGT_SENSE CSP1_2PH
[16] VCCGT_SENSE 47
VSP_2PH 9
CSP2_2PH +5VALW
2

1
PC413 PR424 PC414
1000P_0402_25V7-K 1.21K_0402_1% 0.1U_0402_25V6-K PR423
1

2
1 2 48 10_0402_1%
VSN_2PH 8 1 2
CSREF_2PH CSN1 [81]
PC415 PR425
3300P_0402_50V7-K 26.1K_0402_1%
VSSGT_SENSE
[16] VSSGT_SENSE
1 2 1 2 1
IOUT_2PH
PC416 1
470P_0402_50V8-J PC417
1 2 0.1U_0402_16V7-K

2
PR426
52.3K_0603_1%
2 7 1 2 CSP1
DIFFOUT_2PH CSSUM_2PH
3
FB_2PH

2
PC418 PC419
PR428 PR429 PC420 100P_0402_50V7-K 1000P_0402_25V7-K

1
1K_0402_5% 4.75K_0402_1% 2200P_0402_25V7-K PR427 PR430
1 2 1 2 1 2 4 73.2K_0402_1% 165K_0402_1%
PR431 PC421 PC422 COMP_2PH 6 1 2 1 2
49.9_0402_1% 470P_0402_50V8-J 15P_0402_50V8-J CSCOMP_2PH PR432
B 1 2 1 2 1 2 12.4K_0402_1% B
PC423 PR433 5 1 2 PLACE CLOSE TO
1000P_0402_25V7-K 2.7K_0402_1% ILIM_2PH
1 2 1 2 PRT403 1 2 VCCGT PL406
PR434 MURAT_NCP15WM224J03RC
2.7K_0402_1%
[16] VCCSA_SENSE 1 2 45
VSP_1B PR435
@ 0_0402_5%
11 1 2 PRT404 1 2
TSENSE_2PH
2

2
MURAT_NCP15WF104F03RC

1
PC425 PR436
1000P_0402_25V7-K PC424 61.9K_0402_1% PLACE CLOSE TO
1

PR437 0.1U_0402_25V6-K
VCCGT PU403

2
1K_0402_1%

1
[16] VSSSA_SENSE 1 2 44
VSN_1B
PWM_1B
PC427 36
PWM_1B PWM_1B [85]
15P_0402_50V8-J PC426 1 2 3300P_0402_50V7-K
SW_1B
1 2 43 40 PR438 1 2 7.5K_0603_1% SW_1B [85]
PC428 COMP_1B CSP_1B
0.01U_0402_25V6-K 1 2 PRT405 1 2
1 2 1 2 PR441 MURAT_NCP15WF104F03RC
41.2K_0402_1% 12K_0402_1%
ROSC_COREGT

1
PR440 1 2 42 PR439
PC429 PC439 PLACE CLOSE TO

ADDR_VBOOT
ICCMAX_2PH

ILI M_1B
ROSC_SAUS

0.018U_0402_50V7-J

3300P_0402_50V7-K
1.5K_0402_1%
ICCMAX_1B
ICCMAX_1A

PR442 VCCSA PL408

2
113K_0402_1%
CSB_1B
1 2 39 41 CSB_1B [85]
IOUT_1B CSN_1B

TAB
PC430
270P_0402_50V7-M
15

20
14

18

19

21

49
1 2
48.7K_0402_1%

90.9K_0402_1%

15.8K_0402_1%

PC431
24K_0402_1%

10K_0402_1%
24K_0402_1%

1000P_0402_50V7-K
1 2
2

2
1

1
PR443

PR444

PR445

PR446

PR447

PR448

A A

https://dr-bios.com Security Classification

Issued Date 2013/08/05
LC Future Center Secret Data
Deciphered Date 2014/12/31
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title

Size
A1

Date :
IMVP8
Document Number
AIVL2_NM-A351
Wednesday, September 23, 2015 Sheet 79 of 99
Re v
0.1

5 4 3 2 1
 5 4 3 2 1

D D

PL401
EMC@ EMC@ RF_NS@ BLM18KG300TN1D
1 2
EMC@ B+
PC432 PC433 PC434 PC435 PC436 PC437 PL402
1 BLM18KG300TN1D

47P_0402_50V8-J

33U_D2_25VM_R40M

33U_D2_25VM_R40M
C C

1
1 2

PC438
1 1 1 1 1

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6
10U_0805_25V6-K

2200P_0402_25V7-K

68U_25V_M_R0.36

68U_25V_M_R0.36

68U_25V_M_R0.36
EMC@ + + + + +
+VCC_CORE

PC526

PC527

PC528
PC525

PC529
2

2
2
2.2_0603_1%
2 2 2 2 2 TDC= 21A

5
PR449
2 1 @ @
IccMAX=28A

2
PC442
0.22U_0603_25V7-K
HG_A1
OCP = 36A
PU402 4 PQ401

1
NCP81253MNTBG_DFN8_2X2 TPCA8065-H

1 8 PL403
BST DRVH CMLE064T-R15MS0R725-88(0.72mohm+/-5%)

3
2
1
2 7 SW_A1 1 2
[79] PWM_1A PWM SW
+VCC_CORE

2
3 6
[79,81,85] DRVON EN GND PR450 1

1
4 5
FLAG

+5VALW VCC DRVL 4.7_0603_5%

PR451 PR452 + PC443
EMC_NS@ 0_0402_5% 0_0402_5% 330U_D2_2VM_R9M

1 1
LG_A1
1

PC444 4 4 @ @
9

1U_0402_10V 2

2
PC445
2

680P_0402_50V7K

2
EMC_NS@
3
2
1

3
2
1
PQ402 PQ403
TPCA8057-H TPCA8057-H
CSN_1A [79]

SW_1A [79]

B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 80 of 99

5 4 3 2 1
 5 4 3 2 1

D D

PL404
EMC@EMC@RF_NS@ BLM18KG300TN1D
1 2
EMC@ B+
PC446 PC447 PC448 PC449 PC450 PC451 PL405
C C
1 BLM18KG300TN1D

47P_0402_50V8-J
1

1
1 2

PC452
10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6

2200P_0402_25V7-K
EMC@

2
2
2.2_0603_1%

5
PR453
2 1 PQ404 +VCC_GT
TPCA8065-H
TDC= 18A

2
PC453
0.22U_0603_25V7-K
HG_B1 4 IccMAX=31A

1
PU403
NCP81151MNTBG_DFN8_2X2 OCP min = 40A
1 8 PL406
BST DRVH CMLE064T-R15MS0R725-88(0.72mohm+/-5%)

3
2
1
2 7 SW_B1 1 2
[79] PWM1_2PH PWM SW
+VCC_GT

2
3 6 1
[79,80,85] DRVON EN GND PR454 PC454
4 5 +
+5VALW VCC DRVL 4.7_0603_5%
FLAG

EMC_NS@

330U_D2_2VM_R9M
1

1
@ @

2 1
LG_B1 2
1

PC455 4 4
1U_0402_10V 0_0402_5% 0_0402_5%
9

PC456 PR455 PR456

2

680P_0402_50V7K

2
EMC_NS@
3
2
1

3
2
1
PQ405 PQ406
TPCA8057-H TPCA8057-H

CSN1 [79]

B B
CSP1 [79]

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VCC_GT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 81 of 99

5 4 3 2 1
 A
B
C
D

5
5

+VCC_GT

1
2
1
2
1
2
+VCC_CORE

PC513 PC488 PC465

+VCC_SA
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC514 PC489 PC466

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2

PC490 PC467
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2

4
4

1
2
1
2

PC515
22U_0603_6.3V6M PC491 PC468
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC516
22U_0603_6.3V6M PC492 PC469
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC517
22U_0603_6.3V6M PC493 PC470
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

PC518
22U_0603_6.3V6M PC494 PC471
25pcs 22uF for +VCC_GT

22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
1
2
1
2

12pcs 22uF for +VCC_SA

PC519
22U_0603_6.3V6M PC495 PC472
22U_0603_6.3V6M 22U_0603_6.3V6M

1
2
PC520
1
2
1
2

22U_0603_6.3V6M
PC496 PC473

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC521
23pcs 22uF for +VCC_CORE

1
2
1
2

22U_0603_6.3V6M
PC497 PC474

1
2
22U_0603_6.3V6M 22U_0603_6.3V6M
PC522
22U_0603_6.3V6M
+VCC_GT

1
2

1
2
PC498
PC523 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC499
PC524 22U_0603_6.3V6M
1
2

22U_0603_6.3V6M

3
3

1
2
+VCC_CORE

PC475
PC500 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC476
PC501 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC477
PC502 22U_0603_6.3V6M
22U_0603_6.3V6M

Issued Date
1
2

PC503

Security Classification
22U_0603_6.3V6M
1
2
1
2
Based on PDDG rev 0.7 Table 5-1.

+VCC_CORE

PC504 PC478
22U_0603_6.3V6M 22U_0603_6.3V6M
1
2
1
2

PC505 PC479
22U_0603_6.3V6M 22U_0603_6.3V6M
1
2

1
2

PC480

2013/08/05
PC506 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

1
2

PC481

https://dr-bios.com
PC507 22U_0603_6.3V6M
22U_0603_6.3V6M
1
2

PC482
22U_0603_6.3V6M
+VCC_GT

1
2
1
2

PC508
22U_0603_6.3V6M PC483
22U_0603_6.3V6M
1
2

2
2

1
2

PC509
22U_0603_6.3V6M PC484
Deciphered Date

22U_0603_6.3V6M
1
2
1
2

PC510
22U_0603_6.3V6M PC485
LC Future Center Secret Data

22U_0603_6.3V6M
1
2

PC511
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
1
2

22U_0603_6.3V6M
PC486
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1
2

22U_0603_6.3V6M
PC512
1
2

22U_0603_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2014/12/31

PC487
22U_0603_6.3V6M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Date:
Title

Custom
Size Document Number

1
1

Wednesday, September 23, 2015

PROCESSOR DECOUPLING

Sheet
82
of
AIVL2_NM-A351
99
Re v
0.1
A
B
C
D
 5 4 3 2 1

ISL62771 Schematic for FT3 solution PL601 DIS_EMC@

MURATA BLM18KG300TN1D
+5VALW +5VALW
1 2
DIS_EMC@ +VGA_B+
DIS_EMC@

2
PR601 PR602 DIS_RF_NS@ DIS_EMC@ PL602
MURATA BLM18KG300TN1D B+
PR603 0_0603_5% 0_0603_5%

10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K

0.1U_0402_25V6
D @ 0_0402_5% 1 2 D
@ @

5
[14,27,36] VGA_ON 1 2 1

47P_0402_50V8-J
1

1
VDD_62771

PC602

PC611

PC607
PC606
PC603
1
PC601

2
2

1
+3VS_VGA 0.1U_0402_25V6 PC604 PC605
DIS@ 1U_0402_10V 1U_0402_10V VGA_UGATE1 4 PQ601

DIS@

DIS@
2
TPCA8065-H

2
DIS@
+VGA_CORE

26
25
@ PR604 DIS@ DIS@ DIS@ PL603

3
2
1
10K_0402_1% .24UH 20% PCME063T-R24MS1R145 35A

VDD

VDDP
VGA_PHASE1 1 2
PR605 1 8
ENABLE
@ 0_0402_5%
PG_VDD DIS_EMC_NS@
[14,15,36] DGPU_PWROK
1 2 20
35 PGOOD
@ PR614
0_0603_5%
DIS@ PC612
0.22U_0603_25V PQ602 PQ603 PR607 DIS@ DIS_EMC@
PGOOD_NB

2
21 1 2 1 2 TPCA8057-H TPCA8057-H 4.7_0603_5% PR608 3.65K_0402_1%
[27,28] PLT_RST_VGA# BOOT1

0.1U_0402_25V6
330U_D2_2VM_R9M

330U_D2_2VM_R9M
5

5
PR606 @ 1 20_0402_5% 9 DIS@ @ VSUM+ 1 2 1 1
PR609 @ 1 2 0_0402_5% 3 PWROK
[28] SVI2_SVC SVC

1
+ +
20121218 PR615 @ 1 2 0_0402_5% 5 22

PC614

PC615
PC613
[28] SVI2_SVD SVD UGATE1
1 PR611 @ 1 2 0_0402_5% 7 ISEN1 1 2
T96 SVT

1
PR612 @ 0_0402_5%
[28,61] GPU_VR_HOT#
PR610 @ 1 2 0_0402_5% 4
VR_HOT_L DIS_EMC_NS@

2
2 2

2
1 2 6 23 4 4 PR616 10K_0402_1%
+3VS_VGA VDDIO PHASE1

1
PC616 DIS@

DIS@
DIS@
1 2 PC609 DIS@ 680P_0402_50V

1
PR613 DIS@ 100P_0402_50V8-J 24 VGA_LGATE1 PC608
LGATE1

2
42.2K_0402_1% 0.22U_0603_25V

3
2
1

3
2
1
DIS@ 1 2 1 2 19 @ PR620 DIS@ PC618 DIS@
+VGA_CORE PC617 PR617 COMP 0_0603_5% 0.22U_0603_25V7-K PR618 1_0402_1%
[29] VDDC_SEN 470P_0402_50V1 2 1 2 PC610 DIS@ 30 1 2 1 2 VSUM- 1 2
DIS@ 499_0402_1% 1 2 150P_0402_50V8-J BOOT2 DIS@
1

@ PR619
1

@ PR622 1 2 32.4K_0402_1% 18 29
C
10_0402_1% PC620 FB UGATE2 C
0_0402_5%
1

DIS@ DIS@ PR623 1 2 1 2 @ 680P_0402_50V7-K

PR621 PC619 DIS@ 1.1K_0402_1% 28
PHASE2
2

330P_0402_50V7-K @ PR624 2.7K_0402_1% +VGA_B+

2

16
VSEN DIS_RF_NS@ DIS_EMC@ DIS_EMC@
1

27
PC621 LGATE2
330P_0402_50V7-K 17 DIS@ PU601
RTN
2
1

@ DIS@

10U_0805_25V6K
2200P_0402_50V7K

0.1U_0402_25V6

10U_0805_25V6K
5
DIS@ PC622 ISL62771HRTZ_TQFN40_5X5
0_0402_5% PR626 1000P_0402_25V7-K 1

47P_0402_50V8-J
2

PR625

1
10_0402_1% DIS@

PC623

PC625

DIS@ PC626

DIS@ PC627
PC624
2

36 31 VDD_62771
COMP_NB BOOT_NB

2
VGA_UGATE2 4 PQ604 2
[29] VDDC_RTN PR627 TPCA8065-H
@ 10K_0402_5% 32 PR628 DIS@
UGATE_NB 10K_0402_1%
1 2 37 DIS@
FB_NB

3
2
1
33 1 2 DIS@ PL604
PHASE_NB .24UH 20% PCME063T-R24MS1R145 35A +VGA_CORE
34 1 2 VGA_PHASE2 1 2
38 LGATE_NB
VSEN_NB PR629
DIS_EMC_NS@
10K_0402_1%
VGA_LGATE2
PQ605 PQ606
DIS_EMC@

2
DIS@ TPCA8057-H TPCA8057-H PR630 PR631 3.65K_0402_1%

5
DIS@ @ 4.7_0603_5% VSUM+ DIS@ 1 2
VSUM+ 14 13 ISEN1

330U_D2_2VM_R9M

0.1U_0402_25V6
ISUMP ISEN1

330U_D2_2VM_R9M
1 1
12 ISEN2 ISEN2 1 2
ISEN2

1
15 PR632 10K_0402_1% + +

PC631
DIS@ PC629

DIS@ PC630
ISUMN

2
4 4
DIS_EMC_NS@ DIS@

1
PR633
DIS@

@ PC635

2
B PC632 PC628 2 2 B

1
1

40 680P_0402_50V7K 0.22U_0603_25V
ISUMP_NB

2
1

DIS@

3
2
1

3
2
1
2.61K_0402_1%

PR634
DIS@

PC633
DIS@

PC634
DIS@

PR635
DIS@

DIS@
39
330P_0402_50V

1 PR636 1_0402_1%
ISUMN_NB
2
1

1 2
@ PR637

VSUM-
2

PR638 100K_0402_1%
1 DIS@ 1 2
11K_0402_1%

0.1U_0402_25V7K

82N_0402_50V

649_0402_1%

2 NTC_NB
2

CLOSE PL603 11
@ PR639

NTC
2

2
2

10
0_0402_5%

IMON
1

2
IMON_NB +VGA_CORE
TP

DIS@ PRT601 TDC: 37A

100_0402_1%

10K_0402_NTC
OCP: 60A
1

41

1
Fsw: 300KHz

1
CLOSE PQ601
DIS@
PR640

DIS@
PC636

DIS@
PR642

DIS@
PR641 27.4K_0402_1%
1

VSUM- DIS@ PRT602

2

470K_0402NEW_3%
2

100K_0402_1%

0.1U_0402_25V

130K_0402

2
PC637 DIS@
1

0.1U_0402_25V6
1

BOTTOM PAD
CONNECT TO GND
Through 8 VIAs
PR643
DIS@
1
10.7K_0402_1%

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 83 of 99

5 4 3 2 1
 5 4 3 2 1

D B+ +5VLP/ 100mA D

Power Line SILERGY Richtek

MOSFET SYX198CQNC RT8068A
+5VALW/8A 1.8VALW/1A
Adapter PWM FOR 1.8VALW
FOR SYSTEM EC_ON2 EN
EC_ON EN PGOOD +5V_PWRGD

SILERGY +3VLP/ 100mA

SYX198BQNC
PWM
+3VALW/8A
FOR SYSTEM
EC_ON EN PGOOD +3V_PWRGD

TI
C BQ24780SRUYR Richtek +1.35VP/11A C

Battery Charger RT8231A

SYSON S5
FOR DDR3L +0.675VSP/1.5A
Switch Mode SUSP# S3

Batt. Discharge ON NCP81253 VCORE/TDC 21A/EDC 28A

MOSFET
SMBus
NCP81208 NCP81151 VCCGT/TDC 18A/EDC 31A
APUPWR_EN EN
FOR SKL U22 CPU
NCP81253 VCCSA/TDC 4A/EDC 5A

Main Battery
Li-ion
B
Intersil B

ISL62771HRTZ
TQFN40_5X5 +VGA_CORE TDC 36A /EDC 55A
SVI2 VIDs
Switch Mode
IGPUPWR_EN EN FOR GPU VDDC

TI V1.00A/10A
TPS51367
FOR V1.00A
S5_EN EN PGOOD

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date Block Diagram
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. AIVL2_NM-A351
Date: Wednesday, September 23, 2015 Sheet 84 of 99
5 4 3 2 1
 5 4 3 2 1

D D

PL407
EMC@EMC@ RF_NS@ BLM18KG300TN1D
1 2
B+
PC457 PC458 PC459 PC460 EMC@
1

47P_0402_50V8-J
1

PC461
10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6

2200P_0402_25V7-K
C C

2
2
2.2_0603_1%

5
PR457
2 1

+VCC_SA

2
PC462
0.22U_0603_25V7-K
PU404 HG_1PH 4 PQ407 TDC= 4A

1
NCP81253MNTBG_DFN8_2X2 AON7408L
IccMAX=5A
1
BST DRVH
8 PL408
0.47UH_PCMB063T-R47MS3R675_18A_20%(DCR+/-5%) OCP = 9A

3
2
1
2 7 SW_1PH 1 2
[79] PWM_1B PWM SW

+VCC_SA

5
3 6
[79,80,81] DRVON EN GND

1
4 5
FLAG

+5VALW VCC DRVL

2
PR459 PR460
PR458 0_0402_5% 0_0402_5%
LG_1PH 4
1

PC463 PQ408 4.7_0603_5% @ @

9

1U_0402_10V AON7408L
EMC_NS@

2
2

1 1
3
2
1
PC464
680P_0402_50V7K

2
CSB_1B [79]
EMC_NS@
SW_1B [79]

B B

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 VCCSA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 85 of 99

5 4 3 2 1
 A B C D

1 1

PJ301
2 1
2 1
@ JUMP_43X118

2
PJ302
1
+1.35V
+1.35VP 2 1
@ JUMP_43X118

+1.35VP PJ303
2 1
+0.675VSP 2 1 +0.675VS
B+
PJ304
B+_1.35V EMC@ EMC@ RF_NS@ RF_NS@

1
2 1
2 1 PC301 @ JUMP_43X39
@ JUMP_43X79 10U_0603_6.3V6M

220K_0402_1%
2200P_0402_25V

47P_0402_50V8-J

68P_0402_50V8J
0.1U_0402_25V6

2
1

10U_0805_25V6-K
10U_0805_25V6-K
1

1
PC304

PC306
PC302

PC307

PC305
PC303
+0.675VS
2

2
2
TDC: 1.5A

+0.675VSP
PR301
100K_0402_1% +0.675VSP

+1.35VP
1 2
1.35V

PR302
TDC: 11 A

10U_0603_6.3V6M
2

0.1U_0402_6.3V7-K
1

1
OCP: 15 A
2 2

PC309
PC308
Fsw: 300KHz

13

19
14

11

20

2
PQ301

VID

VTT
CS
PGND

VLDOIN
AON7408L PR303 21
2.2_0603_5% PAD
4 1 2 1 2 18 1
BOOT VTTGND
PC310
0.22U_0603_25V7K DH_1.35V 17
UGATE VTTSNS
2 +0.675VSP
PL301

1
2
3
1UH_PCMC063T-1R0MN_+-20%
3
EMC@ EMC@ 1 2 LX_1.35V 16
PU301
RT8231AGQW
GND VTTREF_0.675V
+1.35VP PHASE
VTTREF_0.675V
EMC_NS@ VTTREF
4
2

PR306
PR304 DL_1.35V 15 5.1_0603_5%
2200P_0402_25V7-K

LGATE
1

1 4.7_0603_5% 12 2 1 +5VALW
470P_0402_50V7K

VDD
0.1U_0402_25V6

330U_D2_2V_R9M

1
PR305

PGOOD
1
1

+ 7.87K_0402_1% 5 PC315
PC312

PC313

PC311

@ PC314

VDDQ 1

TON
1

PQ302 0.033U_0402_16V7K

FB

S5

S3

2
AON7534 PC316
2

2 2 1U_0402_10VA-K
EMC_NS@

7
2

10
4
2

PC317
680P_0402_50V7K

2 TON_1.35V

S5_1.35V

S3_1.35V
@ PR308
1
1

100K_0402_1%
1
2
3

PR307 1 2 +3VS
10K_0402_1%
PR310

887K_0402_1%
@ 0_0402_5% SM_PG_CTRL [25]
2

1 2

PR309
3
FB_1.35V 3

@ PR311

1
B+_1.35V 0_0402_5% SUSP# [61,70,71]
PR312 1 2
@ 0_0402_5%
1 2
[61,70,71] SYSON

1
@ PC318

2
0.1U_0402_6.3V7-K

2
1
@ PR313 @PC319
47K_0402_5% 0.1U_0402_16V

4 4

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.35V/+0.675VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 86 of 99

A B C D
 5 4 3 2 1

D D

PR701
@ 0_0402_5%
1 2
[61,88] EC_ON2

0.1U_0402_6.3V7-K
1

2
PC701

2
0.1U_0402_16V7-K PR702

PC702
210K_0402_1% +3VS

2
@ PR704

2
PR703 100K_0402_1%

24

25

26

27

28

29
210K_0402_1%

1
EN
RA
REFIN

VREF
REFIN2

GND2
+V1.00AP

1
C +5VALW VDDPALW_PWRGD C
23
GSNS PGOOD
1
FSW=800KHz
PC703
22
VSNS LP#
2 @ PR705
0_0402_5%
TDC:10A
@ PR706
0_0402_5%
2 1 21
SLEW MODE
3 1 2 OCP:16A
1 2 0.01U_0402_25V7-K 20 4 @ PR707 PC704
TRIP NC 0_0603_5% 0.1U_0603_25V7K
PC705 19 5 BST_1.00VS
1 2 1 2 PL701
PU701
2.2U_0603_10V6-K GND1 BST
SW_1.00VS
1UH_PCMC063T-1R0MN_+-20%
EMC@ EMC@ +V1.00AP
1 2 18 TPS51367RVER SW1 6 1 2
V5
2
PJ701
1 RF_NS@ EMC@ EMC@ VIN_1.00VS 17 7
B+ 2 1 VIN3 SW2

2
68P_0402_50V8J

2200P_0402_25V7-K
10U_0805_25V6-K

10U_0805_25V6-K

0.1U_0402_25V6

@ JUMP_43X79 16 8 PR708
VIN2 SW3

2200P_0402_25V7-K
1

1@ 4.7_0603_5%
PC706

PC710
PC707

PC708

PC709

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

22U_0805_6.3V6-M

0.1U_0402_25V6
15 9
PC714
VIN1 SW4 EMC_NS@

1
47P_0402_50V8-J

PC716

PC717
1 1 1 1

PGND4

PGND3

PGND2

PGND1
PGND5
2

PC711

PC712

PC713

PC715
2

2
2 2 2 2

14

13

12

11

10

1
PC718
680P_0402_50V7K
EMC_NS@

2
B B

Mode Frequency PJ702

2 1
2 1

GND 400KHz @ JUMP_43X118

PJ703
2 1
+V1.00AP 2 1 +1VALW
Float 800KHz @ JUMP_43X118

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/01 Deciphered Date 2014/08/01 +V1.00A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 87 of 99

5 4 3 2 1
 5 4 3 2 1

D D

PL801

4
PJ801 1UH_PH041H-1R0MS_20%
2 1 VIN_+1.8VSP 10 1 1.8VSP_LX 1 2
+5VALW +1.8VSP

PG
2 1 PVIN2 LX1
C C

2
9 2
@ JUMP_43X39 PVIN1 LX2

1
PR803

1
8 3
PC801 PC802
10U_0603_10V SVIN1 LX3 EMC_NS@ 4.7_0603_5%
10U_0603_10V PR804 PC805
EMC@

2
PU801 20K_0402_1% 22P_0402_50V

2 1

2
RT8068AZQW

22U_0805_6.3VAM

0.1U_0402_25V6
22U_0805_6.3VAM
2

1
5 6 PC804

GND
EN FB
PR801
EMC_NS@

NC

PC807

PC808
PC806
@ 0_0402_5% 680P_0402_50V

2
1 2 EN_1.8VSP
[61,87] EC_ON2

7
11
+1.8VALW
TDC: 1A

2
1 2

1
@ PR802
Fsw: 1MHz

1
1M_0402_5% @ PC803
@ PD801 0.22U_0402_10V6-K

2
RB751V-40 PR805

1
10K_0402_1%

2
PJ802
+1.8VSP 2 1 +1.8VALW
2 1
B B
@ JUMP_43X39

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/08/05 Deciphered Date 2014/12/31 +1.8VS_VGA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
AIVL2_NM-A351 0.1

Date: Wednesday, September 23, 2015 Sheet 88 of 99

5 4 3 2 1
 5 4 3 2 1

D D

Screw Hole
H20 H8 H17 H25 H16 H15 H23 H24 H14 H9

@ @ @ @ @ @ @ @ @ @

1
PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3

H18 H13 H11 H12 H10

@ @ @ @ @

1
PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3 PAD_C6P0D2P3

H28

C C
@

1
PAD_C3P5D2P3

H19 H22 H27

@ @ @
1

1
PAD_shapeT6P0X8P5CB6P0D2P3 PAD_SHAPET6P0X8P5CB6P0D2P3 PAD_shapeT6P0X8P5CB6P0D2P3
H5 H6 H1 H2 H3 H4

@ @ @ @ @ @
1

1
PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15 PAD_C6P0D3P15

H26 H21
Center Zero
B @ @ B
1

PAD_O2P3X2P8D2P3X2P8N PAD_C2P3D2P3N

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4 FD5 FD6
1

A A

Security Classification LC Future Center Secret Data Title

https://dr-bios.com
Issued Date 2013/09/07 Deciphered Date 2014/09/07 XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
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Custom
BE560 0.1

Date: Wednesday, September 23, 2015 Sheet 99 of 99

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