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2019MidtermTest (Eng)

The document is a midterm exam for an Electronic Circuit course, dated April 22, 2019. It includes questions on transistor operation, amplifier design, and calculations related to FET circuits, requiring students to provide detailed solving procedures. The exam consists of multiple parts, focusing on circuit analysis, voltage calculations, and frequency response.

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14 views2 pages

2019MidtermTest (Eng)

The document is a midterm exam for an Electronic Circuit course, dated April 22, 2019. It includes questions on transistor operation, amplifier design, and calculations related to FET circuits, requiring students to provide detailed solving procedures. The exam consists of multiple parts, focusing on circuit analysis, voltage calculations, and frequency response.

Uploaded by

jjongpalihannam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Electronic Circuit 2 G03050 Midterm Exam (2019/04/22)

Student ID number : Student Name:

* For every answer to the problems, the solving procedure should be included.

1. [10] For the transistors in Fig. 1, (a) draw the basic construction, (b) sketch ID-VDS
curve with 3 regions of operation, and fill in (c), (d), and (e) with voltage relations
between VGS and VDS for each operating regions. (Use the form in Table 1 as an
answer sheet.)

A. [5] B. [5]

Fig. 1. FET circuit symbols

Table 1. Form to be filled in

Basic
ID-VDS curve Conditions for the operating region
construction
Ohmic (c)

(a) (b) Saturation (d)

Cut-off (e)
Electronic Circuit 2 G03050 Midterm Exam (2019/04/22)

2. [25] Consider a cascade amplifier shown in Fig. 2 with parameters in Table 2. Assume
two FETs have identical characteristics and operate under the same bias condition as
each other.

A. [2] Design the required values of RD and RS. (*Don’t try to find the standard
commercial values. Leave them as they are after calculations.)

B. [3] Find the dc voltages, VC1, VC2, VC3, applied to the coupling capacitors. (*Follow
the voltage polarity shown in Fig. 2.)

C. [2] Calculate the trans-conductance (gm) at the bias point.

D. [9] Disconnect Rsig and RL , and calculate the no-load voltage gain(AvNL,mid=vo/vi),
input impedance(Zi,mid), and output impedance(Zo,mid) of the amplifier in the mid-
band frequency.

E. [3] Find the mid-band overall voltage gain Av,mid=vo/vs including Rsig and RL.

F. [3] Find all of the lower cut-off frequencies (rad/s) by s.c. time constant method.

G. [3] Find all of the upper cut-off frequencies (rad/s) by o.c. time constant method.

Table 2. Parameter values

VP=-3V
IDSS=5.63mA
FET rdinfinite
Cgs=Cgd=10pF
Cds=0(ignorable)
VDD=20V
Bias VDSQ=12V
IDQ=2.5mA
Rsig=0.2kΩ
RL=10kΩ
Circuit
C1=C2=C2=10uF
Cw=0(ignorable)
Fig. 2. FET amplifier circuit

(==End of test!==)

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