MP MODULE- 5 –Important Questions

PENTIUM PROCESSOR
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Q.1 Explain features of Pentium processor.

Ans- The Pentium processor supports the features of previous Intel Architecture
processors and provides significant enhancements including the following:

1) 64-Bit Data Bus -

64 bit data bus permits 8 bytes or 4 words to be transferred in a single bus
cycle. It supports 64 bit addressing scheme.
2) Superscalar, Super pipelined Architecture –
The Intel486 processor can execute only one instruction at a time. With
superscalar execution, the Pentium processor can sometimes execute two
instructions simultaneously. It has two integer pipelines U and V (32 bit
each) that enhances the speed of execution
3) Dynamic Branch Prediction –
Branch prediction is implemented in the Pentium processor. To support
this, the Pentium processor implements two prefetch buffers, one to
prefetch code in a linear fashion, and one that prefetches code according
to the Branch Target Buffer (BTB)
4) Pipelined Floating-Point Unit-
The Pentium processor executes individual instructions faster through
execution pipelining, which allows multiple floating-point instructions to be
executed at the same time.
5) Improved Instruction Execution Time
Due to superscalar architecture, floating point pipeline stages, instruction
execution time speeds up.
6) Separate Code and Data Caches: Separate 8KB for code and 8KB for data
cache. It reduces read – write conflicts.
7) New Instructions- There are new instructions added in Pentium Processor

e.g CMOV – Conditional Move, RDMSR- Read Model Specific Register

Q.2) Draw and Explain Pentium Processor Architecture.

Ans-

The Pentium is a 32-bit processor, but it has a 32-bit address bus and a
64-bit data bus. shows the internal architecture of Pentium processor.

It consists of 8K byte code cache, 8K byte data cache, Translation

Look-aside Buffer (TLB), Branch Trace Buffer (BTB), Integer pipelines U
and V, floating-point pipeline, Microcode ROM, and Control Unit (CU).

Code and Data Cache There are separate code and data caches, and the
cache line size is 32 bits just like the 80486 processor. Each cache is
connected with its own Translation Look-aside Buffer (TLB).

Branch Prediction Branch prediction consists of a Control Unit (CU) and a

Branch Trace Buffer (BTB).
 Control Unit (CU) The control unit controls the five-stage integer pipelines
U and V, and the eight-stage floating-point

Branch Trace Buffer (BTB) The BTB is used to store the target address and
statistical information about the branch operation. Hence, the branch
prediction is able to predict branches

In the Architecture of Pentium Processor, the integer pipelines are used for
all instructions which are not involved in any floating-point operations.
Therefore, the Pentium can transmit two integer instructions in the same
clock cycle and performance of the processor is improved. This method is
called superscalar architecture,

Q.3 ) Explain Integer Pipelines U and V in Pentium.

The Pentium is a superscalar processor and it has two integer pipelines, called
U and V. The process of issuing two instructions in parallel is known
as pairing.
 • The U-pipeline is able to handle the full instruction set of the Pentium
but the V-pipeline has limited handling capability.
• The V-pipeline is able to handle only simple instructions without any
microcode support.
• When instructions are paired, initially the instruction is issued to the U-
pipe and then the next sequential instruction is issued to the V-pipe.

There are two integer pipelines and a floating-point unit in the Architecture of
Pentium Processor. Figure 12.3 shows an integer pipeline. Each integer unit
has the basic five-stage pipeline as given below:

• Prefetch (PF)
• Decode-1 (D1)
• Decode-2 (D2)
• Execute (E)
• Write Back (WB)
Prefetch (PF) In the prefetch stage of integer pipeline of the Pentium
processor, instructions are fetched from the instruction cache. After
completion of the prefetch stage, the decode stages D1 and D2 will be
executed.

Decode-1 (D1) In the decode-1 (D1) pipeline stage, the CPU decodes the
instruction and generates a control word. The D1 pipeline stage has two
parallel instruction decoders. These implement the pairing rules.

Decode-2 (D2) The decode-2(D2) pipeline stage is required whenever the

control word from D1 stage is decoded to complete the instruction decoding.
In this stage, the CPU generates addresses for data memory.

Execute (E) The execution stage is used for both ALU operations and data
cache access. In the execution stage, all U-pipe and V-pipe instructions, except
conditional branches, are verified for correct branch prediction. 3

Write Back (WB) The final stage of the five-stage pipeline is Write Back (WB).
In the WB stage, the CPU updates the contents of registers and status of the
flag register after completion of execution.
Q.4) Explain Floating-Point pipe line in Pentium Processor.

The Floating-Point Unit (FPU) of Pentium has an eight-stage pipeline as

shown in Fig. 12.4. The eight pipeline stages are

• Prefetch (PF)
• Decode-1 (D1)
• Decode-2 (D2)
• Execute (dispatch)
• Floating Point Execute-1 (X1)
• Floating Point Execute-2 (X2)
• Write Float (WF)
• Error Reporting (ER)

The first five stages of the pipeline are similar to the U and V integer pipelines.
During the operand fetch stage, the FPU fetches the operands either from the
floating-point register or from the data cache. The floating-point unit has
eight general-purpose floating point registers. There are two execution stages
in Pentium such as the first execution stage (X1 stage) and the second
execution stage (X2 stage). In the X1 and X2 stages, the floating-point unit
reads the data from the data cache and executes the floating-point
calculation.

Prefetch (PF) The prefetch stage is same as the integer pipeline of Pentium
processor.

Decode-1 (D1) The decode-1 (D1) pipeline stage is also same as the integer
pipeline of Pentium processor.

Decode-2 (D2) The decode-2 (D2) pipeline stage is worked as required.

Operand Fetch During the execution stage (E), the floating-point unit
accesses the data cache and the floating-point register to fetch operands.

Floating Point Execute-1 (X1) In the Floating Point Execute-1 (X1) stage, the
floating-point unit executes the first steps of the floating-point calculations..
Floating Point Execute-2 (X2) During the Floating Point Execute-2 (X2) stage,
the Floating Point unit execute the remaining steps of the floating-point
computations.

Write Float (WF) In the Write Float (WF) stage, the floating-point unit
completes the execution of the floating-point calculations and then writes the
computed result into the floating-point register file.

Error Reporting (ER) In the error reporting(ER) stage, the floating-point unit
generates a report about the internal special situations and updates the
floating point status.

Q.5 Explain in brief, 'Branch Prediction Logic' used in Pentium Processor.

➢ Branch prediction logic: Pentium uses a scheme called Branch Prediction

logic. In this scheme, a prediction is made for the branch instruction currently in
the pipeline.
➢ The prediction will either be taken or not taken.
➢ If the prediction is true then the pipeline will not be flushed and no clock cycles
will be lost.
 ➢ If the prediction is false then the pipeline is flushed and starts over with the
current instruction.
It is implemented using 4 way set associated cache. This is called Branch Target
Buffer (BTB). The directory entry for each line consists of:
• Valid bit: Indicates whether the entry is valid or not.
• History bit: Track how often bit has been taken.

History Resulting Prediction If branch If branch not

Bits Description made taken taken

Branch Remains in Downgraded to

11 Strongly Taken
Taken same state weakly taken

Branch Upgraded to Downgraded to

10 Weakly Taken
Taken strongly taken weakly not taken

Weakly Not Branch Not Upgraded to Downgraded to

01
Taken Taken weakly taken strongly not taken

Upgraded to
Strongly Not Branch Not Remains in same
00 weakly not
Taken Taken state
taken

Q.8 Enlist the instruction pairing rules of ‘U’ and ‘V’ pipeline in Pentium.
Ans- The Pentium processor can issue one or two instructions every clock. In order to
issue two instructions simultaneously they must satisfy the following conditions:

• Both instructions in the pair must be "simple" as defined below

• There must be no read-after-write or write-after-write register dependencies
between them

• Instructions must not have register contention – Register contention results if 2

instructions attempt to accesst he same register during parallel execution.
• Neither instruction may contain both a displacement and an immediate
 • Instructions with prefixes (other than 0F of JCC instructions) can only occur in the
u-pipe

Q.9 Explain MESI (Modified, Exclusive, Shared, Invalid) Protocol in detail.

The abbreviation of MESI is Modified, Exclusive, Shared, and Invalid, which are
the four possible states of a cache line.

The MESI protocol is a general mechanism to control cache consistency, using

snooping techniques.

The Pentium processors can change the state of a cache line through read or
write cycles or internal snooping.

The MESI protocol provides each cache line that can be one of the four states,
and the MESI protocol is managed by the two MESI bits.

Figure 12.47 shows the state transition diagram of MESI protocol. The
modified, exclusive, shared, and invalid stages of the protocol are explained in
this section.

Modified (M) When the data of a cache line is marked as modified (M), it is
available in a single cache of the complete system only. This cache line can be
read or written to without an external cycle.
Exclusive (E) The exclusive (E) cache line is always stored in only one of the
caches in a computer system, though it has not been modified.

Shared (S) The shared (S) line can be stored in other caches of the system.

Invalid (I) The cache line which is marked as invalid is not available in the
cache. The catch lines marked as invalid (I) lines might be empty or could have
invalid data in the cache.

It is clear from the state transition diagram of MESI protocol that there are six
read access states, R1 to R6; five write access states, W1 to W5, and seven
inquiry or snooping states S1 to S7. The function of each state is given below:

Six Read Access States R1 to Five Write Access States, W1 Seven Inquiry or Snooping
R6 to W5 States, S1 to S7

• R1 (M←M). • W1 (M←M). • S1 (S←M).

• R2 (E←E). • W2 (M←E). • S2 (I←M).
• R3 (S←S). • W3 (E←S). • S3 (S←E).
• R4 (E←I). • W4 (S←S). • S4 (I←E).
• R5 (S←I). • W5 (I←I). • S5 (S←S).
• R6 (I←I). • S6 (I←S).

• S7 The (I←S).