Multiplier with input and output

architectures
 Multiplier
• Consider a multiplier with inputs X and Y and the
product Z.
• If X and Y are represented with n bits each, Z can
have a maximum of 2n bits.
• Assume that both X and Y ·are in the memory and
the product Z has also to be written back to the
memory.
• A single-cycle execution of the multiplication will
then require n bits width bus (for X and Y) and a
third bus of width 2n bits (for' Z).
• This type of bus architecture is expensive to
implement.
 Multiplier
• First, the program bus can be used to transfer one
of the operands (say. Y) after the· multiplication
instruction has been fetched from the program
memory.
• This does not cause an additional overhead when
repeated multiplications are carried out, as is
generally the case with many DSP algorithms.
• This is because, the instruction, once fetched,
usually resides in an on chip cache.
• Second, if separate bus for the product Z can be
discarded, since one of the buses (say, that of X) can
be used to transfer the product to the memory as
the operand X would have been latched long before
the product Z is made available.
 Multiplier
• To handle the 2n bits of Z, there are two available
alternatives:
• Use the X bus (n bits) and save Z at two successive
memory locations using two memory accesses.

• Discard the lower n bits of Z and save only the

higher n bits.
• This is the option most often used since one of the
two operands X and Y (usually Y) is normalized to
one before multiplication so that the n bits dis-
carded from Z are the less significant fractional
bits.
 Shifters
• Shifter is an essential component of any DSP
architecture.
• Shifters are required to scale, down or scale up
operands and results to avoid errors resulting from
overflows and underflows during computations.
• Case (1) It is required to compute the sum of N
numbers, each represented by n bits.
• As the accumulated sum grows, the number of bits
required representing it increases.
• The maximum number of bits to which the sum can
grow is (n +log2 N) bits.
 Shifters
• However, if each of the N numbers is scaled down
by log2 N bits prior to the addition, the loss of the
result due to overflow can be avoided.
• The accumulator will then hold the sum scaled
down, by log2 N bits.
• Although the accuracy of the sum is reduced be-
cause of the loss of log2 N lower-order bits, the
summation would be completed without the
occurrence of the overflow error.
• The actual sum can be obtained' by scaling up the
result by log2 N bits, when required.
 Shifters
• When this product is saved in memory, which is also
n bits wide, the lower-order n bits are generally
discarded, resulting in loss of accuracy.
• For multiplication of two signed numbers, the
accuracy can be slightly improved by shifting the
product by one bit position to the left before saving
the n higher-order bits.
• This is because the 2n-bit product will have two sign
bits and even after discarding one of them (by a
single-bit left shift), the sign of the product is still
preserved.
• The accuracy improves because, instead of
discarding all the n lower-order bits, we now
discard only (n- 1) bits.
 Shifters
• When carrying out floating-point additions, the
operands should be normalized to have the same
exponent.
• Obtained by shifting one of the operands by the
required number of bit positions so that it has the
same exponent as the other operand.
• (1.4*10^2) * (5.7*10^3)
• (1.4*10^2) * (57*10^2)
• (0.14*10^3) * (5.7*10^3)
 Problem
• It is required to find the sum of 64 numbers each
represented by 16 bits. How many bits should the
accumulator have so that the sum can be computed
without the occurrence of overflow error or loss of
accuracy?

• Solution :
• When 64 numbers are added, the sum can grow by
a maximum of logz 64 = 6 bits. To avoid overflow,
the total number of bits the, accumulator should
have is 16 +6 = 22.
 Problem
• If, for the problem of Example 4.2, it is decided to
have an accumulator with only 16 bits but shift the
numbers before the addition to prevent overflow, by
how many bits should each number be shifted?

• Since the sum can grow by 6 bits, in order to

prevent overflow, each number should be shifted by
6 bits to the right before the addition
 Barrel Shifter
• In conventional microprocessors shifting is
normally implemented by an operation similar to
the one performed in a shift register.
• The operation takes one clock cycle for every single
bit shift.
• Such a scheme requires unduly large amounts of time
to implement multibit shifts, which are generally
required in DSP computations
 Barrel Shifter
• In DSPs, on the other hand, in order to preserve the
computational speed of single-cycle instruction
execution, shifts by several bits should be
accomplished in a single cycle.
• Implemented using a Combinational circuit known
as the barrel shifter.
• Barrel shifter connects the input lines representing
a word to a group' of output lines with the
required shift determined by its control inputs.
 Barrel Shifter
• Control input also determines the direction of the shift
(left or right).
• If the input word has n bits, and shifts from 0 to n- 1 bit
positions to the right or left are to be implemented, the
control input requires log2n lines to determine the
number of bits to be shifted.
• An additional line is also required for the control input
to indicate the direction of the shift.
 Barrel Shifter
• Direction of shift is usually fixed, with the result
that only log2 n lines are required for the control
input.
• Bits shifted out of the input word are discarded and
the new bit positions are filled with zeros in the case
of left shift.
• In the case of right shift, the new bit positions are
replicated with the most significant bit to maintain
the sign of the shifted result.
 Barrel Shifter
• Four input bits, (A3A2A1A0) and four output bits
(B3B2B1B0).
• Using this shifter, it is possible to realize right shift by 0,1,
2, or 3 bit positions by setting the control inputs (So, S1, S2,
or S3) high, respectively.
• Only one of the control inputs can be high at any time and
this input closes all the switches controlled by it and enables
the appropriate paths between the inputs and the outputs.
 Barrel Shifter
• Since the circuit for a barrel shifter is a combinational
logic circuit, the time taken to implement the shift is the
total combinational delay involved in decoding the,
control lines and setting up the path from the input lines to
the output lines
• Delay is only a fraction of a clock cycle
 Barrel Shifter
• DSPs, shifting is combined with data transfer.
• Both operations are executed in a single clock cycle.
 Problem
• A barrel shifter is to be designed with 16 inputs for left
shifts from 0 to 15 bits. How many control lines are
required to implement the shifter?

• Number of control lines required is four, since 4 bits

are needed to code any number between 0 and 15, the.
range over which the shift is required to be
accomplished.