Analytical Expression for DC Link Capacitor

Current in a Cascaded H-Bridge Multi-Level Active

Front-End Converter
Muhammad Shehroz Malik Jonathan W. Kimball
Department of Electrical Engineering Department of Electrical Engineering
Missouri University of Science and Technology Missouri University of Science and Technology
Rolla, MO, USA Rolla, MO, USA
[email protected] [email protected]

Abstract—Medium-voltage grid-tied systems often use a cas- to accurately express is so that when such a system is realized
caded H-bridge multi-level active front-end. In this converter, on the dc side by a battery and a shunt aluminium electrolytic
dc link bus capacitors play an important role in stabilizing capacitor, to take a typical example, the amount of current
the converter and enabling both active and reactive power
injections. The present work provides analytical expressions for going through the capacitor can be quantified. The portion of
the capacitor current, which are essential for optimizing system is going through the dc bus capacitor will inherently contain
design (especially capacitor size vs. lifetime). Then, the expression harmonics naturally caused by the switching.
is incorporated into the grid connected bidirectional power These switching harmonics impact the lifetime of the ca-
system model. Consequently, this work contributes to the guiding pacitor. The frequency dependent ESR of the bus capacitor
principles to choose accurate dc link capacitor ratings against
grid-side power delivery requirements. The analytical results dictates the heat dissipated inside it causing the electrolyte
have been validated with detailed simulations and hardware to evaporate and the component itself to age. For typical
results. aluminium electrolytic capacitors, the life of the capacitor
Index Terms—cascaded H-bridge, carrier-based PWM, dc-link halves for every 10 °C rise above the rated temperature as
capacitor lifetime, var compensation dictated by Arrhenius Law [1], [2]. The capacitor lifetime’s
dependency on temperature has been an important concern
I. I NTRODUCTION for reliability of ac-dc converters both in literature as well as
A cascaded H-bridge ac-dc converter consists of more than field operations [3]–[5].
one full-bridge, depending on the number of voltage levels Therefore, various approaches have been used in literature
needed on the ac side. Therefore, to begin with, the building to quantify the dc-link current (instantaneous and rms). One
block of the converter alone is illustrated in Fig. 1 and is method is to rely on a passive solution (i.e., simulations).
referred to as a module in the cascaded system ahead. While simulations are an effective way of finding the dc-
link current in a particular circuit, the results do not reveal
the underlying mathematical relationship which is essential
for studying the overall system. Later in this paper, the
results show how a mathematical framework helps choose the
capacitor with optimal current ratings, instead of a trial-and-
error approach.
In [6], the authors present expression for dc-link current for
a three phase two-level voltage source converter in compressed
integral form. Although the measurement and calculation
results have been presented, the solution of integrals or a
method of calculation is not reported.
Another approach to calculate dc-link current in H-bridge
Fig. 1. Defined quantities in a full bridge circuit based converters is to use analytical estimation techniques,
which can simplify analysis at the cost of accuracy and more
Throughout this paper, the dc-link current is referred as is , importantly, are limited to associated application. A recent
the voltage of the ac side of the full-bridge as vo and the work in [7] evaluates dc-link current for a single phase H-
current, also through the ac side of the full-bridge, as ig . If ig bridge converter by ignoring high frequency harmonics for
is modeled by a sinusoidal current source, then is depends on computational convenience. In the current paper, a mathemat-
how the switches Q1 , Q2 , Q1 and Q2 are driven. It is valuable ical argument illustrates that in a generic case, the rms sum
 ∞ ∞
1 M X X 2 h π i
s1 (t) = + cos(ωo t + θo ) + Jn (m M ) cos(m[ωc t + θc ] + n[ωo t + θo ]) (5)
2 2 m=1 n=−∞
mπ 2

∞ ∞
1 M X X 2 h π i
s2 (t) = + cos(ωo t + θo + π) + Jn (m M ) cos(m[ωc t + θc ] + n[ωo t + θo ] + π) (6)
2 2 m=1 n=−∞
mπ 2

of the higher order harmonics can be equal, or even greater, II. A NALYTICAL BACKGROUND
than the rms of the highest magnitude harmonic. Consider a full-bridge circuit with a dc voltage source and
Fundamental work by McGrath and Holmes [8] expresses ac load in Fig. 1. The first step is to accurately quantify the
the dc-link current in a carrier-based PWM driven half-bridge dc-link current in a single H-bridge and then apply the result
using the double Fourier Series analysis method introduced to the cascaded system later. To solve for the exact dc-link
in [9]. The former reference applies the derived results of current in Fig. 1, the modulated voltage on the ac-side of the
a cosine-triangle PWM based half-bridge converter under H-bridge is defined as
sinusoidal ac-side current on to two-level three phase VSI and
on a three-level flying capacitor inverter. The same authors vo (t) = M cos(ωo t + θo ) (1)
have utilized their framework to derive three-level flying
where M is the modulation index, i.e., the percentage of the
capacitor converter’s voltage balancing dynamics [10] and dc-
amplitude of maximum possible vo that is targeted, while ωo
link current harmonics in dual active bridge dc-dc converters
and θo are the modulation angular frequency and phase of
[11].
vo respectively. The current in the ac side of the H-bridge is
In [12], the focus is on the dc link capacitor current for modeled by a current source as,
a three phase cascaded H-bridge converter connected with a
ig (t) = Ig cos(ωo t + θo + φ) (2)
diode rectifier. A closed form expression for the instantaneous
dc link current is given for the three phase system but a where φ is the relative phase between ig and vo .
(mathematical) argument of why it is applicable to their three Next, the relationship between the switching functions of
phase application has not been discussed. For instance, the the respective half-bridges, s1 (t) and s2 (t), and the ac-side
presented equation shows that in a three phase, multilevel current, ig , is explored. In this case, the dc-link current is a
cascaded H-bridge system, the dc-link current does not depend superposition of the products of switching function and the
on modulator and carrier signals’ phases. However, it does ac-side current. The dc link current can be expressed as
not reveal the dependence of dc-link current on the modu-
lation and carrier phases in the individual H-bridge of the is (t) = [s1 (t) − s2 (t)]ig (t) (3)
cascaded system. A modular relationship is useful in various where s1 (t) and s2 (t) are the switching functions of Q1 and
ways including control for voltage balancing in unbalanced Q2 respectively, as derived for naturally sampled phase shifted
loads. Moreover, an expression for the dc-bus capacitor’s rms cosine-triangle PWM. Q1 and Q2 are complementary switches
current is also presented in the same paper. Even though an of the Q1 and Q2 . These switching functions have been
instantaneous dc-link current expression is available, it serves derived in [9] and are categorized into carrier and modulator
the authors better to use the formula proposed in [13]. The harmonics in Eqs. (5)-(6) (at the top of the page for clarity).
formula has been developed based on graphical observation Here, m is the harmonic number for the fundamental carrier
method after drawing waveforms for a particular load angle (triangle) frequency, wc , and n is the harmonic number for the
and carrier frequency value, which can not be used arbitrarily fundamental modulation (cosine) frequency, wo . Moreover, θc
in a closed form. is the carrier phase in radians, defined for a cascaded phase-
This paper presents a precise analytical model for calculat- shifted-carrier PWM system as follows.
ing dc-link current in a multi-phase cascaded H-bridge multi-  
y−1
level converter on a modular level with detailed analysis and θc = 2π (4)
reporting. The modular results help mathematically explain (N − 1)/2
behavior of the converter, such as the natural voltage balancing In (4), y is the module number and N is the total number
property of the converter, and also provide a framework of levels in vo . Here, the denominator in the bracketed term
that can be utilized in a straightforward manner to study is equal to the number of modules in the cascaded N-level
its interaction on a system level. This leads to the second converter. Additionally, note that in (6), π is added to create the
contribution which is in expressing dc-bus capacitor’s rms anti-phase for the modulation signal in the half-bridge on the
current in terms of active and reactive power at the grid in right side in Fig. 1. π has been separated to avoid confusion in
a bidirectional configuration. case the modulation signal is non-symmetric. This implies that
 M Ig Ig
F −1 [S1 (ω) ∗ Ig (ω)] (t) = cos(φ) + [cos(ωo t + θo ) cos(φ) − sin(ωo t + θo ) sin(φ)]
4 2
∞ ∞ (7)
M Ig X X Ig
+ [cos(2ωo t − 2θo ) cos(φ) + sin(2ωo t − 2θo ) sin(φ)] + α
4 m=1 n=−∞
2

M Ig Ig
F −1 [S2 (ω) ∗ Ig (ω)] (t) = − cos(φ) + [cos(ωo t + θo ) cos(φ) − sin(ωo t + θo ) sin(φ)]
4 2
∞ ∞ (8)
M Ig X X Ig
− [cos(2ωo t − 2θo ) cos(φ) + sin(2ωo t − 2θo ) sin(φ)] − α
4 m=1 n=−∞
2

∞ ∞
M Ig M Ig X X
is (t) = cos(φ) + [cos(2ωo t − 2θo ) cos(φ) + sin(2ωo t − 2θo ) sin(φ)] + Ig α (9)
2 2 m=1 n=−∞

: α = (Km,n+1 + Km,n−1 ) cos(m[ωc t + θc ] + n[ωo t + θo ]) cos(φ) + (Km,n+1 − Km,n−1 ) sin(m[ωc t + θc ] + n[ωo t + θo ]) sin(φ)

2 π
: Kmn = mπ Jn (m 2 M ) sin([m + n] π2 ).

θo is not only defined as the modulation angle of the overall TABLE I

multilevel voltage on the ac-side, but also as the modulation S IMULATION PARAMETERS FOR SECTION III
angle of the left half-bridge in each module. Finally, Jn is the Ig (A) φ (rad) fc (Hz) M N fo (Hz)
Bessel function of the first kind with order n. In a cascaded
7 π/3 3000 0.9 5 60
converter, each half-bridge would have its unique switching
function. Therefore, the equations have been set up to obtain
intra-modular dynamics to investigate the individual dc-link
currents. that this equation can be applied to each module (due to the
series connection) separately to provide information about all
III. D ERIVATION OF DC - LINK CURRENT IN THE IDEAL the modules. Therefore, this equation is applicable to any H-
MODEL AND ITS VALIDATION bridge as in Fig. 1 driven by a naturally sampled cosine-
The derivation strategy is as follows. To obtain the exact triangle pulse width modulation strategy.
harmonic expression for the dc link current for the circuit Now, the validity of the equation is carried using compari-
in Fig. 1, first, the Fourier transform is applied to (3). The son with simulation of Fig. 1 by modeling ig as a sinusoidal
multiplication in the time domain indicated in (3) becomes current source defined in (2) in a single phase five-level
convolution in the frequency domain. The inverse Fourier unidirectional system. The simulation parameter are mentioned
transform is applied to the subsequent result. This process is in table I. In this table, Ig stands for the peak value of the ac-
carried out for each half-bridge of the module separately and load current and other modulation parameters have already
then the contributions are superposed. The contributions from been defined.
the left and right half-bridges towards the dc-link current, is Fig. 2 shows a comparison of the simulation and analytical
of Fig. 1 is summarized in (7) and (8) and then the results are results in time and frequency domain. The difference between
substituted in (3) respectively, to obtain the dc link current for Fig. 2(a) and Fig. 2(b) is because in numerical implementation
the module in (9) (again placed at the top of the page). of (9), the double series sum is for finite indices of m and n. In
Each half-bridge generates a fundamental modulation fre- this implementation, maximum value of m = 10 and n ranges
quency component which is effectively canceled in the super- between -500 and 500. The waveform corresponding to the
position. Whereas, the dc component and remaining modula- numerical implementation of the analytical result exhibits the
tion and carrier harmonics add up to twice the magnitudes. Gibbs phenomenon. Note that this trade-off is more efficient
The elimination of the fundamental modulator harmonic is than ignoring the higher order harmonics as observed in
because of the redistribution of harmonic energy (amplitude) literature. A random frequency band is chosen for comparison
to higher frequencies. Therefore, for dc-link capacitor, a full- in Fig. 2(c) and Fig. 2(d) and the results show a close match
bridge modulation is harmonically more efficient as compared in all of the finite frequency bands up to three decimal places,
to that in a half-bridge converter as the ESR of the capacitor thereby permitting to move ahead.
is relatively lower at higher frequencies. Next, a two-module (five-level) system is studied. It is
Eq. (9) is associated to dc-link current in one independent observed that within one phase, each module has the same
module. The topology of cascaded H-bridge converters is such dc-link current even though each half-bridge is switched
  2  2
 2 
Vˆg
∞ ∞
"  #
1 − ω 2
L C ωCf β 4 π

mπ p 2
f f
X X
2
 2  
Icap,rms =  Pg + Qg −
 2V 2 + sin([m + n] )J β

 
2 Vˆ
 1 − ω 2 Lf Cf DC m=1 n=−∞
mπ 2 VDC
g

 2  2
P g Q g
:β= (2ωLf − ω 3 L2f Cf ) +  (2ωLf − ω 3 L2f Cf ) + Vˆg (1 − ω 2 Lf Cf ) (10)
Vˆg Vˆg

(a) Analytical current in time (b) Simulated current in time

(c) Analytical current harmonics (d) Simulation current harmonics Fig. 3. The grid-tied cascaded H-bridge converter
Fig. 2. (a)-(d) Validation of the ideal dc-link current model

differently from the three remaining half-bridges. In this way,

the natural voltage balancing property is mathematically illus-
trated for the cascaded multilevel converter. These conclusions
motivate hardware implementation and results are evaluated
while studying a grid-tied system in the next section.
IV. A NALYSIS OF A GRID - TIED SYSTEM , AND EVALUATION
OF RESULTS IN THREE DOMAINS
A. Mapping grid power to Icap,rms
A system overview in Fig. 3 shows a typical active front-end
configuration where the grid is modeled by a voltage source
and a five-level cascaded H-bridge converter is connected to
the grid through an LCL filter. It is now possible to map the Fig. 4. DC link capacitor’s rms current contours
the grid’s active and reactive power flow (Pg , Qg ) to the dc-
link current rms of the bus capacitor. Utilizing (9), the rms
current flowing through the bus capacitors is obtained and is A contour plot is shown for (10) in Fig. 4. Close exami-
shown in (10). nation shows that the round contours are not centered at the
In (10), |V̂g | is the line-to-neutral rms of the grid voltage origin and do not form an exact ellipse, as is identified by the
shown in Fig. 5. All other parameters are constant or running equation. For a specific contour, as Pg goes higher, the amount
sum indices. Lf and Cf are the filter inductance and capac- of Qg decreases according to the described relationship. The
itance, J stands for the Bessel function as defined earlier, area enclosed by a contour would depict the complex power
VDC is the dc-bus voltage of each module, ω is the grid’s operating points supported by the corresponding rms rating of
fundamental frequency, while Pg and Qg are the grid’s active the capacitor installed in the hardware.
and reactive power using generator sign convention. Because The relationship between the dc-link capacitor’s rms current
of the symmetry within and between balanced phases, the and grid power Pg and Qg is examined using a surface
equation is applicable to a multi-phase and multilevel system. plot in Fig. 5. Using 10, the graph shows that as operating
 TABLE II 1) Evaluation of analytical and simulation results: The
C ONFIGURATION PARAMETERS analytical model was compared with a simulation setup fol-
Parameter Value
lowing the circuit in Fig. 3. All the parameters from table II
were used except Lh , VDCa and Rf . VDCb was used in the
VDCa (V) 20
analysis of analytical and simulation results of the grid-tied
VDCb (V) 1800
system. The analytical model has been developed based on
fcut−of f (kHz) 6
a sinusoidal current source model whereas its results are to
Lf (mH) 20.63
be compared with Fig. 3 which contains the LCL filter. The
Cf (nF) 34.11
filter was designed for a cut-off frequency of 6 kHz to best
Rf (Ω) 22.35
accommodate the Bode gain and phase plots in the desired
fc (kHz) 3
operating point. Lf was set to 0.05 p.u. of base impedance.
Lh (mH) 1.8
Fig. 6 shows a comparison between the analytical model and
Vg l-n rms (V) 7200
the simulation results.

TABLE III
power levels are increased, the stress on the dc-link capacitor T EST P OINTS TO C OMPARE S IMULATION AND A NALYTICAL C APACITOR
increases non-linearly. It is observed that this plot is not S TRESSES
symmetric around the grid’s active and reactive power. This 1 2 3 4 5 6 7 8
fact is most visible by shifting the discussion focus back to the Pg (kW) 321 0 -321 0 -183 183 166 -167
contours in Fig. 4. Consider the two points where the 94.75 A Qg (kVAR) 5 338 5 -363 168 168 -161 -141
contour crosses zero Pg . In this case, the reactive power being
supplied to the grid, positive Qg , is 0.9 MVAR and in another
operating scenario, the reactive power being drawn from the
grid is around 1.2 MVAR, a point below the chosen contour.
In other words, there is more stress on the capacitor when
the same amount of reactive power is being consumed by the
grid as compared to when it is being supplied by the grid.
The LCL filter demands additional reactive power beyond the
amount being fed to the grid.

Fig. 6. Simulation and analytical comparison for the capacitor stresses

The worst case error in simulation and analytical com-

parison is noted to be about 4.8%. The difference can be
explained based on a few factors. The first reason lies in
the difference between the analytical model of (10), which
assumes sinusoidal ac-side current, and the simulation which
has an LCL filter with a cut-off frequency of 6 kHz. The 6 kHz
range allows for multilevel voltage harmonics to propagate in
the system, thus causing ac-side current harmonics. This in-
turn effects the dc-link current which is a sampled version of
the ac-side current. Therefore, the bus capacitor’s rms current
Fig. 5. Relationship of Icap−rms with grid power will have a different rms than the sinusoidal ac-load case.
Another source of error is evident from the fact that the
simulation implements regularly sampled PWM whereas the
analytical model is based on naturally sampled PWM. Besides
B. Discussion of various results
explaining errors, the results show that for all the sampled
A combination of hardware and simulation results were points in Table. III, the rms portion of the 120 Hz harmonic
compared with analytical model to validate the derived equa- was close to the sum of rms contribution from non-120 Hz
tions. A single phase five-level cascaded converter was de- harmonics (i.e., within 1 A).
veloped and its configuration parameters are shown in ta- 2) Hardware and simulation results evaluation: For hard-
ble II. This table contains specific parameters selected for ware results, a single phase five-level H-bridge converter is
corresponding discussion. Other parameters like modulation operated in the inverter mode with an RL load. Therefore,
frequency, fo , are not mentioned. VDCa , Rf , Lh and fc are hardware and simulation parameters
in this case. For this setup, the dc-link current was measured
and compared with simulations. The five-level voltage, the RL
load current and the voltage output from both half-bridges of
one module can be seen in Fig. 7.

Fig. 9. Simulation dc-link current in one module

to the simulation blocks. This difference has direct impact

on the hardware data-processing of the dc-link current as the
pulse widths are not the same in the microcontroller as the
simulation. However, this is only partially contributing to the
Fig. 7. Hardware results for the five-level cascaded H-bridge converter
deviation in pulse widths as it is a difference due to voltages
but load current does not exist. When the load is turned on,
The ac-side current through the RL load and the output a dynamic behavior between the body diode and IGBT-based
voltage of the half bridges were measured directly as seen in half-bridge causes the pulse width to deviate as well. This
Fig. 7. Since the dc-link current is of discontinuous nature, a deviation is evident from Fig. 7. The conduction of body diode
regular Hall-effect based current probe cannot be used to mea- is initiated during deadtime. Based on the polarity of the load
sure it directly. Therefore, the method recommended in [14] current, corresponding body diodes will conduct. Due to the
was used. The method is described as follows. As illustrated in body diode’s forward voltage drop, the pulses seen in Fig. 7
the referred work, the half-bridge outputs were multiplied with are slightly above and below VDC as well as slightly below and
the ac-side load current to obtain the hardware dc-link current. above the 0 voltage level. Therefore, the overall pulse width
This hardware result was then compared with the simulation profile in the hardware, which is used to calculate dc -link
results as shown in Fig. 8 and Fig. 9 respectively. current, is significantly different than that in the simulation.
The hardware prototype is finally shown in Fig. 10 with two
modules for the five-level converter, micrcontroller and RL
load.

Fig. 8. Hardware dc-link current in one module

The rms current measured in the hardware and that in the

simulation had a worst case difference of 9.2%. This difference
is explained in two parts. The switching functions from the
ideal simulation blocks are not the same as those coming from
Fig. 10. Hardware prototype of the cascaded H-bridge system
the microcontroller. The code implemented in the microcon-
troller contains deadtime which has not been incorporated in
 V. C ONCLUSION AND FUTURE WORK [14] R. W. Reese, L. Wei, and R. A. Lukaszewski, “An indirect method
of measuring dc bus capacitor current,” in Twentieth Annual IEEE
In this paper, a detailed and exact mathematical model Applied Power Electronics Conference and Exposition, 2005. APEC
2005., vol. 2, 2005, pp. 971–978 Vol. 2.
has been developed for the dc-link current in a cascaded
H-bridge multilevel converter. The detail of the model has
been used to study the converter’s interaction with a grid-
tied system. The grid’s active and reactive power commands
have been mapped to the dc-link current stress in the bus
capacitors. The analytical, simulation and hardware results
have been evaluated in a variety of setups and these show a
good match thereby validating the work. For future work, the
derivations motivate deriving a framework for capacitor sizing
against the dc-bus voltage specifications. Overall, this work
contributes to estimating the lifetime of the dc-link capacitors
in an accurate manner which in-turn adds to system reliability
by avoiding contingency outages and improving scheduled
outages in power systems.

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