EE 671: VLSI Design Assignment 1
Name: ABHISHEK AGARWAL Roll no: 23M1171
Q–1 Design a CMOS inverter which gets a rail to rail square wave as the input
with rise/fall times of 20 ps. Your inverter should have equal rise/fall times of
200 + 2×nn ps, where nn represents the last two digits of your roll number. The
design involves the choice of appropriate widths for n and p channel transistors
such that it meets the rise/fall time requirements with the given load. Measure
the rise/fall times of the output by finding the time taken by the output to
traverse between 10% of VDD and 90% of VDD.
Code:
* Minimum Inverter
.subckt inv supply Inp Output
* This subcircuit defines a CMOS inverter with equal n and p widths
.param Wn=0.349u
.param Wp=1.134u
.param l=0.18u
MP1 Output Inp Supply Supply cmosp
+ L=l W=wp AD = {wp*0.36U} AS = {wp*0.36U} PD = {2*(wp+0.36U)} PS =
{2*(wp+0.36U)}
MN1 Output Inp 0 0 cmosn
+ L=l W=wn AD = {wn*0.36U} AS = {wn*0.36U} PD = {2*(wn+0.36U)} PS =
{2*(wn+0.36U)}
.ends
vdd supply 0 dc 1.8
* Device under test
x1 supply Ck dutout inv
* Load Capacitor
C1 dutout 0 0.05pF
.include models-180nm
*TRANSIENT ANALYSIS with pulse inputs
VCk Ck 0 DC 0 PULSE(0 1.8 0nS 20pS 20pS 4nS 8.0nS)
.tran 1pS 35nS 0nS
.control
run
plot 4.0+V(Ck) V(dutout)
meas tran inrise TRIG v(ck) VAL=0.18 RISE=2 TARG v(Ck) VAL=1.62 RISE=2
meas tran infall TRIG v(ck) VAL=1.62 FALL=2 TARG v(Ck) VAL=0.18 FALL=2
meas tran drise TRIG v(dutout) VAL=0.18 RISE=2 TARG v(dutout) VAL=1.62
RISE=2
meas tran dfall TRIG v(dutout) VAL=1.62 FALL=2 TARG v(dutout) VAL=0.18 FALL=2
.endc
.end
For Wn=0.349u and Wp=1.134u The rise time and fall time of the output of the
above inverter has came 342ps which was the desired value.
Q–2 Use ng-spice to plot the static transfer characteristics of this inverter by
using a DC sweep on the input from 0 to VDD. Determine the static noise margins
for it by drawing tangents with slope = -1.
Code:
* Minimum Inverter
.subckt inv supply Inp Output
* This subcircuit defines a CMOS inverter with equal n and p widths
.param Wn=0.24u
.param Wp=0.24u
.param l=0.18u
.param l=0.18u
MP1 Output Inp Supply Supply cmosp
+ L=l W=wp AD = {wp*0.36U} AS = {wp*0.36U} PD = {2*(wp+0.36U)} PS =
{2*(wp+0.36U)}
MN1 Output Inp 0 0 cmosn
+ L=l W=wn AD = {wn*0.36U} AS = {wn*0.36U} PD = {2*(wn+0.36U)} PS =
{2*(wn+0.36U)}
.ends
vdd supply 0 dc 1.8
* Device under test
x2 supply Ck dutout inv
* Load Capacitor
C1 dutout 0 0.05pF
.include models-180nm
*TRANSIENT ANALYSIS with pulse inputs
VCk Ck 0 DC 0 PULSE(0 1.8 0nS 20pS 20pS 4nS 8.0nS)
.dc vck 0 1.8 0.001
*.tran 1pS 35nS 0nS
.control
run
plot V(dutout) vs V(Ck)
plot deriv(V(dutout)) vs V(Ck)
*noise margin
let der = deriv(V(dutout))
meas dc VIl find V(Ck) when der = -1
meas dc VIh find V(Ck) when der = -1 rise = last
meas dc VOh find V(dutout) when V(ck) = VIL
meas dc VOl find V(dutout) when V(ck) = VIH
let noisemargin_high = VOh - VIh
let noisemargin_low = VIl - VOl
print noisemargin_low
print noisemargin_high
.endc
.end
In the plot of d(v(dutout))/d(v(ck)) vs v(ck) meas function finds the value where
the value of derivative is -1, first value is VIL and the second time the derivative
goes -1 gives VIH, now using these values we find the value of V(dutout) at these
2 inputs, being an inverter at Vil we’ll get Voh and at Vih we’ll get Vol.
High noise margin is calculated by Voh-Vih, and low noise margin by Vil-Vol.
Q–3 Using the above inverter as the base design, apply series-parallel rules to
design a logic gate which produces A · (B + C) at its output. Find the rise and fall
times of this gate for the following input combinations:
a) A = ‘1’, B = ‘0’, C = 0 → 1 and C = 1 → 0.
b) A = ‘1’, C = ‘0’, B = 0 → 1 and B = 1 → 0.
c) B = ‘0’, C = ‘1’, A = 0 → 1 and A = 1 → 0. Take a logic ‘1’ to be 0.9VDD and a
logic ‘0’ to be 0.1VDD.
Code:
*question 3
.include models-180nm
.subckt pmos G D S
.param Wp=1.134u
.param l=0.18u
Mp D G S S cmosp
+ L=l W=wp AD = {wp*0.36U} AS = {wp*0.36U} PD = {2*(wp+0.36U)} PS =
{2*(wp+0.36U)}
.ends
.subckt nmos G D S
.param Wn=0.349u
.param l=0.18u
Mn D G S S cmosn
+ L=l W=wn AD = {wn*0.36U} AS = {wn*0.36U} PD = {2*(wn+0.36U)} PS =
{2*(wn+0.36U)}
.ends
*supply voltage
Vdd supply 0 dc 1.8
*load capacitance
C1 out 0 0.05pF
*circuit calling
x1 B d supply pmos
x2 C out d pmos
x3 A out supply pmos
x4 A out k nmos
x5 B k 0 nmos
x6 C k 0 nmos
*a part
VA A 0 DC {0.9*1.8}
VB B 0 DC {0.1*1.8}
VC C 0 DC 0 PULSE(0 1.8 0nS 20pS 20pS 4nS 8.0nS)
*b part
*VA A 0 DC {0.9*1.8}
*VC C 0 DC {0.1*1.8}
*VB B 0 DC 0 PULSE(0 1.8 0nS 20pS 20pS 4nS 8.0nS)
*c part
*VB B 0 DC {0.1*1.8}
*VC C 0 DC {0.9*1.8}
*VA A 0 DC 0 PULSE(0 1.8 0nS 20pS 20pS 4nS 8.0nS)
.tran 1ps 40ns 0ns
.control
run
plot 2+v(A) 4+v(B) 6+v(C) v(out)
meas tran drise TRIG v(out) VAL=0.18 RISE=2 TARG v(out) VAL=1.62 RISE=2
meas tran dfall TRIG v(out) VAL=1.62 FALL=2 TARG v(out) VAL=0.18 FALL=2
.endc
.end
a)
As we can see A is permanent on, and B is off so the output is just complement
of C, rise time and fall time of the following is calculated using meas
b)
As we can see A is permanent on, and C is off so the output is just complement
of B, rise time and fall time of the following is calculated using meas
c)
As we can see C is permanent On, and B is off so output is nothing but
complement of A, rise time and fall time is calculated using meas
