SN54HC541, SN74HC541

SCLS305E – JANUARY 1996 – REVISED MAY 2022

SNx4HC541 Octal Buffers and Line Drivers With 3-State Outputs

1 Features 3 Description
• Wide Operating Voltage Range of 2 V to 6 V These octal buffers and line drivers feature the
• High-Current 3-State Outputs Drive Bus Lines performance of the SNx4HC541 devices and a pinout
Directly or Up to 15 LSTTL Loads with inputs and outputs on opposite sides of the
• Low Power Consumption, 80-µA Maximum ICC package. This arrangement greatly facilitates printed
• Typical tpd = 10 ns circuit board layout.
• ±6-mA Output Drive at 5 V
The 3-state outputs are controlled by a two-input NOR
• Low Input Current of 1 µA Maximum
gate. If either output-enable (OE1 or OE2) input is
• Data Flow-Through Pinout (All Inputs on Opposite
high, all eight outputs are in the high-impedance state.
Side From Outputs)
The SNx4HC541 devices provide true data at the
2 Applications outputs.
• LEDs Device Information
• Servers PART NUMBER PACKAGE
(1)
BODY SIZE (NOM)
• PCs and Notebooks SN74HC541DW SOIC (20) 12.80 mm × 7.50 mm
• Wearable Health and Wellness Devices SN74HC541DB SSOP (20) 7.20 mm × 5.30 mm
• Electronic Points of Sale
SN74HC541N PDIP (20) 24.33 mm × 6.35 mm
SN74HC541NS SO (20) 12.60 mm × 5.30 mm
SN74HC541PW TSSOP (20) 6.50 mm × 4.40 mm
SN54HC541J CDIP (20) 24.20 mm × 6.92 mm
SN54HC541FK LCCC (20) 8.89 mm × 8.89 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
1
OE1
19
OE2

2 18
A1 Y1

To Seven Other Channels

Copyright © 2016, Texas Instruments Incorporated

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 6.14 Operating Characteristics......................................... 8
2 Applications..................................................................... 1 6.15 Typical Characteristics.............................................. 9
3 Description.......................................................................1 7 Parameter Measurement Information.......................... 10
4 Revision History.............................................................. 2 8 Detailed Description...................................................... 11
5 Pin Configuration and Functions...................................3 8.1 Overview................................................................... 11
Pin Functions.................................................................... 3 8.2 Functional Block Diagram......................................... 11
6 Specifications.................................................................. 4 8.3 Feature Description...................................................11
6.1 Absolute Maximum Ratings........................................ 4 8.4 Device Functional Modes..........................................11
6.2 ESD Ratings............................................................... 4 9 Application and Implementation.................................. 12
6.3 Recommended Operating Conditions.........................4 9.1 Application Information............................................. 12
6.4 Thermal Information....................................................5 9.2 Typical Application.................................................... 12
6.5 Electrical Characteristics, TA = 25°C.......................... 5 10 Power Supply Recommendations..............................14
6.6 Electrical Characteristics, SN54HC541...................... 5 11 Layout........................................................................... 14
6.7 Electrical Characteristics, SN74HC541...................... 6 11.1 Layout Guidelines................................................... 14
6.8 Switching Characteristics, CL = 50 pF, TA = 25°C.......6 11.2 Layout Example...................................................... 14
6.9 Switching Characteristics, CL = 50 pF, 12 Device and Documentation Support..........................15
SN54HC541.................................................................. 7 12.1 Related Links.......................................................... 15
6.10 Switching Characteristics, CL = 50 pF, 12.2 Receiving Notification of Documentation Updates..15
SN74HC541.................................................................. 7 12.3 Support Resources................................................. 15
6.11 Switching Characteristics, CL = 150 pF, TA = 12.4 Trademarks............................................................. 15
25°C.............................................................................. 7 12.5 Electrostatic Discharge Caution..............................15
6.12 Switching Characteristics, CL = 150 pF, 12.6 Glossary..................................................................15
SN54HC541.................................................................. 8 13 Mechanical, Packaging, and Orderable
6.13 Switching Characteristics, CL = 150 pF, Information.................................................................... 15
SN74HC541.................................................................. 8

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2016) to Revision E (May 2022) Page
• Updated ESD ratings table to include modern TI terminology............................................................................4
• Junction-to-ambient thermal resistance values increased. DB was 90.2 is now 122.7, DW was 77.5 is now
109.1, N was 45.2 is now 84.6, NS was 72.8 is now 113.4, PW was 98.3 is now 131.8.................................... 5

Changes from Revision C (August 2003) to Revision D (September 2016) Page

• Added Applications section, Thermal Information table, ESD Ratings table, Feature Description section,
Device Functional Modes, Application and Implementation section, Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section............................................................................................................................................. 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the
datasheet............................................................................................................................................................ 1
• Changed RθJA for DB package from 70°C/W: to 90.2°C/W................................................................................ 5
• Changed RθJA for DW package from 58°C/W: to 77.5°C/W............................................................................... 5
• Changed RθJA for N package from 69°C/W: to 45.2°C/W...................................................................................5
• Changed RθJA for NS package from 60°C/W: to 72.8°C/W................................................................................ 5
• Changed RθJA for PW package from 83°C/W: to 98.3°C/W............................................................................... 5

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5 Pin Configuration and Functions

DB, DW, N, NS, J, or PW Package FK Package

20-Pin SSOP, SOIC, PDIP, SO, CDIP, or TSSOP 20-Pin LCCC
Top View Top View

Pin Functions
PIN (1)
I/O DESCRIPTION
NO. NAME
1 OE1 I Output enable (active low) Both OE must be low to enable outputs
2 A1 I Channel 1 input
3 A2 I Channel 2 input
4 A3 I Channel 3 input
5 A4 I Channel 4 input
6 A5 I Channel 5 input
7 A6 I Channel 6 input
8 A7 I Channel 7 input
9 A8 I Channel 8 input
10 GND — Ground
11 Y8 O Channel 8 output
12 Y7 O Channel 7 output
13 Y6 O Channel 6 output
14 Y5 O Channel 5 output
15 Y4 O Channel 4 output
16 Y3 O Channel 3 output
17 Y2 O Channel 2 output
18 Y1 O Channel 1 output
19 OE2 I Output enable (active low) both OE must be low to enable outputs
20 VCC — Power pin

(1) Signal Types: I = Input, O = Output, I/O = Input or Output.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±35 mA
Continuous current through VCC or GND ±70 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

See note(1)
MIN NOM MAX UNIT
VCC Supply voltage 2 5 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 V
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 V
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
Δt/Δv Input transition rise and fall time VCC = 4.5 V 500 ns
VCC = 6 V 400
Operating free-air temperature SN54HC541 –55 125
TA °C
SN74HC541 –40 85

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

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6.4 Thermal Information

SN74HC541
DB (SSOP) DW (SOIC) N (PDIP) NS (SO) PW (TSSOP)
THERMAL METRIC 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS UNIT
RθJA Junction-to-ambient thermal
(1) 122.7 109.1 84.6 113.4 131.8 °C/W
resistance
RθJC (top) Junction-to-case (top) thermal
81.6 76 72.5 78.6 72.2 °C/W
resistance
RθJB Junction-to-board thermal
77.5 77.6 65.3 78.4 82.8 °C/W
resistance
ΨJT Junction-to-top characterization
46.1 51.5 55.3 47.1 21.5 °C/W
parameter
ΨJB Junction-to-board
77.1 77.1 65.2 78.1 82.4 °C/W
characterization parameter
RθJC(bot) Junction-to-case (bottom)
N/A N/A N/A N/A N/A °C/W
thermal resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics, TA = 25°C

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 1.9 1.998
IOH = –20 µA 4.5 V 4.4 4.499
VOH VI = VIH or VIL 6V 5.9 5.999 V
IOH = –6 mA 4.5 V 3.98 4.3
IOH = –7.8 mA 6V 5.48 5.8
2V 0.002 0.1
IOL = 20 µA 4.5 V 0.001 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 V
IOL = 6 mA 4.5 V 0.17 0.26
IOL = 7.8 mA 6V 0.15 0.26
II VI = VCC or 0 6V ±0.1 ±100 nA
IOZ VO = VCC or 0 6V ±0.01 ±0.5 µA
ICC VI = VCC or 0, IO = 0 6V 8 µA
Ci 2 V to 6 V 3 10 pF

6.6 Electrical Characteristics, SN54HC541

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 1.9
IOH = –20 µA 4.5 V 4.4
VOH VI = VIH or VIL 6V 5.9 V
IOH = –6 mA 4.5 V 3.7
IOH = –7.8 mA 6V 5.2

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over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 0.1
IOL = 20 µA 4.5 V 0.1
VOL VI = VIH or VIL 6V 0.1 V
IOL = 6 mA 4.5 V 0.4
IOL = 7.8 mA 6V 0.4
II VI = VCC or 0 6V ±1000 nA
IOZ VO = VCC or 0 6V ±10 µA
ICC VI = VCC or 0, IO = 0 6V 160 µA
Ci 2 V to 6 V 10 pF

6.7 Electrical Characteristics, SN74HC541

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 1.9
IOH = –20 µA 4.5 V 4.4
VOH VI = VIH or VIL 6V 5.9 V
IOH = –6 mA 4.5 V 3.84
IOH = –7.8 mA 6V 5.34
2V 0.1
IOL = 20 µA 4.5 V 0.1
VOL VI = VIH or VIL 6V 0.1 V
IOL = 6 mA 4.5 V 0.33
IOL = 7.8 mA 6V 0.33
II VI = VCC or 0 6V ±1000 nA
IOZ VO = VCC or 0 6V ±5 µA
ICC VI = VCC or 0, IO = 0 6V 80 µA
Ci 2 V to 6 V 10 pF

6.8 Switching Characteristics, CL = 50 pF, TA = 25°C

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 40 115
tpd A Y 4.5 V 12 23 ns
6V 10 20
2V 80 150
ten OE Y 4.5 V 17 30 ns
6V 15 26
2V 40 150
tdis OE Y 4.5 V 18 30 ns
6V 17 26
2V 28 60
tt Y 4.5 V 8 12 ns
6V 6 10

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6.9 Switching Characteristics, CL = 50 pF, SN54HC541

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 171
tpd A Y 4.5 V 34 ns
6V 29
2V 224
ten OE Y 4.5 V 45 ns
6V 38
2V 224
tdis OE Y 4.5 V 45 ns
6V 38
2V 90
tt Y 4.5 V 18 ns
6V 15

6.10 Switching Characteristics, CL = 50 pF, SN74HC541

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 144
tpd A Y 4.5 V 29 ns
6V 25
2V 188
ten OE Y 4.5 V 38 ns
6V 32
2V 188
tdis OE Y 4.5 V 38 ns
6V 32
2V 75
tt Y 4.5 V 15 ns
6V 13

6.11 Switching Characteristics, CL = 150 pF, TA = 25°C

over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 65 165
tpd A Y 4.5 V 16 33 ns
6V 14 28
2V 100 200
ten OE Y 4.5 V 20 40 ns
6V 17 34
2V 45 210
tt Y 4.5 V 17 42 ns
6V 13 36

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6.12 Switching Characteristics, CL = 150 pF, SN54HC541

over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 246
tpd A Y 4.5 V 49 ns
6V 42
2V 298
ten OE Y 4.5 V 60 ns
6V 51
2V 315
tt Y 4.5 V 63 ns
6V 53

6.13 Switching Characteristics, CL = 150 pF, SN74HC541

over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 7-1)
FROM TO
PARAMETER VCC MIN TYP MAX UNIT
(INPUT) (OUTPUT)
2V 206
tpd A Y 4.5 V 41 ns
6V 35
2V 250
ten OE Y 4.5 V 50 ns
6V 43
2V 265
tt Y 4.5 V 53 ns
6V 45

6.14 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per buffer/driver No load 35 pF

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6.15 Typical Characteristics

80 100
tpd tpd
70 ten 90 ten
tdis tt
tt 80
60
70
50

Time (ns)
Time (ns)

60
40
50
30
40
20 30
10 20

0 10
2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6
Vcc (Volts) Vcc (Volts) D001
D001

Figure 6-1. Typical Delay vs. VCC for CL = 50 pF Figure 6-2. Typical Delay vs. VCC for CL = 150 pF

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7 Parameter Measurement Information

VCC
PARAMETER RL CL S1 S2

S1 tPZH 50 pF Open Closed

Test or
t en 1 kΩ
Point RL tPZL Closed Open
From Output 150 pF
Under Test tPHZ Open Closed
CL t dis 1 kΩ 50 pF
S2 tPLZ Closed Open
(see Note A)
50 pF
t pd or t t –– or Open Open
150 pF
LOAD CIRCUIT

VCC
Input 50% 50%
0V
tPLH tPHL

In-Phase VOH
90% 90%
Output 50% 50%
10% 10% V
OL
tr tf Output
Control VCC
tPHL tPLH
VOH (Low-Level 50% 50%
Out-of-Phase 90% 90% Enabling) 0V
50% 50%
Output 10% 10% tPZL tPLZ
VOL
tf tr Output ≈VCC ≈VCC
Waveform 1 50%
VOLTAGE WAVEFORMS
(See Note B) 10% VOL
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
tPZH tPHZ
VCC Output VOH
Input 90% 90% 90%
50% 50% Waveform 2 50%
10% 10% 0 V
(See Note B) ≈0 V
tr tf

VOLTAGE WAVEFORM VOLTAGE WAVEFORMS

INPUT RISE AND FALL TIMES ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 7-1. Load Circuit and Voltage Waveforms

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8 Detailed Description
8.1 Overview
The SN74HC541 device has 8 inputs and outputs where data from the A inputs go to the Y outputs. The output
enables of the device control whether the information from the A inputs go to the Y outputs. These enable pins
cause the device to go into high Z if either OE1 or OE2 are high. The OEs should be tied to VCC through a
pull up resistor to ensure the high impedance state during power up or power down; the minimum value of the
resistor is determined by the current sinking capability of the driver.
8.2 Functional Block Diagram
1
OE1
19
OE2

2 18
A1 Y1

To Seven Other Channels

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Figure 8-1. Logic Diagram (Positive Logic)

8.3 Feature Description

The SNx4HC541 has a wide operating voltage range of 2 V to 6 V. The device has multiple enable pins, and the
device pinout enables simple board layout with outputs across from inputs.
8.4 Device Functional Modes
Table 8-1 lists the functional modes of the SNx4HC541.
Table 8-1. Function Table (Each Buffer/Driver)
INPUTS OUTPUT
OE1 OE2 A Y

L L L L
L L H H
H X X Hi-Z
X H X Hi-Z

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

SN74HC541 is a wide range CMOS device that can be used over large voltage ranges. The device can be used
anywhere from 2 to 6 Volts. The device can drive up to 6 mA of current at 5 Volts. This makes it perfect for
driving bus lines directly or up to 15 LSTTL Loads. It can be used to drive anything from micro controllers and
system logic devices to LEDs.
9.2 Typical Application

OE1 VCC

OE2

A1 Y1
Microcontroller
System Logic
LEDs
Microcontroller or A8 Y8
System Logic
GND

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Figure 9-1. Typical Application Diagram

9.2.1 Design Requirements

This device uses CMOS technology and has a wide voltage range. Take care to avoid pulling too much current
from the outputs as to not exceed 6 mA. Also, take care to not go over VCC voltage to avoid damage to the
device.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs: See (Δt/ΔV) in the Section 6.3 table.
• Specified high and low levels: See (VIH and VIL) in the Section 6.3 table.
• Inputs should not be pulled above VCC.
2. Recommended Output Conditions
• Load currents should not exceed 6 mA for the part
• Outputs should not be pulled above VCC.

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9.2.3 Application Curve

1000
950
900

Input Transition Time (ns)

850
800
750
700
650
600
550
500
450
400
2 2.5 3 3.5 4 4.5 5 5.5 6
Vcc (Volts) D001

Figure 9-2. Input Transition Time vs. VCC

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10 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1-μF is recommended; if there are multiple VCC pins, then 0.01-μF or 0.022-μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1-μF
and a 1-μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. The Section 6.3 section specifies the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever makes more sense or is more convenient. It is generally acceptable to
float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the output
section of the part when asserted. This does not disable the input section of the I/Os, so they cannot float when
disabled.
11.2 Layout Example
Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 11-1. Layout Diagram

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12 Device and Documentation Support

12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54HC541 Click here Click here Click here Click here Click here
SN74HC541 Click here Click here Click here Click here Click here

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: SN54HC541 SN74HC541
 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

JM38510/65711BRA Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 JM38510/
65711BRA
SN54HC541J Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC541J
SN74HC541DBR Active Production SSOP (DB) | 20 2000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 85 HC541
SN74HC541DW Obsolete Production SOIC (DW) | 20 - - Call TI Call TI -40 to 85 HC541
SN74HC541DWR Active Production SOIC (DW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC541
SN74HC541N Active Production PDIP (N) | 20 20 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC541N
SN74HC541NSR Active Production SOP (NS) | 20 2000 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -40 to 85 HC541
SN74HC541PW Obsolete Production TSSOP (PW) | 20 - - Call TI Call TI -40 to 85 HC541
SN74HC541PWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC541
SN74HC541PWT Obsolete Production TSSOP (PW) | 20 - - Call TI Call TI -40 to 85 HC541
SNJ54HC541FK Active Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54HC
541FK
SNJ54HC541J Active Production CDIP (J) | 20 20 | TUBE No SNPB N/A for Pkg Type -55 to 125 SNJ54HC541J

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC541, SN74HC541 :

• Catalog : SN74HC541
• Military : SN54HC541

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC541DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC541DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HC541DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74HC541DWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74HC541NSR SOP NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74HC541NSR SOP NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74HC541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HC541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC541DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74HC541DBR SSOP DB 20 2000 356.0 356.0 35.0
SN74HC541DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74HC541DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74HC541NSR SOP NS 20 2000 367.0 367.0 45.0
SN74HC541NSR SOP NS 20 2000 367.0 367.0 45.0
SN74HC541PWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74HC541PWR TSSOP PW 20 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN74HC541N N PDIP 20 20 506 13.97 11230 4.32
SN74HC541NE4 N PDIP 20 20 506 13.97 11230 4.32
SNJ54HC541FK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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