Ultralow Power, Low Distortion,

Fully Differential ADC Drivers

Data Sheet ADA4940-1/ADA4940-2
FEATURES FUNCTIONAL BLOCK DIAGRAMS
ADA4940-1
Small signal bandwidth: 260 MHz

13 –VS
16 –VS
15 –VS
14 –VS
Ultralow power 1.25mA
Extremely low harmonic distortion
−122 dB THD at 50 kHz –FB 1 12 DISABLE
−96 dB THD at 1 MHz +IN 2 11 –OUT
Low input voltage noise: 3.9 nV/√Hz –IN 3 10 +OUT

0.35 mV maximum offset voltage +FB 4 9 VOCM

Balanced outputs

+VS 8
+VS 7
+VS 5
+VS 6
Settling time to 0.1%: 34 ns
Rail-to-rail output: −VS + 0.1 V to +VS − 0.1 V
NOTES

08452-001
Adjustable output common-mode voltage 1. CONNECT THE EXPOSED PAD TO
–VS OR GROUND.
Flexible power supplies: 3 V to 7 V (LFCSP)
Figure 1. ADA4940-1
Disable pin to reduce power consumption

20 DISABLE1
ADA4940-1 is available in LFCSP and SOIC packages

19 –OUT1
23 –FB1
22 –VS1
21 –VS1
24 +IN1
APPLICATIONS
Low power PulSAR®/SAR ADC drivers
–IN1 1 18 +OUT1
Single-ended-to-differential conversion +FB1 2 17 VOCM1
Differential buffers +VS1 3 16 –VS2
ADA4940-2
Line drivers +VS1 4 15 –VS2
–FB2 5 14 DISABLE2
Medical imaging
+IN2 6 13 –OUT2
Industrial process controls

VOCM2 11
–IN2 7
+FB2 8

+OUT2 12
+VS2 9
+VS2 10
Portable electronics

GENERAL DESCRIPTION

07429-202
NOTES
The ADA4940-1/ADA4940-2 are low noise, low distortion fully 1. CONNECT THE EXPOSED PAD TO
–VS OR GROUND.
differential amplifiers with very low power consumption. They
Figure 2. ADA4940-2
are an ideal choice for driving low power, high resolution, high
The ADA4940-1 is available in a 3 mm × 3 mm, 16-lead LFCSP
performance SAR and Σ-Δ analog-to-digital converters (ADCs)
and an 8-lead SOIC. The ADA4940-2 is available in a 4 mm ×
with resolutions up to 16 bits from dc to 1 MHz on only 1.25 mA
4 mm, 24-lead LFCSP. The pinouts are optimized to facilitate
of quiescent current. The adjustable level of the output common-
printed circuit board (PCB) layout and minimize distortion.
mode voltage allows the ADA4940-1/ADA4940-2 to match the
The ADA4940-1/ADA4940-2 are specified to operate over the
input common-mode voltage of multiple ADCs. The internal
−40°C to +125°C temperature range.
common-mode feedback loop provides exceptional output balance,
as well as suppression of even-order harmonic distortion products. Table 1. Similar Products to ADA4940-1/ADA4940-2
ISUPPLY Bandwidth Slew Rate Noise
With the ADA4940-1/ADA4940-2, differential gain configurations Product (mA) (MHz) (V/μs) (nV/√Hz)
are easily realized with a simple external feedback network of AD8137 3 110 450 8.25
four resistors determining the closed-loop gain of the amplifier. ADA4932-1 9 560 2800 3.6
The ADA4940-1/ADA4940-2 are fabricated using Analog Devices, ADA4941-1 2.2 31 22 5.1
Inc., SiGe complementary bipolar process, enabling them to Table 2. Complementary Products to ADA4940-1/ADA4940-2
achieve very low levels of distortion with an input voltage noise Power Throughput Resolution SNR
of only 3.9 nV/√Hz. The low dc offset and excellent dynamic Product (mW) (MSPS) (Bits) (dB)
performance of the ADA4940-1/ADA4940-2 make them well AD7982 7.0 1 18 98
suited for a variety of data acquisition and signal processing AD7984 10.5 1.333 18 96.5
applications. AD7621 65 3 16 88
AD7623 45 1.333 16 88

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADA4940-1/ADA4940-2 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information .............................................................. 23
Applications ....................................................................................... 1 Analyzing an Application Circuit ............................................ 23
General Description ......................................................................... 1 Setting the Closed-Loop Gain .................................................. 23
Functional Block Diagrams ............................................................. 1 Estimating the Output Noise Voltage ...................................... 23
Revision History ............................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 24
Specifications..................................................................................... 4 Calculating the Input Impedance of an Application Circuit 24
VS = 5 V.......................................................................................... 4 Input Common-Mode Voltage Range ..................................... 25
VS = 3 V.......................................................................................... 6 Input and Output Capacitive AC Coupling ............................ 26
Absolute Maximum Ratings ............................................................ 8 Setting the Output Common-Mode Voltage .......................... 26
Thermal Resistance ...................................................................... 8 DISABLE Pin .............................................................................. 26
Maximum Power Dissipation ..................................................... 8 Driving a Capacitive Load......................................................... 26
ESD Caution .................................................................................. 8 Driving a High Precision ADC ................................................ 27
Pin Configurations and Function Descriptions ........................... 9 Layout, Grounding, and Bypassing .............................................. 28
Typical Performance Characteristics ........................................... 11 ADA4940-1 LFCSP Example .................................................... 28
Test Circuits ..................................................................................... 20 Outline Dimensions ....................................................................... 29
Terminology .................................................................................... 21 Ordering Guide .......................................................................... 30
Definition of Terms .................................................................... 21
Theory of Operation ...................................................................... 22

Rev. E | Page 2 of 30
Data Sheet ADA4940-1/ADA4940-2
REVISION HISTORY
4/2018—Rev. D to Rev. E Changes to Figure 37, Figure38, Figure 39, and Figure 41 ........ 15
Changes to Figure 2........................................................................... 1 Changes to Figure 49, Figure 50, and Figure 51 .......................... 17
Changes to Figure 6.........................................................................10 Added Figure 55 and Figure 57 ..................................................... 18
Updated Outline Dimensions ........................................................29 Changes to Differential VOS, Differential CMRR, and VOCM
CMRR Section ................................................................................. 20
5/2016—Rev. C to Rev. D Changes to Calculating the Input Impedance of an Application
Changes to Figure 1........................................................................... 1 Circuit Section ................................................................................. 23
Deleted Figure 2................................................................................. 1 Changes to Figure 71 ...................................................................... 25
Added Figure 2; Renumbered Sequentially ................................... 1 Changes to Driving a High Precision ADC Section and
Updated Outline Dimensions ........................................................29 Figure 73 ........................................................................................... 26
Changes to Ordering Guide ...........................................................30 Changed ADA4940-1 Example Section to ADA4940-1 LFCSP
Example Section .............................................................................. 27
9/2013—Rev. B to Rev. C Changes to Ordering Guide ........................................................... 29
Updated Outline Dimensions ........................................................30
Changes to Ordering Guide ...........................................................31 12/2011—Rev. 0 to Rev. A
Changes to Features Section, General Description Section, and
3/2012—Rev. A to Rev. B Table 1 ................................................................................................. 1
Reorganized Layout ........................................................... Universal Replaced Figure 1 and Figure 2 ....................................................... 1
Added ADA4940-1 8-Lead SOIC Package ..................... Universal Changes to VS = ±2.5 V (or +5 V) Section and Table 3 ............... 3
Changes to Features Section, Table 1, and Figure 1; Replaced Changes to Table 6 ............................................................................ 5
Figure 2 ............................................................................................... 1 Replaced Figure 7, Figure 8, Figure 9, and Figure 10 ................... 9
Changed VS = ±2 V(or +5 V) Section to VS = +5 V Section ....... 3 Replaced Figure 14, Figure 15, and Figure 17 ............................. 10
Changes to VS = +5 V Section and Table 3 .................................... 3 Replaced Figure 24 and Figure 27 ................................................. 12
Changes to Table 4 and Table 5 ....................................................... 4 Changes to Figure 37 ...................................................................... 14
Changes to VS = 3 V Section and Table 6 ....................................... 5 Replaced Figure 43 and Figure 46 ................................................. 15
Changes to Table 7 and Table 8 ....................................................... 6 Replaced Figure 53 .......................................................................... 18
Added Figure 5 and Table 12, Renumbered Sequentially ............ 9 Changes to Estimating the Output Noise Voltage Section, Table 14,
Changes to Figure 7, Figure 8, and Figure 9 ................................10 Table 15, and Calculating the Input Impedance of an Application
Added Figure 15 and Figure 18; Changes to Figure 13, Circuit Section ................................................................................. 21
Figure 14, and Figure 16 .................................................................11 Changes to Input Common-Mode Voltage Range Section ....... 22
Changes to Figure 19 and Figure 20 .............................................12 Changes to Driving a High Precision ADC Section and
Changes to Figure 25, Figure 26, and Figure 27; Added Figure 65 ........................................................................................... 24
Figure 28, Figure 29, and Figure 30 ..............................................13
Changes to Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, 10/2011—Revision 0: Initial Version
and Figure 36 ...................................................................................14

Rev. E | Page 3 of 30
ADA4940-1/ADA4940-2 Data Sheet

SPECIFICATIONS
VS = 5 V
VOCM = midsupply, RF = RG = 1 kΩ, RL, dm = 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
(See Figure 61 for the definition of terms.)
+DIN or –DIN to VOUT, dm Performance
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p, G = 1 260 MHz
VOUT, dm = 0.1 V p-p, G = 2 220 MHz
VOUT, dm = 0.1 V p-p, G = 5 75 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2 V p-p, G = 1 25 MHz
VOUT, dm = 2 V p-p, G = 2 22 MHz
VOUT, dm = 2 V p-p, G = 5 19 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 2 V p-p, G = 1 and G = 2 14.5 MHz
Slew Rate VOUT, dm = 2 V step 95 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 34 ns
Overdrive Recovery Time G = 2, VIN, dm = 6 V p-p, triangle wave 86 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VOUT, dm = 2 V p-p, fC = 10 kHz −125/−118 dBc
VOUT, dm = 2 V p-p, fC = 50 kHz −123/−126 dBc
VOUT, dm = 2 V p-p, fC = 50 kHz, G = 2 −124/−117 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz −102/−96 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz, G = 2 −100/–92 dBc
IMD3 VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz −99 dBc
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.81 pA/√Hz
Crosstalk VOUT, dm = 2 V p-p, fC = 1 MHz −110 dB
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = VOCM = 0 V −0.35 ±0.06 +0.35 mV
Input Offset Voltage Drift TMIN to TMAX 1.2 µV/°C
Input Bias Current −1.6 −1.1 µA
Input Bias Current Drift TMIN to TMAX −4.5 nA/°C
Input Offset Current −500 ±50 +500 nA
Input Common-Mode Voltage Range −VS − 0.2 to V
+VS − 1.2
Input Resistance Differential 33 kΩ
Common mode 50 MΩ
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ∆VIN, cm = ±1 V dc 86 119 dB
Open-Loop Gain 91 99 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output −VS + 0.1 to −VS + 0.07 to V
+VS − 0.1 +VS − 0.07
Linear Output Current f = 1 MHz, RL, dm = 22 Ω, SFDR = −60 dBc 46 mA peak
Output Balance Error f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm −65 −60 dB

Rev. E | Page 4 of 30
Data Sheet ADA4940-1/ADA4940-2
VOCM to VOUT, cm Performance
Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, cm = 0.1 V p-p 36 MHz
−3 dB Large Signal Bandwidth VOUT, cm = 1 V p-p 29 MHz
Slew Rate VOUT, cm = 1 V p-p 52 V/µs
Input Voltage Noise f = 100 kHz 83 nV/√Hz
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 0.99 1 1.01 V/V
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range −VS + 0.8 to V
+VS − 0.7
Input Resistance 250 kΩ
Offset Voltage VOS, cm = VOUT, cm − VOCM; VIP = VIN = VOCM = 0 V −6 ±1 +6 mV
Input Offset Voltage Drift TMIN to TMAX 20 µV/°C
Input Bias Current −7 +4 +7 µA
CMRR ΔVOS, dm/ΔVOCM, ΔVOCM = ±1 V 86 100 dB

General Performance
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
SOIC 3 6 V
Quiescent Current per Amplifier Enabled 1.05 1.25 1.38 mA
Quiescent Current Drift TMIN to TMAX 4.25 µA/°C
Disabled 13.5 28.5 µA
+PSRR ΔVOS, dm/ΔVS, ΔVS = 1 V p-p 80 90 dB
−PSRR ΔVOS, dm/ΔVS, ΔVS = 1 V p-p 80 96 dB
DISABLE (DISABLE PIN)
DISABLE Input Voltage Disabled ≤(−VS + 1) V
Enabled ≥(−VS + 1.8) V
Turn-Off Time 10 µs
Turn-On Time 0.6 µs
DISABLE Pin Bias Current per Amplifier
Enabled DISABLE = +2.5 V 2 5 µA
Disabled DISABLE = −2.5 V −10 −5 µA
OPERATING TEMPERATURE RANGE −40 +125 °C

Rev. E | Page 5 of 30
ADA4940-1/ADA4940-2 Data Sheet
VS = 3 V
VOCM = midsupply, RF = RG = 1 kΩ, RL, dm = 1 kΩ, TA = 25°C, LFCSP package, unless otherwise noted. TMIN to TMAX = −40°C to +125°C.
(See Figure 61 for the definition of terms.)
+DIN or –DIN to VOUT, dm Performance
Table 6.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, dm = 0.1 V p-p 240 MHz
VOUT, dm = 0.1 V p-p, G = 2 200 MHz
VOUT, dm = 0.1 V p-p, G = 5 70 MHz
−3 dB Large Signal Bandwidth VOUT, dm = 2 V p-p 24 MHz
VOUT, dm = 2 V p-p, G = 2 20 MHz
VOUT, dm = 2 V p-p, G = 5 17 MHz
Bandwidth for 0.1 dB Flatness VOUT, dm = 0.1 V p-p 14 MHz
Slew Rate VOUT, dm = 2 V step 90 V/µs
Settling Time to 0.1% VOUT, dm = 2 V step 37 ns
Overdrive Recovery Time G = 2, VIN, dm = 3.6 V p-p, triangle wave 85 ns
NOISE/HARMONIC PERFORMANCE
HD2/HD3 VOUT, dm = 2 V p-p, fC = 50 kHz (HD2/HD3) −115/−121 dBc
VOUT, dm = 2 V p-p, fC = 1 MHz (HD2/HD3) −104/−96 dBc
IMD3 VOUT, dm = 2 V p-p, f1 = 1.9 MHz, f2 = 2.1 MHz −98 dBc
Input Voltage Noise f = 100 kHz 3.9 nV/√Hz
Input Current Noise f = 100 kHz 0.84 pA/√Hz
Crosstalk VOUT, dm = 2 V p-p, fC = 1 MHz −110 dB
INPUT CHARACTERISTICS
Input Offset Voltage VIP = VIN = VOCM = 1.5 V −0.4 ±0.06 +0.4 mV
Input Offset Voltage Drift TMIN to TMAX 1.2 µV/°C
Input Bias Current −1.6 −1.1 µA
Input Bias Current Drift TMIN to TMAX −4.5 nA/°C
Input Offset Current −500 ±50 +500 nA
Input Common-Mode Voltage Range −VS − 0.2 to V
+VS − 1.2
Input Resistance Differential 33 kΩ
Common mode 50 MΩ
Input Capacitance 1 pF
Common-Mode Rejection Ratio (CMRR) ΔVOS, dm/ΔVIN, cm, ∆VIN, cm = ±0.25 V dc 86 114 dB
Open-Loop Gain 91 99 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output −VS + 0.08 to −VS + 0.04 to V
+VS − 0.08 +VS − 0.04
Linear Output Current f = 1 MHz, RL, dm = 26 Ω, SFDR = −60 dBc 38 mA peak
Output Balance Error f = 1 MHz, ΔVOUT, cm/ΔVOUT, dm −65 −60 dB

Rev. E | Page 6 of 30
Data Sheet ADA4940-1/ADA4940-2
VOCM to VOUT, cm Performance
Table 7.
Parameter Test Conditions/Comments Min Typ Max Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth VOUT, cm = 0.1 V p-p 36 MHz
−3 dB Large Signal Bandwidth VOUT, cm = 1 V p-p 26 MHz
Slew Rate VOUT, cm = 1 V p-p 48 V/µs
Input Voltage Noise f = 100 kHz 92 nV/√Hz
Gain ΔVOUT, cm/ΔVOCM, ΔVOCM = ±0.25 V 0.99 1 1.01 V/V
VOCM CHARACTERISTICS
Input Common-Mode Voltage Range −VS + 0.8 to V
+VS − 0.7
Input Resistance 250 kΩ
Offset Voltage VOS, cm = VOUT, cm − VOCM; VIP = VIN = VOCM = 1.5 V −7 ±1 +7 mV
Input Offset Voltage Drift TMIN to TMAX 20 µV/°C
Input Bias Current −5 +1 +5 µA
CMRR ΔVOS,dm/ΔVOCM, ΔVOCM = ±0.25 V 80 100 dB

General Performance
Table 8.
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range LFCSP 3 7 V
SOIC 3 6 V
Quiescent Current per Amplifier Enabled 1 1.18 1.33 mA
TMIN to TMAX 4.25 µA/°C
Disabled 7 22 µA
+PSRR ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p 80 90 dB
−PSRR ΔVOS, dm/ΔVS, ΔVS = 0.25 V p-p 80 96 dB
DISABLE (DISABLE PIN)
DISABLE Input Voltage Disabled ≤(−VS + 1) V
Enabled ≥(−VS + 1.8) V
Turn-Off Time 16 µs
Turn-On Time 0.6 µs
DISABLE Pin Bias Current per Amplifier
Enabled DISABLE = +3 V 0.3 1 µA
Disabled DISABLE = 0 V −6 −3 µA
OPERATING TEMPERATURE RANGE −40 +125 °C

Rev. E | Page 7 of 30
ADA4940-1/ADA4940-2 Data Sheet

ABSOLUTE MAXIMUM RATINGS

The power dissipated in the package (PD) is the sum of the
Table 9. quiescent power dissipation and the power dissipated in the
Parameter Rating package due to the load drive for all outputs. The quiescent
Supply Voltage 8V power dissipation is the voltage between the supply pins (±VS)
VOCM ±VS times the quiescent current (IS). The load current consists of the
Differential Input Voltage 1.2 V differential and common-mode currents flowing to the load, as
Operating Temperature Range −40°C to +125°C well as currents flowing through the external feedback networks
Storage Temperature Range −65°C to +150°C and internal common-mode feedback loop. The internal
Lead Temperature (Soldering, 10 sec) 300°C resistor tap used in the common-mode feedback loop places a
Junction Temperature 150°C negligible differential load on the output. Consider rms voltages
ESD and currents when dealing with ac signals.
Field Induced Charged Device Model (FICDM) 1250 V
Airflow reduces θJA. In addition, more metal directly in contact
Human Body Model (HBM) 2000 V
with the package leads from metal traces, through holes, ground,
Stresses at or above those listed under Absolute Maximum and power planes reduces the θJA.
Ratings may cause permanent damage to the product. This is a
Figure 3 shows the maximum safe power dissipation in the
stress rating only; functional operation of the product at these
package vs. the ambient temperature for the 8-lead SOIC (θJA =
or any other conditions above those indicated in the operational
158°C/W, single) the 16-lead LFCSP (θJA = 91.3°C/W, single)
section of this specification is not implied. Operation beyond
and 24-lead LFCSP (θJA = 65.1°C/W, dual) packages on a JEDEC
the maximum operating conditions for extended periods may
standard 4-layer board. θJA values are approximations.
affect product reliability.
3.5
THERMAL RESISTANCE
3.0
MAXIMUM POWER DISSIPATION (W)

θJA is specified for the worst-case conditions, that is, θJA is

ADA4940-2 (LFCSP)
specified for the device soldered on a circuit board in still air. 2.5

ADA4940-1 (LFCSP)
Table 10. 2.0
Package Type θJA Unit
8-Lead SOIC (Single)/4-Layer Board 158 °C/W 1.5

16-Lead LFCSP (Single)/4-Layer Board 91.3 °C/W

1.0
24-Lead LFCSP (Dual)/4-Layer Board 65.1 °C/W
ADA4940-1 (SOIC)
0.5

MAXIMUM POWER DISSIPATION

0

08452-004
The maximum safe power dissipation in the ADA4940-1/ –40 –20 0 20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
ADA4940-2 packages is limited by the associated rise in
junction temperature (TJ) on the die. At approximately 150°C, Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
ESD CAUTION
can change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4940-1/ADA4940-2. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.

Rev. E | Page 8 of 30
Data Sheet ADA4940-1/ADA4940-2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADA4940-1

16 –VS
15 –VS

13 –VS
14 –VS
PIN 1
INDICATOR

–FB 1 12 DISABLE
+IN 2 11 –OUT
–IN 3 10 +OUT
+FB 4 9 VOCM

+VS 8
+VS 7
+VS 5
+VS 6

08452-101
NOTES
1. CONNECT THE EXPOSED PAD TO
–VS OR GROUND.

Figure 4. ADA4940-1 Pin Configuration (16-Lead LFCSP)

Table 11. ADA4940-1 Pin Function Descriptions (16-Lead LFCSP)

Pin No. Mnemonic Description
1 −FB Negative Output for Feedback Component Connection.
2 +IN Positive Input Summing Node.
3 −IN Negative Input Summing Node.
4 +FB Positive Output for Feedback Component Connection.
5 to 8 +VS Positive Supply Voltage.
9 VOCM Output Common-Mode Voltage.
10 +OUT Positive Output for Load Connection.
11 −OUT Negative Output for Load Connection.
12 DISABLE Disable Pin.
13 to 16 −VS Negative Supply Voltage.
Exposed pad (EPAD) Connect the exposed pad to −VS or ground.

–IN 1 8 +IN
VOCM 2 7 DISABLE
+VS 3 6 –VS
08452-003

+OUT 4 5 –OUT
ADA4940-1

Figure 5. ADA4940-1 Pin Configuration (8-Lead SOIC)

Table 12. ADA4940-1 Pin Function Descriptions (8-Lead SOIC)

Pin No. Mnemonic Description
1 −IN Negative Input Summing Node
2 VOCM Output Common-Mode Voltage
3 +VS Positive Supply Voltage
4 +OUT Positive Output for Load Connection
5 −OUT Negative Output for Load Connection
6 −VS Negative Supply Voltage
7 DISABLE Disable Pin
8 +IN Positive Input Summing Node

Rev. E | Page 9 of 30
ADA4940-1/ADA4940-2 Data Sheet

20 DISABLE1
19 –OUT1
23 –FB1
22 –VS1
21 –VS1
24 +IN1
–IN1 1 18 +OUT1
+FB1 2 17 VOCM1
+VS1 3 16 –VS2
ADA4940-2
+VS1 4 15 –VS2
–FB2 5 14 DISABLE2
+IN2 6 13 –OUT2

VOCM2 11
–IN2 7
+FB2 8

+OUT2 12
+VS2 9
+VS2 10

08452-102
NOTES
1. CONNECT THE EXPOSED PAD TO
–VS OR GROUND.

Figure 6. ADA4940-2 Pin Configuration (24-Lead LFCSP)

Table 13. ADA4940-2 Pin Function Descriptions (24-Lead LFCSP)

Pin No. Mnemonic Description
1 −IN1 Negative Input Summing Node 1.
2 +FB1 Positive Output Feedback Pin 1.
3, 4 +VS1 Positive Supply Voltage 1.
5 −FB2 Negative Output Feedback Pin 2.
6 +IN2 Positive Input Summing Node 2.
7 −IN2 Negative Input Summing Node 2.
8 +FB2 Positive Output Feedback Pin 2.
9, 10 +VS2 Positive Supply Voltage 2.
11 VOCM2 Output Common-Mode Voltage 2.
12 +OUT2 Positive Output 2.
13 −OUT2 Negative Output 2.
14 DISABLE2 Disable Pin 2.
15, 16 −VS2 Negative Supply Voltage 2.
17 VOCM1 Output Common-Mode Voltage 1.
18 +OUT1 Positive Output 1.
19 −OUT1 Negative Output 1.
20 DISABLE1 Disable Pin 1.
21, 22 −VS1 Negative Supply Voltage 1.
23 −FB1 Negative Output Feedback Pin 1.
24 +IN1 Positive Input Summing Node 1.
Exposed pad (EPAD) Connect the exposed pad to −VS or ground.

Rev. E | Page 10 of 30
Data Sheet ADA4940-1/ADA4940-2

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VS = ±2.5 V, G = 1, RF = RG = 1 kΩ, RT = 52.3 Ω (when used), RL = 1 kΩ, unless otherwise noted. See Figure 59 and Figure 60 for the
test circuits.
3 3
G = 1, RL = 1kΩ
2 2

1 1

0 0 G = 2, RL = 1kΩ

NORMALIZED GAIN (dB)

NORMALIZED GAIN (dB)

–1 –1

–2 G = 1, RL = 200Ω –2

–3 –3

–4 G = 2, RL = 1kΩ –4
G = 2, RL = 200Ω
–5 –5

–6 G = 2, RL = 200Ω –6
–7 G = 1, RL = 200Ω
–7
G = 1, RL = 1kΩ
–8 –8
VOUT, dm = 0.1V p-p VOUT = 2V p-p
–9 –9

08452-009
08452-006
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 7. Small Signal Frequency Response for Various Gains and Loads Figure 10. Large Signal Frequency Response for Various Gains and Loads
(LFCSP)
3 3
VS = ±3.5V
2 2
1 1 VS = ±3.5V
0 0
VS = ±2.5V
–1 –1
VS = ±2.5V
GAIN (dB)

–2
GAIN (dB)

–2
VS = ±1.5V
–3 –3 VS = ±1.5V
–4 –4
–5 –5
–6 –6
–7 –7
–8 –8
VOUT, dm = 0.1V p-p VOUT = 2V p-p
–9 –9
08452-007

08452-010
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 8. Small Signal Frequency Response for Various Supplies (LFCSP) Figure 11. Large Signal Frequency Response for Various Supplies

3 3
2 2
–40°C
1 1
0 0 –40°C
–1 –1
+25°C +25°C
–2
GAIN (dB)

–2
GAIN (dB)

–3 +125°C
–3
+125°C
–4 –4
–5 –5
–6 –6
–7 –7
–8 –8
VOUT, dm = 0.1V p-p VOUT, dm = 2V p-p
–9 –9
08452-008

08452-011

1 10 100 1000 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 9. Small Signal Frequency Response for Various Temperatures (LFCSP) Figure 12. Large Signal Frequency Response for Various Temperatures

Rev. E | Page 11 of 30
ADA4940-1/ADA4940-2 Data Sheet
4 3
SOIC-1 LFCSP-1
3 LFCSP-1 2 LFCSP-2: CH1
2 LFCSP-2: CH2
1
SOIC-1
1 0
0
LFCSP-2: CH2 –1
–1
–2
GAIN (dB)

GAIN (dB)
–2 LFCSP-2:CH1
–3
–3
–4
–4
–5
–5
–6
–6
–7 –7

–8 VOUT, dm = 0.1V p-p –8

VOUT = 2V p-p
–9 –9

08452-012

08452-015
0.1 1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 13. Small Signal Frequency Response for Various Packages Figure 16. Large Signal Frequency Response for Various Packages

3 3
VOCM = –1V
2 VOCM = 0V 2
VOCM = 0V
1 1 VOCM = +1V

0 0
VOCM = –1V
–1 –1
–2 –2
GAIN (dB)

GAIN (dB)

VOCM = +1V
–3 –3
–4 –4
–5 –5
–6 –6
–7 –7
–8 VOUT, dm = 0.1V p-p –8 VOUT, dm = 2V p-p
–9 –9
08452-013

08452-016
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 14. Small Signal Frequency Response at Various VOCM Levels (LFCSP) Figure 17. Large Signal Frequency Response at Various VOCM Levels

4 4
VOCM = 0V SOIC: RL = 1kΩ
3 3
SOIC: RL = 200Ω
2 2
1 1
0 0
LFCSP: RL = 1kΩ
–1 VOCM = –1V –1
GAIN (dB)

GAIN (dB)

–2 –2
VOCM = +1V LFCSP: RL = 200Ω
–3 –3
–4 –4
–5 –5
–6 –6
–7 –7
–8 V –8 V
OUT, dm = 0.1V p-p OUT, dm = 0.1V p-p
–9 –9
08452-205

08452-203

0.1 1 10 100 1000 0.1 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 15. Small Signal Frequency Response for Various VOCM (SOIC) Figure 18. Small Signal Frequency Response for Various Packages and Loads

Rev. E | Page 12 of 30
Data Sheet ADA4940-1/ADA4940-2
4 4
CCOM1 = CCOM2 = 2pF CCOM1 = CCOM2 = 0pF
3 3
CCOM1 = CCOM2 = 0.5pF
2 2 CCOM1 = CCOM2 = 1pF
CCOM1 = CCOM2 = 2pF
1 1
0 0
–1 CCOM1 = CCOM2 = 1pF –1
GAIN (dB)

GAIN (dB)
–2 CCOM1 = CCOM2 = 0.5pF –2
–3 CCOM1 = CCOM2 = 0pF –3
–4 –4
–5 –5
–6 –6
–7 –7
–8 CDIFF = 0pF –8 CDIFF = 0pF
VOUT = 0.1V p-p VOUT = 2V p-p
–9 –9

08452-014

08452-017
1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 19. Small Signal Frequency Response for Various Capacitive Loads Figure 22. Large Signal Frequency Response for Various Capacitive Loads
(LFCSP)
0.25 0.25

0.20 0.20

0.15 0.15
NORMALIZED GAIN (dB)

NORMALIZED GAIN (dB)

0.10 0.10

0.05 0.05 G = 1, RL = 1kΩ

0 0

–0.05 –0.05
G = 2, RL = 200Ω G = 2, RL = 200Ω
–0.10 –0.10 G = 2, RL = 1kΩ
G = 2, RL = 1kΩ
–0.15
G = 1, RL = 200Ω
–0.15 G = 1, RL = 200Ω

–0.20 –0.20
VOUT, dm = 0.1V p-p G = 1, RL = 1kΩ VOUT, dm = 2V p-p
–0.25 –0.25
08452-018

08452-021
0.1 1 10 100 1000 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 20. 0.1 dB Flatness Small Signal Frequency Response for Figure 23. 0.1 dB Flatness Large Signal Frequency Response for
Various Gains and Loads (LFCSP) Various Gains and Loads
3 3
2 2

1 1

0 0
VS = ±2.5V
–1 VS = ±2.5V –1

–2 –2
GAIN (dB)
GAIN (dB)

VS = ±1.5V
–3 –3 VS = ±1.5V

–4 –4

–5 –5

–6 –6

–7 –7

–8 –8 VOUT, dm = 1V p-p
VOUT, dm = 0.1V p-p
–9 –9
08452-022
08452-019

1 10 100 1000 1 10 100 1000

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 21. VOCM Small Signal Frequency Response for Various Supplies Figure 24. VOCM Large Signal Frequency Response for Various Supplies

Rev. E | Page 13 of 30
ADA4940-1/ADA4940-2 Data Sheet
–20 –20
VOUT, dm = 2V p-p VOUT, dm = 2V p-p
–30 –30
HD3, G = 2
–40 –40
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

HD3, G = 1
–50 –50

–60 –60
HD3, G = 2
–70 –70

–80 HD3, G = 1 –80

–90 HD2, G = 2 –90 HD2, G = 2

–100 HD2, G = 1 –100 HD2, G = 1

–110 –110

–120 –120

–130 –130

08452-023

08452-200
0.01 0.1 1 10 0.01 0.1 1 10
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 25. Harmonic Distortion vs. Frequency for Various Gains (LFCSP) Figure 28. Harmonic Distortion vs. Frequency vs. Gain (SOIC)

–20 –20
VOUT, dm = 2V p-p VOUT, dm = 2V p-p
–30 –30
–40 –40
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

–50 –50
HD3, RL = 200Ω
–60 –60
HD3, RL = 200Ω
–70 –70
–80 HD3, RL = 1kΩ
–80
HD2, RL = 200Ω
–90 –90
HD2, RL = 1kΩ
–100 HD2, RL = 1kΩ –100
HD2, RL = 200Ω
–110 –110

–120 –120
HD3, RL = 1kΩ
–130 –130
08452-020

08452-201
0.01 0.1 1 10 0.01 0.1 1 10
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 26. Harmonic Distortion vs. Frequency for Various Loads (LFCSP) Figure 29. Harmonic Distortion vs. Frequency for Various Loads (SOIC)

–20 –20
VOUT, dm = 2V p-p VOUT, dm = 2V p-p
–30 –30

–40 –40
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

–50 –50

–60 –60

–70 –70

–80 –80
HD2, VS = ±3.5V –90
–90
HD3, VS = ±1.5V
–100 –100
HD2, VS = ±1.5V HD2, ±2.5V
HD2, ±1.5V
–110 HD3, VS = ±3.5V –110
HD2, VS = ±2.5V
–120 –120
HD3, VS = ±2.5V HD3, ±1.5V HD3, ±2.5V
–130 –130
08452-202
08452-024

0.01 0.1 1 10 0.01 0.1 1 10

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 27. Harmonic Distortion vs. Frequency for Various Supplies (LFCSP) Figure 30. Harmonic Distortion vs. Frequency for Various Supplies (SOIC)

Rev. E | Page 14 of 30
Data Sheet ADA4940-1/ADA4940-2
–20 –20
f = 1MHz VS = ±1.5V HD2
VOUT, dm = 2V p-p
–30 –30
SPURIOUS-FREE DYNAMIC RANGE (dBc)

–40 VS = ±1.5V HD3

–40

HARMONIC DISTORTION (dBc)

–50 –50
–60 VS = +3V, 0V HD3
–60
–70 VS = +3V, 0V HD2
–70
–80 VS = ±3.5V HD2
–80 VS = ±2.5V HD2
SOIC: RL = 200Ω –90
–90
SOIC: RL = 1kΩ –100 VS = ±3.5V HD3
–100
–110 VS = ±2.5V HD3
–110
–120
LFCSP: RL = 1kΩ
–120 –130
LFCSP: RL = 200Ω
–130 –140

08452-030

08452-027
0.01 0.1 1 10 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz) VOUT, dm (V p-p)

Figure 31. Spurious-Free Dynamic Range vs. Frequency at Figure 34. Harmonic Distortion vs. VOUT, dm for Various Supplies, f = 1 MHz
RL = 200 Ω and RL = 1 kΩ (LFCSP)
–20 –20
VOUT, dm = 2V p-p +VS = +3V, –VS = 0V
–30 –30 VOUT, dm = 2V p-p
–40 –40
HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

–50
–50
–60
–60
–70
–70
–80 HD3 AT 1MHz
HD2 AT 1MHz –80
–90
–90 HD2 AT 1MHz
–100
–100 HD3 AT 1MHz
–110
–120 –110
HD2 AT 100kHz
–130 –120 HD3 AT 100kHz
–140 HD2 AT 100kHz –130
HD3 AT 100kHz
–150 –140
08452-025

08452-028
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0
VOCM (V) VOCM (V)

Figure 32. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, Figure 35. Harmonic Distortion vs. VOCM for 100 kHz and 1 MHz, 3 V Supply
±2.5 V Supplies (LFCSP) (LFCSP)
–20 –20
VOUT, dm = 2V p-p
–30 HD3 AT VOUT, dm = 8V p-p –30

–40 HD2 AT VOUT, dm = 8V p-p –40

HARMONIC DISTORTION (dBc)

HARMONIC DISTORTION (dBc)

–50 –50
HD3 AT VOUT, dm = 4V p-p
–60
–60 HD2 AT VOUT, dm = 4V p-p
–70
–70
HD3, RF = RG = 499Ω
HD2 AT VOUT, dm = 2V p-p –80
–80
–90
–90
–100 HD2, RF = RG = 499Ω
HD3 AT VOUT, dm = 2V p-p
–100 HD3, RF = RG = 1kΩ
–110
–110 –120
–120 –130 HD2, RF = RG = 1kΩ

–130 –140
08452-026

08452-029

0.01 0.1 1 10 0.01 0.1 1 10

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 33. Harmonic Distortion vs. Frequency for Various VOUT, dm (LFCSP) Figure 36. Harmonic Distortion vs. Frequency for Various RF and RG (LFCSP)

Rev. E | Page 15 of 30
ADA4940-1/ADA4940-2 Data Sheet
10 –60
VOUT, dm = 2V p-p VOUT, dm = 2V p-p
0 (ENVELOPE)
–10 –70
NORMALIZED SPECTRUM (dBc)

–20
–80
–30

CROSSTALK (dB)
CHANNEL 1 TO CHANNEL 2
–40
–90
–50
–60
–100
–70
–80
–110
–90 CHANNEL 2 TO CHANNEL 1
–100 –120
–110
–120 –130

08452-033

08452-039
1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 37. 2 MHz Intermodulation Distortion (LFCSP) Figure 40. Crosstalk vs. Frequency, ADA4940-2

130 120

120 110

100
110
LFCSP
90
100
80 –PSRR
CMRR (dB)

PSRR (dB)

90
70
80
SOIC 60
+PSRR
70
50
60
40

50 30

40 20
08452-100

08452-034
0.1 1 10 100 0.1 1 10 100
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 38. CMRR vs. Frequency Figure 41. PSRR vs. Frequency

–10 100 0
VOUT, dm = 2V p-p 90 –15
–20 80 –30
70 –45
OUTPUT BALANCE (dB)

–30 60 –60

PHASE (Degrees)
50 –75
GAIN (dB)

–40 40 –90
30 –105
–50 20 –120
10 –135
–60 0 –150
–10 –165
–70 –20 –180
–30 –195
–80 –40 –210
08452-035
08452-032

0.1 1 10 100 10k 100k 1M 10M 100M 1G

FREQUENCY (MHz) FREQUENCY (Hz)

Figure 39. Output Balance vs. Frequency Figure 42. Open-Loop Gain and Phase vs. Frequency

Rev. E | Page 16 of 30
Data Sheet ADA4940-1/ADA4940-2
8 2.0 0.5
G = +2
1.6 0.4
6
VOUT, dm 1.2 INPUT 0.3
4
OUTPUT VOLTAGE (V)

0.8 0.2
2

VOLTAGE (V)
2 × VIN 0.4 OUTPUT 0.1

ERROR (%)
%ERROR
0 0 0

–0.4 –0.1
–2
–0.8 –0.2
–4
–1.2 –0.3
–6
–1.6 –0.4
VOUT, dm = 2V p-p
–8 –2.0 –0.5

08452-041

08452-065
0 100 200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80
TIME (ns) TIME (ns)

Figure 43. Output Overdrive Recovery, G = 2 Figure 46. 0.1% Settling Time

100 100
INPUT VOLTAGE NOISE (nV/√Hz)

10

OUTPUT IMPEDANCE (Ω)

10 1

0.1

1 0.01
08452-037

08452-040
10 100 1k 10k 100k 1M 10M 0.1 1 10 100
FREQUENCY (Hz) FREQUENCY (MHz)
Figure 44. Voltage Noise Spectral Density, Referred to Input Figure 47. Closed-Loop Output Impedance Magnitude vs. Frequency, G = 1

1.50 0 2.50 0
+2.5V 0V
R1 R2
1.25 –0.25 2.25 –2.5V –0.25
–OUT, VICM = 1V –FB DISABLE

1.00 –0.50 2.00

+IN –OUT DISABLE –0.50
DISABLE PIN VOLTAGE (V)

VOCM

DISABLE PIN VOLTAGE (V)

0.75 –0.75 1.75
0.1µF +OUT
–0.75
OUTPUT VOLTAGE (V)

0V VICM
+2.5V
OUTPUT VOLTAGE (V)

R1 R2 –IN

–2.5V +FB
0.50 –FB DISABLE
–1.00 1.50 R1 R2 –1.00
–2.5V

+IN –OUT
0.25 DISABLE –1.25 1.25 –1.25
VOCM
0 VICM
0.1µF +OUT –1.50 1.00 –1.50
–IN
–0.25 +FB –1.75 0.75 –1.75
R1 R2
–OUT, VICM = 1V
–2.5V
–0.50 –2.00 0.50 –2.00
–0.75 +OUT, VICM = 1V –2.25 +OUT, VICM = 1V
0.25 –2.25
–1.00 –2.50 0 –2.50
–1.25 –2.75 –0.25 –2.75
08452-038

08452-057

0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (µs) TIME (µs)

Figure 45. DISABLE Pin Turn-Off Time Figure 48. DISABLE Pin Turn-On Time

Rev. E | Page 17 of 30
ADA4940-1/ADA4940-2 Data Sheet
100 1.5
G = 1, RL = 200Ω
80
G = 2, RL = 200Ω 1.0
60
OUTPUT VOLTAGE (mV)

OUTPUT VOLTAGE (V)

40
G = 2, RL = 1kΩ 0.5
20
G = 1, RL = 1kΩ
0 0

–20
–0.5 G = 1, RL = 1kΩ
–40 G = 1, RL = 200Ω
G = 2, RL = 1kΩ
–60 G = 2, RL = 200Ω
–1.0
–80
VOUT, dm = 0.1V p-p VOUT, dm = 2V p-p
–100 –1.5

08452-042

08452-045
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns) TIME (ns)

Figure 49. Small Signal Transient Response for Various Gains and Loads Figure 52. Large Signal Transient Response for Various Gains and Loads
(LFCSP)
100 1.5
VS = ±3.5V VS = ±1.5V
80
VS = ±1.5V
1.0
60
VS = ±2.5V
OUTPUT VOLTAGE (mV)

OUTPUT VOLTAGE (V)

40
VS = ±2.5V 0.5
20

0 0

–20
–0.5
–40

–60
–1.0
–80 VS = ±3.5V
VOUT, dm = 0.1V VOUT, dm = 2V p-p
–100 –1.5
08452-043

08452-046
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns) TIME (ns)

Figure 50. Small Signal Transient Response for Various Supplies (LFCSP) Figure 53. Large Signal Transient Response for Various Supplies

100 1.5

80
1.0
60
OUTPUT VOLTAGE (mV)

OUTPUT VOLTAGE (V)

40
0.5
20

0 0
CCOM1 = CCOM2 = 0pF CCOM1 = CCOM2 = 0pF
–20 CCOM1 = CCOM2 = 0.5pF CCOM1 = CCOM2 = 0.5pF
CCOM1 = CCOM2 = 1pF –0.5 CCOM1 = CCOM2 = 1pF
–40 CCOM1 = CCOM2 = 2pF CCOM1 = CCOM2 = 2pF

–60
–1.0
–80 CDIFF = 0pF CDIFF = 0pF
VOUT, dm = 0.1V p-p VOUT, dm = 2V p-p
–100 –1.5
08452-044

08452-047

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns) TIME (ns)

Figure 51. Small Signal Transient Response for Various Capacitive Loads Figure 54. Large Signal Transient Response for Various Capacitive Loads
(LFCSP)

Rev. E | Page 18 of 30
Data Sheet ADA4940-1/ADA4940-2
100 100
LFCSP-1 LFCSP-1
80 LFCSP-2: CH1 80 LFCSP-2: CH1
LFCSP-2: CH2 LFCSP-2: CH2
SOIC-1 SOIC-1
60 60
OUTPUT VOLTAGE (mV)

OUTPUT VOLTAGE (mV)

40 40

20 20

0 0

–20 –20

–40 –40

–60 –60

–80 –80
VOUT, dm = 0.1V p-p VOUT, dm = 0.1V p-p
–100 –100

08452-204

08452-206
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
TIME (ns) TIME (ns)

Figure 55. Small Signal Transient Response for Various Packages, CL = 0 pF Figure 57. Small Signal Transient Response for Various Packages, CL = 2 pF

100 1.00

80
VS = ±2.5V 0.75 VS = ±2.5V
60
0.50
OUTPUT VOLTAGE (mV)

OUTPUT VOLTAGE (V)

40
VS = ±1.5V
VS = ±1.5V 0.25
20

0 0

–20
–0.25
–40
–0.50
–60
–0.75
–80
VOUT, dm = 0.1V p-p VOUT, dm = 1V p-p
–100 –1.00
08452-048

08452-053
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
TIME (ns) TIME (ns)

Figure 56. VOCM Small Signal Transient Response Figure 58. VOCM Large Signal Transient Response

Rev. E | Page 19 of 30
ADA4940-1/ADA4940-2 Data Sheet

TEST CIRCUITS
1kΩ
NETWORK NETWORK
ANALYZER +2.5V ANALYZER
OUTPUT INPUT
50Ω 1kΩ 475Ω 50Ω

52.3Ω 54.9Ω
VIN VOCM ADA4940-1/
ADA4940-2 54.9Ω
1kΩ 50Ω

25.5Ω 475Ω

08452-067
–2.5V
1kΩ

Figure 59. Equivalent Basic Test Circuit

1kΩ
DC-COUPLED +2.5V
GENERATOR
100Ω 50Ω
50Ω LOW-PASS 1kΩ 475Ω 2:1 DUAL HP
FILTER FILTER LP
54.9Ω
VIN VOCM ADA4940-1/ CT
52.3Ω
ADA4940-2
1kΩ 475Ω 54.9Ω

25.5Ω

08452-056
–2.5V
1kΩ

Figure 60. Test Circuit for Distortion Measurements

Rev. E | Page 20 of 30
Data Sheet ADA4940-1/ADA4940-2

TERMINOLOGY
DEFINITION OF TERMS Common-Mode Offset Voltage
–FB
The common-mode offset voltage is defined as the difference
RF
between the voltage applied to the VOCM terminal and the
RG common mode of the output voltage.
+DIN +IN
–OUT – VOS, cm = VOUT, cm − VOCM
+VOCM ADA4940-1/ RL, dm
ADA4940-2 VOUT, dm Differential VOS, Differential CMRR, and VOCM CMRR
+
RG +OUT
–DIN –IN The differential mode and common-mode voltages each have
RF
their own error sources. The differential offset (VOS, dm) is the

08452-090
+FB voltage error between the +IN and −IN terminals of the amplifier.
Differential CMRR reflects the change of VOS, dm in response to
Figure 61. Circuit Definitions changes to the common-mode voltage at the input terminals
Differential Voltage +DIN and −DIN.
Differential voltage refers to the difference between two node ΔV IN, cm
CMRR DIFF 
voltages. For example, the differential output voltage (or ΔVOS, dm
equivalently, output differential mode voltage) is defined as
VOCM CMRR reflects the change of VOS, dm in response to
VOUT, dm = (V+OUT − V−OUT)
changes to the common-mode voltage at the output terminals.
where V+OUT and V−OUT refer to the voltages at the +OUT and
ΔVOCM
−OUT terminals with respect to a common reference. CMRRVOCM 
ΔVOS, dm
Similarly, the differential input voltage is defined as
Balance
VIN, dm = (+DIN − (−DIN))
Balance is a measure of how well the differential signals are
Common-Mode Voltage (CMV)
matched in amplitude; the differential signals are exactly 180°
CMV refers to the average of two node voltages. The output apart in phase. By this definition, the output balance is the
common-mode voltage is defined as magnitude of the output common-mode voltage divided by
VOUT, cm = (V+OUT + V−OUT)/2 the magnitude of the output differential mode voltage.
Similarly, the input common-mode voltage is defined as VOUT , cm
Output Balance Error 
VIN, cm = (+DIN + (−DIN))/2 VOUT , dm

Rev. E | Page 21 of 30
ADA4940-1/ADA4940-2 Data Sheet

THEORY OF OPERATION
The ADA4940-1/ADA4940-2 are high speed, low power The differential feedback loop forces the voltages at +IN and −IN
differential amplifiers fabricated on Analog Devices advanced to equal each other. This fact sets the following relationships:
dielectrically isolated SiGe bipolar process. They provide two + DIN V
= − −OUT
closely balanced differential outputs in response to either RG RF
differential or single-ended input signals. An external feedback
network that is similar to a voltage feedback operational − DIN V
= − +OUT
amplifier sets the differential gain. The output common-mode RG RF
voltage is independent of the input common-mode voltage and Subtracting the previous equations gives the relationship that
is set by an external voltage at the VOCM terminal. The PNP shows RF and RG setting the differential gain.
input stage allows input common-mode voltages between the
negative supply and 1.2 V below the positive supply. A rail-to- RF
(V+OUT − V−OUT) = (+DIN – (−DIN)) ×
rail output stage supplies a wide output voltage range. RG
The DISABLE pin can reduce the supply current of the The common-mode feedback loop drives the output common-
amplifier to 13.5 µA. mode voltage that is sampled at the midpoint of the output
Figure 62 shows the ADA4940-1/ADA4940-2 architecture. voltage divider to equal the voltage at VOCM. This results in the
The differential feedback loop consists of the differential trans- following relationships:
conductance GDIFF working through the GO output buffers and V+OUT = VOCM + VOUT, dm
the RF/RG feedback networks. The common-mode feedback 2
loop is set up with a voltage divider across the two differential V−OUT = VOCM − VOUT, dm
outputs to create an output voltage midpoint and a common- 2
mode transconductance, GCM. Note that the differential amplifier’s summing junction input
+DIN
RG RF voltages, +IN and −IN, are set by both the output voltages and
CC the input voltages.
 RF   RG 
V+ IN = + DIN   
 + V−OUT  R + R


GO –OUT  RF + RG   F G 
 RF   RG 
+IN V− IN = − DIN   + V+OUT 
 R +R


–IN
GDIFF GCM
VOCM
 RF + RG   F G 
VREF

GO +OUT
08452-058

RG CC
–DIN
RF

Figure 62. ADA4940-1/ADA4940-2 Architectural Block

Rev. E | Page 22 of 30
Data Sheet ADA4940-1/ADA4940-2

APPLICATIONS INFORMATION
VnRG1 VnRF1
ANALYZING AN APPLICATION CIRCUIT RG1 RF1

The ADA4940-1/ADA4940-2 use open-loop gain and negative inIN+

feedback to force their differential and common-mode output
+
voltages in such a way as to minimize the differential and common- VnIN ADA4940-1/ VnOD
mode error voltages. The differential error voltage is defined as inIN–
ADA4940-2
the voltage between the differential inputs labeled +IN and −IN (see
Figure 61). For most purposes, this voltage is zero. Similarly, the
difference between the actual output common-mode voltage and VOCM

the voltage applied to VOCM is also zero. Starting from these two

08452-050
VnCM
RG2 RF2
assumptions, any application circuit can be analyzed. VnRG2 VnRF2

Figure 63. ADA4940-1/ADA4940-2 Noise Model

SETTING THE CLOSED-LOOP GAIN
Determine the differential mode gain of the circuit in Figure 61 As with conventional op amp, the output noise voltage densities
by using the following equation: can be estimated by multiplying the input-referred terms at +IN
and −IN by the appropriate output factor,
VOUT , dm RF where:
=
VIN , dm RG 2
GN = is the circuit noise gain.
(β1 + β2 )
This assumes that the input resistors (RG) and feedback resistors
RG1 RG2
(RF) on each side are equal. β1 = and β2 = are the feedback factors.
RF1 + RG1 RF2 + RG2
ESTIMATING THE OUTPUT NOISE VOLTAGE
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
Estimate the differential output noise of the ADA4940-1/
becomes
ADA4940-2 by using the noise model in Figure 63. The input-
referred noise voltage density, vnIN, is modeled as a differential 1 R
GN = =1+ F
input, and the noise currents, inIN− and inIN+, appear between β RG
each input and ground. The noise currents are assumed equal
Note that the output noise from VOCM goes to zero in this case.
and produce a voltage across the parallel combination of the gain
The total differential output noise density, vnOD, is the root-sum-
and feedback resistances. vnCM is the noise voltage density at the
square of the individual output noise terms.
VOCM pin. Each of the four resistors contributes (4kTRx)1/2. Table 14
summarizes the input noise sources, the multiplication factors, 8

and the output-referred noise density terms. For more noise

vnOD = ∑ vnOi
2

i =1
calculation information, go to the Analog Devices Differential
Amplifier Calculator (DiffAmpCalc™), click
ADIDiffAmpCalculator.zip, and follow the on-screen prompts.

Table 14. Output Noise Voltage Density Calculations

Input Noise Output Output-Referred Noise
Input Noise Contribution Input Noise Term Voltage Density Multiplication Factor Voltage Density Term
Differential Input vnIN vnIN GN vnO1 = GN (vnIN)
Inverting Input inIN− inIN− × (RG2||RF2) GN vnO2 = GN [inIN− × (RG2||RF2)]
Noninverting Input inIN+ inIN+ × (RG1||RF1) GN vnO3 = GN [inIN+ × (RG1||RF1)]
VOCM Input vnCM vnCM GN (β1 − β2) vnO4 = GN (β1 − β2)(vnCM)
Gain Resistor RG1 vnRG1 (4kTRG1)1/2 GN (1 − β2) vnO5 = GN (1 − β2)(4kTRG1)1/2
Gain Resistor RG2 vnRG2 (4kTRG2)1/2 GN (1 − β1) vnO6 = GN (1 − β1)(4kTRG2)1/2
Feedback Resistor RF1 vnRF1 (4kTRF1)1/2 1 vnO7 = (4kTRF1)1/2
Feedback Resistor RF2 vnRF2 (4kTRF2)1/2 1 vnO8 = (4kTRF2)1/2

Rev. E | Page 23 of 30
ADA4940-1/ADA4940-2 Data Sheet
Table 15 and Table 16 list several common gain settings, recommended resistor values, input impedances, and output noise density for both
balanced and unbalanced input configurations.
Table 15. Differential Ground-Referenced Input, DC-Coupled, RL = 1 kΩ (See Figure 64)
Nominal Gain (dB) RF (Ω) RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 2000 11.3 11.3
6 1000 500 1000 15.4 7.7
10 1000 318 636 20.0 6.8
14 1000 196 392 27.7 5.5

Table 16. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, RL = 1 kΩ (See Figure 65)

Nominal Gain (dB) RF (Ω) RG (Ω) RT (Ω) RIN, se (Ω) RG1 (Ω) 1 Differential Output Noise Density (nV/√Hz) RTI (nV/√Hz)
0 1000 1000 52.3 1333 1025 11.2 11.2
6 1000 500 53.6 750 526 15.0 7.5
10 1000 318 54.9 512 344 19.0 6.3
14 1000 196 59.0 337 223 25.3 5
1
RG1 = RG + (RS||RT)

IMPACT OF MISMATCHES IN THE FEEDBACK For an unbalanced, single-ended input signal (see Figure 65),
NETWORKS the input impedance is
Even if the external feedback networks (RF/RG) are mismatched,  
 
the internal common-mode feedback loop still forces the outputs RIN , se =  RG 
to remain balanced. The amplitudes of the signals at each output  RF 
 1 − 2 × (R + R ) 
remain equal and 180° out of phase. The input-to-output,  G F 

differential mode gain varies proportionately to the feedback RF

mismatch, but the output balance is unaffected. +VS

As well as causing a noise contribution from VOCM, ratio-matching RG +IN

errors in the external resistors result in a degradation of the ability +DIN
VOCM ADA4940-1/
of the circuit to reject input common-mode signals, much the ADA4940-2
VOUT, dm
–DIN
same as for a four resistors difference amplifier made from a RG –IN
conventional op amp.

08452-051
In addition, if the dc levels of the input and output common- RF

mode voltages are different, matching errors result in a small Figure 64. ADA4940-1/ADA4940-2 Configured for Balanced (Differential) Inputs
differential mode, output offset voltage. When G = 1, with a RF

ground-referenced input signal and the output common-mode +VS

level set to 2.5 V, an output offset of as much as 25 mV (1% of RS RG

+IN
the difference in common-mode levels) can result if 1% tolerance
RT VOCM
resistors are used. Resistors of 1% tolerance result in a worst- ADA4940-1/ VOUT, dm
ADA4940-2
case input CMRR of about 40 dB, a worst-case differential mode RG

output offset of 25 mV due to the 2.5 V level-shift, and no RS RT

–IN
08452-052

significant degradation in output balance error. RF

CALCULATING THE INPUT IMPEDANCE OF AN Figure 65. ADA4940-1/ADA4940-2 Configured for

APPLICATION CIRCUIT Unbalanced (Single-Ended) Input

The effective input impedance of a circuit depends on whether The input impedance of the circuit is effectively higher than it
the amplifier is being driven by a single-ended or differential would be for a conventional op amp connected as an inverter
signal source. For balanced differential input signals, as shown because a fraction of the differential output voltage appears at
in Figure 64, the input impedance (RIN, dm) between the inputs the inputs as a common-mode signal, partially bootstrapping
(+DIN and −DIN) is simply RIN, dm = 2 × RG. the voltage across the input resistor RG1.

Rev. E | Page 24 of 30
Data Sheet ADA4940-1/ADA4940-2
Terminating a Single-Ended Input RS RTH
50Ω RT 25.5Ω
This section describes how to properly terminate a single-ended VS 52.3Ω VTH
2V p-p 1.02V p-p
input to the ADA4940-1/ADA4940-2 with a gain of 1, RF = 1 kΩ

08452-061
and RG = 1 kΩ. An example using an input source with a terminated
output voltage of 1 V p-p and source resistance of 50 Ω illustrates Figure 68. Calculating the Thevenin Equivalent
the three steps that must be followed. Because the terminated RTS = RTH = RS||RT = 25.5 Ω. Note that VTH is greater than
output voltage of the source is 1 V p-p, the open-circuit output 1 V p-p, which was obtained with RT = 50 Ω. The modified
voltage of the source is 2 V p-p. The source shown in Figure 66 circuit with the Thevenin equivalent (closest 1% value used for
indicates this open-circuit voltage. RTH) of the terminated source and RTS in the lower feedback
RF loop is shown in Figure 69.
1kΩ RF
RIN, se
1.33kΩ +VS
1kΩ
RS RG +VS

50Ω 1kΩ RTH RG

VS ADA4940-1
VOCM
2V p-p ADA4940-2 RL VOUT, dm 25.5Ω 1kΩ
VTH
RG VOCM ADA4940-1 RL VOUT, dm
1.02V p-p
ADA4940-2
1kΩ RG

RTS 1kΩ
–VS
25.5Ω
08452-059

RF
–VS
1kΩ

08452-062
RF
Figure 66. Calculating Single-Ended Input Impedance, RIN 1kΩ

1. The input impedance is calculated by Figure 69. Thevenin Equivalent and Matched Gain Resistors

    Figure 69 presents a tractable circuit with matched feedback

    loops that can be easily evaluated.
R =  1000  = 1.33 kΩ
RIN , se =  G
 RF   1000  It is useful to point out two effects that occur with a terminated
 1 −   1 − 
 2 × ( R G + R F )   2 × ( 1000 + 1000 ) input. The first is that the value of RG is increased in both loops,
2. To match the 50 Ω source resistance, calculate the lowering the overall closed-loop gain. The second is that VTH
termination resistor, RT, using RT||1.33 kΩ = 50 Ω. is a little larger than 1 V p-p, as it would be if RT = 50 Ω.
The closest standard 1% value for RT is 52.3 Ω. These two effects have opposite impacts on the output voltage,
and for large resistor values in the feedback loops (~1 kΩ), the
RF
effects essentially cancel each other out. For small RF and RG,
1kΩ
RIN, se
50Ω +VS or high gains, however, the diminished closed-loop gain is not
cancelled completely by the increased VTH. This can be seen by
RS RG
evaluating Figure 69.
50Ω RT 1kΩ
VS
2V p-p
52.3Ω VOCM ADA4940-1 RL VOUT, dm The desired differential output in this example is 1 V p-p
ADA4940-2
RG because the terminated input signal was 1 V p-p and the
1kΩ closed-loop gain = 1. The actual differential output voltage,
however, is equal to (1.02 V p-p)(1000/1025.5) = 0.996 V p-p.
–VS
This is within the tolerance of the resistors, so no change to
08452-060

RF
1kΩ
the feedback resistor, RF, is required.
Figure 67. Adding Termination Resistor RT
INPUT COMMON-MODE VOLTAGE RANGE
3. Figure 67 shows that the effective RG in the upper feedback
The ADA4940-1/ADA4940-2 input common-mode range is
loop is now greater than the RG in the lower loop due to the
shifted down by approximately 1 VBE, in contrast to other ADC
addition of the termination resistors. To compensate for the
drivers with centered input ranges, such as the ADA4939-1/
imbalance of the gain resistors, add a correction resistor (RTS)
ADA4939-2. The downward-shifted input common-mode range
in series with RG in the lower loop. RTS is the Thevenin
is especially suited to dc-coupled, single-ended-to-differential,
equivalent of the source resistance, RS, and the termination
and single-supply applications.
resistance, RT, and is equal to RS||RT.
For ±2.5 V or +5 V supply operation, the input common-mode
range at the summing nodes of the amplifier is specified as −2.7 V
to +1.3 V or −0.2 V to 3.8 V, and is specified as −0.2 V to +1.8 V
with a +3 V supply.

Rev. E | Page 25 of 30
ADA4940-1/ADA4940-2 Data Sheet
INPUT AND OUTPUT CAPACITIVE AC COUPLING +VS

Although the ADA4940-1/ADA4940-2 is best suited to dc-

coupled applications, it is nonetheless possible to use it in ac-
coupled circuits. Input ac coupling capacitors can be inserted
between the source and RG. This ac coupling blocks the flow
of the dc common-mode feedback current and causes the AMPLIFIER
BIAS CURRENT
ADA4940-1/ADA4940-2 dc input common-mode voltage to DISABLE

equal the dc output common-mode voltage. These ac coupling

capacitors must be placed in both loops to keep the feedback

08452-063
factors matched. Output ac coupling capacitors can be placed in –VS

series between each output and its respective load. Figure 70. DISABLE Pin Circuit

SETTING THE OUTPUT COMMON-MODE VOLTAGE DRIVING A CAPACITIVE LOAD

The VOCM pin of the ADA4940-1/ADA4940-2 is internally A purely capacitive load reacts with the bond wire and pin
biased at a voltage approximately equal to the midsupply point, inductance of the ADA4940-1/ADA4940-2, resulting in high
[(+VS) + (−VS)]/2. Relying on this internal bias results in an frequency ringing in the transient response and loss of phase
output common-mode voltage that is within approximately margin. One way to minimize this effect is to place a resistor in
100 mV of the expected value. series with each output to buffer the load capacitance. The resistor
and load capacitance form a first-order, low-pass filter; therefore,
In cases where more accurate control of the output common-mode
the resistor value must be as small as possible. In some cases,
level is required, it is recommended that an external source, or
the ADCs require small series resistors to be added on their inputs.
resistor divider (10 kΩ or greater resistors), be used. The output
common-mode offset listed in the Specifications section assumes Figure 71 illustrates the capacitive load vs. the series resistance
that the VOCM input is driven by a low impedance voltage source. required to maintain a minimum 45° of phase margin.
120
It is also possible to connect the VOCM input to a common-mode
VIN
R3 R4 +2.5V

level (CML) output of an ADC. However, care must be taken to 100 +IN
–FB
–OUT RS

ensure that the output has sufficient drive capability. The input VOCM
CL
SERIES RESISTANCE (Ω)

impedance of the VOCM pin is approximately 250 kΩ. 0.1µF CL

+OUT
80 –IN RS

DISABLE PIN
+FB
R1 R2
–2.5V

The ADA4940-1/ADA4940-2 feature a DISABLE pin that can 60

be used to minimize the quiescent current consumed when the

device is not being used. DISABLE is asserted by applying a low 40

logic level to the DISABLE pin. The threshold between high and
20
low logic levels is nominally 1.4 V above the negative supply rail.
See Table 5 and Table 8 for the threshold limits.
0

08452-064
The DISABLE pin features an internal pull-up network that 5 10 100 1000
LOAD CAPACITANCE (pF)
enables the amplifier for normal operation. The ADA4940-1/
Figure 71. Capacitive Load vs. Series Resistance (LFCSP)
ADA4940-2 DISABLE pin can be left floating (that is, no
external connection is required) and does not require an
external pull-up resistor to ensure normal on operation (see
Figure 70). When the ADA4940-1/ADA4940-2 is disabled, the
output is high impedance. Note that the outputs are tied to the
inputs through the feedback resistors and to the source using the
gain resistors. In addition, there are back-to-back diodes on the
input pins that limit the differential voltage to 1.2 V.

Rev. E | Page 26 of 30
Data Sheet ADA4940-1/ADA4940-2
DRIVING A HIGH PRECISION ADC mode voltage of 2.5 V, each ADA4940-1 output swings between
The ADA4940-1/ADA4940-2 are ideally suited for broadband 0 V and 5 V, opposite in phase, providing a gain of 1 and a
dc-coupled applications. The circuit in Figure 73 shows a front- 10 V p-p differential signal to the ADC input. The differential RC
end connection for an ADA4940-1 driving an AD7982, which is section between the ADA4940-1 output and the ADC provides
an 18-bit, 1 MSPS successive approximation, analog-to-digital single-pole, low-pass filtering with a corner frequency of 1.79 MHz
converter (ADC) that operates from a single power supply, 3 V and extra buffering for the current spikes that are output from the
to 5 V. It contains a low power, high speed, 18-bit sampling ADC input when its sample-and-hold (SHA) capacitors are
ADC and a versatile serial interface port. The reference voltage, discharged.
REF, is applied externally and can be set independent of the The total system power in Figure 73 is under 35 mW. A large
supply voltage. As shown in Figure 73, the ADA4940-1 is dc- portion of that power is the current coming from supplies to the
coupled on the input and the output, which eliminates the need output, which is set at 2.5 V, going back to the input through the
for a transformer to drive the ADC. The amplifier performs a feedback and gain resistors. To reduce that power to 25 mW,
single-ended-to-differential conversion if needed and level increase the value of the feedback and gain resistor from 1 kΩ
shifts the input signal to match the input common mode of the to 2 kΩ and set the value of the resistors R5 and R6 to 3 kΩ. The
ADC. The ADA4940-1 is configured with a dual 7 V supply ADR435 is used to regulate the +6 V supply to +5 V, which ends
(+6 V and −1 V) and a gain that is set by the ratio of the up powering the ADC and setting the reference voltage for the
feedback resistor to the gain resistor. In addition, the circuit VOCM pin.
can be used in a single-ended-input-to-differential output or Figure 72 shows the FFT of a 20 kHz differential input tone
differential-input-to-differential output configuration. If needed, sampled at 1 MSPS. The second and third harmonics are down
a termination resistor in parallel with the source input can be at −118 dBc and −122 dBc.
used. Whether the input is a single-ended input or differential, 0
the input impedance of the amplifier can be calculated as shown in
the Terminating a Single-Ended Input section. If R1 = R2 = R3 = –20

R4 = 1 kΩ, the single-ended input impedance is approximately –40

1.33 kΩ, which, in parallel with a 52.3 Ω termination resistor,
AMPLITUDE (dB)

provides a 50 Ω termination for the source. An additional 25.5 Ω –60

(1025.5 Ω total) at the inverting input balances the parallel –80

impedance of the 50 Ω source and the termination resistor driving
–100
the noninverting input. However, if a differential source input is
used, the differential input impedance is 2 kΩ. In this case, two –120
52.3 Ω termination resistors are used to terminate the inputs.
–140
In this example, the signal generator has a 10 V p-p symmetric,
ground-referenced bipolar output. The VOCM input is bypassed for –160

08452-069
0 20k 40k 60k 80k 100k
noise reduction and set externally with 1% resistors to 2.5 V to FREQUENCY (Hz)
maximize the output dynamic range. With an output common- Figure 72. Distortion Measurement of a 20 kHz Input Tone (See CN-0237)
+6V

ADR435

+5V
+DIN +6V 10µF
R3 R4

–FB
+2.5V
+IN

–OUT 33Ω REF VDD

R5
IN+
VOCM 2.7nF
ADA4940-1 AD7982
R6 0.1µF 2.7nF
IN–
+OUT 33Ω GND

–IN
SERIAL
+FB INTERFACE
08452-066

R1 R2
–DIN –1V

Figure 73. ADA4940-1 (LFCSP) Driving the AD7982 ADC

Rev. E | Page 27 of 30
ADA4940-1/ADA4940-2 Data Sheet

LAYOUT, GROUNDING, AND BYPASSING

As a high speed device, the ADA4940-1/ADA4940-2 are Bypass the power supply pins as close to the device as possible
sensitive to the PCB environment in which they operate. and directly to a nearby ground plane. Use high frequency ceramic
Realizing their superior performance requires attention to chip capacitors. Use two parallel bypass capacitors (1000 pF and
the details of high speed PCB design. 0.1 µF) for each supply. Place the 1000 pF capacitor closer to the
device. Further away, provide low frequency bypassing using
ADA4940-1 LFCSP EXAMPLE
10 µF tantalum capacitors from each supply to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4940-1 as possible. Ensure that signal routing is short and direct to avoid parasitic
However, clear the area near the feedback resistors (RF), gain effects. Wherever complementary signals exist, provide a
resistors (RG), and the input summing nodes (Pin 2 and Pin 3) symmetrical layout to maximize balanced performance. When
of all ground and power planes (see Figure 74). Clearing the routing differential signals over a long distance, ensure that
ground and power planes minimizes any stray capacitance at PCB traces are close together, and twist any differential wiring
these nodes and prevents peaking of the response of the such that loop area is minimized. Doing this reduces radiated
amplifier at high frequencies. energy and makes the circuit less susceptible to interference.
1.30
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer 0.80

circuit board, as described in EIA/JESD 51-7.

1.30 0.80

08452-087
Figure 75. Recommended PCB Thermal Attach Pad Dimensions (mm)
08452-086

Figure 74. Ground and Power Plane Voiding in Vicinity of RF and RG

1.30

TOP METAL

GROUND PLANE

0.30

PLATED
VIA HOLE

POWER PLANE
08452-088

BOTTOM METAL

Figure 76. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)

Rev. E | Page 28 of 30
Data Sheet ADA4940-1/ADA4940-2

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10 0.30
3.00 SQ 0.23
PIN 1 2.90 0.18
INDICATOR
13 16 PIN 1
0.50 INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
BSC 12 1

1.45
EXPOSED
PAD 1.30 SQ
1.15
9 4

0.50 8 5 0.20 MIN

TOP VIEW BOTTOM VIEW
0.40
0.30
FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 SIDE VIEW THE PIN CONFIGURATION AND
0.05 MAX
0.70 FUNCTION DESCRIPTIONS
0.02 NOM SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING 0.08
PLANE 0.20 REF

10-11-2017-B
PKG-004337

COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6

Figure 77. 16-Lead Lead Frame Chip Scale Package [LFCSP]

3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 78. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

Rev. E | Page 29 of 30
ADA4940-1/ADA4940-2 Data Sheet
DETAIL A
(JEDEC 95)
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.18
INDICATOR PIN 1
19 24
INDIC ATOR AREA OPTIONS
0.50 (SEE DETAIL A)
BSC 18 1

EXPOSED 2.65
PAD
2.50 SQ
2.45
13 6

0.50 12 7
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
3.16 MIN
0.30
0.80 FOR PROPER CONNECTION OF
0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO
0.02 NOM THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
0.08
SEATING
PLANE

10-19-2017-B
0.20 REF
PKG-004462

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.

Figure 79. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option Ordering Quantity Marking Code
ADA4940-1ACPZ-R2 −40°C to +125°C 16-Lead LFCSP CP-16-21 250 H29
ADA4940-1ACPZ-RL −40°C to +125°C 16-Lead LFCSP CP-16-21 5,000 H29
ADA4940-1ACPZ-R7 −40°C to +125°C 16-Lead LFCSP CP-16-21 1,500 H29
ADA4940-1ARZ −40°C to +125°C 8-Lead SOIC_N R-8 98
ADA4940-1ARZ-RL −40°C to +125°C 8-Lead SOIC_N R-8 2,500
ADA4940-1ARZ-R7 −40°C to +125°C 8-Lead SOIC_N R-8 1,000
ADA4940-2ACPZ-R2 −40°C to +125°C 24-Lead LFCSP CP-24-7 250
ADA4940-2ACPZ-RL −40°C to +125°C 24-Lead LFCSP CP-24-7 5,000
ADA4940-2ACPZ-R7 −40°C to +125°C 24-Lead LFCSP CP-24-7 1,500
1
Z = RoHS Compliant Part.

©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D08452-0-4/18(E)

Rev. E | Page 30 of 30