IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO.

5, MAY 2006 501

HotSpot: A Compact Thermal Modeling Methodology

for Early-Stage VLSI Design
Wei Huang, Student Member, IEEE, Shougata Ghosh, Siva Velusamy, Karthik Sankaranarayanan,
Kevin Skadron, Senior Member, IEEE, and Mircea R. Stan, Senior Member, IEEE

Abstract—This paper presents HotSpot—a modeling method- example, knowing the across-die temperature distribution at de-
ology for developing compact thermal models based on the pop- sign time permits thermally self-consistent leakage power calcu-
ular stacked-layer packaging scheme in modern very large-scale lations in an iterative manner, as shown in Fig. 1(a) [1]–[3]. Sim-
integration systems. In addition to modeling silicon and pack-
aging layers, HotSpot includes a high-level on-chip interconnect ilarly, an efficient thermal model can also help to close the loop
self-heating power and thermal model such that the thermal for temperature-aware performance and reliability analysis, as
impacts on interconnects can also be considered during early suggested in Fig. 1(b). In particular, it is crucial to take thermal
design stages. The HotSpot compact thermal modeling approach effects into account as early as possible in the design flow, be-
is especially well suited for preregister transfer level (RTL) and cause optimal early and high-level thermally related design de-
presynthesis thermal analysis and is able to provide detailed static
and transient temperature information across the die and the cisions can significantly improve design efficiency and reduce
package, as it is also computationally efficient. design cost.
Index Terms—Compact thermal model, early design stages, in-
Obviously, it is impractical to accurately analyze thermal
terconnect self-heating, temperature, VLSI. effects and model temperature distribution of a system together
with the environment in their full details. Using numerical
thermal analysis methods, such as the finite-element method
I. INTRODUCTION (FEM), is a time-consuming process not suitable for de-
sign-time and run-time thermal analysis. In order to gain more
A N unfortunate side effect of miniaturization and the con-
tinued scaling of CMOS technology is the ever-increasing
power densities. The resulting difficulties in managing temper-
insights of the thermal effects during early IC design stages, the
tradeoff solution is to build compact thermal models (CTMs)
atures, especially local hot spots, have become one of the major that give reasonably accurate temperature predictions with little
challenges for designers at all design levels. High temperatures computational effort at desired levels of abstraction [5]. Early
have several significant impacts on VLSI systems. First, the design stages present unique challenges that we believe require
carrier mobility is degraded at higher temperature, resulting in a by-construction compact modeling approach.
slower devices. Second, leakage power is escalated due to the Based on the well-known duality between thermal and elec-
exponential increase of subthreshold current with temperature. trical phenomena,1 a CTM is a lumped thermal RC network,
Third, the interconnect resistivity increases with temperature, with heat dissipation modeled as current sources. The resulting
leading to worse power-grid IR drops and longer interconnect thermal RC networks are typically relatively small, can be
RC delays, hence causing performance loss and complicating solved for temperature very efficiently and introduce little
timing and noise analysis. Finally, elevated temperatures can computational overhead. Due to this computational efficiency,
shorten interconnect and device life times and package relia- at pre-register transfer level (RTL) and presynthesis design
bility can be severely affected by local hot spots and higher stages, it is desirable to have compact thermal models for
temperature gradients. For all of these reasons, in order to fully both temperature-aware design and fast simulations of archi-
account for the thermal effects, it is important to model temper- tecture-level dynamic thermal management techniques. Here,
ature for VLSI systems in an accurate but still efficient way. For temperature-aware design refers to a design methodology that
uses temperature as a guideline throughout the design flow. The
Manuscript received November 26, 2004; revised July 19, 2005, and
resulting design can thus be thermally optimized, as it takes
November 13, 2006. This work was supported in part by the National Science into account potential thermal limitations [4].
Foundation under Grants CCR-0133634 and CCF-0429765, two grants from The major contributions of this work are the following.
Intel MRL, and by the University of Virginia through the FEST Excellence
Award.
1) We propose a modeling methodology—HotSpot—for gen-
W. Huang and M. R. Stan are with the Charles L. Brown Department of Elec- erating CTMs that can be used in early VLSI design stages
trical and Computer Engineering, University of Virginia, Charlottesville, VA where detailed layout is not available. With this method,
22904 USA (e-mail: [email protected]; [email protected]).
S. Ghosh was with the University of Virginia, Charlottesville, VA 22904
reasonably accurate spatial and temporal temperature vari-
USA. He is now with the Department of Electrical Engineering, Princeton Uni- ations of the silicon die as well as the package can be
versity, Princeton, NJ 08544 USA (e-mail: [email protected]). quickly obtained to help efficient design decisions during
S. Velusamy was with the University of Virginia, Charlottesville, VA 22904
USA. He is now with Xilinx Inc., San Jose, CA 95124 USA. 1In this duality, the heat flow passing through a thermal resistance is analo-
K. Sankaranarayanan and K. Skadron are with the Department of Computer gous to electrical current, and the temperature difference is analogous to voltage.
Science, University of Virginia, Charlottesville, VA 22904 USA (e-mail: Thermal capacitance, which is based on the material’s specific heat and defining
[email protected]; [email protected]). the heat absorbing capability, is analogous to electrical capacitance which ac-
Digital Object Identifier 10.1109/TVLSI.2006.876103 cumulates electrical charge.

1063-8210/$20.00 © 2006 IEEE

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 502 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

Fig. 1. (a) Thermal model closes the loop for leakage power calculation [3]. (b) The role of temperature in power, performance, and reliability models [4].

early design stages. The modeling method is based on the from detailed numerical thermal simulations by data fitting.
stacked-layer packaging configuration that is predominant These models are accurate and have the important property of
in modern VLSI packaging schemes and is an improve- (quasi-)boundary condition independence (BCI). One limita-
ment compared with our previous work [4], [6], [7]. tion of these models is that they have only one or a few junction
2) We analytically investigate the relationship between the nodes representing die temperature distributions. Also, because
number of nodes in the compact thermal model and the the models are constructed by data fitting, they are not physical
accuracy of the model. For thermal analysis during early (i.e., not derived from design geometries and material prop-
design stages, it is important to find the right thermal mod- erties), and, hence, are not parameterizable. Parametrization
eling grid density in order to achieve faster computation is important for CTMs to be used in exploring new design
speed without sacrificing accuracy. alternatives, where empirical fitting is often not possible [14],
3) We also propose a high-level on-chip interconnect self- [15].
heating power and temperature model, which can be used There also have been a number of previous works on thermal
for early analysis of thermal impacts on interconnect-re- modeling of on-chip interconnects and vias. For example, Chen
lated performance, power grid drop, and electromi- et al. [16] present an interconnect thermal model that closely
gration, again, during early design stages when detailed considers thermal coupling phenomenon between nearby inter-
routing and layout information is not available. connects. This model is accurate but it is on a per-intercon-
There have been several published efforts in full-chip thermal nect basis and is not extended to model multilevel structure at
modeling and compact thermal modeling for microelectronics a higher design abstraction. Chiang et al. [17] describe an an-
systems. Wang et al. [8] present a detailed and stable die-level alytical multilevel interconnect thermal model with considera-
transient thermal model based on full-chip layout, solving tem- tions of via effects. This model copes with the thermal effect
peratures for a large number of nodes with an efficient numer- of vias by lumping the heat transferred through the vias into
ical method. The die-level thermal models by Su et al. in [9] an equivalent thermal conductivity for the inter-layer dielectrics
and Li et al. in [10] also provide the detailed temperature dis- (ILDs). However, to make interconnect thermal analysis com-
tribution across the silicon die and can be solved efficiently, but plete, self-heating power also needs to be modeled. Unfortu-
with no information about the transient behavior. An earlier de- nately, to the best of our knowledge, we have not seen any pre-
tailed full-chip thermal model by Cheng et al. [11] has an accu- vious works providing models on the multilayer interconnect
rate three-dimensional (3-D) model for the silicon and one-di- self-heating power at a higher design level.
mensional (1-D) model for the package. A significant limitation The remainder of this paper is organized as follows. Section II
of the above modeling approaches is the oversimplified thermal describes different aspects of the HotSpot compact thermal
package model. For example, the thermal interface material and modeling approach and is divided into three subsections.
heat spreader that greatly affect the die temperature distribution Section II-A presents the layered thermal modeling approach
are either not included or not properly modeled. The bottom in detail, Section II-B addresses the issue of grid density versus
surface of the silicon substrate is treated as isothermal by the accuracy of the thermal model, and Section II-C proposes the
above previous works, which significantly deviates from reality high-level interconnect self-heating power and thermal model
and therefore introduces errors. Additionally, these models are for early design stages. Following that, Section III shows
not quite suitable for early design stages, since their computa- several validation steps that we have performed for the HotSpot
tion effort is nontrivial while fine-grained thermal analysis is CTMs. Then, in Section IV, we show some example applica-
not necessary when detailed layout information is not available. tions of the HotSpot CTMs. Finally, Section V concludes the
Finally, except for [11], none of these models has shown valida- paper and points out future work.
tion from simulations with detailed numerical models or mea-
surements from real designs. II. MODELING DETAILS
On the other hand, Lasance et al. [12], Sabry [5], and Bosch A compact thermal modeling approach must have several fea-
[13] present package-level compact thermal models extracted tures for it to be useful. First, it should provide detailed tem-
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 HUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 503

Fig. 2. Stacked layers in a typical ceramic ball grid array (CBGA) package [18]

perature distribution at the desired level of abstraction (e.g., a

single node representing the die temperature is unacceptable for
thermal modeling at the IC level). In addition, both static and
transient thermal behavior should be modeled. Second, a CTM
should model just at the needed accuracy and hide the details of
lower levels, so that the model itself is no more complex than
necessary. Third, the model structure should be kept as simple
as possible and should introduce little computational overhead.
The HotSpot compact thermal modeling methodology proposed
in this paper has all of the above desired features.

A. General Methodology
Most modern VLSI systems have a package consisting of
several stacked layers made of different materials, as shown in
Fig. 3. (a) Partitioning of large-area layers (top view). (b) One block with its
Fig. 2. This is also the package scheme adopted for the HotSpot lateral and vertical thermal resistances (side view). (c) A layer, for example, the
thermal models used in this paper. Typical layers include heat silicon die, can be divided into an arbitrary number of blocks if detailed thermal
sink, heat spreader, thermal paste, silicon substrate, on-chip in- information is needed (top view).
terconnect layers, C4 pads, ceramic packaging substrate, and
solder balls. The recently proposed stacked chip-scale pack-
aging (SCP) [19] and 3-D IC designs [20] are also stacked-layer computation speed requirements. The remaining peripheral part
structures and can be easily modeled as extensions of the generic in Fig. 3(a) is then divided into four trapezoidal blocks, each
stack structure in Fig. 2. assigned to one node.
When deriving a compact thermal model in HotSpot, the dif- Every block or grid cell in each layer has one vertical thermal
ferent layers, their positions and adjacency are first identified. resistance connected to the next layer and several lateral re-
Each layer is then divided into a number of blocks. For example, sistances to its neighbors in the same layer. Fig. 3(b) shows a
in Fig. 3(c), the silicon substrate layer is divided according to side view of one block with both the lateral and the vertical
architecture-level units or into regular grid cells, depending on thermal resistances. The vertical thermal resistance is calculated
what the die-level design requires. Note that only three blocks by , where is the thickness of that layer,
are shown in Fig. 3(c) for simplicity. Other layers that greatly is the thermal conductivity of the material of that layer, and
affect across-die temperature distribution (e.g., thermal inter- is the cross-sectional area of the block. We see that each layer is
face material) can be modeled similarly to the silicon substrate. not further divided into multiple thinner layers in the vertical di-
For the analysis of the needed size of regular grid cells, see rection, i.e., our modeling method is not fully 3-D. This is a rea-
Section II-B. sonable approximation for early design stages since each layer
For other layers that require less detailed thermal information is relatively thin (a millimeter or less), further discretization in
(such as heat spreader and heat sink), we simply divide that layer the vertical direction would induce more computation while not
as illustrated in Fig. 3(a). The center shaded part in a layer shown improving accuracy significantly.
by Fig. 3(a) is the area covered by another adjacent layer such as Calculating lateral thermal resistance is not as straightfor-
the one shown in Fig. 3(c). This center part can have the same ward as the vertical resistance. This is because heat spreading
number of nodes as its smaller neighbor layer or can collapse or constriction in the lateral directions must be accounted for.
those nodes into fewer nodes, depending on the accuracy and Basically, the lateral thermal resistance on one side of a block
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 504 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

can be considered as the spreading/constriction thermal resis-

tance of the neighboring part within a layer to that specific block.
Lateral thermal resistances are normally much greater than their
vertical counterparts due to the fact that the lateral heat-transfer
cross-sectional areas are usually much less than vertical ones.
We calculate the spreading/constriction resistance based on the
formulas given in [21]. The resistance is a spreading one if the
Fig. 4. Modeling at the granularity of (a) functional blocks, (b) uniform grid
lateral area of the source is smaller than the bulk lateral area, cells, and (c) hybrid-sized grid cells [2].
and it is a constriction one otherwise.
For each node, there is also a thermal capacitance
, connected to ground, where and are the spe-
cific heat and density of the material, respectively. The factor
is a scaling factor accounting for lumped versus dis-
tributed thermal time constants.2
Finally, the heatsink-to-air convection thermal resistance can
be modeled as , where is the surface
area and is the heat transfer coefficient that is boundary condi-
tion dependent. For a first-order approximation, this is adequate Fig. 5. (a) A 1-D slab of material with left half dissipating power. (b) Temper-
for thermal analysis during early design stages. Typical values ature distribution along the length of the slab.
of for typical heat sinks under different convection conditions
usually be found in the heat sink datasheets.
Details of the derivations and formulas of all the above a hybrid grid scheme that combines both the per-function unit
thermal resistances and capacitances can be found in [7] and model and the uniform-size grid model as in Fig. 4(c) [2]. By
[21]. An example of how a HotSpot compact thermal model is doing this, we could still get detailed thermal information for
assembled can be found in [4]. particular blocks under consideration while saving computa-
From the above descriptions, it can be seen that our method tion effort by introducing fewer nodes inside other blocks. It
can model relatively detailed static and transient temperature is clear that the desired accuracy determines the minimum grid
variations for the silicon die. In particular, different packaging cell size needed, i.e., the temperature difference across one grid
components can be modeled with more detailed temperature cell should be less than a certain percentage of the maximum
distribution information, which is not available in existing temperature difference across the die. In what follows, we show
works such as [8]–[10]. Additionally, because the thermal an analytical method to derive the proper size of a grid cell.
models are built as lumped thermal RC networks, the com- Let us first start from a simple case. Assume that there is a slab
putational overhead for solving the temperatures is small. of material with unit width and infinite length. The thickness of
Therefore, the modeling method is suitable for developing the slab is , and the bottom surface of the slab is isothermal.
compact thermal models used during early design stages. Half of the slab has a uniform power density of , while the
Compact thermal models developed from this method are also power density of the other semi-infinite half is , as shown in
parameterizable and BCI. The models are parameterizable be- Fig. 5(a). The resulting temperature distribution of the top sur-
cause they are built only using the physical geometries and ma- face of the slab is approximated in Fig. 5(b). The far end of the
terial properties. The models are also BCI because the entire in- left half with power density has a temperature of , and
ternal RC network is built independent of boundary conditions. the far end of the right half with no power dissipated has a tem-
More discussions on parametrization and BCI of the HotSpot perature of , for simplicity. Due to symmetry, the temperature
models can be found in [14] and [15]. at the boundary between the two halves is . The temper-
ature at point can then be derived from the equivalent lumped
B. Thermal Modeling Accuracy Analysis thermal circuit in Fig. 6(a). The lateral and vertical thermal re-
sistances of an infinitesimal portion of the slab with length of
One important aspect of model development is to decide the are
proper number of nodes at which temperatures are modeled. At
one extreme, a single junction temperature for the chip would
be enough for board-level designs, but not enough for die-level and (1)
designs. Taking the die-level temperature modeling as an ex-
ample, temperature can be modeled at the functional unit level where is the thermal conductivity of the slab material. Now,
[see Fig. 4(a)] or the die can be divided into regular grid cells to the equivalent thermal resistance for the semi-infinite half of
get more detailed temperature distribution as a function of the the slab should be the same whether or not it includes the first
size of each grid cell [see Fig. 4(b)]. Ideally, we would prefer vertical thermal resistance , i.e.,
2There should be no surprise that the same factor also appears in the analysis
of distributed RC electrical interconnect lines. This approximation is legitimate
since the lateral thermal resistances are usually much greater and make negli- and also
gible contribution to the thermal RC time constants compared with the vertical
thermal resistances. (2)
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 HUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 505

Fig. 6. (a) Thermal resistance network for Fig. 5(a). (b) Thermal circuit at node x for calculating temperature T (x).

Solving the above two equations for leads to

(3)

When , we have and should have a finite value,

which means we can neglect the term in the above two
equations of . Therefore, both equations become

i.e., (4)

Next, to find the temperature , we consider the circuit in Fig. 7. Comparing FEM simulation result with (7) and (8) for the structure in
Fig. 6(b), in which heat flows into node . According to Fig. 5(a). Power density = 0:5 W/mm ; t 20 mm. Bottom surface of the
Kirchoff’s Current Law, we have silicon slab is approximately isothermal.

(5) Fig. 7 confirms the accuracy of the above analysis by comparing

with FEM simulations using FloWorks.3
Next, we consider the scenario where heat is dissipated on a
Substituting with , and with , and then rear- finite part of the slab, as shown in Fig. 8(a). The corresponding
ranging both sides of the equation, we obtain FEM-simulated temperature distributions within that part of the
slab are shown in Fig. 8(b) for different block sizes .
It is obvious in Fig. 8(b) that, if the size is sufficiently small, the
heated part of slab does not actually reach its maximum tem-
(6) perature, as can be seen in Fig. 5(b). This is due to the above
mentioned spatial constant, and it means that a block with small
size acts as a temperature-spatial low-pass “filter” that prevents
Taking the integral for both sides from to and
the temperature from reaching the maximum possible value.
from to , respectively, and solving for , we obtain
In contrast, with the same power density, a bigger block with
its size much larger than the “spatial” constant can have sig-
nificantly higher temperature differences. The above analysis
(7) explains the “abnormal“ observations that although, some tiny
structures such as clock buffers in a microprocessor have very
The above equation shows that the temperature distribution for high power densities, they do not necessarily cause hot spots,
the right half of the slab is approximately an exponential decay due to this “spatial temperature filtering“ effect.
curve with a “spatial” constant of , which is the thickness from For a particular grid size , from (8) and Fig. 8(b), the tem-
the surface under consideration to the isothermal surface. Fur- perature difference within the grid is
thermore, we can write the temperature distribution of the left
half of the slab as a function of position according to symmet-
rical nature of the slab structure
(9)

3FloWorks is an FEM software analyzing computational fluid dynamics and

(8) heat transfer. Available at http://www.nika.biz/index2.htm
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 506 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

w
Fig. 8. (a) Part of the slab of material dissipating power. The size of the part is . (b) FEM simulation results—temperature distribution along the slab with
different sizes dissipating power(w < w ) t = 20
. Smaller size “filters” out the temperature difference. (Silicon thickness mm.)

By setting

% (10)

where % is the tolerable percentage error, and now rep-

resents the maximum possible temperature difference across the
silicon die.4 Solving (10), we get the lower bound for as

(11)
%

Note that , which is the thickness from the surface under con-
sideration to the isothermal surface, needs to be calculated first.
An isothermal surface is an ideal concept that is not found in
Fig. 9. Minimum necessary grid size for different desired levels of precision,
real packages, but surfaces with negligible temperature differ- with t=4 mm and t=2 X 1T
mm, respectively. The -axis is the ratio of
ences can be considered as isothermal.5 For instance, the thick- to T p
, i.e., , in percentage. For example, for a system witht=4 mm, if
ness for the silicon surface of the package shown in Fig. 2 can 3% temperature precision is desired, from the solid line, one finds that a grid
cell size of 0.5 mm would be enough.
be found by adding up the thickness of silicon substrate, thermal
interface material, and heat spreader. An important detail is that,
if we use the conductivity of silicon in the above equations, we
need to first convert the actual thicknesses of the thermal inter- die into 40 40 grid cells. Any finer grid size is unnecessary in
face material and the heat spreader to “equivalent“ silicon thick- this case.6
ness by multiplying their thickness by the ratio of their thermal One assumption that we have made so far is that the power is
conductivities to the one for silicon. uniform within each grid cell. This assumption is legitimate if
Fig. 9 plots the required grid size for different desired levels the thermal analysis is performed at early design stages, because
of precision according to (11), with equivalent thicknesses detailed layout and power information are not available yet. In
mm and mm. The horizontal axis is the ratio of later design stages, the structures that are included in one grid
to , i.e., , in percentage. For example, consider that we cell may turn out to be heterogenous. In this case, we can always
have a 20 mm 20 mm silicon die, and the maximum possible first resort to finer grid cells inside which power distribution can
temperature difference across the die is 30 , then, from Fig. 9, be considered as uniform, then perform the above accuracy anal-
we can find that, if we desire all grid temperature error of less ysis and decide whether or not that finer grid size is necessary or
than 3% ( % ) for mm, a grid size of approx- not. Due to the “spatial temperature filtering effect“ mentioned
imately 0.5 mm is sufficient. This corresponds to dividing the above, often we should find that temperature difference within
a finer grid cell is negligible and we need to come back to larger
4 T is dependent on the power distribution across the die and cannot be grid cells, unless the power density is extremely high.
known a priori without performing thermal analysis. However, one can always
start with a reasonable guessed value forT based on previous design expe- 6It is worth noting that the above granularity analysis is based on simplifi-
rience and then solve the thermal model and iterate the analysis in Section II-B cations of classical heat transfer equations, which underestimates temperature
for a few times to get the needed grid size. when applied at size scales less than the phonon–phonon mean free path (about
5One example is the bottom surface of the heat spreader, since the heat 300 nm for silicon at room temperature) [22]. Thus, for granularity analysis at
spreader is usually made of materials with high thermal conductivity, such as the transistor level, the phonon Boltzmann transport equation (BTE) should be
copper. used instead.
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 HUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 507

Fig. 10. (a) An example of wire-length distribution at 45nm technology node, with three regions (local, semi-global, and global). (b) Metal-layer assignment by
calculating number of metal layers needed for each of the three regions. (c) Metal-layer assignment by filling every two metal layers with signal wires, starting
from Metal 1 and Metal 2. The example in (c) is superior to that given in (b) by providing more detailed metal-layer assignment information.

C. Interconnect Self-Heating Power and Thermal Modeling a) Average interconnect length in each metal layer for
There are two major heat transfer paths inside an IC package signal interconnects: We predict the average signal intercon-
[18]—a primary heat transfer path (e.g., silicon substrate, heat nect length in each metal layer by adopting and extending the
spreader, or heat sink) and a secondary heat transfer path (e.g., statistical a priori wire-length distribution model presented
silicon substrate, on-chip interconnect layers, C4 pads, ceramic by Davis et al. in [25], which improves the wire-length dis-
packaging substrate, solder balls, or printed circuit board). On tribution model by Donath [26]. It is important to note that
the other hand, the secondary heat transfer path usually removes an interconnect thermal model at high levels of abstraction
a nonnegligible amount of total generated heat (up to 30%). strongly depends on the a priori wire-length distribution model
Neglecting the secondary heat transfer path can lead to inac- and, hence, is limited by the accuracy and efficiency of the
curate temperature predictions. In addition, as part of the sec- wire-length distribution model.
ondary heat transfer path, the on-chip interconnect layers are of The model in [25] is based on the well-known Rent’s Rule:
particular interest, because interconnect temperature informa- , where and are Rent’s Rule parameters, is the
tion allows designers to perform more accurate electromigra- number of gates in a circuit, and is the predicted number of
tion, wire delay, and IR drop analysis. Until now, a high-level in- I/O terminals in the circuit. If the interested circuit block is of
terconnect self-heating model has been unavailable for early de- a heterogeneous nature, i.e., there are different Rent’s Rule pa-
sign stages. Most existing interconnect self-heating power and rameters for different subcircuit blocks, then equivalent Rent’s
thermal models are either based on analysis of only a few wires Rule parameters can be found using the heterogeneous Rent’s
[23] or need full-chip detailed layout information that is not Rule proposed by Zarkesh-Ha et al. [27].
available during early design stages [24]. Three wire-length regions are considered in [25]—local,
There are two aspects to be considered in the interconnect semi-global, and global. The model predicts the number of
model: 1) the average self-heating power of interconnects in wires of any specific length, which is called the interconnect
each metal layer and 2) the equivalent thermal resistance for density function , where is the wire length in gate pitches.
metal wires and their surrounding inter-layer dielectric. Vias Fig. 10(a) shows an example wire-length distribution based
also play an important role in heat transfer among different on ITRS data [28] for high-performance designs at the 45-nm
metal layers, and, therefore, need to be included as well. technology node, where , , and are maximum
1) Interconnect Self-heating Power Model: The self-heating local, semi-global, and global wire lengths, respectively.
power of a metal wire can be written as Using the interconnect density function , one can calculate
the average length and number of wiring nets for each region.
For example, for the semi-global region, we have
(12)

where is the rms current flowing through the wire,

is the electrical resistance, is the metal
resistivity (which is temperature-dependent), and and
are the length and cross-sectional area of the individual wire,
respectively. Because the model needs to predict wire temper- (13)
atures before physical layout is available, first it has to be able
to predict the average wire length and the self-heating current where is the correction factor that converts the point-to-point
(rms current) for wires in each metal layer. It is also important interconnect length to wiring net length (using a linear net model
to notice that, because the routing schemes are significantly , and is the average number of fan-outs per
different for the signal interconnects and the power distribution wiring net. More details can be found in [25].
network, the methods of predicting average wire length and However, there is no wire-length distribution information re-
self-heating current are also different for signal and power garding each metal layer when using this three-region division
supply wires, and, therefore, we treat them separately. method in [25]. For the interconnect CTM, we need the wire-
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 508 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

where is the wire pitch of a metal layer, and is the

available routing area for the pair of metal layers under consid-
eration. Using this relationship, and starting at Metals 1 and 2
with , we are able to solve for and for each
pair of metal layers. An example metal-layer assignment for the
interconnect distribution of Fig. 10(a) is shown in Fig. 10(c).
Another way to assign signal wiring nets to different layers is
to calculate the number of metal layers needed for each of the
three regions, namely, local, semi-global, and global, as in [25].
The resulting metal-layer assignment is shown in Fig. 10(b). As
can be seen, the results in Fig. 10(c) and (b) are similar, but
Fig. 10(c) provides detailed metal-layer assignment estimations
for every two metal layers without considering the three regions,
while the information provided in Fig. 10(b) is coarser. There-
fore, we prefer the approach used in Fig. 10(c). On the other
hand, if the total number of metal layers is fixed, the parameters
and can be adjusted accordingly to fit all of the signal in-
terconnects into the metal layers.
b) Average interconnect length in each metal layer for
power and ground: So far, we have considered the average
M
Fig. 11. Scheme to assign signal interconnects to metal layers. is the number signal interconnect length in each metal layer. We also need to
of signal wires between two power rails and Sp is ratio of the space between find the average wire length for the power and ground networks,
every two signal wires to average signal wire length of that metal layer.
which are usually grid-like. This is relatively simple: we only
need to find the length of the power grid section in each metal
length distribution predictions of every metal layer. Because of
layer. The assumption here is that the power grid for each metal
the predominant usage of Manhattan routing, in general, two
layer is uniformly distributed, which is a reasonable assumption
metal layers are needed to route one wiring net—one layer for
for early high-level design stages.
horizontal routing, the other for vertical routing. In this paper,
With this, we are done with estimating wire length. Next,
we estimate the pair of metal layers where each wiring net is
we need to use this information to estimate interconnect self-
routed by filling every two metal layers with wiring nets, starting
heating power.
from the shortest wiring nets. We thus assume that the shortest
c) Average interconnect rms self-heating current in each
wiring nets of the wire-length distribution in Fig. 10(a) are as-
metal layer for signal interconnects: For each switching event,
signed to Metals 1 and 2. Once the first two metal layers are
half of the energy drawn from the power supply is dissipated in
filled, we proceed to Metals 3 and 4, and so on and so forth,
the form of heat on the charging/discharging transistor and on
until all the wiring nets are assigned to their corresponding pair
the output signal interconnect. The average current flow through
of metal layers. Although this is an oversimplification, we ex-
the interconnect during a switching event can be solved from the
pect it to be representative of an actual routing strategy. A useful
following equation:
byproduct of our approach is that we are also able to estimate
the total number of metal layers needed for a design. As illus-
trated in Fig. 11, assuming the length of the shortest and longest
(16)
point-to-point interconnects that can be assigned to a pair of
metal layers are and in gate pitches, we can then
find the average length and total number of wiring nets within a where is the self-heating current per wire in each metal
pair of metal layers by layer. is the on-resistance of the transistor, is the wire
resistance, is the switching activity factor, is the load ca-
pacitance, and is the delay of the switching event. For long in-
terconnects, repeaters are inserted in order to achieve optimum
delay, and these need to be also taken into account. The crit-
ical wire-length between repeaters , the delay for one sec-
(14)
tion of buffered interconnect , the optimal number of re-
peaters , and the optimal size of repeaters for
Furthermore, by assuming the routing structure of Fig. 11, interconnects in each region can be found using the repeater in-
where is the number of signal wires between two power rails sertion model proposed in [29]. The calculations of , ,
and is ratio of the space between every two signal wires to , and are different for wires with or without inserted re-
(both and are design parameters and are tunable by peaters—the wire length is either the total wiring net length or
the designer), we get the following relation: the length of a wire section between repeaters; the driving and
load gates are either gates with average transistor size or re-
peaters with size of . Finally, the delay of the switching
(15) event can be approximated as for interconnects with
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 HUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 509

repeaters or as clock cycle time/logic depth for interconnects

without repeaters.
d) Average interconnect rms self-heating current in each
metal layer for power and ground: To calculate average rms
currents for power supply grid sections, we can use one of two
methods.
The first method is to build a grid-like resistive network model
for VDD and GND, somewhat resembling the grid-like die-level
thermal model as in Fig. 4(b). Each resistor connecting two
nodes in the same metal layer is now the electrical resistance of
one power supply grid section. Resistors connecting power grid
nodes of different metal layers represent the vias. The topology Fig. 12. Interconnect structures for calculating equivalent thermal resistance
of the network is obtained by knowing the pitch between power of wires with surrounding dielectric.
rails in each metal layer, average length, and number of power
grid sections between power grids. Next, by applying voltage
sources to the top-layer C4 pad sites and adding current loads at above Wire1, where is the thickness of the ILD between two
Metal-1 endpoints, the resistive network is solved to find the av- metal layers. The other half of belongs to the metal layer above
erage self-heating current of the power grid in each metal layer. Wire1 and is considered when calculating equivalent thermal re-
The other method to calculate average rms self-heating cur- sistance for wires in that layer. Since we have assumed that all of
rent of power grid section in a metal layer is quite straight- the wires in the same metal layer are the same, Wire1 and Wire2
forward—we can simply divide the total current delivered to a are two identical wires dissipating the same power at the same
metal layer by the number of power grid sections. This method time. Consequently, Wire1 and Wire2 also have the same tem-
is suitable for high-level design stages but is not as accurate as perature. We approximate the isothermal surface by the outer
the first method. dashed area in Fig. 12. This isothermal surface is used for the
e) Total interconnect self-heating power in each metal calculation of and is away from the wires. Also, it does
layer: With all the above information of average interconnect not overlap with similar isothermal surfaces for the perpendic-
length and rms self-heating current in each layer (for both ular wires in neighboring layers. The effective heat-conducting
signal interconnects and power grid sections), we calculate the angle which is used for the calculation of can be approxi-
average self-heating power per interconnect in each metal layer mated by , as shown in the figure.
as There is also a lateral thermal resistance between Wire1 and
Wire2— . However, because Wire1 and Wire2 are identical
and have the same temperature, there is no heat transfer in the
(17) lateral direction and can be removed.
For the calculation of , we first calculate the thermal resis-
where and are the cross-sectional area and the av- tance of the dark slice of ILD shown in Fig. 12, which can be
erage length of signal interconnects or power grid sections in written in the form of the integral
each metal layer, respectively.
Finally, we calculate the self-heating power for each metal
layer. For example, we calculate the self-heating power of metal
layer as
(19)

(18) where is the integral variable, is the thermal conductivity

of ILD, is the angle of the slice, is the equiva-
where and are the self-heating power of lent radius of the wire, and is the length of the wire.
each individual signal interconnect and power supply wire for If we define thermal conductance as the reciprocal of
metal layer , respectively. and are the number of thermal resistance , we have
signal interconnects and power supply sections in Metal .
So far, we are done with the first aspect of interconnect
thermal modeling—self-heating power calculation of metal (20)
layers. Next, we need to calculate the equivalent thermal resis-
tance of wires and the surrounding dielectric, together with the and thus the total equivalent thermal resistance is
thermal resistance of vias.
2) Equivalent Thermal Resistance of Wires/Dielectric and
Vias: In order to derive a model, we consider the case in Fig. 12, (21)
where two wires (Wire1 and Wire2) are adjacent to each other.
On top of and beneath them are orthogonal wires in neighboring Inter-layer heat transfer also happens through vias. A simplistic
metal layers. All wires are surrounded by ILDs. We want to approximation of the number of vias for signal interconnect is
find the equivalent thermal resistance ( ) from Wire1 to to assume that each wiring net has two vias, one connected to
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 510 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

then be calculated for each functional unit using similar methods

as described before. As part of our future work, the power and
temperature estimations for each metal layer at the functional
unit level or other abstraction levels will be investigated.
4) Accuracy Concerns About the Interconnect Power and
Fig. 13. Estimating the number of vias for signal interconnects. A wiring net
Thermal Model: From the above descriptions of the proposed
with fan-out 3 is shown in this figure. The number of vias is (21f :o: + 2). interconnect power and thermal model for early design stages,
one might raise some concerns about accuracy. Here we address
them one by one.
1) Usefulness of the interconnect model—Because in-
terconnect layers usually have much higher absolute
temperatures and greater temperature differences than
silicon, reliability issues such as thermo-mechanical stress
between metal layers, thermo-electromigration of long
wires, are increasingly more important. If reasonably
accurate early-stage wire-temperature estimations are
available, they will be helpful for the designers to discover
Fig. 14. Estimating the number of vias for power supply wires. An array of
vias are put in the intersection of power wires at two metal layers. W and and deal with such thermally related reliability hazards
W are the widths of the power wire and the via, respectively. early in the design flow, hence greatly expediting the
design convergence process. For example, the architect
needs a way to reason about the thermal and reliability
the upper metal layer, and another one connected to the lower properties among different architectural choices at the
metal layer. A more accurate approximation is to assume that pre-RTL architecture determination stage. These kinds of
each wiring net has vias, where f.o. is the average choices do not necessarily need high degrees of precision,
fan out number of each gate. As illustrated in Fig. 13, it is enough only to know what combination of choices
vias are at the ends of the wiring net and connecting the wiring might be problematic.
net to lower metal layers and eventually to the device layer at 2) Accuracy concern of Rent’s Rule—For a mature circuit
the silicon surface. The other vias are used to aid the routing design style of a specific functional unit along a micro-
of the wiring net between the pair of metal layers in which the processor family, Rent’s Rule parameters derived from an-
wiring net resides. For the power supply grid, in order to in- cestor designs can be used to predict future designs’ wire-
crease the reliability and because the wires are typically wider length distributions with good accuracy, as indicated by
than minimum size, designers usually use multiple vias at the Rent’s Rule validation data presented in previous works on
intersection of two power rails between different metal layers. both traditional and improved Rent’s Rules, such as [25],
As illustrated in Fig. 14, the number of vias at an intersection [27], [30], [31], [32]. Rent’s Rule is indeed inaccurate for
of power rails can be estimated by , any individual wires, but is quite accurate about aggregate
where and are the widths of the power wire and the average wire behavior for mature circuit design styles. This
via, respectively. The thermal resistance of each via is approx- is also true about other applications of Rent’s Rule.
imately calculated as , where is thermal 3) Concern about current loading accuracy—We think that
conductivity of via-filling material, and and are the thick- reasonably accurate average/rms current estimations for
ness and cross-sectional area of the via. typical signal wires are achievable as presented earlier in
All thermal resistors of wires and vias between two metal this section. This is because power estimations at this level
layers can be considered parallel to each other. Thus, combining (dynamic power with switching factors and static power)
all of the thermal resistors between two metal layers, we obtain are available from tools such as Wattch [33]. Average
the total equivalent thermal resistance between two metal layers. current loading in the power/gound network can also be
Now, we are almost done with the interconnect thermal mod- roughly estimated by solving a coarse VDD/GND mesh
eling. One last step is to stack the thermal resistances for each (which is similar to the regular-grid-cell thermal resistive
layer to construct the whole thermal circuit for all interconnect network in HotSpot) without loss of much accuracy. It is
layers. Thermal capacitances can also be calculated for each also obvious that this kind of approach is consistent with
metal layer and the ILD based on dimensions and material prop- the needs of pre-RTL architectural modeling.
erties using an equation similar to the one in Section II-A.
3) Interconnect Power and Thermal Model at Different Gran-
ularities: Although the above interconnect thermal modeling D. Computation Speed of Hotspot Compact Thermal Models
approach was presented at the entire die level, in principle, it
is also applicable at other granularities. For example, Rent’s The computation speed of HotSpot thermal models to obtain
Rule can also be applied at the functional unit level to esti- steady-state and transient solutions for several different simu-
mate intra- and inter-functional-unit wire-length distribution for lated time intervals at different granularities are in the order of
metal layers above each functional unit. The total self-heating milliseconds to minutes, depending upon the number of blocks/
power and the equivalent metal-layer thermal resistance can grids, number of material layers, and the simulated transient
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 HUANG et al.: HOTSPOT: A COMPACT THERMAL MODELING METHODOLOGY 511

TABLE I
COMPUTATION SPEED OF A HOTSPOT MODEL, RUNNING ON A
DUAL-PROCESSOR (AMD MP 1.5 GHZ) SYSTEM. (CONVERGING
METHOD FOR TRANSIENT SOLUTIONS IS DIFFERENT FROM
THAT FOR STEADY-STATE SOLUTIONS

time interval. Table I shows the CPU time used to simulate a

HotSpot model with 40 40 grid cells.
The small overhead is due to the relatively small and man-
ageable number of nodes in the lumped thermal RC circuit,
together with the use of first-order difference equations to
iteratively solve the RC network. The computational efficiency Fig. 15. Floorplan with six functional blocks implemented in an FPGA for
HotSpot primary heat transfer path model validation.
of HotSpot models means there is little computation overhead
for existing design methodologies to incorporate the compact
thermal models for temperature-aware design or dynamic TABLE II
thermal management simulations. COMPARISONS OF TEMPERATURE READINGS FROM THE FPGA AND THE
HOTSPOT THERMAL MODEL. TEMPERATURES ARE WITH RESPECT TO
AMBIENT TEMPERATURE. ERRORS ARE WITHIN 0.2 C
III. VALIDATION
The HotSpot modeling approach was first validated through
detailed FEMs in FloWorks [34]. It was also validated by com-
paring with real temperature measurements from a commercial
thermal testing chip [4]. Validation of the interconnect thermal
model also can be found in [4]. Here, we present another step
that we have taken recently to further validate HotSpot models.
We designed an field-programmable gate array (FPGA)- not show much interesting “hot” temperatures and temperature
based system that monitors the temperature at various locations gradients.
on a Xilinx Virtex-2 Pro FPGA [35]. The system is composed of
a controller interfacing to an array of temperature sensors that IV. HOTSPOT APPLICATIONS
are implemented on the FPGA fabric. We use ring oscillators as The HotSpot thermal models can be utilized to achieve
temperature sensors by exploiting the fact that the frequency of accurate preliminary design estimations and precise run-time
oscillation is approximately proportional to temperature [36]. thermal management techniques. As an example, die-level tem-
Calibrations are done for six different sensors placed near the perature estimations from HotSpot can be used as a guideline
center of each unit on the die. Power consumption for different for temperature-aware design during the entire design flow
units is extracted through various methods. Using the floorplan [4]. Other example applications are: HotSpot compact thermal
shown in Fig. 15, we compare the sensor readings with values models have been used to close the loop of leakage power
obtained from the corresponding HotSpot model. The results calculation [3], explore different architecture-level run-time
are in Table II. We see that, on average, the temperatures dynamic thermal management (DTM) techniques [34], [37],
predicted by the HotSpot thermal model and those obtained aid the analysis of state-of-the-art computer architectures [38],
from the sensors differs by less than 0.2 C. and perform temperature-aware electromigration (EM) analysis
The low temperature rise (4.1 C maximum) and small tem- for more accurate interconnect lifetime predictions [39].
perature difference across the FPGA chip (0.7 C maximum) Apart from the above published applications of HotSpot, here
are due to the fact that typical operating powers for the PPC and we show the importance of modeling packaging components
MB blocks on the FPGA are not significant enough to heat up (e.g., thermal interface material (TIM), heat spreader and heat
the chip (because of this, the FPGA chip is not equipped with sink) in greater detail by comparing across-die temperature dif-
a heatsink). In order to achieve greater across-die temperature ference for different TIM thicknesses. TIM is a thin layer of
differences, we have intentionally left two “zero-power” blank material that glues the silicon die to the heat spreader, made of
blocks (blank1 and blank2). Regardless of the relatively cool material with a much lower thermal conductivity than silicon
die temperature, the errors between the HotSpot model and the and metals. Therefore, this thin layer of TIM plays an impor-
thermal sensor measurements are within 10% of the measured tant role in preventing effective heat spreading and resulting in
temperatures, for example, for “MB” in Table II, the percentage higher temperature gradient at the bottom of the die. Table III
error is %. This confirms the validity of shows the across-die temperature difference from a HotSpot
the HotSpot model, although the FPGA application itself does thermal model built for a POWER4-like microprocessor with
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 512 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006

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and D. Tarjan, “Temperature-aware computer systems: Opportunities puter architecture in general and thermal and power-
and challenges,” IEEE Micro, vol. 23, no. 6, pp. 52–61, 2003. aware microarchitectures in particular.
[38] Y. Li, D. Brooks, Z. Hu, and K. Skadron, “Performance, energy, and
thermal considerations for SMT and CMP architectures,” in Proc. High
Performance Comput. Architecture, Feb. 2005, pp. 71–82.
[39] Z. Lu, W. Huang, J. C. Lach, M. R. Stan, and K. Skadron, “Interconnect
lifetime prediction under dynamic stress for reliability-aware design,” Kevin Skadron (SM’05) received the B.S.E.E. and
in Proc. Int. Conf. Comput.-Aided Design, Nov. 2004, pp. 327–334. the B.S. degree in economics from Rice University,
[40] M. Moudgill, J. D. Wellman, and J. H. Moreno, “Environment for Pow- Houston, TX, and the M.A. and Ph.D. degrees from
erPC microarchitecture exploration,” IEEE Micro, vol. 19, no. 3, pp. Princeton University, Princeton, NJ.
He joined the Department of Computer Science,
15–25, 1999.
University of Virginia, Charlottesville, in 1999 and
[41] D. Brooks, P. Bose, V. Srinivasan, M. Gschwind, P. G. Emma, and M. is now an Associate Professor. His research interests
G. Rosenfield, “New methodology for early-stage microarchitecture- focus on the implications of technology trends and
level power-performance analysis of microprocessors,” IBM J. Res. physical constraints for computer architecture.
Devel., vol. 47, no. 5/6, pp. 653–670, 2003. Dr. Skadron is a member of the Association for
Computing Machinery. He was recipient of three
Best Paper Awards, National Science Foundation ITR and CAREER Awards,
co-chaired MICRO 2004 and PACT 2002, has served on numerous program
committees, and is founding Associate Editor-in-Chief of IEEE Computer
Architecture Letters.

Wei Huang (S’01) received the B.S. degree in

electrical engineering from the University of Science
and Technology of China, Hefei, China. He is Mircea R. Stan (SM’98) received the Diploma in
now working toward Ph.D. degree in electrical and electronics and communications from “Politehnica”
computer engineering at the University of Virginia, University, Bucharest, Romania, and the M.S. and
Charlottesville. Ph.D. degrees in electrical and computer engineering
His research interests include low-power circuit from the University of Massachusetts at Amherst.
design, modeling and analysis of temperature and Since 1996, he has been with the Department of
other parameter variations at the circuit and microar- Electrical and Computer Engineering, University of
chitecture levels, and the design of variation-aware Virginia, Charlottesville, where he is now an Asso-
VLSI circuits and systems. He was an intern with ciate Professor. He is teaching and doing research
the IBM T. J. Watson Research Center,in the VLSI Design Department during in the areas of high-performance and low-power
the summer of 2004. VLSI, temperature-aware circuits and architecture,
Mr. Huang was the recipient of the Best Student Paper Award at ISCA 2003. embedded systems, and nanoelectronics. He has more than eight years of
industrial experience, was a visiting scholar at the University of California,
Berkeley, in 2004–2005, a Visiting Faculty Member with IBM in 2000, and
with Intel in 2002 and 1999.
Dr. Stan is a member of the Association for Computing Machinery, Usenix,
Shougata Ghosh received the B.S. degree in elec- Eta Kappa Nu, Phi Kappa Phi, and Sixma Xi. He was a Distinguished Lecturer
trical and computer engineering from the University for the IEEE Circuits and Systems Society for 2004–2005. He was the recipient
of Virginia, Charlottesville. He is currently working of the National Science Foundation CAREER Award in 1997 and was a coau-
toward the Ph.D. degree in computer engineering at thor on Best Paper Awards at ISCA 2003 and SHAMAN 2002. He was a pro-
Princeton University, Princeton, NJ. gram chair for ISLPED 2005, the general chair for GLSVLSI 2003, has been
His research interests are in low-power computing on technical committees for several conferences, has been a Guest Editor for
and thermal aspects of microprocessors. He is also in- the IEEE COMPUTER Special Issue on Power-Aware Computing in December
terested in in-network cache coherence architectures 2003 and an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND
in CMPs. SYSTEMS since 2004 and for the IEEE TRANSACTIONS ON VERY LARGE-SCALE
INTEGRATION (VLSI) SYSTEMS in 2001–2003.

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