AND8145/D

A 75 W TV Power Supply
Operating in Quasi−square
Wave Resonant Mode using
the NCP1207 Controller
http://onsemi.com
Prepared by: Nicolas Cyr
ON Semiconductor APPLICATION NOTE

Introduction
Quasi−square wave resonant converters, also known as 230
quasi−resonant (QR) converters, allow designing flyback
Lf
Switch−Mode Power Supplies (SMPS) with reduced IP 
170 CTOT
Electro−Magnetic Interference (EMI) signature and
VDS (t) (V)

improved efficiency. Due to the low level of generated

noise, QR SMPS are therefore very well suited to 110
applications dealing with RF signals, such as TVs.
ON Semiconductor NCP1207 is a QR controller that will 50
ease your design of an EMI−friendly TV power supply with
only a few additional components, and able to lower its
standby power down to 1.0 W. −10

What is Quasi−Resonance?
The term quasi−resonance is normally related to the Figure 1. A Truly Resonating VDS Signal on a
association of a real hard−switching converter and a Quasi−resonant Flyback Converter
resonant tank. While the operation in terms of control is
similar to that of a standard PWM controller, an additional The main problem with this technique lies in the very high
network is added to shape the variables around the voltage generated at the switch opening. Most of the time,
MOSFET: current or voltage. Depending on the operating these resonant offline designs require around 1.0 kV BVdss
mode, it becomes possible to either switch at zero current MOSFETs whose price is clearly incompatible with high
(ZCS) or zero voltage (ZVS). Compared to a conventional volume markets. As a result, designers orientate their choice
PWM converter, a QR operation offers less switching losses toward another compromise called quasi−square wave
but the RMS current circulating through the MOSFET resonant power supply.
increases and forces higher conduction losses; with a careful
Quasi−Square Wave Resonant Converters
design, efficiency can be improved. However, one of the
As we saw, true resonant operation put a constraint on
main advantages in favor of the quasi−resonance is the
MOSFET selection by imposing a high voltage at the switch
reduced spectrum content either conducted or radiated.
opening. If we closely look at the standard hard−switching
True ZVS quasi−resonance means that the voltage present
waveform (Figure 2), we can see that at a given time the
on the switch looks like a sinusoidal arch. Figure 1 shows
drain voltage goes to a minimum. This occurs just after the
how such a signal could look like.
core reset.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

March, 2004 − Rev. 0 AND8145/D
 AND8145/D

1
2    LLEAK  CTOT CORE IS RESET

DRAIN VOLTAGE

1
2    LP  CTOT
VDS IS MINIMUM
IP

DRAIN CURRENT

Figure 2. Hard−switching Waveforms in Discontinuous Conduction Mode (DCM)

From Figure 2, it is possible to imagine a controller that Depending on the event, two different configurations are
turns a MOSFET ON until its current grows−up to the seen:
setpoint. Then it turns the MOSFET OFF until the core reset • At the switch closing, the primary current flows through
is detected (usually via an auxiliary winding). As a result, the the primary inductance LP but also the leakage
controller does not include any stand alone clock but only inductance, LLEAK. When the turn−on time expires, the
detects the presence of events conditioned by load/line energy stored in LP is transferred to the secondary side of
conditions: this is a so−called free−running operation. the transformer via the coupling flux. However, the
Converters based on this technique are often designated as leakage inductance, which models the coupling between
Self−Oscillating Power Supplies (SOPS), valley switching both transformer sides, reverses its voltage and imposes
converters, etc. a quickly rising drain voltage. The slope of this current is
Oscillations origins can be seen from Figure 3 IP
arrangement where L−C networks appear. where CTOT gathers all capacitors
CTOT (eq. 1)
surrounding the drain node: MOSFET capacitors,
RP 1:N
primary transformer parasitic capacitors but also those
reflected from the secondary side, etc. As a result, LLEAK
+ together with CTOT form a resonating network of natural
LP VOUT
1
frequency . The
2    LLEAK  CTOT (eq. 2)
+
VIN maximum drain voltage can then be computed using the
LLEAK
characteristic impedance of this LC network:
LLEAK
VDS max  VIN
1  (VOUT
VF)
IP 
N CTOT
DRV CTOT VDS (eq. 3)

Figure 3. A Typical Flyback Arrangement Shows Two

Different Resonating Networks

http://onsemi.com
2
 AND8145/D

• When the transformer core resets, primary and secondary resonating network, this time made by LP, the primary
currents drop to zero. The secondary diode stops its inductance, and nearly the same CTOT as before. A
conduction and the reflected voltage on the primary sinusoidal ringing takes place, damped by the presence of
naturally dies out. From equation 3, this means that terms ohmic losses (DC + AC resistance of the primary
after VIN all collapse to zero and VDS tends toward VIN. winding, modeled by RP). The drain−source shape rings
However, the transition would be brutal in the lack of a as the formula below details:

VDS(t)  VIN
1  (VOUT
VF)  e at  cos (2    FPRIM  t)

N
(eq. 4)

RP
with: a  the damping factor 700 1  (V RP
2  LP (eq. 5) OUT
VF)  t
N 2  LP
1 e
FPRIM  FPRIM  t=0
2    LP  CTOT (eq. 6) 500

VDS(t) (V)
the natural ringing frequency VIN

VIN the input voltage, VF the diode’s forward drop 300

N
and N the  S turn ratio.
NP 100
We can see from Figure 4 that the drain is the seat of tvalley
Multiple Valleys
various local minimums when going along the ringing wave.
−100
These drops are called “valleys”. If we manage to switch the
MOSFET right in the middle of these valleys, we ensure
minimum turn−on losses, particularly those related to
capacitive dissipation: Figure 4. A Typical Flyback Ringing Waveform
Occurring at the Switch Opening
PavgCAP  1  CTOT  VDS2  FSW → 0.
2 (eq. 7)
Thus, quasi−square wave operation (or valley switching)
will imply a re−activation of the switch when VDS is TOFF
TW
minimum. As various figures portray, this occurs some time
further to the transformer core reset. By implementing this
method, we build a converter that naturally exhibits a
variable frequency operation since the reset time depends
upon the input/output operating conditions. Figure 5 shows
a typical shot of a quasi−square wave converter.
As one can see, the total period is made of different events,
where the core is first magnetized (TON), then fully reset
(TOFF) and finally a time delay (TW) is inserted to reach the First Valley
lowest value on the drain. Let us look at how the frequency TON
moves by respect to the input/output conditions.

Figure 5. A Typical Drain−Source Shot of a

Quasi−square Wave Converter

http://onsemi.com
3
 AND8145/D

Evaluating the Free−Running Switching Frequency For the TW event, which is one fourth of the natural
ringing frequency given by equation 4, we will compute the
derivative of equation 4 and null it to find its minimum:
IPEAK d (VIN
e at  cos (2    FPRIM  t))
0
VOUT
VF dt
SN
LP (eq. 10)
V
S  IN
LP
IP(t)

Which gives a result of:

IP = 0 a  tan a
2FPRIM
ON OFF TW  1  1 
2  ft 2   FPRIM
0 (eq. 11)

TW However, this result is not very practical because of its

inherent complexity. If we observe equation 10, we can see
that the minimum is reached when the term
Figure 6. The Primary Inductance Current is made of cos (2    FPRIM  t) equals −1. Otherwise stated, we can
Two Different Slopes solve t for which the cosine is equal to zero, or the full
product equals . This gives:
The free−running frequency can be evaluated by looking 1
TW     LP  CP
at Figure 6, where the primary current (circulating in the 2  FPRIM
(eq. 12)
primary inductance) is depicted. From the definition of the
various slopes, we can express the first two events, TON and However, this result is valid only for low damping
TOFF quite easily: coefficient, that is to say, e at  1. Experience shows that
LP it is good enough for the vast majority of cases.
TON  I
VIN P (eq. 8)

LP
TOFF   IP
NP  (V (eq. 9)
OUT
V F )
NS

As a result, the final switching period is computed by summing up all these sequences and introducing the input power
expression: T  TON
TOFF
TW. (eq. 13)

 
TON
TOFF
TW  IP  LP  1
1

  LP  CP  1 (eq. 14)
VIN FSW
 NP  (V
NS OUT
VF)

P N
PIN  OUT 1
  2  LP  IP  FSW
2 (eq. 15) with: VREFLECT  P  [VOUT
VF]
NS
2  POUT TW    LP  CP
from equation 15, IP  (eq. 16).  the converter efficiency
  LP  FSW
POUT the output power
Now, plugging FSW in equation 16 gives:
VOUT and VF, respectively the output voltage and
LP  IP 2   the rectifier drop @ ID = IOUT
IP  LP  1
1
TW 
VIN VREFLECT 2  POUT LP the primary inductance.
(eq. 17)

Stating that: 2  LP  POUT  A;

A  VREFLECT
A  VIN
A  VREFLECT 2
2  A  VREFLECT  VIN
A  VIN 2
2    VIN 2  VREFLECT 2  TW
IP 
  LP  VIN  VREFLECT
(eq. 18)

http://onsemi.com
4
 AND8145/D

From equation 16, we can then compute the switching FSW  1

2
frequency using the calculated peak current:
N VOUT
VF
VIN
2  POUT LP  2  POUT
FSW   VIN N VOUT
VF
  LP  IP 2 (eq. 19)

However, equation 18 is not very practical since it (eq. 21)

involves LP, what we are actually looking for... It can
Entering equation 21 into a spreadsheet and plotting FSW
certainly be used to discover the operating peak current from
versus various parameters (VOUT, IOUT, etc.) gives an idea
known inductance and capacitor values. But neglecting TW,
about the high frequency variability of the system. Figure 7
a simpler formula can be used as first frequency iteration
and Figure 8 respectively plot FSW in function of the input
(e.g. to feed a SPICE simulator for instance):
voltage and the output current for a given application.
V
VIN
IP  2  POUT  REFLECT
  VIN  VREFLECT
(eq. 20)

7*104 2*105
POUT = 100 W LP = 1 mH
6*104 LP = 1 mH VOUT = 16 V
VOUT = 16 V
1.5*105 NP:NS = 1:10
NP:NS = 1:10 CP = 100 pF
5*104 CP = 100 pF VIN = 100 V
FSW (Hz)

FSW (Hz)
4*104 1*105

3*104
5*104
2*104

1*104 0
100 150 200 250 300 350 400 0 20 40 60 80 100
VIN (V) POUT (W)

Figure 7. Frequency Variations for a 100 W SMPS Figure 8. Frequency Dependency with Load at a
Operated from a Universal Mains Given Input Voltage (100 V)

3.5
LP = 1 mH
VOUT = 16 V
3.0 NP:NS = 1:10
CP = 100 pF
POUT = 100 W
IP (A)

2.5

2.0

1.5
100 150 200 250 300 350 400
VIN (V)
Figure 9. Peak Current Variations for a 100 W Output
Power with Different Line Voltages

http://onsemi.com
5
 AND8145/D

A Quiet EMI Signature

Manipulating sinusoidal (or close−to) variables always Detecting the Core Reset Event
offer a narrower spectrum content compared to Core reset detection is usually done via a dedicated
hard−switching systems. Figure 10 and Figure 11 depict the auxiliary winding whose voltage image is directly linked to
conducted EMI signature of two systems operated at the the transformer flux by:
same point but implementing different switching d
techniques. VAUX  N  (eq. 22)
dt
Since the MOSFET is re−activated at the lowest drain
Depending on the controller device, the polarity of the
level, the classical COSS capacitor discharge at the switch
observed signal must fit its detection circuitry. In
closing does not exist and the very narrow peak current has
ON Semiconductor NCP1207, this polarity should be of
gone (also this peak is often confusing the current−sense
Flyback type, that is to say, when the MOSFET closes, the
comparator when it is really energetic, even sometimes
auxiliary voltage dips below ground and stays there, safely
despite the presence of the LEB circuitry). As a result,
clamped at −0.7 V, until the MOSFET is turned off.
Quasi−square wave converters are recommended where the
Figure 12 gives an example of the demagnetization signal
Switch−Mode Power Supply (SMPS) needs to operate close
for NCP1207.
to Radio−Frequency section, notably in TV chassis.

Figure 10. A Soft−switching Approach Reduces Figure 11. A Hard−switching System Generates
the Energy Content Above 1 MHz a lot of Noise in the Same Portion

20.0
Leakage Contribution

10.0
VAUX(t) (V)

0 50 mV

−10.0
−N.VIN

−20.0

Figure 12. Core Reset Detection Signal Coming

from a Flyback Winding

http://onsemi.com
6
 AND8145/D

The NCP1207 Quasi−resonant Controller A 75 W TV Power Supply Design

Quasi−square Wave Resonant Operation: Due to its
Power Supply Specification
dedicated pin, NCP1207 is able to detect the end of the
transformer core demagnetization before starting a new Input Voltage Universal input 90 VAC to 265 VAC
switching cycle. The closing of the MOSFET thus occurs at Output Power 60 to 75 W
zero current, cutting out switch turn−on losses and Outputs +108 V 500 mA max (54 W) Regulated
secondary diode recovery losses. By delaying the turn−on +12 V 920 mA max (11 W)
event, it is possible to turn the MOSFET on in the minimum −12 V 670 mA max (8.0 W)
of the drain−source wave, further reducing the losses and the +5 V 70 mA derived from +12 V
electromagnetic interference (EMI). NCP1207 also features through a regulator
a minimum TOFF, preventing a frequency runaway at light +3.3 V 50 mA derived from +5.0 V
through a regulator
loads: when the demagnetization occurs before the end of
the blanking delay, the device waits for the next valley Protections Short−circuit, over−voltage and over−
before enabling a new cycle. power
Low Standby Power: When the output power demand Standby Power Below 1.0 W
decreases, the feedback (FB) pin voltage decreases at the
same time. When it becomes lower than the selected Design Steps
threshold, the device starts to skip cycles, generating just 1. Reflected Voltage
enough switching pulses to maintain the output voltage. This
Let us first start the design by selecting the amount
cycle skipping only occurs at low peak current, ensuring a
of secondary voltage we want to reflect on the
noise−free standby operation.
primary side, which will give us the primary to
Short−circuit Protection: The IC permanently monitors
secondary turn ratio of the transformer. If we decide
the feedback line activity, ready to enter a safe burst mode
that we want to use a rather cheap and common
if it detects a short circuit. Once the short−circuit has
600 V MOSFET, we will select the turn ratio by:
disappeared, the controller automatically goes back to
normal operation. VIN max
N  (VOUT
VF)  600 V
OVP Protection: By sampling the plateau voltage of the VINmax is 370 V and (VOUT + VF) is about 110 V. If
demagnetization winding, the NCP1207 is able to detect an we decide to keep a 10% safety margin, it gives
over voltage on the output. In this case the IC goes in fault, N < 1.5. We will choose a turn ratio of N = 1.2, which
permanently disabling the output. This protection is fully will give a reflected voltage of 130 V.
latched, which means that the power supply has to be
unplugged from the mains to unlatch it. 2. Peak Current
External MOSFET Connection: By leaving the Knowing the turn ratio, we can now calculate the
MOSFET external from the IC, you can choose the device peak primary current needed to supply the 75 W of
exactly suited for your application. You also have the ability output power. If we neglect the delay TW between
to control the shape of the gate signal, giving you an the zero of the current and the valley of the drain
additional way to reduce the amount of EMI and video noise. voltage, we can calculate IPmax (from equation 20)
SPICE Model: A free−running model allows running by:
transient cycle−by−cycle simulations to verify theoretical VINmin
N  (VOUT
VF)
IPmax  2  POUT 
design and help to speed up the design stage of a power   N  VINmin  (VOUT
VF)
supply. An averaged model dedicated to AC analysis is also
available to ease the stabilization of the loop. Ready−to−use VINmin is 110 V and η is 85%. Plugging the other
templates can be downloaded in OrCAD’s PSpice and values gives us a maximum peak current of
Intusoft’s ISPICE from ON Semiconductor web site, IPmax = 2.96 A. We will choose a value of 3.5 A to
NCP1207 related section. take into account various tolerances. NCP1207 max
The data sheet gives complete details regarding the current sense setpoint is 1.0 V, so we should put a
implementation of the NCP1207. sense resistor RS  1.0 V  0.286  . We will use
3.5 A
four standard 1.1  resistors in parallel.

http://onsemi.com
7
 AND8145/D

3. Primary Inductance clamp. You can also use a SPICE simulator to test the
To calculate the primary inductance LP, we need to right values for the components.
decide the switching frequency range we allow the We chose to use an RCD clamp, using a 1N4937
controller to operate. There are two constraints; at diode with a 220 pF snubber capacitor, a 47 k
low line, maximum power, the switching frequency resistor and a 10 nF capacitor: it is an aggressive
should be above the audible range (higher than design (the maximum drain voltage will be very
20 kHz), at high line, lowest nominal power, the close to the maximum voltage allowable for the
OFF time (TOFF + TW) of the MOSFET should be MOSFET), but it gives enough protection without
higher than 8.0 s, to prevent the controller to jump degrading too much the efficiency.
between valleys (because these discrete jumps Once again, if we design the SMPS to work in ZVS,
between 2 valleys can generate noise in the we can have a bigger drain capacitor, that will damp
transformer as well). If we still neglect TW, LP is then the leakage inductor effect (see below).
given by (equation 19):
1 Same Calculation (1 to 4) for a ZVS Power Supply:
LP 
VINmin
N(VOUT
VF)
2 Let us start the design from the beginning, to implement
2  FSWmin  POUTmax  a true ZVS: if we decide to reflect 300 V, assuming that we
NVINmin(VOUT
VF)
have an 800 V MOSFET, we will have a turn ratio of 2.8. The
If we choose 25 kHz min for 75 W of output power exact reflected voltage will be 308 V, and the available
at 110 Vdc, we obtain: LP  687 H. margin for leakage inductance effect will be 117 V. IPmax
To take tolerances into account, we can choose will then be equal to 2.18 A. Applying the same conditions
LP = 600 H, and verify if it satisfies the second for LP will give LP  1.26 mH. If we choose 1.0 mH,
condition: CDRAIN should be higher than 1.6 nF to avoid valley
For 60 W output power at 375 Vdc, IP = 1.46 A. From jumping at 375 Vdc for a 60 W output consumption. If we
equation 9, TOFF = 6.74 s. want to avoid the use of a clamping network to protect the
If we connect a 330 pF drain−to−source capacitor, MOSFET, CTOT should be higher than 2.05 nF (stating that
we calculate TW from equation 12: TW = 1.4 s. LLEAK = 25
H, and that the maximum overvoltage due to
leakage inductance is 115 V). We can choose a capacitor
TOFF + TW = 8.14 s, which is higher than 8.0 s.
CDRAIN = 2.2 nF to be safe.
If nominal output power range of the power supply You can see through the lines we wrote that many
is wider, we can choose a higher LP (650 H for parameters could be changed to obtain different converters
instance) or increase CDRAIN. But this last solution at the end. The reflected voltage is obviously one of the most
will decrease efficiency, as VDS is not equal to 0 sensitive parameters that influence others. Increasing the
when the MOSFET is turned on: in this case Zero reflected voltage to keep a wider ZVS operating range has
Voltage Switching (ZVS) can be a good choice (see a price on other numbers:
below). • The switching frequency increases (reset voltage on LP
4. Clamp is stronger)
In equation 3, we can calculate the overvoltage due • The primary peak current and conduction losses are
LLEAK improved (if FSW goes up, the peak demand goes low)
to the leakage inductance: VOVLEAK  IP .
CTOT • The secondary peak current and conduction losses
At this time we don’t know the value of LLEAK, but increase
we can choose a value of 2% of the primary • The MOSFET undergoes a bigger stress at the switch
inductance (i.e. 12 H), which would not be too far opening
from the final value. Considering again 330 pF on • MOSFET turn−on losses can be really null (if ZVS is
the drain, at 375 V input voltage and 75 W of output achieved).
power, which give IP = 1.83 A, we obtain To simplify the design of your power supply, a
VOVLEAK  349 V. spreadsheet (that includes all the parasitic elements) is
But we only have 95 V available before reaching the available to download from the ON Semiconductor web site
MOSFET breakdown voltage. So we will need to (www.onsemi.com), under NCP1207 page. The formulae
add a clamp to limit the spike at turn−off. are described in the application note AND8089/D. You can
Please refer to application note AN1679/D also simulate the complete power supply in a SPICE
(available at www.onsemi.com) to calculate this simulator, using the NCP1207 models also available from
the website.

http://onsemi.com
8
 AND8145/D

5. SPICE Simulation arrangement, the system simulates very quickly and

The faster and easier way to simulate this power allows an immediate assessment of what has been
supply is to use a simplified free−run model to have suggested by the Excel spreadsheet. The feedback
an idea of the final results. Figure 13 offers a possible loop is purposely simplified with a Zener diode
way to represent a free−running controller: the arrangement, but you can upgrade it with a TL431
demagnetization path includes a standard flip−flop circuitry. It will simply take longer simulation time
that latches the transition while the feedback signal to settle.
fixes the current setpoint. Due to a simple

Vpos12 pos12
D5
MR851
hv
23

X5 Vneg12 neg12
XFMR−AUX B2
RATIO_POW = −0.17 R14 Current
RATIO_AUX = 0.17 120 m 7.0/V(pos12)
12
D6
MR851 R15 B3
120 m Current 21 C10
7.0/V(pos12) 470 
d 22 C11 IC = 10
470 
IC = 10

Vf

X4 IOUT
hv XFMR−AUX  6 VOUT
RPRIM RATIO_POW = −1.2
0.5 RATIO_AUX = −0.06 + +
28 7 VOUT
5
D1
Icoil MR856 Resr1
60 m B1
C1 R7 Idiode
14 Current
10 n 47 k dem
LPRIM 31 COUT1 30/V(VOUT)
600  R6 C6 140 
2.8 K 330 p IC = 107
13 d

LPEAK
+ X2 D2 12 
VIN Free Run DT MUR160
120 rgate = 10 VOUT
11
LEB = 250 n
R1 toffmin = 7.5 + V4
22 k 4
Id
dem 1 8 fb R10
4.7 k
fb 2 7 VDRAIN
24
3 6 R5
10 X1 C3
330 p 16
4 5 MTP6N60E
1 15 X3
C4 MOC8101
Free Run 1.0 n
3
17
Rsense
D3
0.275 BV= 107

Figure 13. Simulation Schematic of the TV Power Supply

http://onsemi.com
9
 AND8145/D

As Figure 14 and Figure 15 show, the simulation is very

close to what is obtained on the board:

VDRAIN (100 V/div)

VSENSE (500 mV/div)

Figure 14. Simulation Results Figure 15. Real Measurements

The SPICE simulation offers another advantage, which is 16 V (max voltage to be applied on VCC pin): we can
the evaluation of the component stresses. Due to good choose a value of 12 V.
models, you can immediately measure the MOSFET The voltage applied on demagnetization pin (pin 1)
conduction losses worse case, the RMS current in the should be lower than the over−voltage protection
rectifiers, in the resonating capacitor and in the output (OVP) threshold, which is 7.2 V. We will add an
capacitors, and choose the right components accordingly. external resistor to divide the auxiliary voltage by 2:
For instance we used the simulated RMS currents to the plateau voltage during normal operation will be
determinate the winding characteristics of the transformer, 6.0 V. It will allow a 2.4 V over−voltage on the
knowing that low line imposes the highest stress on the auxiliary winding, corresponding to a 21.6 V
transformer. Based on the simulation results, the following over−voltage on +108 V output, which is acceptable.
specification has been sent to the transformer manufacturer: There is an internal 28 k resistor, so we just need to
Primary: Input voltage: 90 VAC to 275 VAC add another external 28 k, or 27 k for a more standard
Switching frequency: 30 kHz to 80 kHz value. There is an internal clamping diode to protect
LP = 600 H pin 1 against lethal over−voltages, and the current in
IPpeak = 3.6 A this diode should never be higher than
IP RMS = 1.3 A +3 mA/−2 mA: we must verify that the chosen
resistor is in accordance with this specification. If
Aux: ratio NP/NAUX = 9.0, IRMS = 10 mA during turn−on, the auxiliary winding delivers 35 V
(at the highest line level), then the maximum current
Secondaries: flowing from pin 1 is: (35 V + 0.7 V)/27 k =
B+ (+108 V): ratio NP / NB+ = 1.0, IRMS = 1.0 A 1.32 mA, which is safe.
POW1 (+12 V): ratio NP / NPOW1 = 9.0, IRMS = 1.2 A
POW2 (−12 V): ratio NP / NPOW2 = 9.0, IRMS = 900 mA This resistor, which connects the winding to the pin
(called ROVP1 on the schematic), will also be used to
6. Auxiliary Winding delay the turn−on of the MOSFET to be sure to be
The auxiliary winding will be used to supply the right in the valley of the drain voltage. If the total
controller and to detect the transformer internal capacitance of pin1 (10 pF) is not giving
demagnetization. To supply VCC, the voltage should enough delay, an external capacitor will be added. In
be higher than 11 V (VCCOFF + VF), but lower than our case, we will add a 82 pF capacitor, which will
delay the turn−on exactly in the valley.

http://onsemi.com
10
 AND8145/D

7. DSS reconfiguration is made by a thyristor, activated by

The main reason why the auxiliary winding will also a manual switch to simplify the use of the evaluation
be used to supply the controller is that the maximum board (see Figure 16).
total gate charge of a 6.0 A, 600 V MOSFET can be In fact, the energy stored in the high voltage winding
as high as 50 nC. Knowing that the current consumed is used to refuel the low voltage output capacitor, and
by the output stage is IDRV = FSW x Qg x VDRV, even regulation is now made on this low voltage output.
for a 20 kHz frequency and VDRV = 10 V, IDRV will As the windings are imposing currents (not
be higher than 10 mA. And this current will directly voltages), connecting a high voltage winding to a
flow through the DSS if no auxiliary supply is used. low voltage output is completely safe. But as the
Nevertheless, the DSS is of great interest in a TV regulation loop now forces the high voltage winding
power supply. When a secondary reconfiguration is to deliver a low voltage, then all the other windings
used (or at least the regulation point is lowered) to are also delivering lower voltages than in normal
reduce the standby power, the auxiliary voltage conditions (in the same ratio). The sum of the
collapses. Due to the DSS, the controller is still fully consumptions on all the windings is drastically
powered during standby. This allows to regulate at reduced due to this division of all the output
the lowest possible voltage (minimum input voltage voltages.
of the standby regulator), and the transition from During standby, the regulation is made through the
standby to normal mode is smoother (see Zener diode DZ2 (Figure 17). As NCP1207 is still
measurements section of this document). powered due to the DSS, even is there is no more
The high voltage pin will be connected to one of the auxiliary voltage, the regulation point can be lower
mains inputs through a simple 1N4007 diode to than in normal mode. The only constraint for the
lower the standby power, due to the reduced average output voltage is to be higher than the minimum
voltage due to half−wave rectification (see input voltage of the voltage regulator, but there is no
NCP1207 data sheet for details). need for any guard band. To regulate the 5.0 V
output, we use a standard MC7805 in TO220, with
8. Standby a drop voltage of 2.0 V: the regulation point can be
The standby consumption should be below 1.0 W. To as low as 7.0 V. R9 and C22 can be added to soften
achieve this target, the secondary current the transitions between standby and normal modes.
consumption should be reduced. We choose to use a They are usually not necessary if the loop
secondary reconfiguration that, by re−routing the compensation is correctly designed (by adding RC
high voltage winding to the low voltage output, networks around the TL431).
reduces the voltage of all the unused outputs. The

D12
+12 V +12 V
+ R8 +108 V
C15 C16

IC3
C19 R10
DZ2 C21
D13
+108 V
+
D14 C20 R9
STBY R12
IC2
C22
R17

C24 C25

R18
STBY

Figure 16. Secondary Reconfiguration with Thyristor Figure 17. Standby Regulation for Secondary
Reconfiguration

http://onsemi.com
11
 AND8145/D

The NCP1207 enters a low peak current skip mode Approach 1 (Overpower Compensation):
to lower the consumption in low−load conditions. A classical way to compensate this effect is to add an
But with some cheap transformers, the peak current amount of the input voltage to the primary current sense
might be too high, generating an audible noise. In information (Figure 19):
that case, we propose a different implementation for
the standby regulation (Figure 18): by imposing a +
ripple on the regulated output, we force the Cbulk LPRIM
controller to run in a burst mode, which generates
less mechanical stress in the transformer. RCOMP

STBY
DRV
R8 OUTPUT
RCS
IC3x CS
R19 C28
RSENSE
Burst Generator

DZ2 DZ3
R31 R34
Q1 Figure 19. Classical Overpower Compensation
+ +
C26 R33 C27 SW1
Unfortunately, it is not possible to implement this scheme
with NCP1207 as the resistor in series with the current sense
information (RCS) has to be low, since it is used to adjust the
skip cycle level. It would require a low compensation
R14
Q3 resistor RCOMP, wasting a lot of power.
It would be interesting to have an image of the input
R15 voltage, but at a lower level. It is possible by using the
forward voltage on the auxiliary winding: by adding a diode
in series with the auxiliary winding, we have access to the
forward voltage (Figure 20).
Figure 18. This Standby Regulation Circuitry
+
Imposes a Noise−free Burst Mode Cbulk
LPRIM

9. Overpower Protection
NCP1207 integrates a short−circuit protection, +
RVCC
RFWD
LAUX
CVCC D2
based on the sensing of the peak primary current.
Unfortunately, as we have seen before, this peak CRES
Rdmg
current is dependent of the input voltage (Figure 19): D1
the sense resistor has to be chosen to allow the 8 7 6 5
maximum peak current at low input voltage to flow
in the MOSFET. But at high input voltage, the peak NCP1207
current necessary to deliver the same output power RCOMP
is much lower: the sense resistor being fixed, the 1 2 3 4 RSKIP
maximum output power deliverable at high input
voltage is much greater. The conclusion is that the
built−in short−circuit protection is not an overpower RSENSE
Cdmg
protection (OPP).
It is however possible to implement an OPP by
adding few additional components beside the
controller. We propose two different approaches, Figure 20. Overpower Compensation using
Forward Voltage
one by compensating the CS pin voltage depending
on the input voltage, the other by sensing the output
current.

http://onsemi.com
12
 AND8145/D

This forward voltage is proportional to N.VIN (N being resistor RCOMP to create the desired offset on the current
the turn ratio of the windings). RFWD is added to supply the sense signal at high input voltage.
reverse current during the forward activity. Knowing the Here are some screen shots describing the effect of the
value of the forward voltage and the series resistor RSKIP, it compensation:
is then easy to calculate the value of the compensation

: 400 mV
 COMPENSATION OFFSET

1 − CURRENT SENSE PIN VOLTAGE

2 − SENSE RESISTOR VOLTAGE

3 − COMPENSATION VOLTAGE

4 − DRAIN VOLTAGE

Figure 21. Line Compensation at VIN = 365 Vdc

: 400 mV

 COMPENSATION OFFSET = 0 V

1 − CURRENT SENSE PIN VOLTAGE

2 − SENSE RESISTOR VOLTAGE

3 − COMPENSATION VOLTAGE

4 − DRAIN VOLTAGE

Figure 22. Line Compensation at VIN = 100 Vdc

http://onsemi.com
13
 AND8145/D

Approach 2 (Regulation Foldback): Final Schematic

By sensing the current flowing in an output, it is possible Figure 24 on the following page, shows the final
to build an efficient overcurrent protection, folding back the schematic implemented on the demonstration board. It
regulation level when the current threshold is reached. It is includes all the options presented in the design steps.
purposely completely independent of the input voltage. The board is equipped by default with the following options:
A simple bipolar NPN transistor can sense the voltage • An RCD clamp for non−ZVS designs
across the resistor and pull down the optocoupler emitting
diode (Figure 23). The protection is temperature dependent,
• A regulation by Zener diode when the secondary
but it gives enough precision in most applications. The main reconfiguration is activated
drawback of this approach is that only one output is • An overcurrent protection on the 108 V output
protected: the circuitry must be duplicated on each output The PCB also accepts the following options:
that needs to be protected. • A regulation by the ripple generator when the
secondary reconfiguration is activated (see bill of
+12 V +108 V
material for components mounting for this option)
108 V • An overpower compensation through the use of the
RSENSE forward voltage on the auxiliary winding
0V Two types of transformers can be soldered on the board,
R8 R10
either from OREGA or from VOGT ELECTRONIC.

IC1
Q1

R11
C21

P1

IC2
R12

Figure 23. Overcurrent Foldback on the 108 V Output

http://onsemi.com
14
 GND

+
C13 C14
D11 −12 V

+12 V IC4 +5.0 V IC4

D12 +3.3 V
IN REG OUT IN REG OUT
5.0 V 3.3 V
+ + +
C15 C16 C17 C18
GND
GND
D5 R1
R2 C8 C19 GND
B+
D13 108 V
ROVP1

+ R8
C20
D14 R10
IC3x R22
D1 C9 D6 R3 R31 0V
+ IC1
R19
C4 C5
R23
http://onsemi.com

8
D19

AND8145/D
R17
2

7
D7
C12 TH1 Q4
3

6 R4
D16 R35
R11
C24
15

C3 D8 R5
C25 C28
X1 DZ2
C7 ROVP2 C21
C2 R32
R18 +12 V
R6 D9 P1
R9 IC2
Rs4 Rs3 Rs2 Rs1
C6 +
DZ1 C11 C10 D10 C22
IC3
R12

C1
C23 R13 DZ3 R34
Q2 Q1
F1 R21 R16 R14 + +
R7 Q3 C26 R33 C27

R20 R15
MAINS

Figure 24. Schematic of the Demonstration Board

 AND8145/D

Board Performance length = 1 hour). At VIN = 230 VAC, 5.0 V output loaded
with 30 mA (i.e. 150 mW output power):
Efficiency
• With simple Zener regulation: PSTBY = 850 mW (but
At VIN = 250 VAC, POUT = 70 W, η = 84.3%
might be noisy with some transformers)
At VIN = 90 VAC, POUT = 70 W, η = 85.1%
At VIN = 250 VAC, POUT = 65 W, η = 83.6% • With ripple generator: PSTBY = 1.0 W
At VIN = 90 VAC, POUT = 65 W, η = 84.7% Conducted EMI Signature
Standby Power An EMI test has been conducted on the board, at 110 VAC
Measured on an Infratek wattmeter operating in and 220 VAC, with full load on all the outputs (75 W total
watt−hour accumulation mode for better accuracy (run secondary power): Figure 25. The measurement is done in
quasi−peak (QP) mode.

Figure 25. EMI Signature Captured at 110 VAC and 230 VAC

http://onsemi.com
16
 AND8145/D

WAVEFORMS

P1

P2

P3

P4

Figure 26. VDRAIN for Different Output Power (P1 > P2 > P3 > P4)

Figure 26 shows valley jumping when output power Maximum drain voltage is obtained at high line, full load.
decreases (P3 < P2 < P1), and skip in case of really light load At 380 Vdc, 80 W on the output, we can see from Figure 27
(P4). that the MOSFET is safe.

Figure 27. Max VDRAIN at High Line, Full Load

http://onsemi.com
17
 AND8145/D

As Figure 28 shows, the transition from standby to normal is still regulated in standby, it can be lowered as much as
mode is smooth, without any steps. As the “+12 V” output needed to supply the 5.0 V regulator.

12 V 2 − VCC
10 V

12 V 1 − + 12 V Output

8.5 V

108 V 3 − + 108 V Output

13 V

Figure 28. Standby to Normal Mode Transition

http://onsemi.com
18
 AND8145/D

BILL OF MATERIAL

Standard Equipment of the Board

GENERIC TABLE Part Number Reference
Part Number Reference P1 500 R
IC1 NCP1207 Rs1, Rs2, Rs3, Rs4 1.1 R
IC2 TL431 RVOP1 33 k
IC3 SFH615 R1 15 k
IC4 MC7805 R2 47 k/2 W
IC5 LP2950−3.3 V R3 47 R
X1 IRFIB6N60 R4 10 R
Q1, Q2, Q3, Q4 BC547C R5 Replaced by a wire
D1 KBU4K R6 390 R
D5, D9, D10 1N4007 R7 4.7 Meg/4 kV
D7, D8, D16 1N4148 R8, R18, R19 1k
D6, D14 1N4937 R10 56 k
D13 MR856 R11 47 k
D11, D12 MR852 R12 2.2 k
D19 Replaced by a wire R13, R14, R15, R16, R20, R21 10 k
DZ1 Zener 15 V R17 4.7 k
DZ2 Zener 5.6 V R22, R23 1.5 R
DZ3 Replaced by a wire R34 Replaced by a wire
TH1 MCR22−6 R35 27 k
F1 250 VAC/2.0 A *For a ZVS transformer, order OREGA ref. G7209−03
(C22, C26, C27, R9, R31, R32 and R33 are not implemented, a
T1* Transformer VOGT reference
15 V Zener diode is added in parallel to IC2)
UL030 121/21 or OREGA
reference G7209−01
Modifications needed to implement the standby ripple
L1 Mains filter OREGA
generator:
SW1 TL36P
Part Number Reference
C1, C2 220 nF/275 VAC classe X2
DZ2 Replaced by a wire
C3, C4 1 nF/1 kV
DZ3 Zener 3.9 V
C5 150 F/400 V
C26, C27 1.0 F/25 V
C6, 21 1 nF/50 V
R13 22 R
C7 82 pF/50 V
R33 15 k
C8 10 nF/630 V
R34 47 k
C9, C19 220 pF/1 kV
C10 33 F/50 V
Overpower Compensation:
C11, C13, C15, C25, C28 100 nF/50V
Part Number Reference
C12 330 pF/1 kV
D19 1N4148
C14, C16 470 F/35 V
R31 4.7 k
C17, C18 100 F/16 V
R32 18 k
C20 47 F/250 V
C23 2.2 nF/4 kV classe Y
C24 100 pF/200 V

http://onsemi.com
19
 AND8145/D

PCB LAYOUT

−12 V GND +12 V GND

5V
GND

3.3 V
GND

108 V
0V

STANDBY

Some important points that have been taken into account • The drain track is the shortest possible
to make a proper layout: • The heatsink is connected to ground. It acts as a shield
• The high alternating current loops areas both on between the noisy signals (drain, RCD clamp,
primary and secondary are the smallest possible to transformer) and the sensitive signals around the
minimize noise and EMI emission controller

http://onsemi.com
20
 AND8145/D

Notes

http://onsemi.com
21
 AND8145/D

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: http://onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Order Literature: http://www.onsemi.com/litorder
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your
Email: [email protected] Phone: 81−3−5773−3850 local Sales Representative.

http://onsemi.com AND8145/D
22