3.
Hardware
Objectives
• Define System unit
• Define CPU
• Computer Architecture and its components
System unit
• A case that contains electronic
components of the computer used
to process data
• System units are available in a
variety of shapes and sizes
• The case of the system unit is
made of metal or plastic and
protects the internal electronic
components from damage.
CPU (Central Processing Unit)
• Also called processor /
Microprocessor
• The CPU processes instructions and
data that are input into the
computer so that the result can be
output
• The CPU is the electronic circuit
responsible for executing the
instructions of the computer
program
Motherboard
• System board
• The main circuit
board of the system
unit.
• Many electronic
components attach
to the motherboard
Computer Architecture
• A specification detailing how a
set of software and hardware
technology standards interact
• Von Neumann Architecture
model is based on the ‘stored
program computer’ concept,
where instruction data and
program data are stored in the
same memory
Von Neumann Architecture
• First published by John von
Neumann in mid-1940s
• Architecture design consists
of a Control Unit, Arithmetic
and Logic Unit (ALU),
Memory Unit, and Registers.
Von Neumann Architecture
Von Neumann Architecture characteristics
• Utilises a single processor
• Utilises one memory for both
instructions and data
• Implements programs by
executing one instruction at
a time
Von Neumann Architecture
• Based on the stored program
computer concept, where
instruction data and program
data are stored in the same
memory.
• This design is still used in
most computers produced
today.
CPU - Control Unit
• It handles the movement of instructions to and from
the memory and the execution of instructions one at a
time.
• Reads an instructions from memory.
CPU - Control Unit
• Ensures synchronisation of data flow and program
instruction.
• System clock: produce timing signals on the control
bus to ensure synchronisation takes place.
CPU – Arithmetic Logic Unit
• ALU allows arithmetic (add, subtract etc) and logic
(AND, OR, NOT etc) operations to be carried out
• Comparison operation: greater than, equal to
CPU - Registers
• A register is a temporary storage are built into a CPU
as part of Fetch-Decode-Execute cycle.
• High speed storage areas in the CPU.
• All data must be stored in the register before it can be
processed.
CPU - Registers
Program counter (PC)
• Contains the address of the next instructions to be
executes .
• After instruction carried out, PC able to process where
abouts the next instructions is.
CPU - Registers
Current Instruction Register (CIR)
• The instruction now in MDR is copied into the CIR
• Contains the current instruction during processing
• Stores the current instruction being decodes and
executes
CPU - Registers
Accumulator (ACC)
• Where intermediate arithmetic and logic results are
stored
• Collect results temporarily before being used by other
process.
CPU - Registers
Memory Address Register (MAR)
• The address that was read from the PC is sent
• Stores address of the memory location currently being
read from and written to.
CPU - Registers
Memory Data Register (MDR)
• The memory is searched to find the address being
held in the MAR must be the instruction
• It stores data which has just been read from memory
or data which is about to be written to memory.
Classwork
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CPU - Registers
PC: stores the address of the next instructions to be executes.
CIR: Contains the current instruction being decodes and
executes.
ACC: Where intermediate arithmetic and logic results are
stored
MAR: stores the address of memory location currently being
read from or written to.
MDR: stores data which has just been read from memory or
data which is about to be written to memory
Buses
• Communication link used in the computer system
• Buses transfer data around the computer
• Buses are the means by which data is transmitted
from one part of a computer to another connecting all
major internal components to the CPU and memory
Address bus
• It carries signals relating to addresses, from processor
to the input/output and memory unit
• One direction
• Unidirectional
Data bus
• It send data between the processor, memory unit and
the input/output devices
• Two-way direction
• Bidirectional
Control bus
• It carries signals relating to control and coordination
of all activities within the computer or motherboard
components
• Two-way directional
Address
• Store instructions, data, and intermediate results.
• This unit supplies information to other units of the
computer when needed.
• The computer memory is made up of number of
partition
• Each partition consists of an address and its contents
Memory unit
RAM (Random Access Memory)
• It is an internal chip where data temporary
stored
• Volatile: Data is lost when the computer
switch off.
• Stores data and programs currently on use
ROM (Read only memory)
• Non-volatile: data is not lost when
computer is switch off
• Stores instructions that tell the computer
how to start up
RAM (Random Access ROM (Read Only Memory)
Memory)
Temporary stored data Permanently store data
Volatile Non-volatile
Read and write data Read only
Fetch-Decode-Execute cycle
• The fetch-decode-execute
cycle is the basic operation
(instruction) cycle of a
computer
• During this time, the
computer retrieves a program
instruction from its memory.
Fetch-Decode-Execute cycle
• It then establishes and carries
out the actions that are
required for that instruction.
• This cycle is continually
repeated by the CPU whilst the
computer is turned on.
Fetch-Decode-Execute cycle
• Address bus and data bus are
used in this process
Fetch
During the fetch part of the cycle:
• The contents of the PC, which holds the address of the next
instruction to be executed, is placed into the MAR
• Next, the address is sent from the MAR to main memory
• Next, the instruction at that address is found and copied to
the MDR. At the same time, the contents of the PC is
increased by 1, to point to the next instruction to be
executed.
Fetch
• The processor checks the PC to see which instruction
to run next.
• The PC gives an address value in the memory of where
the next instruction is.
• The processor fetches the instruction value from this
memory location.
Decode
• Once the instruction has been fetched,
it needs to be decoded and executed.
• For example, this could involve taking
one value, putting it into the ALU, then
taking a different value from a register
and adding the two together.
Decode
• In the decode part of the cycle, the
control unit works out what the
instruction is and sends signals to
coordinate the other components.
• Operation Code (opcode) split data in
MDR
• Control unit interprets opcode
Execute
• Lastly, during the execute part of the
cycle, the instruction is executed,
using the ALU if necessary.
• Address copied from CIR or MAR
• Get data from primary memory and
copy to MDR
• Sometimes, this stage requires
loading or saving data to and from
the main memory.
Execute
• Once this is complete, the processor
goes back to the PC to find the next
instruction.
• This cycle is repeated until the
program ends.
Summary of the fetch-decode-execute
• The processor checks the PC to see which instruction to run
next.
• The PC gives an address value in the memory of where the
next instruction is.
• The processor fetches the instruction value from this memory
location.
• Once the instruction has been fetched, it needs to be decoded
and executed.
• Once this is complete, the processor goes back to the PC to
find the next instruction.
Main Memory
1 LOAD 5
2 ADD 6
3 STORE 7
4 STOP
5 10
6 11
8
Fetch-Decode-Execute cycle
• The fetch-decode-execute
cycle is the basic operation
(instruction) cycle of a
computer
• During this time, the
computer retrieves a program
instruction from its memory.
Main Memory
PC 1 MAR 1
1 LOAD 5
2 ADD 6
MDR LOAD 5 CIR LOAD 5
3 STORE 7
4 STOP
5 10
ACC
6 11
7
CU ALU
8
Main Memory
PC 2 MAR 5
1 LOAD 5
2 ADD 6
MDR LOAD 5 CIR LOAD 5
3 STORE 7
4 STOP
5 10
ACC 10
6 11
7
CU LOAD 5 ALU
8
Main Memory
PC 2 MAR 2
1 LOAD 5
2 ADD 6
MDR ADD 6 CIR ADD 6
3 STORE 7
4 STOP
5 10
ACC 10
6 11
7
CU ALU
8
Main Memory
PC 3 MAR 6
1 LOAD 5
2 ADD 6
MDR 11 CIR ADD 6
3 STORE 7
4 STOP
5 10
ACC 21
6 11
7
CU ADD 6 ALU 11+10
8
Main Memory
PC 3 MAR 3
1 LOAD 5
2 ADD 6
MDR STORE 7 CIR STORE 7
3 STORE 7
4 STOP
5 10
ACC 21
6 11
7 21
CU STORE 7 ALU 11+10
8
Main Memory
PC 4 MAR 3
1 LOAD 5
2 ADD 6
MDR STORE 7 CIR STORE 7
3 STORE 7
4 STOP
5 10
ACC 21
6 11
7 21
CU STORE 7 ALU
8
Main Memory
PC 4 MAR 4
1 LOAD 5
2 ADD 6
MDR STOP CIR STOP
3 STORE 7
4 STOP
5 10
ACC 21
6 11
7 21
CU STOP ALU
8
Main Memory
PC 1 MAR 4
1 LOAD 6
2 SUBTRACT 7
MDR STOP CIR STOP
3 STORE 5
4 STOP
5
ACC
6 9
7 4
CU STOP ALU
8
Objective achieved
• System unit
• Control unit
• Von Neumann Architecture
• Buses
• Memory unit
Research
What is heatsink?
What if there is no heat sink and fan?
What is Fetch-Decode-Execute cycle?
Research
• What does clock cycle, cache and core do
relating to computer performance?
