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VHDL Cheat Sheet

This cheat sheet provides essential VHDL syntax and structures, including entity and architecture definitions, combinational logic implementations, priority encoders, and multiplexers. It emphasizes the importance of including default cases and listing all inputs in processes, along with strategies for exam success. Key examples illustrate how to implement logic equations succinctly.

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Laila Wajdane
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20 views2 pages

VHDL Cheat Sheet

This cheat sheet provides essential VHDL syntax and structures, including entity and architecture definitions, combinational logic implementations, priority encoders, and multiplexers. It emphasizes the importance of including default cases and listing all inputs in processes, along with strategies for exam success. Key examples illustrate how to implement logic equations succinctly.

Uploaded by

Laila Wajdane
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Ultra-Simple VHDL Exam Cheat Sheet

(Only what's in Lecture 10 - Just the essentials!)

――――――――――――――――――――――――――――――――――――――――――――――――――

1. Basic Structure
entity NAME is
port (
A, B : in std_logic; -- Inputs
Y : out std_logic -- Output
);
end NAME;

architecture ARCH of NAME is


begin
-- Logic goes here
end ARCH;

2. Combinational Logic
Option 1: Direct Logic (Slide 9)
Y <= (A and B) or C; -- Pure boolean equation

Option 2: when-else (Slide 11)


Y <= '1' when (A='1' and B='1') else '0';

Option 3: process (Slide 13)


process (A, B)
begin
Y <= '0'; -- Default!
if (A='1') then Y <= '1'; end if;
end process;

3. Priority Encoder (Slide 18)


process (y1, y2, y3)
begin
if (y3='1') then dout <= "11"; -- Highest priority
elsif (y2='1') then dout <= "10";
else dout <= "00"; -- Default
end if;
end process;

4. Multiplexer (Slide 24)


2-to-1 MUX
Y <= A when (sel='0') else B;
4-to-1 MUX
with SEL select
Y <= I0 when "00",
I1 when "01",
I2 when "10",
I3 when others; -- Must include!

5. Golden Rules
1. Always include else/others
-- GOOD:
Y <= '0'; -- Default first
if (A='1') then Y <= '1'; end if;

-- BAD (creates latch):


if (A='1') then Y <= '1'; end if;

2. List ALL inputs in process( )


process (A, B) -- All inputs used inside

3. Compare with ='1' or ='0'


if (A='1') then ... -- Correct
if (A) then ... -- WRONG!

6. Bus Basics (Slide 19)


signal BUS : std_logic_vector(3 downto 0); -- 4-bit bus
BUS <= "1010"; -- Assign all bits
BUS(3) <= '1'; -- Set bit 3 (MSB)

Exam Strategy
1. Need logic gates? → Use direct equations (Y <= A and B;)
2. Need priority? → Use if-elsif-else in a process
3. Need a MUX? → Use when-else or with-select
4. Stuck? → Draw the truth table first!

Example: Implement Y = (A ⊕ B) · C
Y <= (A xor B) and C; -- One-line solution

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