Chapter 2

Instructions:
Language of the
Computer
 §2.1 Introduction
Instruction Set
■ The words of a computer’s language
are called instructions, and its
vocabulary is called an instruction Set
■ Different computers have different
instruction sets
■ But with many aspects in common
■ Early computers had very simple
instruction sets
■ Simplified implementation
■ Many modern computers also have simple
Chapter 2 — Instructions: Language of the Computer — 2
Instruction Set Architecture
■ Anything programmers need to know to make a
binary machine language program work
correctly, including:
■ Registers
■ Organization of programmable storage
■ Data types and data structures: encoding
and representations
■ Instruction set
■ Instruction formats
■ Modes of addressing: accessing data items
and instructions
■ Exceptional conditions
Chapter 2 — Instructions: Language of the Computer — 3
The MIPSInstruction
Set
■Used as the example throughout the book Microprocessor
without Interlocked Pipelined Stages
■ Stanford MIPS commercialized by MIPS Technologies
■ using the RISC instruction set (RISC processors typically support
fewer and much simpler instructions)
■ Founded in 1984 by a group of researchers from Stanford
University that included John L. Hennessy
■ Little share of embedded core market
■ Applications in consumer electronics, network/storage
equipment, cameras, printers, …
■ Typical modern ISAs
■ ARM: ARMv7
■ HP: PA-RISC 2.0
■ Intel: x86 - IA-32, x86-64 (Intel 64); IA-64
■ MIPS: MIPS32, MIPS64
■ SUN: SPARC-V9
Chapter 2 — Instructions: Language of the Computer — 4
 §2.2 Operations of the Computer Hardware
Arithmetic
Operations
■Add and subtract, three operands
■ Two sources and one destination
add a, b, c # a gets b + c
■ Operation, operator, operand
■ All arithmetic operations have this form
■ Design Principle 1: Simplicity favors regularity
■ Regularity makes implementation simpler
■ Simplicity enables higher performance at lower cost
31 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

Chapter 2 — Instructions: Language of the Computer — 6

add a, b, c # a gets b + c
This MIPS assembly instruction means:
Add the values stored in registers b and c
Store the result in register a
 §2.3 Operands of the Computer Hardware
RegisterOperands
■ Arithmetic instructions use operands from
registers
■ The size of a register in MIPS architecture
is 32 bits, which is a word
■ The word is the natural unit of access in a
computer, usually a group of 32 bits;
corresponds to the size of a register

Chapter 2 — Instructions: Language of the Computer — 9

RegisterOperands
■ The word size/length, 8b/32b/64b and the
memory address space
■ GPRs（General-Purpose Registers)
lw $t0, 32($s3) # load word
$s3: the size of a register
■ Cf. Width of address bus
■ MIPS: 232 bytes or 230 words
■ Memory is byte addressed

Chapter 2 — Instructions: Language of the Computer —

RegisterOperands
■ MIPS has a 32 × 32-bit register file
■ Use for frequently accessed data
■ Cache of cache?
■ Numbered 0 to 31
■ Assembler names
■ $t0, $t1, …, $t9 for temporary values
■ $s0, $s1, …, $s7 for saved variables
■ $zero
■ Design Principle 2: Smaller is faster
■ Cf. main memory: millions of locations

Chapter 1 — Computer Abstractions and Technology — 10

RegisterOperand Example

Chapter 2 — Instructions: Language of the Computer — 14

Memory Operands

Chapter 2 — Instructions: Language of the Computer — 15

Addressing Alignment Constraints
■ MIPS uses byte addressing for halfword, word,
and doubleword accesses with the following
alignment constraints:
■ Halfword accesses must be aligned on an even byte
boundary (0, 2, 4...).
■ Word accesses must be aligned on a byte boundary
divisible by four (0, 4, 8...).
■ Doubleword accesses must be aligned on a byte
boundary divisible by eight (0, 8, 16...).

Chapter 2 — Instructions: Language of the Computer — 16

Endianness
The term endianness describes the order in which
computer memory stores a sequence of bytes.
Endianness can be either big or small, and the adjectives
refer to the value stored first.

Big-endian is an order in which the big end -- the most

significant value in the sequence -- is first, at the lowest
storage address. Little-endian is an order in which the
little end, the least significant value in the sequence, is
first.
A big-endian computer would store the two bytes required
for the hexadecimal number 4F52 as 4F52 in storage. For
example, if 4F is stored at storage address 1000, 52 will
be at address 1001. A little-endian system would store
them as 524F, with 52 at address 1000 and 4F at 1001.
 Endianness
■ Endianness is the order in which
bytes are stored in a computer's
memory or transmitted over a
network It's also known as "byte
order".
■ MIPS can support both big and
little endian
■ Big endian: most-significant byte at
least address of a word.
■ Motorola 6800, 68000; PowerPC,
System/370; PDP-10; SPARC until
version 9
■ Little endian: least-significant byte at
least address
■ x86, 6502, Z80, VAX, and, largely,
PDP-11
■ Bi-endian: switchable endianness
■ ARM, PowerPC, Alpha, SPARC V9,
Chapter 1 — Computer Abstractions and Technology — 14
MIPS, PA-RISC and IA-64
Memory Operand Example
1
■ C code:

g = h + A[8];
■ g in $s1, h in $s2, base address of A in $s3

■ Compiled MIPS code:

■ Index 8 requires offset of 32
■ 4 bytes per word
lw $t0, 32($s3) # load word add
$s1, $s2, $t0
offset base register

Chapter 2 — Instructions: Language of the Computer — 19

Memory Operand Example
2
■ C code:

A[12] = h + A[8];
■ h in $s2, base address of A in $s3

■ Compiled MIPS code:

■ Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word

Chapter 2 — Instructions: Language of the Computer — 20

Registers vs.
Memory
■ Registers are faster than memory
■ Smaller is faster
■ Operating on memory data requires loads
and stores
■ More instructions to be executed
■ Compiler must use registers for variables
as much as possible
■ Only spill to memory for less frequently used
variables by store
■ Register optimization is important!
Chapter 2 — Instructions: Language of the Computer — 21
Immediate
Operands
■Constant data specified in an instruction
addi $s3, $s3, 4
■ No subtract immediate instruction
■ Just use a negative constant
addi $s2, $s1, -1
■ Design Principle 3: Make the common case fast
■ Small constants are common
■ Immediate operand avoids a load instruction

op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

Chapter 2 — Instructions: Language of the Computer — 22

The Constant
Zero
■ MIPS register 0 ($zero) is the constant 0

■ Cannot be overwritten
■ Hardwired to ground
■ Useful for common operations
■ E.g., move between registers
add $t2, $s1, $zero

Chapter 2 — Instructions: Language of the Computer — 23

 §2.5 Representing Instructions in the Computer
Representing Instructions
■ Machine language
■ Instructions are encoded in binary, called
machine code
■ Used for communication within a computer
■ Very hard to make out which instruction is
which
■ Assembly language
■ Symbolic representation of machine
instructions： mnemonic symbol

Chapter 2 — Instructions: Language of the Computer — 24

MIPS Instruction
Set
■ MIPS instructions

■ Encoded as 32-bit instruction words

■ Small number of formats encoding operation
code (opcode), register numbers, …
■ Similar instructions have the same format
■ Simplicity favors regularity!
■ Register numbers
■ $t0 – $t7 are reg’s 8 – 15
■ $t8 – $t9 are reg’s 24 – 25
■ $s0 – $s7 are reg’s 16 – 23
Chapter 1 — Computer Abstractions and Technology — 26
MIPS R-format
Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

■ Instruction format
■ The layout of the instruction
■ Instruction fields
■ op: operation code (opcode)
■ rs: first source register number
■ rt: second source register number
■ rd: destination register number
■ shamt: shift amount (00000, useless for R-format)
■ funct: function code (extends opcode)
Chapter 2 — Instructions: Language of the Computer — 26
R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016
Machine code
Chapter 2 — Instructions: Language of the Computer — 27
Hexadecimal
■ Base 16
■ Compact representation of bit strings
■ 4 bits per hex digit
0 0000 4 0100 8 1000 c 1100
1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111

■ Example: eca8 6420

■ 1110 1100 1010 1000 0110 0100 0010 0000

Chapter 2 — Instructions: Language of the Computer — 28

MIPS I-format
Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

■ Immediate arithmetic and load/store instructions

■ rt: destination (addi, lw) or source (sw) register
number
■ Constant: –215 to +215 – 1 (signed)
■ Address: offset added to base address in rs
■ Design Principle 4: Good design demands good
compromises
■ Different formats complicate decoding, but allow 32-bit
instructions uniformly
■ Keep formats as similar
Chapter 2 as possible
— Instructions: Language of the Computer — 29
Stored Program
Computers
The BIG Picture
Stored-program concept
■

■ Instructions represented in binary as

numbers, just like data
■ Instructions and data are stored in
memory to be read or written,
just like numbers
■ Programs can operate on
programs
■ E.g., compilers, linkers, …
■ Binary compatibility allows
compiled programs to work on
different computers
■ Often leads industry to align around a
small number of ISAs, e.g. x86,
ARM
■ Ecosystem
Chapter 2 — Instructions: Language of the Computer — 30
 Von Neumann architecture
Computer Organization is like understanding the “blueprint” of how a computer
works internally. One of the most important models in this field is the Von
Neumann architecture, which is the foundation of most modern computers.
Named after John von Neumann, this architecture introduced the concept of
storing both data and instructions in the same memory.
Historically there have been 2 types of Computers:
1.Fixed Program Computers – Their function is very specific and they couldn’t be
reprogrammed, e.g. Calculators.

2.Stored Program Computers – These can be programmed to carry out many

different tasks, applications are stored on them, hence the name.

The Von Neumann architecture popularized the stored-program concept,

making computers more flexible and easier to reprogram. This design stores
both data and instructions in the same memory, simplifying hardware design
and enabling general-purpose computing.
Von Neumann architecture
■ Von Neumann architecture
■ “Stored-program computer“ and
"Von Neumann architecture" are
interchangeably
■ Named after the mathematician
and early computer scientist John
von Neumann
■ Arose from Von Neumann's paper
"First Draft of a Report on the
EDVAC"
■ Von Neumann bottleneck
■ The limited throughput between the
CPU and memory (memory wall)
■ Cf. Harvard architecture

Chapter 1 — Computer Abstractions and Technology — 32

 §2.6 Logical Operations
Logical Operations
■ Instructions for bitwise manipulation
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor

Chapter 2 — Instructions: Language of the Computer — 33

Shift Operations
31 26 25 21 20 16 15 11 10 6 0

0 rt rd sa 5 SLL
SPECIAL
000000 00000 000000
6 5 5 5 5 6

sll $t2, $t1, 3

■ R-format
■ rs: unused
■ shamt: how many positions to shift
■ Useless for add/sub
■ Simplicity favors regularity!
■ Useful for extracting and inserting groups
of bits in a word
Chapter 2 — Instructions: Language of the Computer — 34
Shift Operations
■ Shift left logical
■ Shift left and fill with 0 bits
■ sll by i bits multiplies by 2i
■ Shift right logical
■ Shift right and fill with 0 bits
■ srl by i bits divides by 2i (unsigned
only)
■ Shift right arithmetic
■ Duplicate the sign-bit (bit 31)
■ sra by i bits divides by 2i (signed)

Chapter 1 — Computer Abstractions and Technology — 35

AND Operations
■ Useful to mask bits in a word
■ Select some bits, clear others to 0
31 26 25 21 20 16 15 11 10 6 5 0

SPECIAL rs rt rd 0 AND
000000 00000 100100
6 5 5 5 5 6

and $t0, $t1, $t2

$t2 0000 0000 0000 0000 000 0 11 01 1100

0000
$t1
0000 0000 0000 0000 00 11 0000 0000
1100
$t0
0000 0000 0000 0000 000 0 11 00 0000
0000
Chapter 2 — Instructions: Language of the Computer — 36
OR Operations
■ Useful to include bits in a word
■ Set some bits to 1, leave others unchanged
31 26 25 21 20 16 15 11 10 6 5 0

SPECIAL rs rt rd 0 OR
000000 00000 100101
6 5 5 5 5 6

or $t0, $t1, $t2

$t2 0000 0000 0000 0000 000 0 11 01 1100
0000
$t1
0000 0000 0000 0000 00 11 0000 0000
$t0 1100

0000 0000 0000 0000 00 11 1100 0000

1101 Language of the Computer — 37
Chapter 2 — Instructions:
NOT Operations
■ Useful to invert bits in a word
■ Change 0 to 1, and 1 to 0
■ No NOT operation, but NOR
■ MIPS has NOR 3-operand instruction
■ a NOR b == NOT ( a OR b )
31 26 25 21 20 16 15 11 10 6 5 0

SPECIAL rs rt rd 0 NOR
000000 00000 100111
6 5 5 5 5 6

nor $t0, $t1, $zero

$t1 0000 0000 0000 0000 0011 1100 0000 0000

$t0 1111 1111 1111 1111 1100 0011

1111 1111
Chapter 2 — Instructions: Language of the Computer — 38
 §2.7 Instructions for Making Decisions
Conditional Operations
■ The difference between a computer and a
calculator is the ability to make decisions
■ In high level language
■ if statement
■ go to statement
■ Branch to a labeled instruction if a condition is
true; Otherwise, continue sequentially
■ Conditional and unconditional branches
■ PC-relative and absolute/register indirect
branch

Chapter 2 — Instructions: Language of the Computer — 39

Conditional Operations
■ MIPS defines the following instructions
■ PC-relative conditional branch: bne,beq, ± 128 KB
■ PC-region unconditional jump: j, jal, 256MB region
■ Absolute/register indirect unconditional jump: jr
■ How to “decide”? Program counter (PC)
■ The register containing the address of the instruction
in the program being executed
■ PC is affected only indirectly by certain instructions -
it is NOT an architecturally-visible register

Chapter 2 — Instructions: Language of the Computer — 40

Conditional Operations
■ Conditional branches
■ beq rs, rt, L1
■ if (rs == rt) branch to instruction labeled L1;
■ bne rs, rt, L1
■ if (rs != rt) branch to instruction labeled L1;
■ Cf. ARM
■ cmp r1, r2 #CPSR <= r1-e2 in
■ beq L1 #test CPSR, then..
31 26 25 21 20 16 15 0

BNE rs rt offset
000101
6 5 5 16

Chapter 1 — Computer Abstractions and Technology — 41

Conditional Operations
■ Unconditional branch
■ j L1
■ Unconditional jump to instruction labeled L1
■ PC-region: 256 MB aligned region

31 26 25 0

J instr_index
000010
6 26

Chapter 1 — Computer Abstractions and Technology — 42

Compiling If Statements
■ C code:
if (i==j) f = g+h;
else f = g-h;
■ f, g, … in $s0, $s1, …
■ Compiled MIPS code:
bne $s3, $s4, Else # <> ?
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: … Assembler calculates addresses

Chapter 2 — Instructions: Language of the Computer — 43

Compiling Loop Statements
■ C code:
while (save[i] == k) i += 1; //cf. for
■ i in $s3, k in $s5, base address saved in $s6
■ Compiled MIPS code:
Loop: sll $t1, $s3, 2 #word:4B,*4
add $t1, $t1, $s6 #base+offset*4
lw $t0, 0($t1) #load save[i]
bne $t0, $s5, Exit # <> k ?
addi $s3, $s3, 1 # ==k, i += 1
j Loop
Exit: …

Chapter 2 — Instructions: Language of the Computer — 44

Basic Blocks
■ A basic block is a sequence of instructions
with
■ No embedded branches (except at end)
■ No branch targets (except at beginning)

■ A compiler identifies basic

blocks for optimization
■ An advanced processor
can accelerate execution
of basic blocks
Chapter 2 — Instructions: Language of the Computer — 45
MoreConditional Operations
■ Set on less than: slt
■ Set result to 1 if a condition is true
■ Otherwise, set to 0
31 26 25 21 20 16 15 11 10 6 5 0
SPECIAL rs rt rd 0 SLT
000000 00000 101010
6 5 5 5 5 6

■ slt rd, rs, rt

■ if (rs < rt) rd = 1; else rd = 0;
■ slti rt, rs, constant
■ if (rs < constant) rt = 1; else rt = 0;
■ Use in combination with beq, bne 🡺 blt
slt $t0, $s1, # if ($s1 < $s2) #
$s2 bne $t0, branch to L, ≠ 0
$zero, L Chapter 2 — Instructions: Language of the Computer — 46
Branch Instruction Design
■ Why not blt, bge, etc? (just beq, bne)
■ Pseudoinstruction
■ Hardware for <, ≥, … slower than =, ≠
■ Combining with branch involves more work per
instruction, requiring a slower clock
■ All instructions penalized!
■ beq and bne are the common case
■ Make the common case fast
■ This is a good design compromise
■ Good design demands good compromise

Chapter 2 — Instructions: Language of the Computer — 47

Addressing Mode
■ How the instructions identify the operand (or
operands) of each instruction
■ An addressing mode specifies how to calculate
the effective memory address of an operand by
using information held in registers and/or
constants contained within a machine instruction
or elsewhere.

Chapter 1 — Computer Abstractions and Technology — 48

Addressing Mode
Summary
1. ADDI rt, rs, immediate
addi $s1, $s2, 3

2. ADD rd, rs, rt

add $s1, $s2, $s3

3. LW rt, offset(base)
lw $s1, 20($s2)

4. BNE rs, rt, offset

bne $s1, $s2, 25

5. J target
j 2500

MIPS Addressing: Register operand, Immediate operand, Register + offset

Chapter 2 — Instructions: Language of the Computer — 49