VELAMMAL INSTITUTE OF TECHNOLOGY

Velammal Knowledge Park, Chennai-Kolkatta Highway, Ponneri, Thiruvallur 601204

Department of Mechatronics Engineering
Subject Code & Name : MR3391 – Digital Electronics and Microprocessor
Class : II Year Mechatronics Engineering
Academic Year : 2024-25 (Odd Semester)

PART A

1. What is an instruction format & list different instruction formats in 8085?

The size of an 8085 instruction is 1 to 3 bytes. Each instruction has one byte opcode. The remaining bytesare
either data or address. The format is as shown below
• One-byte instruction (opcode)
• Two-byte instruction (opcode with 8-bit data or address)
• Three-byte instruction (opcode with low byte data/address and high byte data/address).
2. Define addressing modes. And types of addressing modes are available in 8085?
Addressing modes refer to the different ways in which the operands (data or addresses) of an instruction can
be specified. In microprocessors, the addressing mode determines how the address of the operand is calculated
or accessed.
• Immediate Addressing Mode
• Register Addressing Mode
• Direct Addressing Mode
• Indirect Addressing Mode
• Implicit Addressing Mode
3. Write instructions to load the hexadecimal numbers 65H in register C, and 92H in accumulator A.
Display the number 65H at PORT0 and 92H at PORT1?
MVI C, 65H
MVI A, 92H
OUT PORT1;
MOV A, C
OUT PORT0;
HLT
4. Differentiate CALL instruction from JUMP instruction.
CALL is an instruction that transfers the program control to a sub routine with the intention of coming
back to the main program.
jA jump instruction just transfers control to a new place in memory, and continues from there, thus the
program counter is simply loaded with a new address.
5. How is PUSH B instruction executed? Find the status after the execution
This instruction decrements SP by one and copies the higher byte of the register pair into the memory location
pointed by SP. Then decrements the SP again by one and copies the lower byte of the register pair into the
memory location pointed by SP. Ex: SP=2000H, DE=1050H
SP 2000 SP 1FFE
B C 1FFH 1FFH 50
B C
D 10 E 50 1FFFH D 10 E 50 1FFFH 10
H L 2000H 2000H
H L
6. Mention the similarity and difference between compare and subtract instructions.
The compare and subtract instructions in the 8085 both subtract one operand from another, and set flags
accordingly. The subtract instruction stores the result in the accumulator, while the compare instruction does
not - except for the flags, the compare instruction "throws" the result away.
7. What is the function performed by SIM and RIM instruction?
SIM- Set Interrupt Mask: This instruction is used to mask the hardware interrupts RST 7.5, 6.5 and 5.5. The
execution of this instruction output the content of accumulator to program interrupt mask bits and also used
to output serial data on the SOD line.
RIM- Read Interrupt Mask: The RIM instruction is used to check whether an interrupt is masked or not. It is
also used to read data from the SID line.
8. Explain the functioning of CMP instruction.
CMP (Compare register or memory with accumulator A): The contents of the operand register or
memory are compared with the contents of the accumulator. Both contents are preserved. The results of the
comparison are shown by the setting the flags of the PSW as follows:
If (A) < reg/mem; carry flag is set.
If (A) = reg/mem; zero flag is set.
If (A) > reg/mem; carry and zero flags are reset
Eg: CMP B, CMP M
9. What is the function of rotate instructions?
Rotate instruction is used to rotate the accumulator content left to carry or right to carry. It can also be left
through carry or right through carry. One example is RLC which means rotate the accumulator content left
to carry. If the data 32H is given with a carry bit then after giving RLC for this, data becomes 64H and carry
of 00H.
10. Give the difference between JNC, JZ and JNZ.
Instruction Condition Flag Checked Description
JNC Jumps if no carry Carry flag = 0 Jumps if the carry flag is not set.
JZ Jumps if result is zero Zero flag = 1 Jumps if the result of the operation is zero.
JNZ Jumps if result is not zero Zero flag = 0 Jumps if the result of the operation is non-zero.

PART B & C

1. Tabulate the data transfer instruction with example

Instruction Mnemonic Description Example Explanation
Move MOV r1, Transfers data from register r2 MOV A, B Copies the contents of register
r2 to register r1. B into register A.
Move Immediate MVI r, data Loads immediate data into MVI C, 05H Loads the immediate value 05H
register r. into register C.
Load LDA addr Loads the accumulator with LDA 2500H Loads the accumulator with the
Accumulator the data from the memory data from memory location
Direct location specified by addr. 2500H.
Store STA addr Stores the contents of the STA 3000H Stores the contents of the
Accumulator accumulator in the memory accumulator in memory
Direct location specified by addr. location 3000H.
Load LDAX rp Loads the accumulator with LDAX B Loads the accumulator with the
Accumulator the contents of the memory data from the memory location
Indirect location pointed to by register pointed to by register pair BC.
pair rp (B, C) or (D, E).
Store STAX rp Stores the contents of the STAX D Stores the contents of the
Accumulator accumulator in the memory accumulator in the memory
Indirect location pointed to by register location pointed to by register
pair rp (B, C) or (D, E). pair DE.
Load HL Direct LHLD Loads H and L registers with LHLD 2400H Loads H with the contents of
addr the contents of the specified memory location 2401H and L
memory locations. with 2400H.
Store HL Direct SHLD addr Stores the contents of the H SHLD 3200H Stores the contents of L in
and L registers in the specified 3200H and H in 3201H.
memory locations.
Exchange XCHG Exchanges the contents of the XCHG If H = 20H, L = 30H, D = 40H,
H and L registers with the D and E = 50H, then after
and E registers. execution H = 40H, L = 50H, D
= 20H, E = 30H.
 Move to HL SPHL Copies the contents of the HL SPHL If HL = 2700H, after execution,
(SPHL) register pair to the stack SP = 2700H.
pointer.
Move to PCHL Loads the program counter PCHL If HL = 2500H, after execution,
Program with the contents of the HL PC = 2500H.
Counter (PCHL) register pair.
Exchange Stack XTHL Exchanges the contents of HL XTHL If SP = 3100H, and (3100H) =
register pair with the top of the 1234H, after execution HL =
stack. 1234H, and (3100H) will have
the old value of HL.
2. Tabulate the Arithmetic and Logical Instructions with example.
Arithmetic Instructions
Instruction Mnemonic Description Example Explanation
Add ADD r Adds the contents of register ADD B Adds the contents of register
r to the accumulator. B to the accumulator.
ADD M Adds the contents of the ADD M Adds the contents of the
memory location pointed to memory location addressed
by HL to the accumulator. by HL to the accumulator.
Add with Carry ADC r Adds the contents of register ADC D Adds the contents of register
r and the carry flag to the D and the carry flag to the
accumulator. accumulator.
ADC M Adds the contents of the ADC M Adds the contents of the
memory location pointed to memory location addressed
by HL and the carry flag to by HL and the carry flag to
the accumulator. the accumulator.
Add Immediate ADI data Adds immediate 8-bit data to ADI 12H Adds 12H to the contents of
the accumulator. the accumulator.
Add Immediate ACI data Adds immediate 8-bit data ACI 34H Adds 34H and the carry flag
with Carry and the carry flag to the to the contents of the
accumulator. accumulator.
Subtract SUB r Subtracts the contents of SUB C Subtracts the contents of
register r from the register C from the
accumulator. accumulator.
SUB M Subtracts the contents of the SUB M Subtracts the contents of the
memory location pointed to memory location addressed
by HL from the accumulator. by HL from the accumulator.
Subtract with SBB r Subtracts the contents of SBB E Subtracts the contents of
Borrow register r and the borrow flag register E and the borrow flag
from the accumulator. from the accumulator.
SBB M Subtracts the contents of the SBB M Subtracts the contents of the
memory location pointed to memory location addressed
by HL and the borrow flag by HL and the borrow flag
from the accumulator. from the accumulator.
Subtract SUI data Subtracts immediate 8-bit SUI 20H Subtracts 20H from the
Immediate data from the accumulator. contents of the accumulator.
Subtract SBI data Subtracts immediate 8-bit SBI 22H Subtracts 22H and the
Immediate with data and the borrow flag from borrow flag from the
Borrow the accumulator. contents of the accumulator.
Increment INR r Increments the contents of INR A Increments the contents of
register r by 1. register A by 1.
INR M Increments the contents of INR M Increments the contents of
the memory location pointed the memory location
to by HL by 1. addressed by HL by 1.
Decrement DCR r Decrements the contents of DCR B Decrements the contents of
register r by 1. register B by 1.
DCR M Decrements the contents of DCR M Decrements the contents of
the memory location pointed the memory location
to by HL by 1. addressed by HL by 1.
Increment INX rp Increments the contents of INX H Increments the contents of
Register Pair register pair rp by 1. the register pair HL by 1.
 Decrement DCX rp Decrements the contents of DCX D Decrements the contents of
Register Pair register pair rp by 1. the register pair DE by 1.
Double Add DAD rp Adds the contents of DAD B Adds the contents of register
register pair rp to the contents pair BC to register pair HL.
of the HL register pair.
Logical Instructions
Instruction Mnemonic Description Example Explanation
Logical AND ANA r Performs a bitwise AND ANA B ANDs the contents of register B with
operation between the contents the accumulator.
of register r and the
accumulator.
ANA M ANDs the contents of the ANA M ANDs the contents of the memory
memory location pointed to by location addressed by HL with the
HL with the accumulator. accumulator.
Logical AND ANI data Performs a bitwise AND ANI 0FH ANDs the immediate value 0FH with
with operation between immediate the accumulator.
Immediate data and the accumulator.
Logical OR ORA r Performs a bitwise OR ORA C ORs the contents of register C with the
operation between the contents accumulator.
of register r and the
accumulator.
ORA M ORs the contents of the ORA M ORs the contents of the memory
memory location pointed to by location addressed by HL with the
HL with the accumulator. accumulator.
Logical OR ORI data Performs a bitwise OR ORI ORs the immediate value 3CH with
with operation between immediate 3CH the accumulator.
Immediate data and the accumulator.
Logical XOR XRA r Performs a bitwise XOR XRA D XORs the contents of register D with
operation between the contents the accumulator.
of register r and the
accumulator.
XRA M XORs the contents of the XRA M XORs the contents of the memory
memory location pointed to by location addressed by HL with the
HL with the accumulator. accumulator.
Logical XOR XRI data Performs a bitwise XOR XRI 07H XORs the immediate value 07H with
with operation between immediate the accumulator.
Immediate data and the accumulator.
Compare CMP r Compares the contents of CMP A Compares the contents of register A
register r with the contents of with the accumulator (essentially a
the accumulator. subtraction without affecting
accumulator).
CMP M Compares the contents of the CMP M Compares the contents of the memory
memory location pointed to by location addressed by HL with the
HL with the accumulator. accumulator.
Compare with CPI data Compares immediate data with CPI 45H Compares the immediate value 45H
Immediate the contents of the with the accumulator.
accumulator.
Complement CMA Complements (inverts) CMA Inverts all bits in the accumulator (1’s
Accumulator each bit of the accumulator. complement).
Complement CMC Complements the carry CMC Complements the carry flag
Carry flag (if set, resets; if reset, sets). (toggles the carry).
Set Carry STC Sets the carry flag to 1. STC Sets the carry flag irrespective of its
previous state.
Rotate RLC Rotates the accumulator left RLC Rotates all bits in the accumulator one
Accumulator through the carry flag. bit left, with the carry flag storing the
Left leftmost bit.
Rotate RRC Rotates the accumulator right RRC Rotates all bits in the accumulator one
Accumulator through the carry flag. bit right, with the carry flag storing the
Right rightmost bit.
 Rotate Left RAL Rotates the accumulator left RAL Rotates all bits in the accumulator and
Through Carry through the carry flag (carry the carry flag one bit left.
included in the rotation).
Rotate Right RAR Rotates the accumulator right RAR Rotates all bits in the accumulator and
Through Carry through the carry flag (carry the carry flag one bit right.
included in the rotation).
3. Write an assembly language program to arrange array of elements in ascending order
START: LXI H, 8040H : Pointer to the IN-BUFFER
MVI D, 00H : The D register is used as a flag register
MOV C, M : Initialize reg. C with data count
DCR C : Set Reg. C for comparison count
INX H : Pointing to the next location
CHECK MOV A, M : Get the number
INX H : Go to next location
CMP M : Compare the contents of the current memory location with the contents of the
accumulator
JC NEXTBYT : If (A) < second byte, do not exchange
MOV B, M : Get second byte for exchange
MOV M, A : Store first byte in second location
DCX H : Point to first location
MOV M, B : Store second byte in first location
INX H : Get ready for next comparison
MVI D, 01H : Load 1 in D as a remainder for exchange
NEXTBYT DCR C : Decrement comparison count
JNZ CHECK : If comparison count not 0, go back
MOV A, D : Get flag bit in A
RRC : Place flag bit D0in carry
JC START : If flag is 1, exchange occurred
HLT : Terminate the program
Sample Input/Output
Input (8000H) = 05H Output (8000H) = 05H
(8001H) = 01H (8001H) = 01H
(8002H) = 21H (8002H) = 03H
(8003H) = 15H (8003H) = 15H
(8004H) = 03H (8004H) = 21H
(8005H) = 69H (8005H) = 69H
4. Write a program with a subroutine to add ten packed BCD numbers.
LXI H 8040H : Initialize pointer with the first location of IN-BUFFER
MVI C 0AH : Initialize counter with the number of data to be add
XRA A : Clear the contents of the accumulator and the Reg. B
MOV B, A
NEXTBCD: CALL BCDADD : A subroutine that add BCD numbers
INX H : Go to next location
DCR C : Decrement count until 0 is reached
JNZ NEXTBCD
STA 8060 H : Store the result byte available in A
MOV D, A : Temporarily D = A
MOV A, B : Putting B in A
STA 8061 H : To store it in OUT-BUFFER
MOV A, D : Restoring back A
LXI H 8062H : Initialize pointer with the last location of OUT-BUFFER
CALL UNPAK : A subroutine that separates two nibbles from a packed BCD
MOV A, B : Copy B to A
CALL UNPAK : A subroutine that separates two nibbles from a packed BCD
HLT : Terminate the program
BCDADD: ADD M : Add the contents of the memory location specified by the HL register pair
with A
DAA : Decimal adjust accumulator
RNC : If no carry is produced then return to the calling program
MOV D, A : Copy A to D
MOV A, B : If a carry is produced then adjust the contents of the Reg. B
ADI 01H
DAA
MOV B, A
MOV A, D : Copy D to A
RET : Return to the calling program
UNPAK: MOV D, A : Copy A to D
ANI 0FH : Mask off the most significant four bits
MOV M, A : Writing A to the memory
INX H : Go to next location
MOV A, D : Copy D to A
ANI F0H : Mask off the least significant four bits
RRC : Rotate accumulator 4 times to get the first BCD digit
RRC
RRC
RRC
MOV M, A : Writing A to the memory
INX H : Go to next location
RET : Return to the calling program

5. With neat diagram, explain the architecture of 8255 PPI.

The 8255 is a widely used, programmable, parallel I/O device. It can be programmed to transfer data under various
conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical and complex.
Features
• Three 8-bit IO ports PA, PB, PC
• PA can be set for Modes 0, 1, 2. PB for 0,1 and PC for mode 0 and for BSR. Modes 1 and 2 are interrupt driven.
• PC has 2 4-bit parts: PC upper (PCU) and PC lower (PCL), each can be set independently for I or O. Each PC
bit can be set/reset individually in BSR mode.
• PA and PCU are Group A (GA) and PB and PCL are Group B (GB)
• Address/data bus must be externally demultiplexed.
• TTL compatible.
• Improved dc driving capability.

• PA0 – PA7 – Pins of port A

• PB0 – PB7 – Pins of port B
• PC0 – PC7 – Pins of port C
• D0 – D7 – Data pins for the transfer of data
• RESET – Reset input
• RD’ – Read input
• WR’ – Write input
• CS’ – Chip select
• A1 and A0 – Address pins

Figure 5.2. 8255 Pin Diagram

Data Bus Buffer:
This tri-state bi-directional buffer is used to interface the internal data bus of 8255 Pin Diagram to the system
data bus. Input or Output instructions executed by the CPU either Read data from, or Write data into the buffer. Output
data from the CPU to the ports or control register, and input data to the CPU from the ports or status register are all
passed through the buffer.
Control Logic:
The control logic block accepts control bus signals as well as inputs from the address bus, and issues
commands to the individual group control blocks (Group A control and Group B control). It issues appropriate enabling
signals to access the required data/control words or status word. The input pins for the control logic section are described
here.
Group A and Group B Controls:
Each of the Group A and Group B control blocks receives control words from the CPU and issues appropriate
commands to the ports associated with it. The Group A control block controls Port A and PC7-PC4 while the Group B
control block controls Port B and PC3-PC0.
Port A : This has an 8-bit latched and buffered output and an 8-bit input latch. It can be programmed in three modes:
mode 0, mode 1 and mode 2.
Port B : This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be programmed in mode 0 and
mode 1.
Port C : This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C can be splitted into two parts
and each can be used as control signals for ports A and B in the handshake mode. It can be programmed for bit set/reset
operation.

Block Diagram of 8255

Port and register select signals summary

 6. Briefly explain various addressing modes of 8085 microprocessor with example.
Every instruction of a program has to operate on a data. The method of specifying the data to be operated by
the instruction is called Addressing. The 8085 has the following 5 different types of addressing.
• Immediate Addressing
• Direct Addressing
• Register Addressing
• Register Indirect Addressing
• Implicit Addressing
• Indexed Addressing
The addressing modes in the 8085 microprocessor define the way in which the operand (data) is specified within
an instruction. The operand can be a data value, a memory location, or a register. Here’s a brief overview of the different
addressing modes in the 8085 microprocessor:
1. Immediate Addressing Mode
• Description: In this mode, the operand is specified within the instruction itself.
• Example: MVI A, 32H
o Explanation: The immediate value 32H is moved directly into register A. The data (32H) is part of the
instruction.

2. Register Addressing Mode

• Description: The operand is located in one of the registers, and the instruction specifies the register name.
• Example: MOV B, C
o Explanation: The content of register C is moved to register B. Both operands are registers.

3. Direct Addressing Mode

• Description: The address of the operand (data in memory) is specified directly in the instruction.
• Example: LDA 2050H
o Explanation: The contents of memory location 2050H are loaded into the accumulator. The address is
directly specified in the instruction.

4. Register Indirect Addressing Mode

• Description: The address of the operand is specified by a register pair. The instruction does not contain the
address directly, but instead uses the content of a register pair to point to the memory location.
• Example: MOV A, M
o Explanation: The content of the memory location pointed to by the HL register pair is moved to the
accumulator A. Here, M refers to the memory location pointed to by the register pair HL.

5. Implicit Addressing Mode

• Description: The operand is implied within the instruction itself, meaning the instruction operates on the
accumulator or a specific register without needing to specify it.
• Example: CMA
o Explanation: The contents of the accumulator are complemented (all bits are inverted). The instruction
operates on the accumulator without explicitly stating it.

6. Indexed Addressing Mode

• Description: This mode involves modifying a base address using an index value. The base address is typically
stored in a register pair, and the final address is calculated by adding an offset (index) to the base address.
• Note: The 8085 does not explicitly support indexed addressing mode as found in more advanced
microprocessors, but similar effects can be achieved using register indirect addressing with increment or
decrement operations.