AN2867

Application note
Guidelines for oscillator design on STM8AF/AL/S
and STM32 MCUs/MPUs

Introduction
Many designers know oscillators based on Pierce-Gate topology (Pierce oscillators), but not
all of them really understand how they operate, and only a few master their design. In
practice, limited attention is paid to the oscillator design, until it is found that it does not
operate properly (usually when the final product is already in production). A crystal not
working as intended results in project delays, if not overall failure.
The oscillator must get the proper amount of attention during the design phase, well before
moving to manufacturing, to avoid the nightmare scenario of products failing in application.
This document introduces the Pierce oscillator basics, and provides guidelines for its
design. It also shows how to determine the external components, and provides guidelines
for correct PCB design and for selecting crystals and external components.
To speed up the application development, the recommended crystals (HSE and LSE) for the
products listed in Table 1 are detailed in Section 5: Recommended resonators for STM32
MCUs/MPUs and Section 6: Recommended crystals for STM8AF/AL/S MCUs.

Table 1. Applicable products

Type Product categories

STM8S series, STM8AF series and STM8AL series

STM32 32-bit Arm® Cortex® MCUs
Microcontrollers STM32 Wireless MCUs
STM32 Ultra Low Power MCUs
STM32 High Performance MCUs
Microprocessors STM32 Arm® Cortex® MPUs

January 2025 AN2867 Rev 23 1/59

www.st.com 1
Contents AN2867

Contents

1 Quartz crystal properties and model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Oscillator theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Negative resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Negative-resistance oscillator principles . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Pierce oscillator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1 Introduction to Pierce oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Feedback resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Oscillator transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5 Drive level and external resistor calculation . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Calculating the drive level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Another drive level measurement method . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.3 Calculating the external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.7 Crystal pullability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Safety factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8.2 Measurement methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8.3 Safety factor for STM32 and STM8 oscillators . . . . . . . . . . . . . . . . . . . 19
3.9 Oscillation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9.1 What are fundamental and overtone modes? . . . . . . . . . . . . . . . . . . . . 20
3.9.2 Third overtone mode: pros and cons . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.3 Considerations for crystals interfaced with STM32 products . . . . . . . . . 22

4 Guidelines to select a suitable crystal

and external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1 Low-speed oscillators embedded in STM32 MCUs/MPUs . . . . . . . . . . . . 23
4.2 How to select an STM32-compatible crystal . . . . . . . . . . . . . . . . . . . . . . 26

5 Recommended resonators for STM32 MCUs/MPUs . . . . . . . . . . . . . . 29

2/59 AN2867 Rev 23

AN2867 Contents

5.1 STM32-compatible high-speed resonators . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 STM32-compatible low-speed resonators . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Recommended crystals for STM8AF/AL/S MCUs . . . . . . . . . . . . . . . . 42

6.1 Part numbers of recommended crystal oscillators . . . . . . . . . . . . . . . . . . 42
6.2 Recommended ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7 Tips for improving oscillator stability . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7.1 PCB design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2 PCB design examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.3 Soldering guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.4 LSE sensitivity to PC13 activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

9 FAQs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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List of tables AN2867

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Example of equivalent circuit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Typical feedback resistor values for given frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Safety factor (Sf) for STM32 and STM8 oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. LSE oscillators embedded into STM32 MCUs/MPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. HSE oscillators embedded in STM32 MCUs/MPUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. Recommended crystal / MEMS resonators for the LSE oscillator in STM32 products . . . . 31
Table 8. KYOCERA compatible crystals (not exhaustive list). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. NDK compatible crystals (not exhaustive list). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. Recommended conditions (for consumer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 11. Recommended conditions (for CAN-BUS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4/59 AN2867 Rev 23

AN2867 List of figures

List of figures

Figure 1. Quartz crystal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Impedance in the frequency domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. I-V curve of a dipole showing a negative trans-resistance area . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Block diagram of a typical oscillation loop based on a crystal resonator . . . . . . . . . . . . . . 10
Figure 5. Pierce oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Inverter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Current drive measurement with a current probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Negative resistance measurement methodology description . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Fundamental and overtone frequencies of an AT-cut quartz crystal . . . . . . . . . . . . . . . . . 20
Figure 10. Quartz crystal theoretical model with third overtone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Oscillator implementation for third overtone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Classification of low-speed crystal resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Recommended layout for an oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. PCB with separated GND plane and guard ring around the oscillator . . . . . . . . . . . . . . . . 46
Figure 15. GND plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 16. Signals around the oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 17. Preliminary design (PCB design guidelines not respected) . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 18. Final design (following guidelines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 19. GND plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Top layer view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. PCB guidelines not respected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. PCB guidelines respected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

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Quartz crystal properties and model AN2867

1 Quartz crystal properties and model

A quartz crystal is a piezoelectric device converting electric energy into mechanical energy,
and vice versa. The transformation occurs at the resonant frequency. The quartz crystal can
be modeled as shown in Figure 1.

Figure 1. Quartz crystal model

C0

Q
Lm Rm Cm

MS36117V1

• C0 represents the shunt capacitance resulting from the capacitor formed by the
electrodes
• Lm (motional inductance) represents the vibrating mass of the crystal
• Cm (motional capacitance) represents the elasticity of the crystal
• Rm (motional resistance) represents the circuit losses
The impedance of the crystal (assuming that Rm is negligible) is

2
(1) j w × Lm × Cm – 1
Z = ---- × ------------------------------------------------------------------------------------------
w 2
( C0 + Cm ) – w × Lm × Cm × C0

Figure 2 shows the impedance in the frequency domain.

Figure 2. Impedance in the frequency domain

Impedance
Area of parallel
resonance: Fp
Inductive behavior:
the quartz oscillates

Fs Fa
Capacitive behavior: Frequency
no oscillation

Phase (deg)
+90

Frequency
–90
ai15834c

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AN2867 Quartz crystal properties and model

Fs is the series resonant frequency when Z = 0. Its expression can be deduced from
equation (1) as follows:

(2) F 1
= -----------------------------
s 2π L m C m

Fa is the antiresonant frequency when Z tends to infinity. Using equation (1), it is expressed
as follows:

(3) Cm
F a = F s 1 + ---------
C0

The region delimited by Fs and Fa (shaded area in Figure 2) is the area of parallel
resonance. In this region, the crystal operates in parallel resonance and behaves as an
inductance that adds an additional 180° phase to the loop. Its frequency Fp (or FL: load
frequency) has the following expression:

(4) ⎛ Cm ⎞
F = F ⎜ 1 + -----------------------------
-⎟
p s⎝ 2 ( C + C )⎠
0 L

According to this equation, the oscillation frequency of the crystal can be tuned by varying
the load capacitance CL. This is why, in their datasheets, crystal manufacturers indicate the
exact CL required to make the crystal oscillate at the nominal frequency.
Table 2 gives an example of equivalent crystal circuit component values for an 8 MHz
nominal frequency.

Table 2. Example of equivalent circuit parameters

Equivalent component Value

Rm 8Ω
Lm 14.7 mH
Cm 0.027 pF
C0 5.57 pF

Using equations (2), (3), and (4), it is possible to calculate Fs, Fa, and Fp of this crystal:
• Fs = 7988768 Hz
• Fa = 8008102 Hz
If the load capacitance CL is equal to 10 pF, the crystal oscillates at Fp = 7995695 Hz.
To have an oscillation frequency of exactly 8 MHz, CL must be 4.02 pF.

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58
Oscillator theory AN2867

2 Oscillator theory

Oscillators are among the backbone components of modern digital ICs. They can be
classified into different subfamilies, depending upon their topology and operating principles.
For each subfamily there is a mathematical model that can be used to study the oscillator
behavior, and theoretically determine its performance.
This section deals only with harmonic oscillators (relaxation oscillators are out of the scope
of this document), with particular focus (see Section 3) on Pierce oscillators. This is
because all the oscillators requiring external passive components (resonator, load
capacitors, etc.) covered by this document are of the previously mentioned type and
topology.
The harmonic oscillator family can be divided into two main subfamilies:
• negative-resistance oscillators
• positive-feedback oscillators.
These two subfamilies of oscillators are similar for what concerns the output waveform.
They deliver an oscillating waveform at the desired frequency. This waveform is typically
composed of a fundamental sine wave of the desired frequency, plus a sum of overtone
harmonics (at frequencies multiple of the fundamental one), due to the nonlinearity of
components of the oscillation loop.
The two subfamilies differ in their operating principles. A specific mathematical model
describes and analyzes each of them.
Positive-feedback oscillators are usually modeled using the Barkhausen model, where an
oscillator must fulfill the Barkhausen criterion to maintain a stable oscillation at the desired
frequency.
The Barkhausen model is not fully adequate to describe negative-resistance oscillators: the
most suitable approach is to use the negative-resistance model described in [1].
STM32 microcontrollers and microprocessors (based on Arm®(a) cores) feature low-speed
external (LSE) and high-speed external (HSE) oscillators designed according to the
negative-resistance principle, hence this section focuses on the presentation of this model.

2.1 Negative resistance

Theoretically speaking, a negative resistance is a dipole that absorbs heat and converting it
in electrical current, proportional to the applied voltage, but flowing in the opposite direction
(the opposite mechanism of an electrical resistance). In the real world, such a dipole does
not exist.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

8/59 AN2867 Rev 23

AN2867 Oscillator theory

The term negative resistance is a misnomer of negative transresistance, defined as the ratio
between a given voltage variation (∆V) and the induced current variation (∆I). Unlike the
resistance, always positive, the transresistance (also known as differential resistance) can
be either positive or negative. Figure 3 shows the current-voltage curve for a dipole with a
negative transresistance region. It is obvious that the V/I ratio is always positive, this is not
the case for the ∆V/∆I ratio.
The portion of the I-V curve in purple shows a negative transresistance:
ΔV V(D) – V(C)
-------- = --------------------------------- < 0
ΔI I(D) – I(C)

The portions in blue feature a positive transresistance:

ΔV V(B) – V(A)
-------- = -------------------------------- > 0
ΔI I(B) – I(A)

Figure 3. I-V curve of a dipole showing a negative trans-resistance area

2.2 Transconductance
Similarly to the conductance, defined as the inverse of the resistance, the transconductance
is defined as the inverse of the transresistance. Transconductance can also be defined as
the differential conductance, expressed as ∆I / ∆V.

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58
Oscillator theory AN2867

2.3 Negative-resistance oscillator principles

An oscillation loop is made of two branches (see Figure 4):
• The active branch, composed by the oscillator itself, provides the energy to make the
oscillation start and build up until it reaches a stable phase. When a stable oscillation is
reached, this branch provides the energy to compensate for the losses of the passive
branch.
• The passive branch is mainly composed by the resonator, the two load capacitors and
all the parasitic capacitances.

Figure 4. Block diagram of a typical oscillation loop based on a crystal resonator

Passive branch Active branch

Xtal

STM32
C

MSv36188V1

According to the small signals theory, when the active branch (oscillator part) is correctly
biased, to maintain a stable oscillation around the oscillator biasing voltage the latter must
have its transconductance equal to the passive branch conductance.
However, at startup, the oscillator transconductance must be higher than (multiple of) the
conductance of the passive part of the oscillation loop, to maximize the possibility to build up
the oscillation from the inherent noise of the loop. An excessive oscillator transconductance
compared to the oscillation loop passive branch conductance can saturate the oscillation
loop, and cause a startup failure.
To ensure the successful oscillator start, and to maintain stable oscillation, the ratio between
the negative resistance of the loop and the crystal maximal equivalent series resistance
(ESR) is specified for STM32 and STM8 products. It is recommended to have a ratio higher
than 5 for the HSE oscillators, and higher than 3 for the LSE oscillators.

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AN2867 Pierce oscillator design

3 Pierce oscillator design

This section describes the different parameters, and how to determine their values to be
compliant with the Pierce oscillator design.

3.1 Introduction to Pierce oscillators

Pierce oscillators are variants of Colpitts oscillators, widely used with crystal resonators. A
Pierce oscillator (see Figure 5) requires a reduced set of external components, this results
in a lower final design cost. In addition, the Pierce oscillator is known for its stable oscillation
frequency when paired with a crystal resonator, in particular a quartz-crystal resonator.

Figure 5. Pierce oscillator circuitry

Microcontroller
RF

In v

OSC_IN OSC_OUT

R Ext
Q

C L1 Cs C L2

ai15836b

• Inv: the internal inverter that works as an amplifier

• Q: crystal quartz or a ceramic resonator
• RF: internal feedback resistor
• RExt: external resistor to limit the inverter output current
• CL1 and CL2: are the two external load capacitances
• Cs: stray capacitance, sum of the device pin (OSC_IN and OSC_OUT) and the PCB (a
parasitic) capacitances.

3.2 Feedback resistor

In most MCUs/MPUs manufactured by ST, RF is embedded in the oscillator circuitry. Its role
is to make the inverter act as an amplifier. The feedback resistor is connected between Vin
and Vout to bias the amplifier at Vout = Vin, and force it to operate in the linear region (shaded

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58
Pierce oscillator design AN2867

area in Figure 6). The noise (for example, the thermal noise of the crystal) is amplified within
the range of serial to parallel frequency (Fa, Fp), thus starting the oscillation.

Figure 6. Inverter transfer function

Linear area: the inverter acts as an amplifier

Vout

VDD

Saturation Saturation
region region

Vin
~VDD/2 V DD

ai15837b

Table 3 provides typical values of RF.

Table 3. Typical feedback resistor values for given frequencies

Frequency Feedback resistor range

32.768 kHz 10 to 25 MΩ

1 MHz 5 to 10 MΩ

10 MHz 1 to 5 MΩ

20 MHz 470 kΩ to 5 MΩ

3.3 Load capacitance

The load capacitance is the terminal capacitance of the circuit connected to the crystal
oscillator. This value is determined by the external capacitors CL1 and CL2, and the stray
capacitance of the printed circuit board and connections (Cs). The CL value is specified by
the crystal manufacturer. For the frequency to be accurate, the oscillator circuit must show
the same load capacitance to the crystal as the one the crystal was adjusted for. Frequency
stability requires that the load capacitance be constant. The external capacitors CL1 and CL2
are used to tune the desired value of CL, to reach the value specified by the crystal
manufacturer.
The following equation gives the expression of CL:

C L1 × C L2
C L = -----------------------------
- + Cs
C L1 + C L2

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AN2867 Pierce oscillator design

For example, with CL = 15 pF and Cs = 5 pF ,

C L1 × C L2
C L – C s = ------------------------------ = 10 pF
C L1 + C L2

hence CL1 = CL2 = 20 pF.

3.4 Oscillator transconductance

Theoretically, to make the oscillation start and reach a stable phase, the oscillator must
provide sufficient gain to compensate for the loop losses and to provide the energy for the
oscillation buildup. When the oscillation becomes stable, the power provided to the oscillator
and the one it dissipates in the loop are equal.
Practically, because of tolerances on passive component values and their dependency upon
environmental parameters (such as temperature), the ratio between oscillator gain and
oscillation loop critical gain cannot just exceed 1. This would induce a too long oscillator
startup time, and even prevent the oscillator from starting up.
This section describes the two approaches that can be used to check if an STM32 oscillator
can be paired with a given resonator, to ensure that the oscillation is started and maintained
under the specified conditions for both resonator and oscillator. The approach depends on
how the oscillator parameters are specified in the device datasheet:
• If the oscillation loop maximum critical transconductance parameter (Gm_crit_max) is
specified, ensure that it is greater than the oscillation loop critical crystal gain (gmcrit,
see the formula below). Note that the maximum critical crystal transconductance can
be named either Gm_crit_max or Gm, depending on the STM32 product documentation.
• If the oscillator transconductance parameter (gm) is specified, make sure that the gain
margin ratio (gainmargin) is bigger than 5.
The gain margin ratio is determined by the formula gainmargin = gm / gmcrit, where
• gm is the oscillator transconductance specified in the STM32 datasheet. The HSE
oscillator transconductance is in the range of a dozen of mA/V, while the LSE oscillator
transconductance ranges from a few to a few dozens of µA/V, depending upon the
product.
• gmcrit is defined as the minimal transconductance required to maintain a stable
oscillation when it is a part of the oscillation loop for which this parameter is relevant.
gmcrit is computed from oscillation loop passive components parameters.
Assuming CL1 = CL2, and that the crystal sees the same CL on its pads as the value given
by the crystal manufacturer, gmcrit is expressed as follows:
2 2
g mcrit = 4 × ESR × ( 2πF ) × ( C 0 + C L )

where:
• ESR is the equivalent series resistance
• C0 is the crystal shunt capacitance
• CL is the crystal nominal load capacitance.
• F is the crystal nominal oscillation frequency

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Pierce oscillator design AN2867

For example, to design the oscillation loop for the HSE oscillator embedded in an STM32F1
microcontroller with a transconductance value (gm) of 25 mA/V, we choose a quartz crystal
from Fox, with the following characteristics:
• Frequency = 8 MHz
• C0 = 7 pF
• CL = 10 pF
• ESR = 80 Ω
To check if this crystal oscillates, let us calculate gmcrit:
6 2 – 12 – 12 2
g mcrit = 4 × 80 × ( 2 × π × 8 × 10 ) × ( 7 × 10 + 10 × 10 ) = 0.23 mA ⁄ V

Calculating the gain margin gives:

gm 25
gain m arg in = ----------------- = ----------- = 107
g mcrit 0.23

The gain margin is sufficient to start the oscillation and the gainmargin > 5 condition is met.
The oscillator is expected to reach stable oscillation after the typical delay specified in the
datasheet.
If an insufficient gain margin is found (gainmargin < 5), the oscillation can start when
designing and testing the final application, but this does not guarantee that the oscillation
starts in operating conditions. It is highly recommended that the selected crystal has a gain
margin higher than or equal to 5 (try to select a crystal with a lower ESR and/or a lower CL).
In a second example of the case where the maximal critical crystal transconductance is
given, the HSE oscillator embedded in STM32G0 microcontrollers has Gm = 1.5 mA/V. gmcrit
for the implemented oscillator must stay below this value. The Fox quartz crystal described
above respects this condition.
The conversion between the oscillator transconductance (gm) and the oscillation loop
maximal critical transconductance (Gm_crit_max) is given by Gm_crit_max = gm / 5.
Note: Before any verification, the crystal chosen must vibrate at a frequency that respects the
oscillator frequency range given in the STM32 datasheet.

3.5 Drive level and external resistor calculation

The drive level (DL) and external resistor value (RExt) are closely related, and are
addressed in the same section.

3.5.1 Calculating the drive level

The drive level is the power dissipated in the crystal. It must be limited, otherwise the quartz
crystal can fail because of excessive mechanical vibrations. The maximum drive level is
specified by the crystal manufacturer, usually in mW. Exceeding this value can lead to
crystal damage, or to a shorter device lifetime.

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2
The drive level is given by the formula: DL = ESR × I Q , where:
• ESR is the equivalent series resistor (specified by the crystal manufacturer):
C 2
ESR = R m × ⎛⎝ 1 + ------0-⎞⎠
C L

• IQ is the current flowing through the crystal in RMS. This current can be displayed on
an oscilloscope as a sine wave. The current value can be read as the peak-to-peak
value (IPP). When using a current probe (as shown in Figure 7), the voltage scale of an
oscilloscope may be converted into 1 mA / 1 mV.

Figure 7. Current drive measurement with a current probe

Crystal
To oscilloscope

Current probe

ai15838b

So, as described previously, when tuning the current with the potentiometer, the current
through the crystal (assuming it is sinusoidal) does not exceed IQmax RMS, given by:
DL max I Qmax PP
I Qmax RMS = ----------------- = -----------------------
-
ESR 2 2

Therefore, the current through the crystal (peak-to-peak value read on the oscilloscope)
should not exceed a maximum peak-to-peak (IQmaxPP) equal to:
2 × DL max
I Qmax PP = 2 × ---------------------------
-
ESR

Hence, the need for an external resistor RExt (refer to Section 3.5.3) when IQ exceeds
IQmaxPP. The addition of RExt becomes mandatory, and is added to ESR in the expression
of IQmax.

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3.5.2 Another drive level measurement method

The drive level can be computed as DL= I²QRMS × ESR (IQRMS is the RMS AC current).
This current can be calculated by measuring the voltage swing at the amplifier input with a
low-capacitance oscilloscope probe (no more than 1 pF). The amplifier input current is
negligible with respect to the current through CL1, so we can assume that the current
through the crystal is equal to the current flowing through CL1. Therefore, the RMS voltage
at this point is related to the RMS current by IQRMS = 2 π F x VRMS x Ctot, with:
• F = crystal frequency
V pp
• V RMS = ----------- , where Vpp is the peak-to-peak voltage measured at CL1 level
2 2
• Ctot = CL1 + (Cs / 2) + Cprobe where:
– CL1 is the external load capacitance at the amplifier input
– Cs is the stray capacitance
– Cprobe is the probe capacitance
2 2
ESR × ( π × F × C tot ) × ( V pp )
Therefore, DL = ----------------------------------------------------------------------------------------- .
2
This value must not exceed the drive level specified by the crystal manufacturer.
Note: Use special care when measuring voltage swing at LSE input, as it is very sensitive to load
capacitance. It is recommended to use a 0.1 pF input capacitance probe.

3.5.3 Calculating the external resistor

The role of this resistor is to limit the drive level of the crystal. With CL2, it forms a low-pass
filter that forces the oscillator to start at the fundamental frequency and not at overtones
(prevents the oscillator from vibrating at the odd harmonics of the fundamental frequency). If
the power dissipated in the crystal is higher than the value specified by the crystal
manufacturer, the external resistor RExt becomes mandatory to avoid overdriving the crystal.
If the power dissipated in the selected quartz is lower than the drive level specified by the
crystal manufacturer, the insertion of RExt is not recommended, and its value is then 0 Ω.
An initial estimation of RExt is obtained by considering the voltage divider formed by RExt
and CL2. Thus, the value of RExt is equal to the reactance of CL2.
Therefore, RExt = 1 / (2 π F CL2), and so, with an oscillation frequency of 8 MHz and
CL2 = 15 pF, we have RExt = 1326 Ω.
The recommended way for optimizing RExt is to first choose CL1 and CL2 as explained
before, and to connect a potentiometer in the place of RExt. The potentiometer should be
initially set to be approximately equal to the capacitive reactance of CL2. It should then be
adjusted as required, until an acceptable output and crystal drive level are obtained.
Caution: After calculating RExt, it is recommended to recalculate the gain margin (refer to Section 3.4)
to make sure that the addition of RExt has no effect on the oscillation condition. The value of
RExt must be added to ESR in the expression of gmcrit, and gm » gmcrit must also remain true:
gm » gmcrit = 4 × (ESR + RExt) × (2 π F)² × (C0 + CL)²
Note: If RExt is too low, there is a considerable increase of the power dissipation by the crystal. If,
on the other hand, RExt is too high, there is no oscillation.

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3.6 Startup time

This is the time required by the oscillation to start and then build up, until it reaches a stable
oscillation phase. The startup time depends, among other factors, on the Q-factor of the
resonator used. If the oscillator is paired with a quartz-crystal resonator characterized by its
high Q-factor, the startup time is higher when ceramic resonators are used (these are known
for their poor Q-factor, compared to quartz-crystal resonators). The startup time also
depends upon the external components, CL1 and CL2, and on the crystal frequency. The
higher the crystal nominal frequency, the lower the startup time. In addition, startup
problems usually arise because the gain margin is not properly dimensioned (as explained
previously). This is caused either by CL1 and CL2 being too small or too large, or by the ESR
being too high.
As an example, an oscillator paired with a few MHz nominal frequency crystal resonator
typically starts up after a delay of a few ms.
The startup time of a 32.768 kHz crystal ranges between 1 and 5 s.

3.7 Crystal pullability

Crystal pullabilty, also known as crystal sensitivity, measures the impact of small variations
of the load capacitance seen by the crystal on the oscillation frequency shifting. This
parameter has more importance when dealing with low-speed oscillators, as they are used
to clock time-keeping functions (such as real-time clock).
When the final application is still in the design stage, the influence of this parameter on the
low-speed oscillator accuracy (and consequently on all the time-keeping functions clocked
by this oscillator) is not obvious. This is because the designer fine tunes the load capacitors
until the desired oscillation frequency is obtained. When the design reaches production
stage it is frozen, and all the passive components including the load capacitors have their
values well defined. Any change of the load capacitance induces a shift of the oscillation
frequency.
Changes in the capacitive load (CL) seen by the crystal can be thought of as due to
inadequate operation environment, and only happening when the final design is not properly
operated. In practice, this is not true since changes of the load capacitance are rather
frequent and must be taken into account by the designer. The main contributors to the
capacitive load (CL) seen by the oscillator are
• the capacitance of the load capacitors CL1 and CL2
• the stray capacitance of the PCB paths
• the parasitic capacitance of the oscillator pins.
Any change on the capacitances listed above directly shifts the oscillation frequency. When
the design is in production stage, many of these capacitance values cannot be accurately
controlled. Selecting a crystal with low pullability limits the influence of such production
uncertainties on the final oscillation frequency accuracy.
Generally speaking, the higher the load capacitance of a crystal, the lower its pullability. As
an example, let us consider a crystal with a pullability of 45 PPM/pF. To fine-tune the
oscillation frequency, this crystal is loaded by two C0G ceramic capacitors (with a ± 5%
tolerance of their nominal value), CL1 and CL2, with the same 7 pF capacitance.
From the crystal point of view, the two load capacitors are mounted in series, which means
that their contribution to CL is (CL1 = CL2) / 2. The tolerance on their contribution to CL

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remains the same, and is equal to ± 5%. If we consider that all the remaining contributors to
the CL are maintained to their nominal values at design stage (to assess the frequency shift
magnitude induced only by load capacitor tolerances), then the load capacitance seen by
the crystal (CL) either decreases by 0.175 pF, or increases by the same value. This induces
an oscillation shift of:

0.175 pF × 45 PPM / pF = ~7.8 PPM (~0.7 s/day for a time-keeping function such as RTC)

The above example shows that lower pullability results in lower impact of small load
capacitance deviation on the frequency shifting. Crystal pullability is an important factor
when defining the final application PPM budget.
6
C m × 10
Pullability ( PPM ⁄ pF ) = -----------------------------------------
2
2 × ( C0 + CL )

where
• Cm is the crystal motional capacitance (in pF)
• C0 is the crystal shunt capacitance (in pF)
• CL is the crystal nominal load capacitance (in pF)
The following sections give a more detailed description on how to calibrate the oscillation
frequency, and how to estimate the final accuracy uncertainty (PPM) budget.

3.8 Safety factor

3.8.1 Definition
Resonators (such as crystal resonators) undergo aging effects that manifest themselves
over time in deviations of resonator parameters from the values defined by the
specifications. Among the impacted parameters there is the resonator ESR, whose value
depends upon the environment conditions, such as moisture and temperature. The
oscillator transconductance depends upon the power supply voltage and upon the
temperature.
The safety factor parameter enables to determine the oscillator safe operation under the
operating conditions and during the application life. It measures the ability of the oscillator
not to fail under operating conditions.
The safety factor is defined as the ratio between the oscillator negative resistance and its
ESR:

Oscillator negative resistance R ADD + Crystal ESR

S f = ------------------------------------------------------------------------------ = ---------------------------------------------------------
Crystal ESR Crystal ESR

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3.8.2 Measurement methodology

To measure the oscillator negative resistance, a resistance is added in series to the
resonator, as indicated in Figure 8.

Figure 8. Negative resistance measurement methodology description

STM32

Q RADD

CL1 CL2

MSv37268V1

The oscillator negative resistance is the value of the smallest series resistance RADD
preventing the oscillator from starting up successfully.
In practice, this value is set by conducting a series of experiments in which the value of the
series resistance is slightly increased compared to the previous experiment. The sequence
stops when the oscillator is unable to start correctly. The oscillator negative resistance is
equal to the value of the added series resistance.

3.8.3 Safety factor for STM32 and STM8 oscillators

Table 4 summarizes the safety factor (Sf) for oscillators embedded in STM32 and STM8
devices. For the LSE oscillator, the oscillation is considered safe for Sf ≥ 3, while for the
HSE oscillator this is true when Sf ≥ 5.

Table 4. Safety factor (Sf) for STM32 and STM8 oscillators(1)

Assurance level
Safety factor (Sf)
HSE LSE

Sf ≥ 5 Safe Very safe

3 ≤ Sf < 5 Safe
Not safe
Sf < 3 Not safe
1. Safe and very safe oscillations are shown in green, unsafe oscillation in yellow.

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3.9 Oscillation modes

3.9.1 What are fundamental and overtone modes?

Equation (4) gives the oscillation frequency Fp of a crystal, which depends on the series
resonant frequency Fs for which the crystal impedance is null. The oscillator is said to
operate in fundamental mode when vibrating around Fp.
Fs (and hence Fp) depend upon the parameters of the crystal theoretical model illustrated in
Figure 1. These parameters, given by the crystal manufacturer, define the frequency for
which the crystal is designed to oscillate around the fundamental frequency.
In real life, an AT-cut quartz crystal impedance reaches a zero value for several frequencies,
which correspond to the odd multiples of its fundamental vibration frequency. A crystal can
also vibrate around one of those odd multiples, these are the overtone oscillation modes.
Figure 9 represents the cancellation of an AT-cut crystal impedance for the fundamental
frequency, its following odd multiples (third and fifth overtones are represented), as well as
some spurious frequencies.

Figure 9. Fundamental and overtone frequencies of an AT-cut quartz crystal

Note: AT-cut quartz corresponds to most of the crystals to use with HSE. For LSE, tuning fork
crystals can be used, but they do not show the same oscillation mode possibilities (Figure 9
is not valid for them). In this part, we consider an AT-cut quartz crystal when referring to a
crystal.
This multiple-time cancellation is because a more accurate quartz crystal theoretical model
shows an RLC branch for each one of its overtone modes, as illustrated in Figure 10.

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Figure 10. Quartz crystal theoretical model with third overtone

C0

=
Lm Rm Cm
Q
Fundamental mode

Third overtone mode

Lm3OT Rm3OT Cm3OT
= Lm > Rm = Cm / 9 MS55485V2

For example, it is possible to use the third overtone mode by implementing the oscillator as
shown in Figure 11, to suppress the fundamental frequency (theoretically each overtone
mode can be selected by suppressing the previous ones).

Figure 11. Oscillator implementation for third overtone

Microcontroller RF

Inv

OSC_IN OSC_OUT

RExt
Q

CL1 LL1 CS CL2

MS55484V1

3.9.2 Third overtone mode: pros and cons

Because of the thickness, the crystals designed for a high frequency fundamental mode are
very expensive, requiring high-end cutting technologies and a lot of caution for
implementation. Practically, it becomes impossible to operate in fundamental mode for a
frequency above 50 MHz. This is why most of the high frequency crystals are designed to
work in the third overtone mode (it is possible to cut the crystal for a frequency three times
lower than the one it oscillates at).

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The model for a crystal operating in third overtone mode (Figure 11) shows a resistance Rm
approximately three times higher and a capacitance Cm nine times lower than those
associated with the fundamental mode.
For the third overtone mode, these differences mean a higher Q-factor since the quality
factor for an RC series circuit is 1 / ωRC (less energy loss, more stable performances, better
jitter, and lower pullability, see Section 3.7). A lower pullability means a lower frequency shift
when the application is deployed in the field, at the expense of lower tunability of the
oscillation frequency.

3.9.3 Considerations for crystals interfaced with STM32 products

The oscillators integrated in the STM32 products have been validated for use in the
fundamental mode, respecting the implementation of Figure 5. If a third overtone crystal is
used with this implementation, the theory indicates that it does not start vibrating at the third
harmonic frequency, but at the fundamental one.
Note: The startup mode of an oscillator can even involuntarily balance between the two modes if
its external components have not been chosen according to what indicated in this
document.

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4 Guidelines to select a suitable crystal

and external components

4.1 Low-speed oscillators embedded in STM32 MCUs/MPUs

The low-speed resonator market provides a wide range of crystal resonators. Selecting the
most adequate one for a given design depends on many parameters. The most important
parameters to be taken into account (only technical factors are listed) are:
• Crystal size or footprint
• Crystal load capacitance (CL)
• Oscillation frequency offset (PPM)
• Startup time
A trade-off between the above parameters must be found, depending on the key design
criteria. Figure 12 shows that the resonators available on the market can be divided into two
categories, depending upon the above-mentioned factors and trade-offs.

Figure 12. Classification of low-speed crystal resonators

High
Crystal load capacitance

(12.5 pF)
Low drift

Incresed robustness against noisy

environments
Medium
(7 pF)

Low power

Low
(”S)
Low Medium High

LSE drive level / Gm_crit_max

MSv36189V3

A resonator with a relatively high load-capacitance (such as 12.5 pF) requires more power
for the oscillator to drive the oscillation loop at the resonator nominal frequency. Designs
targeting low power consumption (for example, RTC application powered by coin-batteries
requiring very long autonomy) are consequently more likely to use resonators with relatively
small load capacitance. On the other side, big load capacitance resonators have a much
smaller pullabilty compared to resonators with small load capacitance. As a result, designs
without severe constraints on power consumption tend to use big load capacitance crystals
to reduce pullability.
One of the key areas where crystal resonators are massively used is the hand-held and
wearable appliance consumer market (such as smartphones, Bluetooth® kits). For this

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market segment, the crystal size is of critical importance. However, it is widely known that
small-footprint crystals come with high crystal ESR. The choice may be harder if the target
design has severe constraints in terms of power consumption (the usual scenario). In this
case, choose a crystal with a load capacitance as small as possible to optimize power
consumption even if this compromises pullabilty. In addition, crystals with high ESR may
have a slightly longer startup time. If there are no constraints on crystal size, then it is
recommended to choose a crystal with the smallest possible ESR.
In noisy environments (almost always the case for industrial applications), if there are no
constraints on power consumption, it is recommended to choose crystals with high load
capacitance. These crystals require a high-drive current from the oscillator, but are more
robust against noise and external perturbations. Another advantage is that the design
pullability is minimized.
Depending on the device used, all the resonator families listed below can be compatible
with your design, or only some of them. STM32 devices embed two types of low-speed
oscillator (LSE):
• Constant gain
This type of LSE oscillator features a constant gain, which makes them compatible only
with a few crystal groups mentioned above. For example, LSE oscillators embedded in
STM32F2 and STM32L1 MCUs target designs with severe power consumption
constraints. The selected crystal should consequently have a low load capacitance and
a moderate ESR. LSE oscillators embedded in STM32F1 MCUs target crystal
resonators with moderate ESR and moderate load capacitance.
• Configurable gain
The main advantage of LSE oscillators belonging to this family is the compatibility with
a large number of crystals. Almost no constraint comes by the device embedding this
kind of oscillator. The large list of compatible resonator crystals allows the designer to
focus on design constraints (such as power consumption, footprint) when selecting a
compatible resonator. These oscillators are divided into two categories:
– Dynamically (on-the-fly) modifiable gain LSE oscillators
The gain of this type of LSE oscillators can be changed either before starting the
oscillator or after enabling it.
– Statically modifiable gain LSE oscillators
The gain can be changed only when the LSE oscillator is turned off. If the
oscillator transconductance has to be increased or decreased, the LSE must be
turned off first.
Table 5 gives the list of low-speed oscillators (LSE) embedded in STM32 devices.
Caution: When the gain is modified statically or on-the-fly, the calibration of the oscillation frequency
must be readjusted to estimate the final accuracy uncertainty (PPM) budget.
Caution: In STM32F0 and STM32F3 MCUs, High drive mode (gm = 25 µA/V) must be used only with
12.5 pF crystals, to avoid saturating the oscillation loop and causing a startup failure. When
used with a low CL crystal (for example 6 pF), the oscillation frequency jitters and duty cycle
can be distorted.

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Table 5. LSE oscillators embedded into STM32 MCUs/MPUs(1)

Series Drive level gm (min) Gm_crit_max Unit

Medium high 8.5 1.7

C0
High 13.5 2.7
Low 5 1.0
µA/V
Medium low 8 1.6
F0, F3
Medium high 15 3
High 25 5
F1, T 5 1
Not available µA/V
F2, F4_g1(2) 2.8 0.56
Low 2.8 0.56
F4_g2(3) µA/V
High 7.5 1.5
Low 2.4 0.48
Medium low 3.75 0.75
F7 µA/V
Medium high 8.5 1.7
High 13.5 2.7
L1 Not available 3 0.6 µA/V

G0, G4 Low 2.5 0.5

H7
L0, L4, L4+, L5 Medium low 3.75 0.75
MP1, MP2
N6 Medium high 8.5 1.7
U0, U3, U5(4) µA/V
WB, WB0, WBA(5), WL High 13.5 2.7

Medium low 3.75 0.75

H5 Medium high 8.5 1.7
High 13.5 2.7
1. Color code:
- Light blue: LSE oscillators with transconductance modifiable on the fly (dynamically)
- Yellow: LSE oscillators with non-modifiable transconductance
- Gray: LSE oscillators with statically-modifiable transconductance
2. STM32F4 series with LSE generation 1 (STM32F401/405/407/415/417/427/429/437/439xx MCUs
featuring LSE oscillators with non modifiable transconductance).
3. STM32F4 series with LSE generation 2 (STM32F410/411/412/413/423/446/469/479xx MCUs featuring
LSE oscillators with statically modifiable transconductance).
4. STM32U575/585 rev. X devices do not support low drive mode.
5. STM32WBA devices do not support low drive mode.

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4.2 How to select an STM32-compatible crystal

This section describes the procedure recommended to select suitable crystal/external
components. The procedure is based on the following steps:

Step 0: Choose a fundamental mode designed resonator

Choose a fundamental mode designed resonator (as explained in Section 3.9, the STM32
oscillators are validated to work with resonator vibrating in fundamental mode and while
using the Pierce oscillator circuitry presented in Figure 5), and make sure that the resonator
chosen is designed to work in fundamental mode.

Step 1: Check the resonator compatibility with the selected STM32

To check the compatibility between the selected crystal and the STM32 MCU/MPU, first
identify the procedure to follow among the two described in Section 3.4. The decision must
be made based on the oscillator specification provided in the datasheet.
• If the oscillator transconductance parameter is specified, then apply the second
procedure. Ensure that the gain margin ratio is higher than five (x5) to make sure that
the crystal is compatible with the selected STM32 part.
• If Gm_crit_max is specified instead, make sure that gmcrit for the oscillation loop is
smaller than the specified Gm_crit_max value.

Step 2: Determine the capacitance value of the load capacitors CL1 and CL2
To determine the correct capacitance values for CL1 and CL2 load capacitors, apply the
formula specified in Section 3.3. The values obtained are approximations of the exact
capacitances to be used. In a second phase, to fine-tune the values of the load capacitors,
go through a series of experimental iterations, until the right capacitance values are found.
During the experimental phase, use a standard crystal, one whose PPM drift is well known
when it is loaded by the crystal nominal load capacitance (CL). This kind of crystal can be
provided by the manufacturer upon request. After this crystal has been chosen, calculate its
oscillation frequency (Fstandard) when the crystal is loaded by its nominal load capacitance.
This frequency is given by the formula:
6
F = F × ⎛ PPM ⁄ 10 ⎞
s tan dard nominal ⎝ s tan dard ⎠

where:
• Fstandard is the standard crystal oscillation frequency when it is loaded by its nominal
load capacitance
• Fnominal is the oscillation nominal frequency specified in the crystal datasheet
• PPMstandard is the oscillation frequency drift of the standard crystal, as characterized by
the crystal manufacturer

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When Fstandard is computed, go through the following sequence:

1. Make the first experimental iteration with CL1 and CL2 capacitance values determined
by calculation:
– If the oscillation frequency is equal to Fstandard, CL1 and CL2 are the correct
capacitances. The user can therefore skip substeps 2 and 3.
– If the oscillation frequency is slower than Fstandard go to substep 2, otherwise
execute substep 3.
2. For this experimental iteration, decrease CL1 and CL2 capacitance values, measure
again the oscillation frequency, and compare it to Fstandard:
– If the oscillation frequency is slower than Fstandard, execute substep 2, otherwise
execute substep 3.
– If the oscillation frequency is almost equal to Fstandard, use the latter CL1 and CL2
capacitance values.
3. For this experimental iteration, increase CL1 and CL2 capacitance values, measure
again the oscillation frequency, and compare it to Fstandard:
– If the oscillation frequency is slower than Fstandard, execute substep 2, otherwise
execute substep 3.
– If the oscillation frequency is almost equal to Fstandard, use the latter CL1 and CL2
capacitance values.

Step 3: Check the safety factor of the oscillation loop

The safety factor must be assessed as described in Section 3.8 to ensure a safe oscillation
of the oscillator under operating conditions.
Note: Many crystal manufacturers can check device/crystal pairing compatibility upon request. If
the pairing is judged valid, they can provide a report including the recommended CL1 and
CL2 values, as well as the oscillator negative resistance measurement. In this case steps 2
and 3 can be skipped.

Step 4: Calculate the drive level and external resistor

Compute the drive level (DL) (see Section 3.5) and check if it is greater or lower than
DLcrystal:
• If DL < DLcrystal, no need for an external resistor (a suitable crystal has been found).
• If DL > DLcrystal, the user should calculate RExt to have: DL < DLcrystal. The user should
then recalculate the gain margin taking RExt into account.
If gain margin > 5, a suitable crystal has been found. If not, then this crystal does not
work, another one must be chosen. Return to Step 1: Check the resonator compatibility
with the selected STM32 to run the procedure for the new crystal.

Step 5 (optional): Calculate the PPM accuracy budget

Use the following formula to estimate the PPM accuracy budget for the application:

PPM Budget = PPM crystal + Deviation ( C L ) × Pullability crystal

where:
• PPMBudget is the estimated accuracy for the oscillation frequency
• PPMcrystal is the crystal PPM accuracy specified in the datasheet

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Deviation (CL) is expressed in pF. It measures the deviation of the load capacitance (CL)
due to tolerances on load capacitor values and the variation of the stray capacitance (CS)
due to PCB manufacturing process deviation.
Pullabilty is expressed in PPM / pF (refer to Section 3.7).
Note: The PPM budget calculated above does not take into account the temperature variation,
which can make the PPM budget bigger.

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5 Recommended resonators for STM32 MCUs/MPUs

5.1 STM32-compatible high-speed resonators

The high-speed oscillator (HSE) embedded into STM32 products(a) is compatible with
almost all the resonators available on the market. The recommended resonators are
provided by a wide range of manufacturers, including:
• ABRACON
• ECS (www.ecsxtal.com)
• EPSON (http://www5.epsondevice.com)
• KYOCERA
• Micro Crystal
• muRata (www.murata.com)
• NDK (http://www.ndk.com)
• RIVER (http://www.river-ele.co.jp)
Several tools are available to select the more recent and high-demand crystals, among
them the STM32 Crystal Selection Tool from ECS, and the IC Matching Information
provided by NDK.
Compatible resonators come with various frequencies and technologies (ceramic
resonators and quartz-crystal resonators working in fundamental mode are all compatible
with the HSE oscillator embedded in STM32 MCUs/MPUs). Table 6 summarizes the
supported frequency ranges.

Table 6. HSE oscillators embedded in STM32 MCUs/MPUs

C0
L4, L4+
L5 H5
F0 F1
Series F2 F4 F7 L0 L1 H7 U3 MP2 N6 Unit
F3 T
G0, G4 U5
MP1
U0

Frequency
4 - 32 4 - 16 4 - 25 4 - 26 4 - 26 1 - 25 1 - 24 4 - 48 4 - 50 16 - 48 16 - 48 MHz
range
gm (min) 10 25 5 5 5 3.5 3.5 7.5 7.5 12.5 9.57
mA/V
Gm_crit_max 2 5 1 1 1 0.7 0.7 1.5 1.5 2.5 1.95

5.2 STM32-compatible low-speed resonators

Table 7 contains a not exhaustive list (only the compatible resonator part numbers checked
by ST are included) of low-speed quartz-crystal 32.768 kHz resonators that are either
compatible with the whole STM32 portfolio, or with a subset.

a. This is not applicable for STM32WB, STM32WB0, STM32WBA and STM32WL series due to the RF
constraints. For information about HSE oscillator compatibility with these devices, refer to Precise HSE
frequency and startup time tuning for STM32 wireless MCUs (AN5042), available on www.st.com.

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Different footprints are provided to facilitate crystal selection, even if there are geometric
constraints for the final application.

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