DR.

BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE

Regular & Supplementary Summer Examination – 2023
Course: B. Tech. Branch : Electrical Engineering
Semester : IV
Subject Code & Name: Analog & Digital Electronics (BTBS404)
Max Marks: 60 Date:26/07/23 Duration: 3 Hr.
Instructions to the Students:
1. All the questions are compulsory.
2. The level of question/expected answer as per OBE or the Course Outcome (CO) on
which the question is based is mentioned in ( ) in front of the question.
3. Use of non-programmable scientific calculators is allowed.
4. Assume suitable data wherever necessary and mention it clearly.
(Level/CO) Marks
Q. 1 Solve Any Two of the following. 12
A) Explain the h-parameter model of CE amplifier & state the typical CO1 6
values of h-parameter for the same.
B) Draw two stage RC coupled amplifier explain its working? CO1 6
C) How transistor its used as an amplifier. Prove it? CO1 6

Q.2 Solve Any Two of the following. 12

A) Draw and explain the differential amplifier with three OP-AMP ? CO2 6
B) Draw & explain the voltage follower using OP-AMP? CO2 6
C) State the De-Morgan’s first & second theorem prove it? CO3 6

Q. 3 Solve Any Two of the following. 12

A) Convert the following decimal number into binary, octal, hexadecimal CO3 6
and BCD equivalent (120)10 ?
B) With sketch realize the expression Y= AB + CD by CO3 6
1. NAND Gate only
2. NOR Gate only
C) Perform following BCD subtraction using 10’s complement method. CO3 6
3. (28)10 – (16)10
4. (12)10 – (32)10

Q.4 Solve Any Two of the following. 12

A) Draw the circuit of a TTL NAND gate and explain its working? CO4 6
B) Draw the divide by 7 asynchronous UP counter using T flip-flop. CO4 6
Write truth table draw the timing diagram?
 C) Draw the block diagram & circuit of SIPO shift register and explain CO4 6
its working.
Q. 5 Solve Any Two of the following. 12
A) Minimize the following expression and realize using basic gates CO5 6
Y = ∑ m (0,2,5,6,7,8,10,13,15)
B) State working principle of de-multiplexer. Explain 1 to 8 line CO5 6
demultiplexer with a neat diagram.?
C) Draw a block diagram of full adder. Write a truth table. Draw logic CO5 6
diagram of it?
*** End ***
The grid and the borders of the table will be hidden before final printing.
 DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Supplementary Winter Examination – 2023
Course: B. Tech. Branch: Electrical Engineering/Electrical & Electronics
Engg./Electrical Engineering (Electrical and Power)
Semester: 4th
Subject Code & Name: BTBS404E_Y19 Analog and Digital Electronics
Max Marks: 60 Date:23-01-2024 Duration: 3 Hr.
Instructions to the Students:
1. All the questions are compulsory.
2. The level of question/expected answer as per OBE or the Course Outcome (CO)
on which the question is based is mentioned in ( ) in front of the question.
3. Use of non-programmable scientific calculators is allowed.
4. Assume suitable data wherever necessary and mention it clearly.
(Level Marks
/CO)
Q. 1 Solve Any Two of the following. 12
A) Define (i) Input Offset Voltage (ii) Input Bias Current (iii) Input impedance CO2 6
B) Illustrate the working of operational amplifier with the help of block diagram. Explain CO2 6
each stage in brief ?
C) Explain the OP-Amp as adder and integrator? CO2 6

Q.2 Solve Any Two of the following. 12

A) Explain frequency response curve in detail? CO1 6
B) Explain cascading of amplifiers with suitable diagram? CO1 6
C) Compare the CB,CE,CC Configuration ? CO1 6

Q. 3 Solve Any Two of the following. 12

A) Define Universal Gates. Implement using universal gates (i) AND gate (ii) OR gate. CO3 6
B) Use 1's complement method to solve the following (101110)2 - (10110)2 and (52)10- CO3 6
(32)10
C) Illustrate in brief working of TTL NAND gate CO3 6

Q.4 Solve Any Two of the following. 12

A) Explain operation of full Subtractor. CO4 6
B) Implement a 4-bit Parallel In Serial Out shift register using D Flip Flops CO4 6
C) Compare combinational circuit and sequential circuit CO4 6
Q. 5 Solve Any Two of the following. 12
A) Simplify the following function using F(A,B,C,D)= ∑m(3,9,10,11,13,14,15) + ∑d CO5 6
(1,6,7) K-Map
B) Explain Serial in Serial out shift register with waveforms CO5 6
C) Design 3-bit ripple binary counter using J-K flip-flop. CO5 6
*** End ***
 DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Supplementary Examination – Winter 2023
Course: B. Tech Branch: Electrical Semester: IV
Subject Code & Name: Analog and Digital Electronics (BTEEE406B_Y19)
Max Marks: 60 Date:29-01-24 Duration: 3 Hrs.
Instructions to the Students:
1. All the questions are compulsory.
2. Use of non-programmable scientific calculators is allowed.
3. Assume suitable data wherever necessary and mention it clearly.
Marks
Q. 1 Solve Any Two of the following.
A) Explain small signal low frequency h-parameter model of transistor amplifiers and also 06
define h-parameters.
B) Determine h-parameters from input and output characteristics of common base 06
transistor.
C) Explain RC coupled amplifier with its circuit diagram 06

Q.2 Solve Any Two of the following.

A) Draw and explain non-inverting amplifier with output equation. 06
B) With a neat circuit diagram show that an Op-Amp could be used as a summer. 06
C) Explain Op-Amp as a differentiator with neat circuit diagram and necessary equations. 06

Q. 3 Solve Any Two of the following.

A) Convert the following numbers: 06
a) (0.1101)2 = ( ? )10
b) (12.4)10 = ( ? )8
c) (FF12)16 = ( ? )10
B) Explain all logic gates with their symbols and truth tables. 06
C) Prove the following De Morgan’s theorems: 06
a) 𝑨𝑩 + 𝑪𝑫 = 𝑨𝑩. 𝑪𝑫
b) (𝑨 + 𝑩). (𝑪 + 𝑫) = (𝑨 + 𝑩) + (𝑪 + 𝑫)

Q.4 Solve Any Two of the following.

A) What are different operational properties of logic family? Explain any 3 properties in 06
detail.
B) Draw and explain 2-input NMOS NAND and NOR logic gates. 06
C) Design an S-R latch using 2-inputs NOR gates. 06

Q. 5 Solve Any Two of the following.

A) Minimize the following expression using K-maps and realize using NOR gates only. 06
𝑓 (𝐴, 𝐵, 𝐶, 𝐷) = 𝜋𝑀(1,2,3,5,6,7,9,10,11,13,14,15)
B) Explain half adder circuit with the truth table. 06
C) Minimize the following logic functions and realize using NAND/NOR gates. 06

𝒇𝟏 (𝑨, 𝑩, 𝑪, 𝑫) = 𝒎 (𝟏, 𝟑, 𝟓, 𝟖, 𝟗, 𝟏𝟏, 𝟏𝟓) + 𝒅(𝟐, 𝟏𝟑)

*** End ***

 DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Supplementary Summer 2024
Course: B. Tech Branch: Electrical Engineering and Allied Semester: IV
Subject Code & Name: Analog and Digital Electronics (BTBS404E_Y19)
Max Marks: 60 Date: 20/06/2024 Duration: 3 Hrs.
Instructions to the Students:
1. All the questions are compulsory.
2. Use of non-programmable scientific calculators is allowed.
3. Assume suitable data wherever necessary and mention it clearly.
Marks
Q. 1 Solve Any Two of the following.
A) What do you mean by frequency response curve? Draw the nature of curve and define 06
upper and lower corner frequencies.
B) Determine h-parameters from input and output characteristics of common base 06
transistor.
C) Explain RC coupled amplifier with its circuit diagram 06

Q.2 Solve Any Two of the following.

A) Illustrate the working of operational amplifier with the help of block diagram. Explain 06
each stage in brief.
B) Explain characteristics of an ideal Op-amp.. 06
C) Explain Op-Amp as a differentiator with neat circuit diagram and necessary equations. 06

Q. 3 Solve Any Two of the following.

A) Convert the following numbers: 06
a) (111001.1101)2 = ( ? )10
b) (75.25)10 = ( ? )8
c) (57.75)8 = ( ? )10
B) Explain all logic gates with their symbols and truth tables. 06
C) Subtract following numbers using 2’s compliment method. 06
i) (15)10 – (10)10 ii) (0110)2 – (1000)2

Q.4 Solve Any Two of the following.

A) Compare TTL with CMOS Logic families. 06
B) State difference between combinational logic and sequential logic digital circuits. Give 06
its examples.
C) Design an S-R latch using 2-inputs NOR gates. 06

Q. 5 Solve Any Two of the following.

A) Compare Half adder and Full adder in detail. Explain design of Half adder using 1 Ex or 06
and 1 AND gate for Sum and Carry.
B) Implement following function using 4:1 multiplexer. F(X,Y,Z) = X’Y’Z + X’YZ’ + 06
XYZ’ + XYZ
C) What do you mean by counters State types of counters and list its applications? 06
*** End ***
 DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE
Regular and Supplementary Summer 2024
Course: B. Tech Branch: Electrical Engineering and Allied Semester: IV
Subject Code & Name: Analog and Digital Electronics BTBS404
Max Marks: 60 Date: 20/06/2024 Duration: 3 Hrs.
Instructions to the Students:
1. All the questions are compulsory.
2. Use of non-programmable scientific calculators is allowed.
3. Assume suitable data wherever necessary and mention it clearly.
Marks
Q. 1 Solve Any Two of the following.
A) Explain the various operations of regions of a transistor in CE configuration on its 06
output characteristics.
B) What are different methods of transistor biasing? Explain any one in detail. 06
C) The h parameters of a transistor used in a single stage amplifier circuit are h ic = 1100, 06
hrc = 1, hfc = -51, hoc = 25µA. Determine the amplifier parameters for CC configuration
when Rs = RL = 10 k .

Q.2 Solve Any Two of the following.

A) What are various characteristics of an ideal Op-Amp? Discuss in details. 06
B) Draw the block diagram of an Op-amp and explain the purpose of using each block. 06
C) Explain Op-Amp as a differentiator with neat circuit diagram and necessary equations. 06

Q. 3 Solve Any Two of the following.

A) Convert the following numbers: 06
a) (1101101.101)2 = ( ? )10
b) (126.75)10 = ( ? )8
c) (375.75)10 = ( ? )16
B) Solve the following arithmetic operations 06
a) Subtract (15)10 from (10)10
b) Subtract (14)10 from (18)10 using 1 s compliment method of binary subtraction.
C) Explain all logic gates with their symbols, output expression and truth table. 06

Q.4 Solve Any Two of the following.

A) Explain TTL NAND gate circuit (Totem Pole Arrangement) with the help of circuit 06
diagram.
B) What is meant by MOS logic family? Explain working of NAND gate by NMOS logic. 06
C) Explain J-K flip-flop with circuit diagram and truth table. 06

Q. 5 Solve Any Two of the following.

A) m (0,1,2,3,5,7,8,9,11,14) using K-map. 06
B) Explain half adder circuit with the truth table. 06
C) Reduce the expression for f 06

*** End ***