EXPT.NO.

1 VOLTAGE SERIES FEEDBACK AMPLIFIER

DATE:

AIM:
To construct and test the Voltage Series feedback amplifier and to calculate the following parameters.
1. Bandwidth and cut-off frequencies.
2. Input and output impedance.

APPARATUS REQUIRED:

S.No EQUIPME RANGE QUANTITY

NTS
1 AFO (0-3)MHz 1
2 CRO (0-20)MHz 1
3 Resistors As per Design Each one
4 Dual Power(0-30V) 1
supply
5 Op-amp μA741 1
6 Bread Board 1
7 Connecting wires Required Quantity

THEORY:
The current series feedback amplifier is characterized by having shunt sampling and series mixing.
In amplifiers, there is a sampling network, which samples the output and gives to the feedback network.
The feedback signal is mixed with input signal by either shunt or series mixing technique. Due to shunt
sampling the output resistance increases by a factor of ‘D’ and the input resistance is also increased by
the same factor due to series mixing. This is basically trans conductance amplifier. Its input is voltage
which is amplified as current.

PIN DIAGRAM

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2 |Pa g e
CIRCUITDIAGRAM

7
6

DESIGN:

Given values, Av=10(Theoretica lvalue)

Assume, Rf=10KΩ;formula: Av=1+(Rf/R1)
=>R1=Rf/(1-Av)=1KΩ WAVE

WAVEFORM

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PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Keeping the input voltage constant, vary the frequency from 500Hz to 3MHz in regular
steps and note down the corresponding output voltage.
3. Plot the graph :Gain(dB)Vs Frequency
4. Calculate the bandwidth from the graph.
5. To measure the Input and Output current, connect ammeter in μA range and mA range in series
with Input resistance and Load resistance respectively. Measure input current (Ii) and output current
(Io)by keeping Vi and Frequency of input signal a constant value.

OBSERVATIONS:

Vi=1.15V
Frequency Output Voltage(V0) Gain=20log(V0/Vi) (dB)
(Hz) (volts)
500 2.1x10 25.23
1000 2.1x10 25.23
1500 2.1x10 25.23
2100 2.1x10 25.23
3000 2.1x10 25.23
4000 2.1x10 25.23
10K 1.8x10 21.94
15K 1.2x10 20.36
25K 0.9x10 17.87
300K 0.6x10 14.34
900K 0.4x10 10.83

Ii =0.27μA Io =0.37mA

Ri=Vi/Ii= 4.44 MΩ

Ro= Vo/Io=38.7KΩ

MODEL GRAPH:

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RESULT :
Thus, the Voltage Series feedback amplifier was designed, and frequency response was plotted.
Theoretical and Practical value of the following parameters are compared.

Practical Value Theoretical Value

Bandwidth 300KHz ∞
Input Impedance 4.44MΩ ∞
Output Impedance 38.7KΩ 0

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 EXPT.NO.2 VOLTAGE SHUNT FEEDBACK AMPLIFIER
DATE:

AIM:
To design and test the voltage-shunt feedback amplifier and to calculate the following parameters with
and without feedback.
1. Band width and cut-off frequencies.
2. Input and output impedance.

APPARATUS REQUIRED:

S.No EQUIPMENTS RANGE QUANTITY

1 AFO (0-3)MHz 1
2 CRO (0-20)MHz 1
3 Resistors As per design Each one
4 Dual Power supply (0-30V) 1
5 Op-amp μA741 1
6 Bread Board - 1
7 Connecting wires - Required Quantity

THEORY:
In voltage shunt feedback amplifier, the feedback signal voltage is given to the base of the transistor
in shunt through the base resistor RB. This shunt connection tends to decrease the input resistance
and the voltage feedback tends to decrease the output resistance. In the circuit RB appears directly
across the input base terminal and output collector terminal. A part of output is feedback to input
through RB and increase e in IC decreases IB. Thus negative feedback exists in the circuit. So this
circuit is also called voltage feedback bias circuit. This feedback amplifier is known a trans
resistance amplifier. It amplifies the input current to required voltage levels. The feedback path
consists of a resistor and a capacitor.

PIN DIAGRAM

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CIRCUIT DIAGRAM

DESIGN:

Given values, Av=3(Theoretical value)

Let,Rf=3KΩ ; formula:Av=-(Rf/R1)

=>R1=Rf/(-Av)=1KΩ.

WAVEFORM

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PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Keeping the input voltage constant, vary the frequency from 50Hz to 3MHz in regular
steps and note down the corresponding output voltage.
3. Plot the graph: Gain (dB) Vs Frequency.
4. Calculate the bandwidth from the graph.
5. To measure the Input and Output current, connect ammeter in μ Arange and mA range in
series with Input resistance and Load resistance respectively. Measure input current (Ii) and
output current (Io) by keeping Vi and Frequency of input signal a constant value.

Observations:

Vi=1.15 V
Frequency Output Voltage(V0) Gain=20log(V0/Vi) (dB)
(Hz) (volts)
500 2.1x10 25.23
1000 2.1x10 25.23
1500 2.1x10 25.23
2100 2.1x10 25.23
3000 2.1x10 25.23
4000 2.1x10 25.23
10K 1.8x10 21.94
15K 1.2x10 20.36
25K 0.9x10 17.87
300K 0.6x10 14.34
500K 0.4x10 10.83

Ii = 0.3μA Io=0.35mA

Ri=Vi/Ii=3.83MΩ

Ro= Vo/Io=28.57KΩ

MODEL GRAPH:

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RESULT :
Thus the Voltage Shunt feedback amplifier was designed and frequency response was
plotted. Theoretical and Practical value of the following parameters are compared.

Practical Value Theoretical Value

Bandwidth 99.9 KHz ∞
Input Impedance 3.83MΩ ∞
Output Impedance 28.57KΩ 0

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 EXPT.NO.3
DATE: INTEGRATOR

AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC741.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC741 1
5. Bread Board 1
6. Resistors As per design 1
7. Capacitors As per design 1
8. Connecting wires and probes As required

THEORY:
A circuit in which the output voltage waveform is the integral of the input voltage waveform is
the integrator. Such a circuit is obtained by using a basic inverting amplifier configuration if the
feedback resistor Rf is replaced by a capacitor Cf .The expression for the output voltage is given as,
Vo=-(1/RfC1) ∫Vidt
Here the negative sign indicates that the output voltage is180 0out of phase with the input signal.
Normally between faand fbthe circuit acts as an integrator. Generally, the value off a< fb. The input signal
will be integrated properly if the Time period T of the signal is larger than or equal to Rf Cf .
That is,
T ≥ RfCf
The integrator is most commonly used in analog computers and ADC and signal-wave shaping
circuits.

1. Select faequal to the highest frequency of the input signal to be differentiated. Then, assuming
a value of C1< 1 µF, calculate the value of Rf.
2. Choose fb=20faand calculate the values of R1and Cf so that R1C1=RfCf.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF INTEGRATOR:

MODEL GRAPH:

DESIGN:
To obtain the output of an Integrator circuit with component values R1Cf= 0.1ms, Cf= 0.1µF
and also if 1V peak sine wave at 1000Hz is applied as input.
We know the frequency at which the gain is 0 dB,fb= 1 / (2π R1Cf) Therefore
R1=1.6KΩ;LetVi=1Vand f=1000Hz,;VO=-(1/R1Cf)Vi dt

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vccand-Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input
voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted
in a graph sheet.

OBSERVATIONS:
(a).Integrator:
Input Voltage Output Voltage
1v(p-p) 0.5(p-p)

RESULT:
Thus the Integrator circuit for the given specifications using Op-Amp IC741 was designed and tested
and its input and output waveforms were drawn.

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 EXPT.NO.4
DATE: DIFFERENTIATOR

AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741.

APPARATUSREQUIRED:

S.No Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1
2. CRO 30 MHz 1
3. Dual RPS 0 – 30 V 1
4. Op-Amp IC741 1
5. Bread Board 1
6. Resistors As per design 1
7. Capacitors As per design 1
8. Connecting wires and probes As required

THEORY:

The differentiator circuit performs the mathematical operation of differentiation; that is, the
output waveform is the derivative of the input waveform. The differentiator may be constructed from a
basic inverting amplifier if an input resistor R1is replaced by a capacitor C1 .The expression for the
output voltage is given as,
Vo=-RfC1(dVi/dt)
Here the negative sign indicates that the output voltage is180 0out of phase with the input signal.
A resistor Rcomp = Rfis normally connected to the non-inverting input terminal of the op-amp to
compensate for the input bias current. A workable differentiator can be designed by implementing the
following steps:
3.
Select faequaltothehighestfrequencyoftheinputsignaltobedifferentiated.Then, assuming a value of
C1< 1 µF, calculate the value of Rf.
4.
Choose fb=20faand calculate the values of R1and Cf so that R1C1=RfCf.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF DIFFERENTIATOR:

MODEL GRAPH:

DESIGN:
[To design a differentiator circuit to differentiate an input signal that varies in frequency
from 10 Hz to about 1 KHz. If a sine wave of 1V peak at 1000Hz is applied to the differentiator,
draw its output waveform.]
Given, fa= 1 KHz We know the frequency at which the gain is 0 dB, f a= 1 / (2π RfC1) Let us
assume C1=0.1µF;then Rf=1.6KΩ; Let Vi=1V and f =1KHz;Vo=-RfC1(dVi\/dt)
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vccand-Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate input
voltage is applied to the inverting input terminal of the Op-Amp.
4. The output voltage is obtained in the CRO and the input and output voltage waveforms are plotted
in a graph sheet.

OBSERVATIONS:
(b).Integrator:
Input Voltage Output Voltage
1V Spike at transition (0.9 V)

RESULT:
Thus the Differentiator circuit for the given specifications using Op-Amp IC741 was designed and tested
and its input and output waveforms were drawn.

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 EXPT.NO.5
DATE: CLIPPERS

AIM:
To design and construct a clippers circuit using op-amp and verify the output waveforms.

APPARATUS REQUIRED:

S.No EQUIPMENTS RANGE QUANTITY

1 AFO (0-1)MHz 1
2 CRO (0-20)MHz 1
3 Resistors 1K,10KΏ Each one
4 Power supply (0-30V) 1
5 Op-Amp uA741 1
5 Capacitors 0.1uF 1
6 Connecting wires - Required
7 Bread Board - 1

THEORY:
The circuit is basically a rectifier circuit, which clips the input waveform according to the
required specification. The diode acts as a clipper. There are several clippers like positive clipper,
negative clipper, etc. Depending upon the connection of diode it can be classified as series and shunt.

CIRCUIT DIAGRAM:

POSITIVECLIPPER:

MODELGRAPH

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 |EC3462LinearIntegratedCircuitsLaboratory
NEGATIVE CLIPPER: MODELGRAPH

TABULATION:
POSITIVE CLIPPER:
INPUT OUTPUT
AMPLITUDE: AMPLITUDE:
TIME PERIOD: TIME PERIOD:

TABULATION:
NEGATIVE CLIPPER:
INPUT OUTPUT
AMPLITUDE: AMPLITUDE:
TIME PERIOD: TIME PERIOD:

RESULT:

Thus clipper circuits was designed and constructed and their output wave forms are verified.

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 EXPT.NO.6
DATE: CLAMPERS

AIM:
To design and construct a clippers circuit using op-amp and verify the output wave forms.

APPARATUS REQUIRED:

S.No EQUIPMENTS RANGE QUANTITY

1 AFO (0-1)MHz 1
2 CRO (0-20)MHz 1
3 Resistors 1K,10KΏ Each one
4 Power supply (0-30V) 1
5 Op-Amp uA741 1
5 Capacitors 0.1uF 1
6 Connecting wires - Required
7 Bread Board - 1

THEORY:

The clamper circuit is a type of wave shaping circuit in which the DC level of the input
signal is altered. The DC voltage is varied accordingly and it is classified as positive clamper or
negative clamper accordingly.

CLAMPER CIRCUIT:

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MODEL
GRAPH:

TABULATION:
POSITIVE CLAMPER:
INPUT OUTPUT
AMPLITUDE: AMPLITUDE:
TIME PERIOD: TIME PERIOD:

TABULATION:
NEGATIVE CLAMPER:
INPUT OUTPUT
AMPLITUDE: AMPLITUDE:
TIME PERIOD: TIME PERIOD:

RESULT:

Thus clamper wave shaping circuits was designed and their output wave forms are verified..

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 EXPT.NO.7
DATE: INSTRUMENTATION AMPLIFIER

AIM:
To design and test instrumentation amplifier using operational amplifier IC741

APPARATUSREQUIRED:

S.No Name of the Apparatus Range Quantity

1. CRO 30 MHz 1
2. Dual RPS 0 – 30 V 2
3. Op-Amp IC741 3
4. Bread Board 1
5. Resistors As per design
6. Connecting wires and probes As required

THEORY:
Instrumentation amplifier is a kind of differential amplifier with additional input buffer stages.
The addition of input buffer stages makes it easy to match (impedance matching) the amplifier with the
preceding stage. Instrumentation are commonly used in industrial test and measurement application.
A circuit providing an output based on the difference between two inputs (times a scale factor)is
given in the circuit diagram. In the circuit diagram, opamps labeled IC1 and IC2 are the input buffers.
Anyway the gain of these buffer stages are not unity because of the presence of R1 and Rg. Op amp
labelled IC3 is wired as a standard differential amplifier. R3 connected from the output of IC3 to its
non-inverting input is the feedback resistor. R2 is the input resistor. The voltage gain of the
instrumentation amplifier can be expressed by using the equation below.
Voltage gain (Av)=Vo/(V2-V1)=(1+2R1/Rg) x R3/R2
Vo={(1 +2R1/Rg)xR3/R2} (V2-V1)
A practical instrumentation amplifier circuit designed based on uA 741 op amp is shown below.
The amplifier operates from +/-12V DC and has a gain 10.If you need a variable gain, then replace Rg
with a 5K POT.
An instrumentation amplifier is a differential amplifier optimized for high input impedance and
high CMRR. An instrumentation amplifier is typically used in applications in which a small differential
voltage and a large common mode voltage are the inputs.

PIN DIAGRAM:

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CIRCUITDIAGRAM:

𝑅3
)
𝑉𝑜 2𝑅1
DESIGN:
=(1 ( )
+
Voltage gain,

𝐴𝑣=
(𝑉2−𝑉1) 𝑅𝑔 𝑅2
2𝑅1 𝑅3
∴ 𝑉=(1 + )( )𝑣( − 𝑣)
0
𝑅𝑔 𝑅2 2 1

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vccand –Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. Set the Input voltage V1 andV2by DRPS.
4. CalculatetheDifferentialvoltage.i.e.,V2-V1
5. For setting different ranges of resistance value of RG, the output voltage is can obtained in the
CRO and note down.
6. Compare the obtained voltage with theoretical output voltage by using the formula

OBSERVATIONS:
InputVoltage(V1)=5volts
InputVoltage(V2)=6volts

𝑉0 =(1+
Theoretical Output voltage
( )(𝑣2−𝑣1)
𝑅3
2 )
𝑅1
𝑅 𝑅2
𝑔

Sl. Differential Resistance Output voltage (Vo)

N voltage(V2–V1) RG (Ω) Theoretical Obtained
o
1 1.0 x5 2.2k Ω 9.55 9.2
2 4.7k Ω 7.15 7
3 10k Ω 6 5.85

RESULT:
Thus the design and testing of the Instrumentation Amplifier was done.
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 EXPT.NO.8
ACTIVE LOW-PASS FILTER
DATE:

AIM:
Design a Second order active Butterworth low pass filter for the given specifications
usingIC741.

APPARATUSREQUIRED:
S.No Name of the Apparatus Range Quantity
1. Function Generator 3MHz 1
1. CRO 30 MHz 1
2. Power Supply 15v-0-15v 1
3. Op-Amp IC741 1
4. Bread Board - 1
5. Resistors As per design
6. Capacitors As per design
7. Connecting wires and probes As required

THEORY:
Second order Low pass filter:
A LPF allows only low frequency signals up to a certain break-point fHto pass through,
while suppressing high frequency components. The range of frequency from 0 to higher cut
off frequency fHis called pass band and the range of frequencies beyond fHis called stop
band.

PIN DIAGRAM:

CIRCUIT DIAGRAM:

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 Design

1
: Given:
=>𝑓𝐻=𝟏𝟎𝟎 −− − − − −− −(1)
2𝜋𝑅
𝟎= 𝐶

=>For n =2 ∴α(damping factor) =1.414,

Let C=0.1µF=>∴From Equation(1)=>R= -----------

∴𝐴𝑜 =(1+ )=1.586 −− −− − (2)

𝑅𝑓
Pass Band Gain Ao=(3–α)= (3-1.414)=1.586.

𝑅1

=1 +0.586
Model Let R1=10KΩ, From Equation(2),Rf=5.86 KΩ
Graph:

Observation:
Input voltage(Vin) =1.2Volt(s)
Input Frequency Output voltage Gain=20log10(Vo/Vin)in dB
S.No. Vo(Volts)
(Hz)
1 100 2 4.43
2 500 2 4.43
3 1K 2 4.43
4 1100 1.8 3.52
5 1200 1.6 2.50
6 1300 1.4 1.33
7 1500 1.2 0
8 1800 1 -3.52
9 2750 0.6 -6.02
10 5000 0.2 -15.56

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. +Vccand-Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. The signal which has to be made sine is applied to the RC filter pair circuit with the non-
inverting terminal.
4. ThesupplyvoltageisswitchedONandtheo/pvoltagesarerecordedthroughCRObyvarying different
frequencies from 10 Hz to 100 KHz.
5. Tabulate the readings. Calculating gain through the formula and plotting the frequency
response characteristics using Semi-log graph sheet and finding out the 3 dB line for fc.

RESULT:
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 ThusthesecondorderactiveButterworthlowpassfilterforthegivenspecificationsusingIC 741 were
designed and frequency response curve were drawn on semi log graph.

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 EXPT.NO.9
HIGH PASS FILTER
DATE:

AIM:
Design a Second order active Butterworth High pass filter for the given specifications using IC
741

APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity

1. Function Generator 3MHz 1

1. CRO 30 MHz 1
2. Power Supply 15v-0-15v 1
3. Op-Amp IC741 1
4. Bread Board 1
5. Resistors As per design
6. Capacitors As per design
7. Connecting wires and probes As required

THEORY:
Second order High pass filter:
The high pass filter is the complement of the low pass filter. Thus the high pass filter can be
obtained by interchanging R and C in the circuit of low pass configuration. A high pass filter allows
only frequencies above a certain bread point to pass through and at terminates the low frequency
components. The range of frequencies beyond its lower cut off frequency fLis called stop band.

PIN DIAGRAM:

CIRCUIT DIAGRAM:

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 |EC3462LinearIntegratedCircuitsLaboratory
Design

1
: Given:
=>𝑓𝐿=𝟏𝟎𝟎 −− −− − − −−(1)
2𝜋𝑅
𝟎= 𝐶
Let C=0.1µF =>∴From Equation(1) =>R= ----------
=>For n =2 ∴α(damping factor) =1.414,

∴𝐴𝑜 =(1+ )=1.586 −− −− − (2)

𝑅𝑓
Pass Band Gain Ao=(3– α)=(3-1.414)=1.586.

𝑅1

=1 +0.586
Model Let,R1=10KΩ, From Equation(2),Rf=5.86 KΩ
Graph:

Observation:
Input voltage (Vin) =1.2 Volt(s)
Input
Frequenc Output voltage Gain=20log10(Vo/Vin)in dB
S.No.
y (Hz) Vo(Volts)
1 100 0
2 300 0.4 -15.56
3 500 0.6 -7.60
4 800 0.8 -3.52
5 1000 1.2 0
6 2000 1.6 2.50
7 3000 1.8 3.52
8 5000 2.1 4.86
9 7000 2.1 4.86
10 10000 2.1 4.86

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. +Vccand-Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. ThesignalwhichhastobemadesineisappliedtotheRCfilterpaircircuitwiththenon-inverting terminal.
4. The supply voltage is switched ON and the o/p voltages are recorded through CRO by varying
different frequencies from 10 Hz to 100 KHz.
5. Tabulatethereadings.Calculatinggainthroughtheformulaandplottingthefrequencyresponse
characteristics using Semi-log graph sheet and finding out the 3 dB line for fc.

RESULT:
Thus the second Order active Butterworth High pass filter for the given specifications using IC741were

24 |Pa g e
designed and frequency response curve were drawn on semi log graph.

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 EXPT.NO.10
BAND PASS FILTER
DATE:

AIM:
Design a Second order active Butterworth Band pass filter for the given specifications using IC
741

APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantit
y
1. Function Generator 3MHz 1
1. CRO 30 MHz 1
2. Power Supply 15v-0-15v 1
3. Op-Amp IC741 1
4. Bread Board 1
5. Resistors As per design
6. Capacitors As per design
7. Connecting wires and probes As required

THEORY:
Second order Band pass filter:
The BPF is the combination of high and low pass filters and this allows a specified range of
frequencies to pass through. It has two stop bands in range of frequencies between 0 to fLand beyond
fH. The band between fLand fHis called pass band. Hence its bandwidth is BW =(fL-fH).

PIN DIAGRAM:

CIRCUIT DIAGRAM:

26 |Pa g e
Design
Given:
fo=1.7KHz; Q=8; Ao=65 at center frequency fo. An

1
expression for the Center frequency is given by
𝑓𝑜=
IfC1=C2=C=0.01µfThen,Center frequency becomes
1 𝑅1+𝑅3
𝑓𝑜 = √
2𝜋 𝑅1𝑅2𝑅3
𝐶

𝑅1= 𝑄 ≈𝟏.𝟐𝑲Ω ; 𝑅
= 𝑄 ≈𝟏.𝟐𝑲Ω
The resistor values can be found using the following formulas

𝑄
2 𝜋𝑓𝐶𝐴 ≈𝟏𝟓𝟎𝑲Ω;𝑅3= )
𝜋𝑓𝐶
2 2
𝑜 𝑜
𝑜
2𝜋𝑓𝐶(2𝑄 −𝑜 𝐴 𝑜

𝑅2
The gain can be found by,
𝐴𝑜=
2𝑅 1

Mode l Graph

27 |Pa g e
 Observation:
Input voltage (Vin) = 1.2 Volt(s)
Input
Frequenc Output
Gain=20log10(Vo/Vin)in dB
S.No. y (Hz) voltage
Vo(Volts)

1 320 3.1 11.41

2 450 3.6 12.70

3 610 4 13.62

4 800 4 13.62

5 1K 4 13.62

6 1.3K 4 13.62

7 1.5K 3.6 12.70

8 2K 3 10.52

9 4K 2 7.60

10 10K 1 1.58

PROCEDURE:
1.Connections are given as per the circuit diagram.
2. +Vccand-Vccsupply is given to the power supply terminal of the Op-Amp IC.
3. The signal which has to be made sine is applied to the RC filter pair circuit with the non-inverting terminal.
4. The supply voltage is switched ON and the o/p voltages are recorded through CRO by varying
different frequencies from 10 Hz to 100 KHz.
5. Tabulate the readings. Calculating gain through the formula and plotting the frequency
response characteristics using Semi-log graph sheet and finding out the 3 dB line for fc.

RESULT:
Thus these cond order active Band pass filter for the given specifications using IC741were designed and
frequency response curve were drawn on semi log graph.

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 EXPT.NO.:11 PLL CHARACTERISTICS
DATE:

AIM:

To construct and study the operation of PLL IC565 and determine its Characteristics.

APPARATUS REQUIRED:

S.No Components Range Quantity

1 IC565 - 1
2 Resistors 6.8KΩ 1
3 Capacitors 0.001µF 1each
0.1µF,1µF
4 Function Generator(Digital) 1Hz–2MHz 1
5 C.R.O - 1
6 Dual Power Supply 0-30 V 1

PIN DIAGRAM (IC565-PLL):

THEORY:
The PLL IC 565 is usable over the frequency range 0.1 Hz to 500 kHz. It has highly stable centre
frequencyandisabletoachieveaverylinearFMdetection.TheoutputofVCOiscapable of producing TTL
compatible square wave. The dual supply is in the range of ±6V to ±12V. The IC can also be operated
from single supply in the range 12V to 24V.

The phase locked loop consists of a phase detector, a voltage control oscillator and, in between them,
a low pass filter is fixed. The input signal „Vi‟ with an input frequency „Fi‟ is conceded by a phase
detector. Basically the phase detector is a comparator which compares the input frequency fi through
the feedback frequency fo. The output of the phase detector is (fi+fo)which is a DC voltage. The out
of the phase detector, i.e., DC voltage is input to the low pass filter (LPF); itremoves the high
frequency noise and produces a steady DC level, i.e., Fi-Fo. The Vf is also a dynamic characteristic of
the PLL.

29 |Pa g e
PROCEDURE:

1. The connections are given as per the circuit diagram.

2. Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal to zero.
Compare it with the calculated value = 0.25 / (RT CT).
3. Nowapplytheinputsignalof1VPPsquarewaveata1KHztopin2.Connect one channel of the scope to pin
2 and display this signal on the scope.
4. Gradually increase the input frequency till the PLL is locked to the input frequency. This frequency
f1 gives the lower end of the capture range. Go on increasing the input frequency, till Pll tracks the
input signal, say ,to a frequency f2.This frequency f2 gives the upper end of the lock range. If input
frequency is increased further, the loop will get unlocked.
5. Now gradually decrease the input frequency till the Pll is again locked. This is the frequency f3,the
upper end of the capture range .Keep on decreasing the input frequency until the loop is unlocked.
This frequency f4 gives the lower end of the lock range.
6. The lock range ∆fL = (f2 – f4).Compare it with the calculated value of ± 7.8 fo / 12 .Also the
capture range is ∆fc=(f3–f1).Compare it with the calculated value of capture range.
∆fc=±(∆fL/(2π)(3.6)(103)C)1/2
CIRCUITDIAGRAM:

30 |Pa g e
MODELGRAPH:

OBSERVATION:
S.No. Amplitude(mV) Timeperiod
2. Output 1.8*2V=3.6V 4.4*1ms=4.4ms

MODELGRAPH:

OUTPUT (MODEL):

RESULT:
Thus the PLL circuit is constructed and its Characteristics is determined and the frequency
multiplier circuit using PLL is constructed and studied.

31 |Pa g e
 EXPT.NO.:12 FREQUENCY MULTIPLIER USING PLL
DATE:

AIM:

To construct Frequency Multiplier circuit using PLL IC565 and verify its output.

APPARATUS REQUIRED:

S.No Components Range Quantity

1 IC565 - 1
2 Resistors 6.8KΩ 1
3 Capacitors 0.001µF 1each
0.1µF,1µF
4 Function Generator(Digital) 1Hz–2MHz 1
5 C.R.O - 1
6 Dual Power Supply 0-30 V 1

PIN DIAGRAM (IC565-PLL):

THEORY:
A divide by N network is inserted between the VCO output and the phase comparator input.
In the lock state, the VCO output frequency fo is given by

fo= Nfs

The multiplication factor can be obtained by selecting a proper scaling factor N of the counter.

32 |Pa g e
PROCEDURE:

1 The connections are given as per the circuit diagram.

2 Measure the free running frequency of VCO at pin4,with the input signal Vi set equal to
zero. Compare it with the calculated value = 0.25 / (RT CT).
3 Nowapplytheinputsignalof1VPPsquarewaveata1KHztopin2.Connect one channel of the scope to
pin 2 and display this signal on the scope.
4 Gradually increase the input frequency till the PLL is locked to the input frequency.
5 Observe the multiplied frequency output on the CRO
6 –plot the output waveform on the graph sheet.

PLLUSED AS FREQUENCY MULTIPLIER

Design:
Let V+=10VandV-=-10
Let the input frequency be1Khz, and the output frequency 5Khz,VCO should run at 5Khz frequency ,
fo=(1.2/4*R1*C1)=5Khz
Take C1=0.01μF Then R1=6KTake C2=10μFandC3=0.001μFuseCc=10μFandR=10k for ac coupling
of input signal

CIRCUIT DIAGRAM OF PLL AS FREQUENCE MULTIPLIER:

OBSERVATION:
S.No. Amplitude(mV) Time
period(ms)
1. Input 1.2 4.4
2. Output 3.6 1.8

33 |Pa g e
MODELGRAPH:

RESULT:
Thus the frequency Multiplier using PLL circuit is constructed and its verified.

34 |Pa g e
 EXPT.NO.:13
DATE: R-2R LADDER TYPED-A CONVERTER USING OP-AMP.

AIM:
To design a 8-bitR-2R Ladder Type D-A Converter using Op-amp and observe the output.

APPARATUSREQUIRED:

S.N Components Specification Quantity

o
1. Op-amp IC741 1

2. Resistor R1=2KΩ As req

3. Regulated Power supply (0-30)KHz 1

4. DC power supply ±15Vand-5V 1

5. Multimeter - 1

THEORY:

A digital-to-analog converter (DAC, D/A, D2A or D-to-A) is a circuit that converts digital
data (usually binary) into an analog signal (current or voltage). One important specification of a DAC
is its resolution. It can be defined by the numbers of bits or its step size. Wide range of resistors used
Weighted Resistor type DAC. This can be avoided by using R-2R ladder type DAC where only two
values of resistors are required.

35 |Pa g e
CIRCUITDIAGRAM:

1. Todesign3bitR-2RDigitaltoAnalogconvertertoconvertanalogvoltageof
binary bit 100.

If binary bit 001:

36 |Pa g e
OBSERVATION:

Vref =-5V
d1 d2 d3 Practical
V0
0
0 0 0
1.25
0 0 1

2.5
0 1 1

3.75
0 1 1

5
1 0 0

6.25
1 0 1
7.5
1 1 0
8.75
1 1 1

PROCEDURE:
 Check the component using multimeter.
 Setup the circuit stage by stage on the bread board
 Verify the working of circuit separately.
 Complete the circuit and apply-5V ref if bit=1.
 Observe the output using multimeter.
 Plot the output waveform on the graph sheet.

RESULT:

Thus the design of R-2R Ladder Type D-A Converter using Op-amp and its output is
observed.

37 |Pa g e
 EXPT.NO.14
DATE: RCPHASESHIFTOSCILLATOR

AIM:
To design and construct the RC Phase shift oscillator for the out frequency of 200Hz and
verify its output waveform and frequency.

APPARATUSREQUIRED:
S.No Name of the Apparatus Range Quantity

1. CRO 30 MHz 1
1. Power Supply 15v-0-15v 1
2. Op-Amp IC741 1
3. Bread Board 1
4. Resistors As per design
5. Capacitors As per design
6. Connecting wires and probes As required

THEORY:
Basically, positive feedback of a fraction of output voltage of a amplifier fed to the input in
the same phase, generate sine wave. The op-amp provides a phase shift of 180 degree as it is used in
the invertingmode.Anadditionalphaseshiftof180degreeisprovidedbythefeedbackRCnetwork.The
frequency of the oscillator fois given by,

𝑓𝑜= 1
2𝜋𝑅𝐶
√6
Also the gain of the inverting op-amp should beat least 29, or RF>29 R1

PIN DIAGRAM:

CIRCUIT DIAGRAM:

37|Page
 Design:

1
Frequency of oscillation,

𝑓𝑜=
2𝜋𝑅𝐶
√6
Av=[𝑅𝑓/𝑅1]=29
𝑅1=10𝑅;𝑅𝑓=29 𝑅1
Given𝑓𝑜=200𝐻𝑧.; Let, 𝐶=0.1𝐹

𝑅= 1
≈3.3𝐾Ω
(2𝜋𝑓𝑜𝐶)
√6

𝑅1=10∗𝑅=33𝐾Ω
To prevent the loading of amplifier by RC network, R1≥10R

Since 𝑅𝑓=29𝑅1
𝑅𝑓=29 ∗33𝐾Ω
𝑅𝑓=957𝐾Ω≈1𝑀Ω

Model Graph:

Observation:
Peak to peak amplitude of the output =8Volts.
Frequency of oscillation (1/T)=f=1/5.6ms=168Hz.

PROCEDURE:

1. Connect the components as sho n in the circuit

2. Switch on the power supply and CRO.
3. Note down the output voltage at CRO.
4. Plot the output wave form on the graph.
5. Compare the output with the theoretical value of oscillation.

RESULT:
Thus, the RC phase shift oscillator is studied and its output wave form traced. Obtained
frequency of Oscillations is, RC phase shift fo=168 Hz.;

38 |Pa g e
 EXPT.NO.15
DATE: WEIN BRIDGE OSCILLATOR

AIM:
To design and construct Wein Bridge Oscillator with the frequency of 1 KHz and verify its
Output wave form and frequency.

APPARATUSREQUIRED:
S.No Name of the Apparatus Range Quantity

1. CRO 30 MHz 1
1. Power Supply 15v-0-15v 1
2. Op-Amp IC741 1
3. Bread Board 1
4. Resistors As per design
5. Capacitors As per design
6. Connecting wires and probes As required

THEORY:

In wein bridge oscillator, wein bridge circuit is connected between the amplifier input terminals
and output terminals. The bridge has a series of RC network in one arm and parallel network in the
adjoining arm. In the remaining 2 arms of the bridge resistors R1and Rf are connected. To maintain
oscillations total phase shift around the circuit must be zero and loop gain unity. First condition occurs
only when the bridge is balanced. Assuming that the resistors and capacitors are equal in value, the
1
𝑓𝑜=
resonant frequency of balanced bridge is given by,

2𝜋𝑅𝐶
At the frequency the gain requir𝑅e d for sustained oscillations is given by,

𝐴=1 𝑓
=3 ∴𝐴=3=>𝑅 =2𝑅
PIN DIAGRAM: + 𝑅1 𝑓 1

39 |Pa g e
CIRCUITDIAGRAM:

R1=10k Rf=20k

+VCC
+15V
7
–
2 6
IC741
+ 4
3
-Vcc
-15V CROVO

R=16k C0.01f

C
16k 0.01f
R

Design:
Gain required for sustained oscillation is Av=1/=3;1+Rf/R1=3 Rf=2R1

= 2𝜋𝑅
Frequency of 1 ; Given fo=1 KHz;Let C=0.01 F;
Oscillation𝑓𝑜 𝐶
∴𝑅=
1 ;
2
R=16 K; Let R1=10 K =>Rf =2* 10 K =20K
𝜋
𝑓 𝑜𝐶
Model Graph:

Observation:
Peak to peak amplitude of the
output=6.8Volts. Frequency of oscillation
f=900
Hz.
PROCEDURE:
1. Connect the components as shown in the circuit.
2. Switch on the power supply and CRO.
3. Note down the output voltage at CRO.
4. Plot the output wave form on the graph.
5. Compare the output with the theoretical value of oscillation.
RESULT:
Hence the Wein bridge oscillator is studied, and its output waveform traced. Obtained frequency of

40 |Pa g e
Oscillations is, Wein Bridge fo=800 Hz.

41 |Pa g e
 EXPT.NO.16
HARTLEY OSCILLATOR
DATE:

AIM:
To design and construct a Hartley oscillator for the given frequency (f0).

APPARATUSREQUIRED:
S.No EQUIPMENTS RANGE QUANTITY
1 AFO (0-1)MHz 1
2 CRO (0-20)MHz 1
3 Resistors 100Ohm,100KOhmPotential Each one
meter
4 Power supply Dual(0-30V) 1
5 Op-amp uA741 1
6 DLB - 2
7 DCB - 1

THEORY:

Hartley oscillator is a type of sine wave generator. The oscillator derives its initial output
from the noise signals present in the circuit. After considerable time, it gains strength and thereby
producing sustained oscillations. Hartley Oscillator has two major parts namely–amplifier part and
feedback part. The amplifier part has a typically Inverting op-amplifies circuit. In the feedback path,
there is a LCL network. The feedback network generally provides a fraction of output as feedback.

CIRCUITDIAGRAM:

10KΩ

10mH 1mH

0.1μF

42 |Pa g e
 DESIGN:

For Hartley oscillator, the frequency of oscillations is given by

fo=1/(2π√(LeqC))

Where Leq=L1

+L2

Forgiven f0=5KHz, Assume L1= 10mH andL2= 1mH and find C=0.1 μF

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Feed the output of the oscillator to a C.R.O by making adjustments in
the Potentiometer connected obtain a stable sine Wave.
3. Measure the time period of the waveform obtained on CRO. & calculate
the Frequency of oscillations.

OBSERVATION:

Amplitude(V) Time(s) Frequency(Hz)

5 0.215ms 4.65KHz

MODELGRAPH:

43 |Pa g e
RESULT:

Thus, the Hartley oscillator was designed and the frequency of oscillation was
obtained Theoretical frequency :
Practical frequency :

44 |Pa g e
 EXPT.NO.17
DATE: COLPITTS OSCILLATOR

AIM:
To design and construct a Colpitts oscillator for the given frequency (f0).

APPARATUSREQUIRED:

S.No EQUIPMENTS RANGE QUANTITY

1 AFO (0-1)MHz 1

2 CRO (0-20)MHz 1

3 Resistors 100Ohm,1000KOhm Each one

Potential meter
4 Power supply Dual(0-30V) 1

5 Op-amp uA741 1

6 DLB - 1

7 DCB - 2
THEORY:

A Colpitts oscillator is the electrical dual of a Hartley oscillator. In the Colpitts circuit, two
capacitors and one inductor determine the frequency of oscillation. The oscillator derives its initial
outputfromthenoisesignalspresentinthecircuit.Afterconsiderabletime,it gains strength and thereby
producing sustained oscillations. It has two major parts namely – amplifier part and feedback part.
The amplifier part has a typically Inverting op-amplifies circuit. In the feedback path, there is a CLC
network. The feedback network generally provides a fraction of output as feedback.

CIRCUITDIAGRAM

10KΩ

0.01μF 0.1μF
20mH

45 |Pa g e
 DESIGN:

The frequency of oscillations in the Colpitts oscillator is given by

f0= 1/ (2π√ (LCeq)) Where

Ceq=C1C2/(C1+C2)

Forgivenf0= 15KHz AssumeC1= 0.01μF ,C2=0.1 μF andfindL1=20mH

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. FeedtheoutputoftheoscillatortoaC.R.ObymakingadjustmentsinthePotentiometer
connected obtains a stable sine Wave.
3. Measure the time period of the wave form obtained on CRO & Calculate
the Frequency of oscillations.

OBSERVATION:

Amplitude(V) Time(s) Frequency(Hz)

6 0.7x0.1ms 14.28KHz

MODELGRAPH:

46 |Pa g e
RESULT:

Thus, the Colpitts oscillator was designed, and the frequency of oscillation was obtained
Theoretical frequency: 15 KHz
Practical frequency: 14.28 KHz

47 |Pa g e
SIMULATION USING PSPICE

48 |Pa g e
 EXPT.NO.18
DATE: TUNED COLLECTOR OSCILLATOR

AIM:
To Simulate the Tuned collector oscillator by using PSPICE software.

SYSTEMREQUIRED:
 PC with SPICE Software
 PC

THEORY:
Tuned collector oscillation is a type of transistor LC oscillator where the tuned circuit (tank)
consists of a transformer and a capacitor is connected in the collector circuit of the transistor. Tuned
collector oscillator is of course the simplest and the basic type of LC oscillators. The tuned circuit
connected at the collector circuit behaves like a purely resistive load at resonance and determines the
oscillator frequency. The common applications of tuned collector oscillator are RF oscillator circuits,
mixers, frequency demodulators, signal generators etc.

PROCEDURE:
1. Construct the circuit as per the circuit diagram.
2. Initialize all the values.
3. Assign the nodes to the circuit.
4. Write the program corresponding to the node.
5. Simulate the program and the waveform was displayed.

CIRCUITDIAGRAM:

49 |Pa g e
MODELGRAPH:

RESULT:
Thus, the Tuned Collector Oscillator was Simulated by using PSPICE software and the output
waveform was observed in the waveform viewer.

50 |Pa g e
 EXPT.NO.19
DATE: WEIN BRIDGE OSCILLATOR

AIM:
To Simulate the Wein bridge oscillator by using PSPICE software.
SYSTEMREQUIRED:
 PC with SPICE Software
 PC

THEORY:
o
Generally in an oscillator, amplifier stage introduces 180 phase shift and feedback network
o o
introduces additional 180 phase shift, to obtain a phase shift of 360 around a loop. This is a condition for
any oscillator. But Wein bridge oscillator uses a non-inverting amplifier and hence does not provide any
o
phase shift during amplifier stage. As total phase shift requires is 0 or 2n radians, in Wein bridge type no
o
phase shift is necessary through feedback. Thus the total phase shift aroundaloopis0 .The output of the
amplifier is applied between the terminals 1 and 3, which are the input to the feedback network. While the
amplifier input is supplied from the diagonal terminals 2 and 4, which is the output from the
feedbacknetwork.ThusamplifiersupplieditsownoutputthroughtheWeinbridgeasafeedbacknetwork..

PROCEDURE:
1. Click on the start menu and select the pspice simulation software
2. Select the parts required for the circuit from the parts menu and place them in
the work space
3. Connect the parts using wires
4. Save the file and select the appropriate analysis
5. Simulate the circuit and observe the corresponding output waveforms

CIRCUIT DIAGRAM:

51 |Pa g e
 MODELGRAPH:

RESULT:
Thus, the Wein bridge Oscillator was Simulated by using PSPICE software and the output
waveform was observed in the waveform viewer.

52 |Pa g e
 EXPT.NO.20 DOUBLE AND STAGGERED TUNED AMPLIFIER
DATE:

AIM:
To simulate the double and staggered tuned amplifier by using PSPICE software.

SYSTEMREQUIRED:
 PC with SPICE Software
 PC
THEORY:
A double-tuned amplifier is a tuned amplifier with transformer coupling between the amplifier
stages in which the inductances of both the primary and secondary windings are tuned separately with a
capacitor across each. The scheme results in a wider bandwidth than a single tuned circuit would achieve.
There is a critical value of transformer coupling coefficient at which the frequency response of the amplifier
is maximally flat in the pass band and the gain is maximum at the resonant frequency. Designs frequently
use a coupling greater than this (over- coupling) in order to achieve an even wider bandwidth at the expense
of a small loss of gain in the centre of the pass band. Staggered tuning is a technique used in the design of
multi-stage tuned amplifiers whereby each stage is tuned to a slightly different frequency. In comparison to
synchronous tuning (where each stage is tuned identically) it produces a wider bandwidth at the expense of
reduced gain.

It also produces a sharper transition from the pass band to the stop band. Both staggered tuning and
synchronous tuning circuits are easier to tune and manufacture than many other filter types. The function
of stagger-tuned circuits can be expressed as a rational function and hence they can be designed to any of
the major filter responses such as Butterworth and Chebyshev. The poles of the circuits are easy to
manipulate to achieve the desired response because of the amplifier buffering between stages.
.

PROCEDURE:
1. Construct the circuit as per the circuit diagram.
2. Initialize all the values.
3. Assign the nodes to the circuit.
4. Write the program corresponding to the node.
5. Simulate the program and the waveform was displayed.

CIRCUITDIAGRAM:

53 |Pa g e
 |EC3462LinearIntegratedCircuitsLaboratory

MODELGRAPH:

54 |Pa g e
RESULT:
Thus, the Double and staggered tuned amplifier was Simulated by using PSPICE software
and the output waveform was observed in the waveform viewer.

55 |Pa g e
 EXPT.NO.21
DATE: BISTABLE MULTIVIBRATOR

AIM:
To Simulate the Bistable multivibrator by using PSPICE software.

SYSTEMREQUIRED:
 PC with SPICE Software
 PC
THEORY:
Bi- stable multivibrator contains two stable states and no quasi states. It requires two clock or
trigger pulses to change the states. It is also called as flip flop, scale of two toggle circuit, trigger circuit.
It is used in digital operations like counting, storing data’s in flip flops and production of square
waveforms.

PROCEDURE:
1. Construct the circuit as per the circuit diagram.
2. Initialize all the values.
3. Assign the nodes to the circuit.
4. Write the program corresponding to the node.
5. Simulate the program and the waveform was displayed.

CIRCUIT DIAGRAM:

MODEL GRAPH:

56 |Pa g e
RESULT:
Thus, the Bistable multivibrator was simulated by using PSPICE software and the output
Waveform was observed in the waveform viewer.

57 |Pa g e
 EXPT.NO.22
SCHMITT TRIGGER CIRCUIT WITH PREDICTABLE HYSTERESIS
DATE:

AIM:
To Simulate the Schmitt trigger circuit with predictable hysteresisbyusing PSPICE.

SYSTEMREQUIRED:
 PC with SPICE Software
 PC
THEORY:
A Schmitt trigger is a comparator circuit with hysteresis, implemented by applying positive
feedback to the input of an amplifier. It is an active circuit which converts an analog input signal to a
digital output signal. The circuit is named a "trigger" because the output retains its value until the input
changes sufficiently to trigger a change. In then on-inverting configuration, when the input is higher
than a certain chosen threshold, the output is high. When the input is below a different (lower) chosen
threshold, the output is low, and when the input is between the two levels, the output retains its value.
This dual threshold action is called hysteresis and implies that the Schmitt trigger possesses memory
and can act as a bistable circuit (latch or flip-flop). There is a close relation between the two kinds of
circuits: a Schmitt trigger can be converted into a latch and a latch can be converted into a Schmitt
trigger.
Schmitttriggerdevicesaretypicallyusedinsignalconditioningapplicationstoremovenoisefrom signals
used in digital circuits, particularly mechanical switch bounce. They are also used in closed loop
negative feedback configurations to implement relaxation oscillators, used in function generators and
switching power supplies.

PROCEDURE:
1. Construct the circuit as per the circuit diagram.
2. Initialize all the values.
3. Assign the nodes to the circuit.
4. Write the program corresponding to the node.
5. Simulate the program and the waveform was displayed.

CIRCUIT DIAGRAM:

58 |Pa g e
 MODEL GRAPH:

RESULT:
Thus, the Schmitt trigger was simulated by using PSPICE software and the output waveform
was observed in the waveform viewer.

59 |Pa g e
 EXPT.NO.23
DATE: ANALYSIS OF POWER AMPLIFIER

AIM:
To design and analysis the test performance of power amplifier.

APPARATUS REQUIRED:

S.No EQUIPMENTS RANGE QUANTIT Y

1 AFO (0-1)MHz 1
2 CRO (0-20)MHz 1
3 Resistors 1.5K,6KΏ,2K,14k,2.3K,10K Each one
4 Power supply (0-30V) 1
5 Transistors BC107 1
6 Capacitors 28uF,10uF,720uF 1
7 Connecting wires - Required

THEORY:
Anelectronicamplifierisusedforincreasingthepowerofasignal.Itdoesthisbytakingenergyfrom a power
supply and controlling the output to match the input signal shape but with a larger amplitude. In this sense,
an amplifier may be considered as modulating the output of the power supply.

PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Give a negative trigger input to Q2.
3. Note the output of transistor rQ2 andQ1.
4. Find the value of Ton and Toff.

DESIGNEXAMPLE:
Given specifications:
VCC=12V;hfe=200;f=1khz;Ic=2mA;Vce(sat)=0.2v;VBB=- 2V

(i) To calculate RC:

RC=VCC-Vce(sat)/IC
-3
RC=12–0.2/2x10 =5.9KΩ

(ii) To calculate R:
-3
IB2(min)=IC2/hfe=2x10 /200=10µASelectIB2>IB1(min)(say25µA) Then R =
VCC – V BE (sat) / IB2
-6
Therefore R=12-0.7/25x10 =452KΩ

(iii) To calculate C:
T=0.69RC
-3 3
1x10 =0.69x452x10 xCC=3.2nf

60 |Pa g e
 TocalculateR1& R2:
VB1={(VBBR1/R1+R2)+(VCE(sat)R2/R1+R2)}SinceQ1isinoffstate,VB1≤0
Then (VBBR1/ R1 +R2) = (VCE (sat)R2 / R1+R2) VBBR1 = VCE (sat)R2
2R1=0.2R2
Assume R1=10KΩ, then R2=100 KΩ
Consider, C1=25pf(commutative
capacitor)

TABULATION:
Amplitude(V) Time period(msec)
TON TOFF

CIRCUIT DIAGRAM:

MODELGRAPH:

RESULT:
Thus, the Power amplifier is designed and the performance is tested.
Theoretical period :
Practical period :

61 |Pa g e