Course Code Course Title L T P C
Digital Logic Design and Computer
BAITE101 3 0 2 4
Organization
Pre-requisite NIL Syllabus Version
1
Course Objectives
To acquire the basic knowledge of digital logic circuits and registers
To familiarize with the basic structure of computer systems, arithmetic operations,
Input/ Output interfacing
To acquire the importance of memory systems Design Pipelining and Parallel
Processing systems
Course Outcomes
Outline the conversion of number systems and illustrate the simplification of Boolean
functions and design combinational circuits
Construct the design and analysis of various Sequential logic circuits using flip flops
Apply the arithmetic algorithms and understand the Input/Output organizat
Apply the arithmetic algorithms and understand the Input/Output organization
Evaluate Memory Design, Pipelining and Multiprocessor Systems
Module:1 Combinational Circuits 9 hours
Introduction to Digital Logic-Number system Conversions-Logic Gates-Universal Gates,
Boolean Algebra–Simplification of two, three, and four -variable Boolean equations
using the Karnaugh maps, Design of combinational logic circuits-Half adder, Full adder,
Half subtractor, Full subtractor, Multiplexers, De-multiplexers, Decoders and Encoder
Module:2 Sequential Circuits 9 hours
Flip flops- Clock and triggering -SR, JK, D and T-characteristic tables and excitation
tables, Design of clocked sequential logic circuit, Design of counters-
Asynchronous/Synchronous Counters, Registers- Shift registers (SISO, SIPO, PISO,
PIPO)
Module:3 Computer Organization 8 hours
Computer Types - Functional Units - Basic Operational Concepts - Bus Structures -
Performance - Processor, Clock, Performance Equation - CISC and RISC-Instructions
and Instruction Sequencing - Addressing Modes -Assembly Language - Basic
Input/Output Operations - Stacks and Queues – Subroutines
Module:4 Arithmetic Operations and IO interfacing 8 hours
Addition and Subtraction of Signed Numbers - Multiplication of Positive Numbers -
Signed-Operand Multiplication - Integer Division - Floating Point Numbers and
Operations, Accessing I/O Devices – Interrupts - Direct Memory Access
Module:5 Memory Design and Pipelining 9 hours
Semiconductor RAM Memories - Read-Only Memories –Cache Memories - Virtual
Memories. Pipelining- Basic Concepts–Data Hazards - Instruction Hazards -
Classification of models - Memory Organization in Multiprocessors-– Multicomputer -
Performance Considerations
Module:6 Contemporary Issues 2 hours
Total Lecture Hours: 45 hours
Text Book(s)
M. Morris Mano, Michael D. Ciletti, "Digital Logic Design", Pearson Education, 4th
Edition, 2019
Carl Hamacher, Zvonko Vranesic and Safwat Zaky, "Computer Organization", Tata
McGraw Hill, 5th Edition, 2024
Reference Books
M. Morris Mano, Michael D. Ciletti, "Digital Design: With an Introduction to the
Verilog HDL, VHDL, and System Verilog", Pearson Education, 6th Edition, 2018
William Stallings , "Computer Organization and architecture- Designing for
Performance", Prentice Hall, 11th Edition, 2019
J. P. Hayes, "Computer architecture and Organization", McGraw Hill, 3rd Edition,
2017
Indicative Experiments
1. Design Boolean function using logic gates and universal gates. 3 hours
2. Design of combinational circuits: Adders, Subtractors. 3 hours
3. Design of combinational circuits: Multiplexer, Demultiplexer, Decoder
3 hours
and Encoder.
4. Design of sequential circuits using various flip-flops. 3 hours
5. Design of Synchronous counter. 3 hours
6. Design of Asynchronous counter. 3 hours
7. Store your name in the RAM using a seven-segment display.
3 hours
Character by character display.
8. Design a combinational circuit to multiply 3bit number by 2bit number. 3 hours
9.
3 hours
Design a circuit that will display the clock timing for just either 15sec or 15min.
Use ‘D’ as display.
10. Identify the primary storage element in CPU to store the answer of
3 hours
the arithmetic process.
Total Laboratory Hours: 30 hours
Mode of Evaluation :Continuous Assessment Test, Digital Assignment, Quiz, Final
Assessment Test, Lab Continuous Assessment, Lab Final Assessment, Oral
Examination, Seminar, Group Discussion, Presentaion
Recommended by Board of Studies : 24-02-2025
Approved by Academic Council : No. 78 12-06-2025
