Department of Electrical & Electronic Engineering
Chittagong University of Engineering & Technology
EEE 476 VLSI Sessional
Experiment No.: 03
DRC, LVS and Post Layout Simulation
Objectives:
To perform the design rule check of the NAND gate layout
To perform the layout vs. schematic check for the NAND gate layout
To perform parasitic extraction on the NAND gate layout
To simulate the extracted view
To perform tape out
3-1. DRC Rules Check by Cadence's ASUURA
1. In Virtuoso Layout Suite L window click Assura Run DRC. Alternately In the same shell
window (if you typed & after virtuoso) execute the command avview.An Assura Window
appears as below. Run the DRC by clicking DRC → Run.
2. A DRC window appears as shown below. Fill the form as indicated in the picture.
Select the Rules File from the path: “/home/eda/cadence/gpdk090_v4.6/assura/drc.rul”
3. Click on the OK button.A DRC completed window appears as shown below:
4. ClickYes. An Open Run window appears. Click Open Run.
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5. Cell name appears. Select the cell and press OK.
6. Error layer appear as shown below with a nand2 layout window which shows the error
7. Clock to the errors and correct them. The Error Layer Window controls pointing out the
error locations whereas VLW windows controls displaying different layers. Thus we can
easily identify the errors and correct them from layout editor. The GPDK reference manual
can be consulted for details on the DRC rules and errors.
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8. After correcting errors we have follow the same procedure until all errors are corrected.
9. When there will be no errors the following appears:
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3-2. Layout versus Schematics (LVS) Check using Assura
We still need to verify that the layout we designed in Lab2 matches the schematic created in Lab 1.
This verification is accomplished by checking Layout Versus Schematic (LVS) rules in Assura.
1. In avview assura window, Run the LVS by clicking LVS → Run or in layout window using
Assura Run LVS. A pop-up window will appear, fill it up as follows:
Select the Extract Rules File from the path: “/home/eda/Cadence/gpdk090_v4.6/assura/extract.rul”
and the Compare Rules File from the path: “/home/eda/Cadence/gpdk090_v4.6/assura/compare.rul”
2. If there is no error, after the LVS run is finished, you should see the following pop-up
window:
(Otherwise correct your layout/schematic accordingly)
3. Click No.
3-3. Parasitic Extraction using Assura
1. In the avview Assura window click on Commands ->Show Setup Functions ->
Technology. The following window will appear.
Select the Assura Technology File from the path:
“/home/eda/cadence/gpdk090_v4.6/assura_tech.lib”
Else in layout window execute Assura Technology and confirm that assura
technology file is defined in ./assura_tech.lib i.e. in the assura_tech.lib in the current
directory. Now click view and confirm the content of the assura_tech.lib file define
gpdk090 as /home/eda/Cadence/gpdk00_v4.6/assura
2. Click Open Run… ->Open Run. After this you will see the RCX -> Run menu in
Assura window become executable.
3. Now click Run RCX the following appears:
4. Click on Close and Assura Parasitic Extraction Run Form will appear. This will show
Technology field grey with NONE. On the Setup Tab, choose Extracted View for
Output. Make sure Setup Dir is: “/home/eda/cadence/gpdk090_v4.6/assura/rcx”.
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5. On the Extraction Tab, choose RC as theExtraction Type and Schematic Names as the
Name Space. Also type gnd! as the reference node. Click OK.
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6. When the Assura run is complete, the following window pops-up. Click Close.
3-4. Post Layout Simulation
1. In the CIW, execute File → Open
2. Set up the OpenFile form as follows –
Library Name – mylib
Cell Name – nand2
View name – av_extracted
Open with – Layout L
After the run you can verify that beside the 2 NMOS and 2 PMOS there area a lot of
parasitic capacitor and resistor extracted. You may zoom in the layout to verify their location.
3. In the Schematic window execute Launch → ADE L. Analog Design Environment
(ADE) window will open.
4. Setup the model libraries by executing Setup → Model Libraries. Select the following
model library: gpdk090_mos.scs, gpdk090_capacitor.scs and gpdk090_resistor.scs.
Choose ‘TT_s1v’ in the Section column.
5. Setup the Stimuli by executing Setup → Stimuli.
6. Click on the input Vdd. Click on Enabled. Choose Function dc. Enter DC Voltage as
1.2V. Click Apply.
7. Click on the input Gnd. Click on Enabled. Choose Function dc. Enter DC Voltage as
0 V. Click Apply.
8. Click on the input Ain. Click on Enabled. Choose Function pulse. Enter Voltage1,
Voltage2, Period, Delay time, Rise time, Falltime and Pulse width as 0V, 1.2V, 40ns,
3ns, 3ns, 3ns and 20ns respectively. Click Apply.
9. Click on the input Bin. Click on Enabled. Choose Function pulse. Enter Voltage1,
Voltage2, Period, Delay time, Rise time, Fall time and Pulse width as 0V, 1.2V, 50ns,
3ns, 3ns, 3ns and 25ns respectively. Click Apply. Click OK.
10. Now choose the analysis to be done by Analysis → Choose. Select transient analysis to
be done. Provide stop time as 200ns.
11. Select the output to be plotted by executing Outputs → To be plotted → Select on
schematic in the ADE window. Select Ain, Bin and Out pins from layout to plot and
save.
12. We will create the netlist and run the simulation by executing the following in the ADE
environment Simulation → Netlist and Run.
13. The simulation will run and the output will appear. From the log file verify the number
of MOS transistors, resistor and capacitors and number of nodes.
14. We can measure the relevant parameters by using Calculator tool and check whether
they meet our requirements.
3-5. Tape Out
1. Now that post layout simulation has been successfully, we proceed to tape out.
2. In the CIW click File → Export → Stream.
3. Fill out the XStream Out window as shown below:
4. Click on Translate.
5. A notification displaying Translation Completed appears.
