Agenda

◼ Introduction
Architecture
Programmers Model
Instruction Set

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 History of ARM
• ARM (Acorn RISC Machine) started as a new, powerful, CPU design for the
replacement of the 8-bit 6502 in Acorn Computers (Cambridge, UK, 1985)
• First models had only a 26-bit program counter, limiting the memory space
to 64 MB (not too much by today standards, but a lot at that time).
• 1990 spin-off: ARM renamed Advanced RISC Machines
• ARM now focuses on Embedded CPU cores
• IP licensing: Almost every silicon manufacturer sells some microcontroller
with an ARM core. Some even compete with their own designs.
• Processing power with low current consumption
• Good MIPS/Watt figure
• Ideal for portable devices
• Compact memories: 16-bit opcodes (Thumb)
• New cores with added features
• Harvard architecture (ARM9, ARM11, Cortex)
• Floating point arithmetic
• Vector computing (VFP, NEON)
• Java language (Jazelle)
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 RISC Architecture
vs CISC Architecture
RISC CISC
It stands for Reduced Instruction Set It stands for Complex Instruction Set
Computer. Computer.
It is a microprocessor architecture that uses This offers hundreds of instructions of
small instruction set of uniform length. different sizes to the users.

These simple instructions are executed in This architecture has a set of special
one clock cycle. purpose circuits which help execute the
instructions at a high speed.

These chips are relatively simple to design. These chips are complex to design.

They are inexpensive. They are relatively expensive.

Examples of RISC chips include SPARC, Examples of CISC include Intel architecture,
POWER PC. AMD.

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 RISC Architecture
vs CISC Architecture
RISC CISC
It has less number of instructions. It has more number of instructions.

It has fixed-length encodings for instructions. It has variable-length encodings of

instructions.

Simple addressing formats are supported. The instructions interact with memory using
complex addressing modes.

It doesn't support arrays. It has a large number of instructions. It

supports arrays.

It doesn't use condition codes. Condition codes are used.

Registers are used for procedure arguments The stack is used for procedure arguments
and return addresses. and return addresses.

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 Facts
• 32-bit CPU
• 3-operand instructions (typical): ADD Rd,Rn,Operand2
• RISC design…
• Few, simple, instructions
• Load/store architecture (instructions operate on registers, not memory)
• Large register set
• Pipelined execution
• … Although with some CISC touches…
• Multiplication and Load/Store Multiple are complex instructions (many cycles
longer than regular, RISC, instructions)
• … And some very specific details
• No stack. Link register instead
• PC as a regular register
• Conditional execution of all instructions
• Flags altered or not by data processing instructions (selectable)
• Concurrent shifts/rotations (at the same time of other processing)
• …
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 Agenda

Introduction
◼ Architecture
Programmers Model
Instruction Set

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 Topologies
Von Neumann Harvard

ARM9s
ARM7s and newers
and olders
Inst. Data

AHB
bus
I D
Cache Cache
MEMORY
& I/O

Bus Interface

AHB
Memory-mapped I/O: bus

• No specific instructions for I/O

(use Load/Store instr. instead) MEMORY
• Peripheral’s registers at some & I/O
memory addresses
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ARM7TDMI (Advanced RISC Machines 7 Thumb Debug Multiplier ICE)
Block Diagram
A[31:0]

Address Register Address

Incrementer

PC bus
PC

REGISTER
ALU bus BANK

Control Lines
INSTRUCCTION
DECODER
Multiplier
A bus

B bus
SHIFT

A.L.U.
Instruction Reg.

Thumb to
ARM
Write Data Reg. Read Data Reg.
translator

D[31:0]
 Agenda

Introduction
Architecture
◼ Programmers Model
Instruction Set

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 Data Sizes and Instruction Sets

◼ The ARM is a 32-bit architecture.

◼ When used in relation to the ARM:

◼ Byte means 8 bits
◼ Halfword means 16 bits (two bytes)
◼ Word means 32 bits (four bytes)

◼ Most ARM’s implement two instruction sets

◼ 32-bit ARM Instruction Set
◼ 16-bit Thumb Instruction Set

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 Processor Modes
◼ The ARM has seven operating modes:

◼ User : unprivileged mode under which most tasks run

◼ FIQ(Fast Interrupt Request) : entered when a high priority (fast) interrupt is

raised

◼ IRQ (Interrupt Request) : entered when a low priority (normal) interrupt is

raised

◼ SVC (SuperVisor Call): entered on reset and when a Software Interrupt

instruction is executed

◼ Abort : used to handle memory access violations

◼ Undef : used to handle undefined instructions

◼ System : privileged mode using the same registers as user mode

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 The Registers

◼ ARM has 37 registers all of which are 32-bits long.

◼ 30 general purpose registers

◼ 1 dedicated program counter
◼ 1 dedicated current program status register
◼ 5 dedicated saved program status registers

◼ The current processor mode governs which of several banks is

accessible. Each mode can access
◼ a particular set of r0-r12 registers
◼ a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
◼ the program counter, r15 (pc)
◼ the current program status register, cpsr

Privileged modes (except System) can also access

◼ a particular spsr (saved program status register)

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 Special Registers

◼ Special function registers:

◼ PC (R15): Program Counter. Any instruction with PC as its destination register
is a program branch

◼ LR (R14): Link Register. Saves a copy of PC when executing the BL instruction

(subroutine call) or when jumping to an exception or interrupt routine
- It is copied back to PC on the return from those routines

◼ SP (R13): Stack Pointer. There is no stack in the ARM architecture. Even so,
R13 is usually reserved as a pointer for the program-managed stack

◼ CPSR : Current Program Status Register. Holds the visible status register

◼ SPSR : Saved Program Status Register. Holds a copy of the previous status
register while executing exception or interrupt routines
- It is copied back to CPSR on the return from the exception or interrupt
- No SPSR available in User or System modes

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 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V undefined I F T mode

f s x c

◼ Condition code flags Interrupt Disable bits.

◼ N = Negative result from ALU I = 1: Disables the IRQ.
◼ Z = Zero result from ALU F = 1: Disables the FIQ.
◼ C = ALU operation Carried out
◼ V = ALU operation oVerflowed
T Bit (Arch. with Thumb mode only)
T = 0: Processor in ARM state
◼ Mode bits
T = 1: Processor in Thumb state
10000 User
10001 FIQ
Never change T directly (use BX instead)
10010 IRQ
Changing T in CPSR will lead to
10011 Supervisor
unexpected behavior due to pipelining
10111 Abort
11011 Undefined
Tip: Don’t change undefined bits.
11111 System
This allows for code compatibility with
newer ARM processors

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 Register Organization Summary
User,
FIQ IRQ SVC Undef Abort
SYS
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
r5 and mode mode mode mode
cpsr r0-r12, r0-r12, r0-r12, r0-r12,
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

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 Addressing Modes

◼ The addressing modes are most conveniently classified with respect to

the type of instruction.
◼ Load/Store Addressing
◼ Data Processing Instruction Addressing
◼ Branch Instruction Addressing
◼ Load/Store Multiple Addressing

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 Load/Store Addressing

Memory is addressed by a register and an offset.

LDR R0, [R1] @ Load the word data from mem[R1] -> R0

Three ways to specify offsets:

❑ Immediate
STRB R0, [R1, #4] ; Load the Byte data from mem[R1+4] -> R0

❑ Register
LDR R0, [R1, R2] ; Load the word data from mem[R1+R2] -> R0

❑ Scaled register
LDR R0, [R1, R2, LSL #2] ; Load the word data from mem[R1+4*R2]
to R0

NB: ‘;’ is used to comment a line

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 Addressing modes

• Pre-index addressing
▪ without a writeback (STRB R0, [R1, #4])
▪ with a writeback (STRB R0, [R1, #4]!)

• Post-index addressing (STRB R0, [R1], #4)

▪ calculation after accessing with a writeback
Addressing modes

(a) Pre-indexing without writeback

(b) Pre-indexing with writeback

Addressing modes

(c) Post-indexing
 Data Processing Addressing

Data processing instructions use either register to address or a mixture of

register and immediate addressing.

ADD R0, R0, R0, LSL #2 Scaled Register addressing

ADD R0, R1, R2 Register

ADD R3, R3, #1 Immediate

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 Branch Instruction Addressing

The only form of addressing for branch instructions is immediate addressing.

The branch instruction contains a 24-bit value.

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 Load/Store Multiple Addressing

Load Multiple instructions load a subset (possibly all) of the general- purpose
registers from memory.

Store Multiple instructions store a subset (possibly all) of the general-purpose

registers to memory.

The list of registers for the load or store is specified in a 16-bit field in the
instruction with each bit corresponding to one of the 16 registers.

Four addressing modes are used : increment after, increment before, decrement
after, and decrement before.

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 Load/Store Multiple Addressing

Load/store a subset of the general-purpose registers from/to

memory.
LDM<suffix> load multiple registers
STM<suffix> store multiple registers

suffix meaning
IA increase after
IB increase before
DA decrease after
DB decrease before
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Load/Store Multiple Addressing

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 ARM Assembly Language
Programming

❏ Outline:

❍ the ARM instruction set

❍ writing simple programs
❍ examples

☞ hands-on: writing simple ARM assembly programs

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 The ARM instruction set

❏ ARM instructions fall into three categories:

❍ data processing instructions

– operate on values in registers
❍ data transfer instructions
– move values between memory and registers
❍ control flow instructions
– change the program counter (PC)

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 The ARM instruction set

❏ ARM instructions fall into three categories:

➜ data processing instructions

– operate on values in registers
❍ data transfer instructions
– move values between memory and registers
❍ control flow instructions
– change the program counter (PC)

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 Data processing instructions

❏ All operands are 32-bits wide and either:

❍ come from registers, or

❍ are literals (‘immediate’ values) specified in the instruction
❏ The result, if any, is 32-bits wide and goes into a register

❍ except long multiplies generate 64-bit results

❏ All operand and result registers are independently specified

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 Data processing instructions

1. Arithmetic Instructions :

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 Data processing instructions

❏ Arithmetic operations:
ADD r0, r1, r2 ; r0 := r1 + r2
ADC r0, r1, r2 ; r0 := r1 + r2 + C
SUB r0, r1, r2 ; r0 := r1 - r2
SBC r0, r1, r2 ; r0 := r1 - r2 + C - 1
RSB r0, r1, r2 ; r0 := r2 - r1
RSC r0, r1, r2 ; r0 := r2 - r1 + C - 1

❍ C is the C bit in the CPSR

❍ the operation may be viewed as unsigned or 2’s complement signed

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 Data processing instructions

2. Logical Instructions :

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 Data processing instructions

❏ Bit-wise logical operations:

AND r0, r1, r2 @ r0 := r1 and r2

ORR r0, r1, r2 @ r0 := r1 or r2
EOR r0, r1, r2 @ r0 := r1 xor r2
BIC r0, r1, r2 @ r0 := r1 and not r2

❍ the specified Boolean logic operation is performed on each bit from 0 to

31
❍ BIC stands for ‘bit clear’
– each ‘1’ in r2 clears the corresponding bit in r1

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 Data processing instructions

3. Move Instructions :

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 Data processing instructions

❏ Register movement operations:

MOV r0, r2 ; r0 := r2
MVN r0, r2 ; r0 := not r2

❍ MVN stands for ‘move negated’

❍ there is no first operand (r1) specified as these are unary operations

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 Data processing instructions

4. Compare Instructions :

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 Data processing instructions

❍ Comparison operations:
CMP r1, r2 ; set cc on r1 - r2

CMN r1, r2 ; set cc on r1 + r2

TST r1, r2 ; set cc on r1 and r2

TEQ r1, r2 ; set cc on r1 xor r2

❍ These instructions just affect the condition codes (N, Z, C, V) in the CPSR

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 Data processing instructions

❏ Immediate operands

❍ The second source operand (r2) may be replaced by a

constant:
ADD r3, r3, #1 ; r3 := r3 + 1
AND r8, r7, #&ff ; r8 := r7

❍ # indicates an immediate value

– & indicates hexadecimal notation
– C-style notation (#0xff) is also supported

❍ Allowed immediate values are (in general): (0 255) x 22n

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 Data processing instructions

5. Shift and Rotate Instructions :

Barrel Shifter

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 Data processing instructions

5. Shift and Rotate Instructions :

Barrel Shifter

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 Data processing instructions

5. Shift and Rotate Instructions :

Barrel Shifter

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 Data processing instructions
❏ Shifted register operands

❍ the second source operand may be shifted

– by a constant number of bit positions:
ADD r3, r2, r1, LSL #3 @ r3 := r2+r1<<3
❍ or by a register-specified number of bits:
ADD r5, r5, r3, LSL r2 @ r5 += r3<<r2
– LSL, LSR mean ‘logical shift left’, ‘logical shift right’
– ASL, ASR mean ‘arithmetic shift left’, ‘ …right’
– ROR means ‘rotate right’
– RRX means ‘rotate right extended’ by 1 bit

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 Data processing instructions

5. Shift and Rotate Instructions :

Barrel Shifter

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 Data processing instructions

❏ Setting the condition codes

❍ All data processing instructions may set the condition codes.

– the comparison operations always do so
❍ For example, here is code for a 64-bit add:
ADDS r2, r2, r0 @ 32-bit carry-out -> C
ADC r3, r3, r1 @ added into top 32 bits
– S means ‘Set condition codes’

❍ The C flag comes from: the adder in arithmetic operations

the shifter in logical operations
❍ the primary use of the condition codes is in control flow
– see later

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 Data processing instructions

6. Multiplication Instructions :

Barrel Shifter

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 Data processing instructions

❏ Multiplication

❍ ARM has special multiplication instructions

MUL r4, r3, r2 ; r4 := (r3 x r2)[31:0]
– only the bottom 32 bits are returned
– immediate operands are not supported
– multiplication by a constant is usually best done with a short
series of adds and subtracts with shifts
❍ There is also a multiply-accumulate form:
MLA r4, r3, r2, r1 ; r4 := (r3xr2+r1)[31:0]
❍ 64-bit result forms are supported too

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 The ARM instruction set

❏ ARM instructions fall into three categories:

❍ data processing instructions

– operate on values in registers
➜ data transfer instructions
– move values between memory and registers
❍ control flow instructions
– change the program counter (PC)

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 Data transfer instructions

❏ The ARM has 3 types of data transfer instructions:

❍ single register loads and stores

– flexible byte, half-word, and word transfers
❍ multiple register loads and stores
– less flexible, multiple words, higher transfer rate
❍ single register - memory swap
– mainly for system use, so ignore it for now

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 Data transfer instructions

❏ The ARM has 3 types of data transfer instructions:

❍ single register loads and stores

– flexible byte, half-word, and word transfers
❍ multiple register loads and stores
– less flexible, multiple words, higher transfer rate
❍ single register - memory swap
– mainly for system use, so ignore it for now

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 Data transfer instructions

❏ Addressing memory

❍ All ARM data transfer instructions use register indirect addressing.

❍ Examples of load and store instructions:

LDR r0, [r1] ; r0 := mem[r1]

STR r0, [r1] ; mem[r1] := r0

❍ Therefore before any data transfer is possible:

a register must be initialized with an address close to the target

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 Data transfer instructions

❏ Single register loads and stores

❍ The simplest form is just registered indirect:

LDR r0, [r1] ; r0 := mem[r1]
❍ This is a special form of base plus offset:
LDR r0, [r1,#4]
; r0 := mem[r1+4]

❍ the offset is within 4 Kbytes

❍ auto-indexing/preindexing is also possible:

LDR r0, [r1,#4]! ; r0 := mem[r1+4]

; r1 := r1 + 4

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 Data transfer instructions

❏ Single register loads and stores (…cntd.)

❍ another form uses post-indexing

LDR r0, [r1],#4 @ r0 := mem[r1]
@ r1 := r1 + 4
❍ finally, a byte or half-word can be loaded instead of a word (with some
restrictions):

LDRB r0, [r1] @ r0 := mem8[r1]

LDRSH r0, [r1] @ r0 := mem16[r1](signed)

❍ stores (STR) have the same forms

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 Data transfer instructions

❏ Initializing an address pointer

❍ any register can be used for an address

❍ the assembler has special ‘pseudo instructions’ to initialize address registers:

ADR r1, TABLE1 @ r1 points to TABLE1

..
@ LABEL
TABLE1

– ADR will result in a single ARM instruction

ADRL r1, TABLE1
– ADRL will handle cases that ADR can’t

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 Data transfer instructions

❏ Multiple register loads and stores

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 Data transfer instructions

❏ Multiple register loads and stores

❍ ARM also supports instructions that transfer several registers:

LDMIA r1, {r0,r2,r5} ; r0 := mem[r1]

; r2 := mem[r1+4]
; r5 := mem[r1+8]
– the {…} list may contain any or all of r0 - r15
– the lowest register always uses the lowest address, and so on, in
increasing order
– it doesn’t matter how the registers are ordered in {…}

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 The ARM instruction set

❏ ARM instructions fall into three categories:

❍ data processing instructions

– operate on values in registers
❍ data transfer instructions
– move values between memory and registers
➜ control flow instructions
– change the program counter (PC)

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Control flow instructions

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 Control flow instructions

❍ Control flow instructions just switch execution around the

program:

❍ normal execution of program is sequential

❍ branches are used to change this

– to move forwards or backwards

❍ Note: data ops and loads can also change the PC!

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 Control flow instructions

❏ Conditional branches

❍ sometimes whether or not a branch is taken depends on the

condition codes:

MOV r0, #0 ; initialise counter

LOOP ..

ADD r0, r0, #1 ; increment counter

CMP r0, #10 ; compare with limit

BNE LOO ; repeat if not equal

.. P ; else continue
– here the branch depends on how CMP sets Z

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 Branch
conditions
Branch Interpretation Normal uses
B BAL Unconditio Always take this branch
nal Always Always take this branch

BEQ Equal Comparison equal or zero result

BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC BLO Carry Arithmetic operation did not give carry-out
clear Unsigned comparison gave lower
Lower

BCS BHS Carry set Arithmetic operation gave carry-out Unsigned

Higher or comparison gave higher or same
same

BVC Overflow clear Signed integer operation; no overflow occurred

BVS Overflow set Signed integer operation; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same
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 “Missing” instructions
Some familiar mnemonics are not present in the ARM instructions:

❍ NOT MVN R0, R0 @ R0 := not(R0)

❍ NEG RSB R0, R0, #0 @ R0 := 0 - R0

❍ RET MOV PC, LR @ ‘Leaf’ return
or (e.g.) LDR PC, [SP], #4 @ Unstack PC
❍ PUSH & POP STMFDSP!, {register list}; Push
LDMFDSP!, {register list}; Pop

❍ LSL, etc. MOV R0, R0, LSL #5

MOV R0, R0, ASR R1

– Note that the shift can be combined with other operations too.