National Cheng-Kung University

Department of Electrical Engineering

Final Exam
LOGIC SYSTEM
Spring of 2022
1. [15%]
(a) [12%] Design a counter with the sequence below by using the J-K flip-flop. (Note: Write
your answer in the form of input equation)
Q2Q1Q0 : 111,011,001,010,101,100,110,111,011,…
(b) [3%] According to part (a) construct the circuit of the counter

Ans:
(a) (b)
JQ2 = Qo’, KQ2 = Q1Q0
JQ1 = Q2’ + Q0’, KQ1 = Q2’
JQ0 = Q1, KQ0 = Q1’
2. [6%] Assume the propagation delays and setup times for the J-K flip-flops are 5 ns and 3 ns,
respectively. For the circuit below, assume the delays of the NAND gates and NOR gates are 3
ns, and assume the delay of the inverter is 1 ns. Answer the following questions.

(a) [3%] What is the minimum clock period for this circuit, if X is changed early enough?
(b) [3%] The clock skew causes CLK edge of flip-flop B arrives 1ns earlier than CLK edge of
flip-flop A. What is the new minimum clock period?

Ans:
(a) 5 + (3 + 3) + 3 = 14
(b)14 + 1 = 15
3. [9%] A L-H flip-flop behaves as follows:
If LH = 11, the flip-flop is set to Q = 0.
If LH = 00, the flip-flop is set to Q = 1.
If LH = 01, the flip-flop changes state.
The input combination LH = 10 is not allowed.
(a) [3%] Give the characteristic (next-state) equation for this flip-flop.
(b) [3%] Complete the table, using don’t-cares where possible.

(c) [3%] Realize the following next-state equation for Q using a LH flip-flop:
Q+ = CQ + DQ’. Find equations for L and H.
Ans:
(a)
Q Q+
LH=00 LH=01 LH=11 LH=10
0 1 1 0 X
1 1 0 0 X Q+ = H’+Q’L’
(b)
QQ+ LH
00 11
01 0X
10 X1
11 00

(c)
Q Q+ Q LH
CD=00 CD=01 CD=11 CD=10 CD=00 CD=01 CD=11 CD=10
0 0 1 1 0 0 11 0X 0X 11
1 0 0 1 1 1 X1 X1 00 00

L = D’Q’
H = C’ + Q’
4. [20%]
The Mearly machine is shown below with input/output format as X1X2/Z1Z2Z3 , and S0 = 00(Q1Q2),
S1 = 01 , S2 = 10 , S3 = 11
4.
(a) [7%] For S0 = 00(Q1Q2), S1 = 01 , S2 = 10 , S3 = 11, complete the truth table of the ROM
required to implement the function of this state machine. Arrange the parameters as specified
below.
Ans：
4.
(b) [3%] Based on the state graph, please complete the output sequences of the following example
with the assumption that Q1 = 0, Q2 = 1 initially.

Ans：
4.
(c) [10%] If we modify the design by removing the output Z1 and reduce the state table to a minimum
number of states, show the reduced state table and the new state graph of the modified design.
Ans：
5. [10%]
For the state diagram is given in the following, derive the state input, state output equation and excita
tion table of these JKFFs
Ans：
6. [15%] Please answer the following question.
(a)Reduce the state table using implication chart.
(b)List each pair of equivalent state.
Present Next state, Next state,
state x=0 x=1 x=0 x=1
a d b 0 0
Ans. b b a 0 0
(a) c h f 0 1
Present Next state, Next state, d a d 1 0
state x=0 x=1 x=0 x=1 e a d 1 0
a d b 0 0
b b a 0 0
f c b 0 0
c D f 0 1 g b f 1 1
d a d 1 0 h a e 1 0
f c b 0 0
g b f 1 1

(b)
𝑑 ≡ 𝑒 ≡ ℎ 𝑜𝑟 (𝑑, 𝑒, ℎ)
7. [15%] Please answer the following question using the incompletely specified state table below.
(a) Reduce the state table to four states in two different ways by filling in the don’t care in the state table in
different ways.
(b)Show that your two state tables in (a) are not equivalent by giving a short input sequence which gives different
outputs for the two state tables.

Ans. Present Next state, Present output,

(a) state x=0 x=1 x=0 x=1
Set don’t care to 0, so 𝑆2 ≡ 𝑆4 ≡ 𝑆5
S0 S1 S5 0 0
S1 S3 S2 1 1
S2 S2 S4 0 1
S3 S4 S2 1 1
S4 S4 S2 - 1
Set don’t care to 1, , so 𝑆1 ≡ 𝑆3 ≡ 𝑆4 S5 S5 S2 0 1
7. [15%] Please answer the following question using the incompletely specified state table below.
(a) Reduce the state table to four states in two different ways by filling in the don’t care in the state table in
different ways.
(b)Show that your two state tables in (a) are not equivalent by giving a short input sequence which gives different
outputs for the two state tables.

Ans. Present Next state, Present output,

(b) state x=0 x=1 x=0 x=1
(just example, there are more than one answer)
S0 S1 S5 0 0
X =1 0
Z =0 1 S1 S3 S2 1 1
Z1=0 0 S2 S2 S4 0 1
S3 S4 S2 1 1
S4 S4 S2 - 1
S5 S5 S2 0 1
8. A Universal Serial Bus (USB) communication link requires a circuit that produces the sequence
00000001. Please design a synchronous sequential circuit that starts producing this sequence for
input X = 1. Once the sequence starts, it completes. If X = 1, during the last output in the sequence,
the sequence repeats. Otherwise, if X = 0, the output remains constant at 1.
(a) Draw the state table and make a state assignment.
Ans :

X=0 X=1 Z
(b) Design the circuit using D flip-flops and logic gates.
Ans :

𝐗′
𝐗′
𝐗′
X
9. [10%] The iterative circuit below the input x is a 2’s complement number and the output z is the
2’s complement of x. (𝑥0 and 𝑧0 are the least significant bits.)
(a) [5%] Construct a transition table for typical cell. (Note that 𝑐0 is 0.)
(b) [5%] Derive expressions for 𝑐𝑖+1 and 𝑧𝑖

Cell Cell Cell

n1 i 0
Ans:
(a)
𝑐𝒊+𝟏 𝒛𝒊
𝑐𝒊
𝑥𝒊 = 𝟎 𝑥𝒊 = 𝟏 𝑥𝒊 = 𝟎 𝑥𝒊 = 𝟏
0 0 1 0 1
1 1 1 1 0

(b) 𝑐𝑖+1 = 𝑐𝑖 + 𝑥𝑖
𝑧𝑖 = 𝑐𝑖 ⨁𝑥𝑖