LTC2952

Pushbutton PowerPath
Controller with Supervisor
FEATURES DESCRIPTION
n Pushbutton On/Off Control The LTC®2952 is a power management device that features
n Automatic Low Loss Switchover Between DC three main functions: pushbutton on/off control of system
Sources power, ideal diode PowerPath™ controllers and system
n Wide Operating Voltage Range: 2.7V to 28V monitoring. The LTC2952’s pushbutton input, which pro-
n Low 25μA Shutdown Current vides on/off control of system power, has independently
n Guaranteed Threshold Accuracy: ±1.5% of adjustable ON and OFF debounce times. A simple micro-
Monitored Voltage Over Temperature processor interface involving an interrupt signal allows
n Adjustable Pushbutton On/Off Timers for proper system housekeeping prior to power-down.
n Simple Interface Allows Graceful μP Shutdown
n
The ideal diode PowerPath controllers provide automatic
Extendable Housekeeping Wait Time Prior to
low loss switchover between two DC sources by regulating
Shutdown
n
two external P-channel MOSFETs to have a small 20mV
200ms Reset Delay and 1.6s Watchdog Timeout
forward drop.
n ±8kV HBM ESD on PB Input
n 20-pin TSSOP and QFN (4mm × 4mm) Packages High reliability systems may utilize the LTC2952’s monitor-
ing features to ensure system integrity. These features in-
clude: power-fail, voltage monitoring and μP watchdog.
APPLICATIONS
The LTC2952 operates over a wide operating voltage range
n Desktop and Notebook Computers to accommodate a large variety of input power supplies. The
n Portable Instrumentations part’s combination of low 20mV external MOSFET regula-
n Cell Phones, PDA and Handheld Computers tion and very low standby current matches battery powered
n Servers and Computer Peripherals and power conscious application requirements.
n Battery Backup Systems L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.

TYPICAL APPLICATION
Pushbutton Controller with Automatic Switchover Between Adapter and Battery Ideal Diode vs Schottky Diode
Forward Voltage Drop
ADAPTER, 3V TO 25V 2.5V 1
VIN VOUT
Si6993DQ
LT1767-2.5 CONSTANT
1k 10k RON
SHDN
12V BATTERY Si6993DQ 365k 1k
511k
CURRENT (A)

1k
G1 VS
100k
G2 PFI IDEAL
D2 DIODE
V1 EN ** CONSTANT
LTC2952 100k D3 VOLTAGE SCHOTTKY
V2 VM DIODE
D1
RST
M1 G1STAT
PFO 0
M2 μP 0.02 0.50
INT FORWARD VOLTAGE (V)
PB KILL 2952 TA01b

ONT GND OFFT WDE

*22nF *68nF *OPTIONAL
**SHDN INTERNALLY PULLED UP BY THE LT1767-2.5 2952 TA01

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LTC2952
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)

Supply Voltages Input Currents

V1, V2, VS .............................................. –0.3V to 30V PB .......................................................–1mA to 100μA
Input Voltages Operating Temperature Range
PB .................................... –6V to MAX (V1, V2, VS) V LTC2952C ................................................ 0°C to 70°C
ONT, OFFT ............................................... –0.3V to 3V LTC2952I .............................................–40°C to 85°C
M1, M2, PFI, VM, WDE, KILL ................... –0.3V to 7V Storage Temperature Range .................. –65°C to 150°C
Output Voltages Lead Temperature (Soldering, 10 sec)................... 300°C
G1, G2, EN .................... –0.3V to MAX (V1, V2, VS) V
G1STAT, PFO, RST, INT ............................ –0.3V to 7V

PIN CONFIGURATION
TOP VIEW
TOP VIEW

G1STAT
KILL
M1
M2

G1
M2 1 20 G1STAT
M1 2 19 G1 20 19 18 17 16
KILL 3 18 V1
VM 1 15 V1
VM 4 17 VS
PFI 2 14 VS
PFI 5 16 V2
WDE 3 21 13 V2
WDE 6 15 G2
PB 4 12 G2
PB 7 14 EN
RST 5 11 EN
RST 8 13 INT
PFO 9 12 GND 6 7 8 9 10
ONT 10
PFO
ONT
OFFT
GND
INT
11 OFFT

F PACKAGE UF PACKAGE
20-LEAD PLASTIC TSSOP 20-LEAD (4mm s 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 90°C/W
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 21), PCB GND CONNECTION OPTIONAL

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2952CF#PBF LTC2952CF#TRPBF LTC2952CF 20-Lead Plastic TSSOP 0°C to 70°C
LTC2952IF#PBF LTC2952IF#TRPBF LTC2952IF 20-Lead Plastic TSSOP –40°C to 85°C
LTC2952CUF#PBF LTC2952CUF#TRPBF 2952 20-Lead 4mm × 4mm Plastic QFN 0°C to 70°C
LTC2952IUF#PBF LTC2952IUF#TRPBF 2952 20-Lead 4mm × 4mm Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LTC2952
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VMAX Operating Supply Voltage V1, V2 or VS l 2.7 28 V
IIN_OFF Quiescent Supply Current Both Ideal V1 = 2.7V to 28V, V2 = 0V, VS = Open or l 24 60 μA
Diodes Switched Off V2 = 2.7V to 28V, V1 = 0V, VS = Open.
(M1 = Open, M2 = 0V) Measured Current at V1 or V2.
V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. l 5 15 μA
Measured Current at V1.
V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. l 23 50 μA
Measured Current at V2.
IIN_ON Quiescent Supply Current Both Ideal V1 = VS = 2.7V to 28V, V2 = 0V or l 65 170 μA
Diodes Switched On V2 = VS = 2.7V to 28V, V1 = 0V. Measured
(M1 = 0V, M2 = 0V) Combined Current at V1 and VS or V2 and VS.
V2PREF_TH V2 Preferential Threshold Voltage V1 = 28V, VS = Open. l 3.3 3.8 V
(M1 = Open, M2 = 0V) (Note 4)
ILEAK V1, V2 and VS Inter Pin Leakage to V1 = 28V, V2 = VS = 0V; V1 = VS = 0V, ±3 μA
the Highest Supply V2 = 28V; V1 = V2 = 0V, VS = 28V
Ideal Diode Function
VFR Ideal Diode PowerPath Forward (V1 or V2) – VS, 2.7V ≤ (V1 or V2) ≤ 28V l 10 20 35 mV
Regulation Voltage
VRTO Ideal Diode PowerPath Fast Reverse (V1 or V2) – VS, 2.7V ≤ (V1 or V2) ≤ 28V l –20 –35 –64 mV
Turn-Off Threshold Voltage ∆IG ≤ –100μA/mV
IG(SRC) Gate Turn-Off Current G1 = G2 = VMAX – 1.5V l –2 –5 –10 μA
IG(SNK) Gate Turn-On Current V1 = V2 = 2.7V to 28V, l 2 5 10 μA
VS = (V1 or V2) – 40mV,
G1 = G2 = VMAX –1.5V.
IG(FASTSRC) Gate Fast Turn-Off Source Current V1 = V2 = 2.7V to 28V, l –0.5 –2.5 –10 mA
VS = (V1 or V2) + 0.1V,
G1 = G2 = VMAX –1.5V.
IG(FASTSNK) Gate Fast Turn-On Sink Current V1 = V2 = 5V to 28V, l 0.3 0.7 2 mA
VS = (V1 or V2) – 0.1V,
G1 = G2 = VMAX – 1.5V.
VG(ON) Gate Clamp Voltage IGX = 2μA, VX = 8V to 28V, VS = VX – 0.1V l 6 7 8 V
Measure VX – VGX
VG(OFF) Gate Off Voltage IGX = –2μA, VX = 2.7V to 28V, VS = VX + 0.1V l 0.2 0.4 V
Measure VMAX – VGX
tG(ON) Gate Turn-On Time VG(OFF) to VGS ≤ –3V, CGATE = 1nF (Note 5), 0.1 2.5 10 μs
V1 = V2 = 12V
tG(OFF) Gate Turn-Off Time VG(ON) to VGS ≥ –1.5V, CGATE = 1nF (Note 6), 0.1 2.5 10 μs
V1 = V2 = 12V
Pushbutton Pin (PB)
VPB(VOC) PB Open-Circuit Voltage IPB = –1μA l 1 4 6 V
IPB PB Input Current VPB(VOC) < VPB ≤ 28V l ±1 μA
0V ≤ VPB < VPB(VOC) l –1 –10 –25 μA
VTH_PB PB Input Threshold Voltage PB Falling From High to Low l 0.65 0.77 0.8 V
VHYS_PB PB Input Hysteresis l 10 25 150 mV

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LTC2952
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V TO 28V unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Debounce Time Pins (ONT, OFFT)
IONT,OFFT ONT/OFFT Pull-Up/Pull-Down Current VONT, VOFFT = 0V (Pull-Up), VONT, VOFFT = 1.5V l ±1.6 ±2.0 ±2.4 μA
When Timer Is Active (Pull-Down)
tDB,ON/OFF Internal Default On-Time/Off-Time tDB,ON: CONT = Open, Measured Time Between l 18 26 34 ms
PB Low → EN High, tDB,OFF: Measured Time
Between PB Low → INT Low
tONT,OFFT Additional Adjustable Turn-On/Turn- CONT = 1500pF, COFFT = 1500pF l 10 15 20 ms
Off Time (Note 7)
Accurate Comparator Input Pins (VM, PFI, M1, M2, KILL)
VTH_VM VM Input Reset Threshold Both Falling and Rising l 0.492 0.500 0.508 V
VTH PFI, M1, M2, KILL Input Threshold Falling l 0.492 0.500 0.508 V
Voltage
VHYS PFI, M1, M2, KILL Input Hysteresis l 5 15 25 mV
IIN_LKG VM, PFI, M2, KILL Input Current V = 0.5V l ±0.1 μA
IM1_SRC M1 Input Pull-Up Current M1 = 1V l –1.5 –3 –5 μA
VM1(VOC) M1 Voltage Open-Circuit l 1 4 6 V
IM1_LKG M1 Input Leak Current M1 = 6V l ±0.1 μA
Watchdog/Extend Pin (WDE)
VWDE(H,TH) Input High Threshold Voltage l 1.5 V
VWDE(L,TH) Input Low Threshold Voltage l 0.3 V
IWDE(IN,HL) High Low Input Current (Note 8) l ±25 μA
IWDE(IN,HZ) Hi-Z Input Current VWDE = 0.7V, 1.1V l ±10 μA
Open-Drain Output Pins (G1STAT, INT, RST, PFO)
IOUT_LKG Leakage Current VPIN = 5V l ±1 μA
VOL Voltage Output Low IPIN = 1mA l 0.4 V
High Voltage Open-Drain Output Pin (EN)
IEN(LKG) EN Leakage Current VEN = 28V, EN Sink Current Off l ±1 μA
VEN(VOL) EN Voltage Output Low IEN = 3mA l 0.4 V
V1 = 1.2V and/or V2 = 1.2V, IEN = 100μA l 0.05 0.3 V
Voltage Monitor/Watchdog Timing
tRST Reset Timeout Period l 140 200 260 ms
tWDE Watchdog Timeout Period l 1.1 1.6 2.1 s
tWDE(PW MIN) Minimum Period Between l 5 10 μs
Consecutive Edges
tVM(UV) VM Undervoltage Detect to RST VM Less Than VTH_VM by More Than 1% 150 μs
tPFI PFI Delay to PFO PFI More or Less Than VPFI_TH by More 150 μs
Than 1%

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 LTC2952
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
μP Handshake Timing
tINT(MIN) INT Minimum Pulse Width Minimum Measured Time PB Rising to l 10 50 250 μs
INT Rising
tKILL(PW) KILL Minimum Pulse Width Full Swing Pulse From 5V to 0V l 150 500 μs
tKILL,ON BLANK KILL On Blanking (Note 9) KILL = 0V, Measured Time Between EN Rising l 270 400 530 ms
→ EN Falling
tKILL, OFF WAIT KILL Wait Time (Note 10) KILL = 1V, COFFT = OPEN, Measured Time l 270 400 530 ms
Between INT Falling → EN Falling
tEN, LOCKOUT Enable Lockout Time (Note 11) Measured Time Between EN Falling → EN l 270 400 530 ms
Rising

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 8: The input current to the three-state WDE pin are the pull-up
may cause permanent damage to the device. Exposure to any Absolute and the pull-down current when the pin is either set to 3.3V or GND,
Maximum Rating condition for extended periods may affect device respectively. In the open state, the maximum pull-up or pull-down leakage
reliability and lifetime. current permissible is 10μA.
Note 2: The greatest of V1, V2 or VS is the internal supply voltage (VMAX). Note 9: The turn-on KILL blanking time is the waiting period immediately
Note 3: All currents into pins are positive; all voltages are referenced to following the EN pin switching high; at the end of this period the input
GND unless otherwise noted. to the KILL needs to be high to indicate that the system has powered up
Note 4: V2PREF_TH is the minimum voltage level at which V2 becomes properly, otherwise the EN pin is immediately switched low.
the preferential source of quiescent current when both of the ideal diodes Note 10: The KILL wait time during the power-down process is the wait
are off. period immediately following a valid turn-off command until the EN pin
Note 5: VS is stepped from (V1 or V2) + 0.2V to (V1 or V2) – 0.2V to switches low.
trigger the event. The gate voltages are initially VG(OFF). Note 11: The enable lockout time is the minimum wait time between the
Note 6: VS is stepped from VX – 0.2V to VX + 0.2V to trigger the event. last falling edge and the next rising edge on the EN pin.
Gate voltages are initially clamped at VG(ON).
Note 7: The adjustable turn-on and turn-off timer period is the adjustable
debounce period following the Internal default-on and default-off timer
period, respectively.

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LTC2952
TIMING DIAGRAMS
Ideal Diode Function – Gate Turn-On and Turn-Off Time
12.2V 12.2V

VS 12V 11.8V 12V

12.05V 12.05V
VGX 9V 10.5V
5.3V
VX = 12V 2952 TD01
tG(ON) tG(OFF)

Pushbutton Debounce Times, KILL Wait Time and Enable Lockout Time with KILL Above Threshold

PB 0.775V

EN 0.5*VPULL-UP

INT 0.5*VPULL-UP

tDB,ON
tONT t < tOFFT tOFFT tKILL, OFF WAIT t > tONT
tDB,OFF tDB,OFF tDB,ON
tINT(MIN)
tEN, LOCKOUT 2952 TD02

KILL On Blanking with KILL Below Threshold

KILL

EN 0.5*VPULL-UP 0.5*VPULL-UP

2952 TD03
tKILL, ON BLANK

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 LTC2952
TIMING DIAGRAMS
PFI and PFO

PFI 0.515V 0.500V

PFO 0.5*VPULL-UP 0.5*VPULL-UP

2952 TD04
tPFI tPFI

WDE Minimum Pulse Width

WDE

tWDE(PW MIN) 2952 TD05

VM, WDE and RST

VM

DON'T
WDE DON'T CARE DON'T CARE DON'T CARE
CARE

RST

tRST tWDE tRST <tWDE tWDE <tRST tRST <tWDE <tWDE tRST <tWDE 2952 TD06
tVM(UV)
200ms 1.6s 200ms 1.6s 200ms 200ms

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LTC2952
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

IIN-OFF vs Input Supply Voltage at IIN-ON vs Input Supply Voltage at V2 Preferential Threshold
Different Temperatures Different Temperatures vs Temperature
50 110 3.5
130°C V1 = VS = VIN, V2 = 0V OR V1 = 28V, VS = OPEN
V2 = VS = VIN, V1 = 0V 130°C
100
90°C 3.4
40 90°C
90
25°C

V2 PREF_TH (V)
IIN_OFF (μA)

IIN_ON (μA)
80 25°C 3.3
30 –45°C
70
–60°C –45°C 3.2

60 –60°C
20
V1 = VIN, V2 = 0, VS = OPEN OR 3.1
V2 = VIN, V1 = 0,VS = OPEN 50
M1 = OPEN, M2 = 0V
10 40 3.0
0 5 10 15 20 25 30 0 5 10 15 20 25 30 –50 –25 0 25 50 75 100 125
INPUT SUPPLY VOLTAGE VIN (V) INPUT SUPPLY VOLTAGE VIN (V) TEMPERATURE (°C)
2952 G01 2952 G02 2952 G03

Worst Case Supply to Supply ONT/OFFT Pull-Up/Pull-Down

Leakage vs Temperature PB Current vs PB Voltage Current vs Temperature
1000 20 2.4
V2 = VS = 0V, V1 = 28V V1 = V2 = VS = 28V
V1 = VS = 0V, V2 = 28V
0
V1 = V2 = 0V, VS = 28V
2.2
–20
100
IONT, OFFT (μA)
ILEAK (nA)

–?40
IPB (μA)

2.0
–60
10
–80 1.8

–100

1 –120 1.6
–50 –25 0 25 50 75 100 125 –10 –5 0 5 10 15 20 25 30 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) PB VOLTAGE (V) TEMPERATURE (°C)
2952 G04 2952 G05 2952 G06

Total Turn-On/Turn-Off Time vs KILL, PFI, M1 and M2 Falling Input VM Input Reset Threshold Voltage
ONT/OFFT Capacitors Value Threshold Voltage vs Temperature vs Temperature
10000 0.508 0.508

0.506 0.506
tDB, ON/OFF + tONT, OFFT (ms)

0.504 0.504
1000
0.502 0.502
VTH_VM (V)
VTH (V)

0.500 0.500

0.498 0.498
100
0.496 0.496

0.494 0.494

10 0.492 0.492
0.1 1 10 100 1000 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
CONT/COFFT (nF) TEMPERATURE (°C) TEMPERATURE (°C)
2952 G07 2952 G08 2952 G09
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 LTC2952
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Typical Transient Duration KILL On Blanking, KILL Wait Time, Reset Timeout Period
vs Comparator Overdrive Enable Lockout Time vs Temperature vs Temperature at Different
(VM, KILL, PFI, M1 and M2) at Different Input Voltages Input Voltages
10 480 260

tKILL, ON BLANK/tKILL, OFFWAIT/tEN, LOCKOUT (ms)

TYPICAL TRANSIENT DURATION (ms)

240
440 V1 = V2 = VS = 28V
1 220 V1 = V2 = VS = 28V

tRST (ms)
COMPARATOR TRIPS
ABOVE CURVE 400 200
V1 = V2 = VS = 2.7V
V1 = V2 = VS = 2.7V 180
0.1
360
160

0.01 320 140

0.01 0.1 1 10 100 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
COMPARATOR OVERDRIVE VOLTAGE (% OF VTH) TEMPERATURE (°C) TEMPERATURE (°C)
2952 G11 2952 G12
2952 G10

Watchdog Time Period G1STAT, PFO, INT and RST Voltage

vs Temperature at Different G1STAT, PFO, INT and RST Pull- Output Low vs Pull-Down Current
Input Voltages Down Current vs Supply Voltage at Different Temperatures
2.0 5.0 2.5
V1 = V2 = VS = VMAX V1 = V2 = VS = 12V

PIN AT 150mV 130°C

4.0 2.0
PULLDOWN CURRENT (mA)

1.8 90°C
V1 = V2 = VS = 28V
25°C
3.0 1.5
tWDE (s)

VOL (V)

1.6 –45°C
2.0 1.0 –60°C
V1 = V2 = VS = 2.7V

1.4 PIN AT 50mV

1.0 0.5

1.2 0 0
–50 –25 0 25 50 75 100 125 0 5 10 15 20 25 30 0 5 10 15 20 25 30
TEMPERATURE (°C) SUPPLY VOLTAGE - VMAX (V) PULL DOWN CURRENT (mA)
2952 G13 2952 G14 2952 G15

EN Voltage Output Low

EN Pull-Down Current EN Pull-Down Current vs Pull-Down Current at
vs Supply Voltage vs Supply Voltage Different Temperatures
10 10000 2.5
V1 = V2 = VS = VMAX V1 = V2 = VS = VMAX V1 = V2 = VS = 12V
EN AT 150mV EN AT 150mV 130°C
1000
8 2.0
PULLDOWN CURRENT (mA)

PULLDOWN CURRENT (μA)

100 90°C
EN AT 50mV
VEN (VOL) (V)

6 1.5
10
25°C

4 1 1.0
–45°C
EN AT 50mV
0.1 –60°C
2 0.5
0.01

0 0.001 0
0 5 10 15 20 25 30 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 10 20 30 40 50 60 70
SUPPLY VOLTAGE - VMAX (V) SUPPLY VOLTAGE - VMAX (V) PULL DOWN CURRENT (mA)
2952 G16 2952 G17 2952 G18
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LTC2952
PIN FUNCTIONS (TSSOP/QFN)

EN (Pin 14/Pin 11): DC/DC Enable Output. This pin is a GND (Pin 12/Pin 9): Device Ground.
high voltage open-drain pull-down used to control system
INT (Pin 13/Pin 10): Interrupt Output. This pin is an
power. EN pin goes high impedance after an initial turn-on
open-drain pull-down pin used to signal the system that
command (via either the digital on or a valid pushbutton
a power shutdown is imminent. The INT pin asserts low
on—refer to the Applications Information section). EN pin
26ms after the initial falling edge of the pushbutton off
pulls low at the end of a valid power-down sequence, or
event and during the power-down sequence. Leave this
when KILL pin is driven low anytime after a valid power-up
pin open or tied to GND if interrupt signal is unused.
sequence.This pin can connect directly to a DC/DC converter
shutdown pin that provides an internal pull-up. Otherwise KILL (Pin 3/Pin 20): System Power Shutdown Input. Set-
a pull-up resistor to an external supply is required. The ting this pin low asserts the EN pin low. In modes where
voltage can not exceed the absolute maximum voltage of M1 is above threshold, setting this pin low also shuts
both the pin and the circuit it is driving. off the ideal diodes. During system turn-on, input to this
pin is ignored until 400ms (tKILL,ON BLANK) after the EN
Exposed Pad (Pin 21, QFN Package): The exposed pad pin first becomes high impedance. This pin has an accu-
may be left open or connected to device ground. rate 0.5V falling threshold and can be used as a voltage
G1 (Pin 19/Pin 16): Primary P-Channel MOSFET Gate Drive monitor input.
Output. When the primary ideal diode function is enabled M1 (Pin 2/Pin 19): Mode Select Input 1. Input to an ac-
and in regulation, the ideal diode controller drives this pin curate comparator with 0.5V falling threshold and 15mV
to maintain a forward voltage (VFR) of 20mV between the hysteresis. Has a 3μA internal pull-up to an internal supply
V1 and VS pins. When another power source is driving
(4V). Together with M2 determines the ideal PowerPath and
the VS pin, causing the voltage level at the VS pin to be
on/off control behavior of the part. Refer to the Operation
greater than the voltage level at the V1 pin or when the
and Applications Information sections for configurations
primary ideal diode driver is disabled via the mode select
based on the voltage levels at M1 and M2.
input pins, this pin pulls up to the MAX (V1, VS) voltage,
turning off the primary P-channel power switch. Leave this M2 (Pin 1/Pin 18): Mode Select Input 2. High imped-
pin open when primary ideal diode function is not used. ance input to an accurate comparator with 0.5V falling
threshold and 15mV hysteresis. When M1 is low, M2
G1STAT (Pin 20/Pin 17): Open-Drain Primary Ideal Diode
controls whether the primary (G1) ideal diode function
Status Output. When the primary P-channel power switch
is enabled. When M1 is high, M2 acts as a digital on/off
is off, the G1STAT pin will go from an open state to a strong
control input: A rising edge on this pin is interpreted as
pull-down. This pin can be used to signal the state of the
a turn-on command and a falling edge is interpreted as
primary ideal diode PowerPath to a microcontroller. Leave
a turn-off command. Refer to the Operation and Applica-
this pin open or tied to GND when unused.
tions Information sections for configurations based on
G2 (Pin 15/Pin 12): Secondary P-Channel MOSFET Gate the voltage levels at M1 and M2.
Drive Output. When the secondary ideal diode function
OFFT (Pin 11/Pin 8): Off Timing Input. Attach 110pF
is enabled and in regulation, the ideal diode controller
of external capacitance (C OFFT) to GND for each
drives this pin to maintain a forward voltage (VFR) of 20mV additional millisecond of turn-off debounce time
between the V2 and VS pins. When another power source
beyond the internally set 26ms. Leave open if additional
is driving the VS pin, causing the voltage level at the VS
debounce time is not needed.
pin to be greater than the voltage level at the V2 pin or
when the secondary ideal diode driver is disabled via the ONT (Pin 10/Pin 7): On Timing Input. Attach 110pF of
mode select input pins, this pin pulls up to the MAX (V2, external capacitance (CONT) to GND for each additional
VS) voltage, turning off the secondary P-channel power millisecond of turn-on debounce time beyond the inter-
switch. Leave this pin open when secondary ideal diode nally set 26ms. Leave open if additional debounce time
function is not used. is not needed.
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 LTC2952
PIN FUNCTIONS (TSSOP/QFN)

PB (Pin 7/Pin 4): Pushbutton Input. Input to a comparator inherent high source impedance). Otherwise, an optional
with 0.775V falling threshold and 25mV hysteresis. PB has bypass capacitor to ground in the range of 0.1μF to 10μF
a 10μA internal pull-up to an internal supply (4V). This can be used.
pin provides on/off power supply control via the EN pin,
V2 (Pin 16/Pin 13): Secondary Input Supply Voltage:
which is typically connected to an external DC/DC con-
2.7V to 28V. Supplies power to the internal circuitry and
verter. Setting the PB pin low for a time determined by the
is the anode input of the secondary ideal diode driver (the
ONT timing capacitor toggles the EN pin high impedance.
cathode input to the ideal diode drivers is the VS pin). A
Letting this pin toggle high and then setting this pin low
secondary power source such as a wall adapter, usually
again for 26ms asserts INT low. After the INT pin asserts
provides power to this input. Minimize the capacitance on
low, if the PB pin is still held low for a time determined by
this pin in applications where the pin can be high imped-
the OFFT timing capacitor, the process of turning off the
ance (disconnected or inherent high source impedance).
system power begins. At the end of the turn-off process,
Otherwise, an optional bypass capacitor to ground in the
the EN pin is set low. Leave this pin open if pushbutton
range of 0.1μF to 10μF can be used.
function is not used.
VM (Pin 4/Pin 1): Voltage Monitor Input. High impedance
PFI (Pin 5/Pin 2): Power Fail Input. High impedance input
input to an accurate comparator with a 0.5V threshold.
to an accurate comparator with a 0.5V falling threshold
Together with the WDE pin controls the state of the RST
and 15mV hysteresis. This pin controls the state of the
output pin. Tie to device GND if voltage monitoring func-
PFO output pin. Tie to device GND if power fail monitoring
tion is not used.
function is not used.
VS (Pin 17/Pin 14): Power Sense Input. This pin supplies
PFO (Pin 9/Pin 6): Power Fail Output. This pin is an open-
power to the internal circuitry and is the cathode input to
drain pull-down which pulls low when the PFI input is
the ideal diode drivers (the anode inputs to the ideal diode
below 0.5V. Leave this pin open or tied to GND if power
drivers are the V1 and V2 pins). Bypass this pin to ground
fail monitoring function is not used.
with one or more capacitors of at least 0.1μF.
RST (Pin 8/Pin 5): Reset Output. This pin is an open-drain
WDE (Pin 6/Pin 3): Watchdog/Extend Input. A three-state
pull-down. Pulls low when VM input is below 0.5V and
input pin. A rising or falling edge must occur on this pin
held low for 200ms after VM input is above 0.5V. Also
within a 1.6s watchdog timeout period (while the RST
pulls low for 200ms when the watchdog timer (1.6s) is
output is high impedance), to prevent the RST pin from
allowed to time out. Leave this pin open or tied to GND if
going low. The watchdog function of this pin is disabled
voltage monitoring function is not used.
when both of the ideal diode drivers are disabled in
V1 (Pin 18/Pin 15): Primary Input Supply Voltage: 2.7V certain PowerPath configurations (refer to the Applica-
to 28V. Supplies power to the internal circuitry and is the tion Information section). During a shutdown process: a
anode input of the primary ideal diode driver (the cathode rising or falling edge on this WDE pin within the 400ms
input to the ideal diode drivers is the VS pin). A battery or tKILL,OFF WAIT period extends the waiting period another
other primary power source usually provides power to this 400ms before the EN line is set low. This extend process
input. Minimize the capacitance on this pin in applications can be repeated indefinitely in order to provide as much
where the pin can be high impedance (disconnected or time as possible for the microprocessor to do its house-
keeping functions before a power shutdown. Leave open
or drive in Hi-Z state with a three-state buffer to disable
watchdog or extend function or both.

2952fb

11
LTC2952
BLOCK DIAGRAM
SECONDARY SUPPLY TO LOAD PRIMARY SUPPLY

V2 VS V1

IDEAL DIODE DRIVER 2 VIN VS V2 VS V1 VS VIN IDEAL DIODE DRIVER 1

– + – +
A2 A1

GATE LINEAR GATE LINEAR GATE GATE

ANALOG ANALOG
DRIVER AND DRIVER AND
CONTROLLER LDO/BAND GAP CONTROLLER
G2 VOLTAGE CLAMP VOLTAGE CLAMP G1
REF STAT
ON/OFF
G1STAT
VCC 0.5V 0.775V
INTERNAL INTERNAL
ENABLE ENABLE

– CP4 CP5 –
KILL VCC M2
+ +
0.5V 0.5V
3μA

VCC PUSHBUTTON
DETECT CP3 –
10μA LOGIC M1
+
0.5V
– CP6

PB 200μS
FILTER GND
+
0.775V

EN
PUSH-BUTTON
OSCILLATOR
ONT

OFFT INT

MONITORS
THREE-STATE/
EDGE DETECTOR CP2 +
WDE 0.5V
+ CP1
0.5V
–
– 200ms RST DELAY/
PFI
1.6s WATCHDOG TIMER
VM
PFO

RST

2952 BD
2952fb

12
 LTC2952
OPERATION
The LTC2952 is designed to simplify applications requiring RST and PFI, PFO pins. The voltage monitoring (VM) and
management of multiple power sources. The three main the watchdog (WDE) input pins determine the state of the
features of the part are: pushbutton control, ideal diode RST output with 200ms reset time and 1.6s watchdog
PowerPath controllers and system monitoring. The Block time. The PFI and PFO pins are the input and output of an
Diagram on the previous page shows the part divided into accurate comparator that can be used as an early power
its main functional blocks. fail monitor.
The pushbutton detect block is responsible for debouncing The KILL, M1 and M2 pins are the inputs to accurate
any pushbutton event on the PB pin. Note that the ON and comparators with 0.5V threshold. The outputs of these
OFF debounce times can be configured independently by comparators interact with the logic block to alter the ideal
using two separate capacitors on the ONT and OFFT pins diode PowerPath controllers and the pushbutton control
respectively. A valid pushbutton on event will set the EN behavior. Specifically, the KILL input provides the system
pin high impedance and a valid off event will drive the with a capability to turn off system power at any point
EN pin low. during operation. The M1 and M2 pins are mode pins
In a typical application the EN pin is tied to the shutdown that configure the part to have different behaviors in the
pin of a DC/DC converter. Therefore, by toggling the EN pin, PowerPath switchover of the two DC sources.
the pushbutton pin has a direct control over the enabling/ Figure 1 shows the four different typical configurations of
disabling of an external DC/DC converter. This control of the LTC2952. In configuration A, both of the ideal-diode
system turn-on/off is done in a graceful manner which PowerPath controllers are always enabled which results
ensures proper system power-up and power-down. in an automatic switchover between the two DC sources.
The ideal diode drivers regulate two external P-channel configuration C is similar to A except for the pushbutton
MOSFETs to achieve low loss switchover between two DC input which now controls both the EN pin and the ideal
sources. Each driver regulates the gate of the PFET such diode PowerPath controllers.
that the voltage drop across its source and drain is 20mV. In configurations B and D, M2 is used as a voltage monitor.
When the load current is larger than the PFET ability to In B, when the M2 input is above its threshold the primary
deliver such current with a 20mV drop across its source ideal diode PowerPath is disabled. In D, M2 needs to be
and drain, the voltage at the gate clamps at VG(ON) and above threshold before PB has control over the EN pin
the PFET behaves like a fixed value resistor. and the ideal diode PowerPath controllers. Furthermore
Besides providing ideal diode PowerPath controllers and in D, the rising and falling edges on M2 are interpreted as
control of system power turn-on/off, the LTC2952 also turn-on and turn-off commands, respectively.
provides system monitoring function via the VM, WDE,

2952fb

13
LTC2952
OPERATION
DC2 DC2

IDEAL DIODE 2 DC/DC IDEAL DIODE 2 DC/DC

SHDN SHDN
DC1 DC1

IDEAL DIODE 1 IDEAL DIODE 1

V2 V1 V2 V1 G1
–
M2 IDEAL DIODE
DRIVER 1
+
+
– 0.5V
* *
PB DETECT PB DETECT
LOGIC LOGIC
PB EN PB EN

CONFIGURATION A CONFIGURATION B
M1 = 0, M2 = 0 M1 = 0

DC2 DC2

IDEAL DIODE 2 DC/DC IDEAL DIODE 2 DC/DC

SHDN SHDN
DC1 DC1

IDEAL DIODE 1 IDEAL DIODE 1

V2 V1 G1 AND G2 V2 V1 G1 AND G2
–
IDEAL DIODE M2 IDEAL DIODE
DRIVER 1 AND 2 DRIVER 1 AND 2
+
+
– 0.5V
* *
PB DETECT PB DETECT
LOGIC LOGIC
PB EN PB EN
2952 F01

CONFIGURATION C CONFIGURATION D
M1 = 1, M2 = 1 M1 = 1
*EXTERNAL PULL-UP REQUIRED

Figure 1. Four Different Typical PowerPath Configurations

2952fb

14
 LTC2952
APPLICATIONS INFORMATION
The LTC2952 is a versatile power management IC with If the load current exceeds the external PFET’s ability to
pushbutton on/off control and system supervisory fea- deliver the current with a 20mV VDS, then the voltage at
tures. The power management function features ideal the GATE clamps and the PFET behaves as a fixed resistor
diode PowerPath control that provides low loss switcho- causing the forward voltage to increase slightly as the load
ver between two DC sources. This PowerPath control current increases. When the VS pin is externally pulled up
behavior is configurable to satisfy various application above the voltage level at VIN, the ideal diode driver shuts
requirements. the external PFET off to prevent reverse conduction. Thus
when both the primary and secondary ideal diode drivers are
The LTC2952’s pushbutton input has independently adjust-
enabled, the two ideal diode drivers work together to bring
able ON and OFF debounce times that control the toggling
VS to within 20mV of the higher of either V1 or V2.
of a low leakage open-drain enable output and in some
configurations, the ideal diode PowerPath operation. A The G1STAT pin indicates the status of the primary
simple interface allows for digital on/off control and proper ideal diode driver. If the external PFET connected to the
system housekeeping prior to power-down. primary driver is providing power to VS, the G1STAT
pin is in a high impedance state and when the PFET con-
The LTC2952 also features robust and accurate system
nected to the primary driver is shut-off, the G1STAT pin
supervisory functions that fit high reliability system ap-
pulls low.
plications. These supervisory functions include power-fail,
voltage monitoring and watchdog reset functions which
can be used to monitor power status and ensure system PowerPath CONFIGURATIONS
integrity.
Configuration A:
The Ideal Diode Drivers Pushbutton Controller with Automatic Switchover
Between WALL Adapter and Battery
In a typical application, each of the ideal diode drivers
is connected to drive an external P-channel MOSFET as In this particular configuration both of the M1 and M2
shown in the Block Diagram and Figure 2. When power pins are connected to ground. These connections set
is available at VIN and the ideal diode driver is enabled, up the LTC2952 to operate with both of the ideal diodes
the ideal diode driver regulates the voltage at the GATE enabled all the time.
to maintain a 20mV difference between VIN and VS. As
In this application, power from the VS node to the system
the load current varies, the GATE voltage is controlled to
is controlled through the EN pin connected to a shutdown
maintain the 20mV difference.

+ +
INPUT OUTPUT *
ADAPTER
SUPPLY TO LOAD
– –
VIN VS Q2

V1/V2 VS
BATTERY Q1 TO SYSTEM
+

DC/DC
A1 PRIMARY/SECONDARY SHDN
IDEAL DIODE DRIVER G1 VS
G2
V1
V2

ANALOG
LINEAR GATE M1 LTC2952 EN **
DRIVER AND
CONTROLLER M2
VOLTAGE CLAMP G1/G2 GATE
*Q1 AND/OR Q2 PFET CAN
PB BE REPLACED BY A SCHOTTKY
G1STAT STAT (ONLY IN DIODE WITH G1 AND/OR G2 FLOATING
INTERNAL S1 **EXTERNAL PULL-UP REQUIRED
ON/OFF PRIMARY DRIVER)
ENABLE
2952 F03
2952 F02

Figure 2. Detailed Ideal Diode Driver Functional Block Diagram Figure 3. PowerPath Configuration A
2952fb

15
LTC2952
APPLICATIONS INFORMATION
pin of a DC/DC converter. The PB input achieves PowerPath Noting the possible current path through the PFET body
control by toggling this EN pin. diode, a back-to-back PFET configuration must be used
Note that in this application both of the ideal diodes are for Q1, Q3 to make sure that no current will flow from the
enabled all the time, therefore either Q1 or Q2 can be battery (V1) to the VS pin even if the wall adapter (V2)
replaced by Schottky diodes as long as the voltage drop voltage is less than the battery (V1) voltage.
across the Schottky diodes and their reverse leakage cur-
Configuration C:
rents are acceptable.
Pushbutton Control of Ideal Diode Drivers
Configuration B: In this configuration the M2 pin is tied to the M1 pin.
Pushbutton Controller with Preferential WALL Adapter Since the M1 pin has a 3μA internal pull-up current, this
Operation and Automatic Switchover to Battery current causes both M1 and M2 to pull high. This allows
In this configuration (Figure 4) the M1 pin is connected the PB pin to have complete control of both the ideal diode
to ground and the M2 pin is used as a monitor on the drivers and the EN pin.
wall adapter input to alter the behavior of the ideal diode The first valid pushbutton input turns on both of the ideal
drivers. When the wall adapter voltage is below the trip diode drivers causing the VS pin to be driven to the higher
threshold, both of the ideal diodes are enabled. of either the wall adapter or the battery input – providing
When the wall adapter voltage is above the trip threshold, power to the system directly. Conversely, a valid pushbut-
the primary ideal diode driver is disabled (shutting off Q1 ton off input turns off the ideal diodes after the shutdown
and Q3) and the secondary ideal diode driver is enabled sequence involving an interrupt to the system.
(turning on Q2). This means the load current will be sup- WALL ADAPTER
plied from the wall adapter (V2) regardless of the voltage Q2 Q4
level at the battery (V1).
If the wall adapter voltage trip threshold is set lower than BATTERY
Q1 Q3
TO SYSTEM
the battery input voltage level and the wall adapter input
G2 G1 VS
can go high impedance, the capacitance on V2 needs to
V1
be minimized. This is to ensure proper operation when the V2
wall adapter goes high impedance and Q1, Q3 is instantly M1 LTC2952 EN
turned on. M2
PB

**WALL ADAPTER S1

Q2 2952 F05

Figure 5. PowerPath Configuration C

BATTERY Q1 Q3
TO SYSTEM
DC/DC
Configuration D:
G2 G1 VS SHDN Battery Backup with Pushbutton PowerPath Controller
V1
V2
In this configuration shown in Figure 6, the M1 pin is left
R9 M1 LTC2952 EN * floating allowing its own 3μA internal pull-up to pull itself
above threshold. With M1 high, the device operates such
M2
PB
*EXTERNAL PULL-UP that rising and falling edges on the M2 pin are interpreted
REQUIRED
R10
S1 **WALL CAN BE LESS as digital on and off commands respectively.
THAN BATTERY
2952 F04 In Figure 6, the M2 pin monitors the wall adapter voltage.
When power is first applied to the wall adapter so that the
Figure 4. PowerPath Configuration B
voltage at the M2 pin rises above its rising trip threshold
2952fb

16
 LTC2952
APPLICATIONS INFORMATION
WALL ADAPTER
out of the V1 pin when a battery is connected in reverse
Q2
TO SYSTEM
and protect the part.
DC/DC
BATTERY Q1
SHDN Note however, this reverse battery protection resistor
G2 G1 VS should not be too large in value since the V1 and V2 pins
V1
V2
are also used as the anode sense pins of the ideal diode
R9 M1 LTC2952 EN * drivers. When the ideal diode driver is on, the VS pin
M2 supplies most of the quiescent current of the part (60μA
R10
C2 PB typ) and the supply pin supplies the remaining quiescent
S1 *EXTERNAL PULL-UP
REQUIRED
current (20μA typ). Therefore, the recommended 1k reverse
battery protection resistor amounts to an additional 20mV
2952 F06

Figure 6. PowerPath Configuration D (1k • 20μA) drop across the P-channel MOSFET.
In Figure 7, when the battery voltage is larger than the wall
(0.515V), both of the ideal diode drivers and the DC/DC adapter voltage, the battery supplies the load current to
converter are enabled. Thus, power is delivered to the the DC/DC converter. The ideal diode driver regulates G1
system. to maintain a fixed voltage drop from V1 to VS of 20mV
As soon as the wall adapter voltage falls below its trip (typ). Since there is a 20mV drop across the reverse battery
threshold, a shutdown sequence is immediately started. At protection resistor (R1) then the regulated voltage drop
the end of the shutdown sequence, the ideal diode drivers from the battery to the VS pin is 40mV (typ).
and the DC/DC converter are disabled. Thus, power is cut WALL ADAPTER
off from the load and the system is in shutdown. Q2
DC/DC
Note that once power is delivered to the system, the PB pin BATTERY Q1
SHDN

can be used to turn off the power. If PB is used to turn off

R12
1k G1 VS
G2
the power in this configuration, there are two methods to * V1 EN **

turn the power back on: a valid pushbutton on event at the

V2
PB pin or a recycling of the wall adapter voltage (bringing M1 LTC2952

the voltage level at the M2 pin down below and then back M2

up above its threshold – a digital on command). PB

*MINIMIZE CAPACITANCE ON V1
S1 **EXTERNAL PULL-UP REQUIRED
Also note that in this application, the voltage threshold of 2952 F07

the wall adapter input (being monitored at the M2 pin) is

usually set higher than the battery input voltage. Therefore,
the only time when power is drawn from the battery (V1 Figure 7. Reverse Battery Protection on V1
pin) to the load is during the shutdown sequence when
Pushbutton Input and Circuitry
the voltage at the wall adapter input (V2 pin) has collapsed
below the battery input voltage level. The PB pin is a high impedance input to an accurate com-
parator with a 10μA pull-up to an LDO regulated internal
Reverse Battery Protection supply of 4V. The PB input comparator has a 0.775V falling
To protect the LTC2952 from a reverse battery connection, trip threshold with 25mV hysteresis. Protection circuitry
place a 1k resistor in series with the respective supply pin allows the PB pin to operate over wide range from –6V
intended for battery connection (V1 and/or V2) and remove to 28V with an ESD HBM rating of ±8kV.
any capacitance on the protected pin. Figure 7 shows a The pushbutton circuitry debounces the input into the PB
configuration with a reverse battery protection on the V1 pin that sets an internal ON/OFF signal. This signal initiates
pin. This resistor will limit the amount of current that flows a turn ON/OFF power sequence.
2952fb

17
LTC2952
APPLICATIONS INFORMATION
VALID PB VALID PB INVALID PB INVALID PB INVALID PB
‘TURN-ON’ EVENT ‘TURN-OFF’ EVENT PUSH EVENT RELEASE EVENT PUSH EVENT

PB

ONT CAP

OFFT CAP

INTERNAL
ON/OFF SIGNAL

INT

2952 F08
tDB,ON tONT tDB tDB,OFF tOFFT tDB <tDB,ON <tONT tDB,ON tONT <tDB tDB <tDB,OFF tDB,OFF tDB,OFF tOFFT
26ms 26ms 26ms 26ms 26ms 26ms 26ms 26ms 26ms 26ms 26ms
tDB,ON <tDB,OFF <tOFFT

Figure 8. Pushbutton Debounce Timing Diagram

The timing diagram in Figure 8 shows the PB pin being duration. The INT pin asserts low when the PB pin is
debounced and setting an internal ON/OFF signal. Note that held low during the OFFT debounce duration and during
a high at the internal ON/OFF signal indicates that the last the shutdown sequence. If the PB pin pulls high before
event was a turn-on command and a low at the internal the OFFT time ends, the INT pin immediately turns high
ON/OFF signal indicates that the last event was a turn-off impedance. On the other hand, if the PB pin is still held
command. Here specifically the turn-on command is a low at the end of the OFFT time, the INT pin continues to
result of a pushbutton on event and the turn-off command assert low throughout the ensuing shutdown sequence.
is a result of a pushbutton off event.
On a release event (rising edge) of the pushbutton switch
Note that a complete pushbutton consists of a push event following a valid push event, the PB pin must be continu-
and a release event. The push event (falling edge) on and ously held above its rising threshold (0.8V) for a fixed
off debounce durations on the PB pin can be increased 26ms internal debounce time.
beyond the fixed internal 26ms by placing a capacitor on
the ONT and OFFT pins respectively. The following equa- In a typical application, the PB pin is connected to a
tions describe the additional debounce time that a push pushbutton switch. If the switch exhibits high leakage
event at the PB pin must satisfy before it is recognized as current (>10μA), connecting an external pull-up resistor
a valid pushbutton on or off. to V1, V2 and/or VS (depending on the application) is
recommended. Furthermore, if the pushbutton switch is
tONT = CONT • (9.3MΩ) physically located far from the LTC2952’s PB pin, signals
tOFFT = COFFT • (9.3MΩ) may couple onto the high impedance PB input. Placing
a 0.1μF capacitor from the PB pin to ground reduces the
CONT and COFFT are the ONT and OFFT external program- impact of signal coupling. Additionally, parasitic series
ming capacitors respectively. inductance may cause undesirable ringing at the PB pin.
Note that during the push event of the pushbutton off, the This can be minimized by placing a 5k resistor in series
INT pin is asserted low after the initial 26ms debounce and located next to the switch.

2952fb

18
 LTC2952
APPLICATIONS INFORMATION
Accurate Comparator Input Pins VTRIP

VM, PFI, KILL, M1 and M2 R1

1%
VM, PFI, KILL, M1 and M2 are high impedance input pins
PIN +
to accurate comparators with a falling threshold of 0.500V. R2
Note the following differences between some of these pins: 1%
–
the VM pin comparator has no hysteresis while the other +
comparators have 15mV hysteresis and the M1 pin has a –
0.5V
3μA pull-up current while the other input pins do not.
2952 F09

Figure 9 shows the configuration of a typical application

when VM, PFI, KILL or M2 pin connects to a tap point on Figure 9. Setting the Comparator Trip Point
an external resistive divider between a positive voltage
and ground. In a typical application the M1 pin is usually either
connected to ground or left floating. When left floating,
Calculate the falling trip voltage from the resistor divider
the internal 3μA pull-up drives the M1 pin high above
value using:
its rising threshold (0.515V). Note that this 3μA pull-up
⎛ R1⎞ current can be used to pull up any or all of the other high
VFALLING− TRIP = 0.5V ⎜ 1+ ⎟ impedance input pins. For example, connect the M2 pin to
⎝ R2 ⎠
the M1 pin to pull both up above their rising thresholds,
Table 1 shows suggested 1% resistor values for various as shown in Figure 5.
applications.
The Voltage Monitor and Watchdog Function
Table 1. Suggested 1% Resistor Values for the Accurate The first voltage monitor input is PFI. As mentioned
Comparators (–6.5% Nominal Threshold)
before, this pin is a high impedance input to an accurate
VSUPPLY VTRIP R1 R2
(V) (V) (kΩ) (kΩ) comparator with 15mV hysteresis. When the voltage at
12 11.25 2150 100 PFI is higher than its rising threshold (0.515V), the PFO
10 9.4 1780 100 pin is high impedance. Conversely, when the voltage level
8 7.5 1400 100
at PFI is lower than its falling threshold (0.500V), the PFO
pin strongly pulls down to GND.
7.5 7 1300 100
6 5.6 1020 100 The second voltage monitor input is VM. The VM pin
5 4.725 845 100 together with the WDE pin (acting as a watchdog monitor
3.3 3.055 511 100 pin) affects the state of the RST output pin. The VM pin is
3 2.82 464 100 also a high impedance input to an accurate comparator.
2.5 2.325 365 100
However, the VM comparator has no hysteresis and hence
the same rising and falling threshold (0.500V).
1.8 1.685 237 100
1.5 1.410 182 100 When the voltage level at VM is less than 0.5V, the RST pin
1.2 1.120 124 100 strongly pulls down to GND. When the voltage level at VM
1.0 0.933 86.6 100 first rises above 0.5V, the RST output pin is held low for
0.9 0.840 68.1 100 another 200ms (tRST) before turning high impedance.
0.8 0.750 49.9 100 After the RST pin becomes high impedance, if the WDE
0.7 0.655 30.9 100 input pin is not left in a Hi-Z state, the watchdog timer
0.6 0.561 12.1 100 is started. The watchdog timer is reset every time there
is an edge (high to low or low to high transition) on the
2952fb

19
LTC2952
APPLICATIONS INFORMATION
WDE pin. The watchdog timer can expire due to any of In this timing sequence, the KILL pin has been set low
the following conditions: since power is first applied to the LTC2952. As soon as the
internal ON/OFF signal transitions high (t1), the EN pin goes
1. No valid edge on the WDE pin in a tWDE (1.6s) time
high impedance and an internal 400ms (tKILL, ON BLANK)
period after the RST pin transitions from pulling low
timer starts. During this 400ms KILL On Blanking period,
to high impedance.
the input to KILL pin is ignored and the EN pin remains in
2. No valid edge on the WDE pin in a tWDE (1.6s) time its high impedance state. This KILL On Blanking period
period since the last valid edge on the WDE pin while is designed to give the system sufficient time to power
the RST pin is high impedance. up properly.
As shown in the Timing Diagrams section, when the Once the μP/system powers on, it sets the KILL pin high
watchdog timer is allowed to expire while voltage at the (t 2) indicating that proper power-up sequence is completed.
VM pin is higher than 0.5V, the RST pin strongly pulls down Failure to set KILL pin high at the end of the 400ms KILL
to ground for tRST (200ms) before again becoming high On Blanking time (t3) will result in immediate system
impedance for tWDE (1.6s). This will continue unless there shutdown (see Aborted Power-On Sequence segment).
is an edge at the WDE pin, the voltage at VM goes below After the KILL On Blanking time expires, the system is
0.5V, or the watchdog function is disabled (by leaving the now in normal operation with power turned on.
WDE in a Hi-Z state).
When the internal ON/OFF signal transitions low (t4), a
In certain PowerPath configurations where both of the shutdown sequence is immediately started. From the start
ideal diode drivers are disabled, the watchdog function of of the shutdown sequence, the system power will turn off
the WDE pin is also disabled. Examples of such configura- in 400ms (tKILL, OFF WAIT), unless an edge (a high-to-low or
tions are configuration C (Figure 5) and configuration D low-to-high transition) at the WDE pin is detected within
(Figure 6) when both of the ideal diode can be turned off the 400ms period to extend the wait period for another
due to a valid pushbutton off or a digital off command. 400ms.

Power-On/Power-Off Sequence This KILL Off Wait time (400ms/cycle) is designed to allow
the system to finish performing its housekeeping tasks
Figure 10 shows a normal power-on and power-off timing before shutdown. Once the μP finishes performing its
diagram. Note that in this timing diagram only the clean power-down operations, it can either let the 400ms KILL
internal ON/OFF signal is shown. A transition at this in- Off Wait time expire on its own or set the KILL pin low
ternal ON/OFF signal can be caused by a valid debounced (t5) immediately terminating the KILL Off Wait time. When
pushbutton ON/OFF or a digital ON/OFF through the mode the KILL Off Wait time expires, the LTC2952 sets EN low,
input pins (M1/M2). turning off the DC/DC converter connected to the EN pin.
When the DC/DC converter is turned off (EN goes low), it
INTERNAL
ON/OFF SIGNAL can take a significant amount of time for its output level
to decay to ground. In order to guarantee that the μP
KILL DON'T CARE
has always powered down properly before it is restarted,
EN
another 400ms (Enable Lockout time, tEN, LOCKOUT) timer
is started to allow for the DC/DC converter output power
t1 t2 t3 t4 t5 t6
level to power down completely to ground. During this
tKILL, ON BLANKING <tKILL, OFF WAIT tEN, LOCKOUT 2952 F10
Enable Lockout time, the EN pin remains in its low state.
Figure 10. Power-On and Power-Off Sequence with At the end of the 400ms Enable Lockout time (t6), the
KILL Deasserting EN During KILL Off Wait Time LTC2952 goes into its reset state with the EN pin remains
strongly pulling down.
2952fb

20
 LTC2952
APPLICATIONS INFORMATION
Aborted Power-On Sequence Extended Power During Turn-Off
The power-on sequence is aborted when the μP fails to In the shutdown process, the availability of power can
set the KILL pin high before the 400ms KILL On Blanking be extended by providing edges to the WDE pin during
time expires, as shown in the timing diagram in Figure 11. the KILL Off Wait time. The timing diagram in Figure 13
When the KILL On Blanking timer expires (t7), the KILL is similar to the power-on/power-off sequence timing
pin is still low indicating that the μP/system has failed to diagram (Figure 10) except for the edges on the WDE pin
power on successfully. When the system failed to set the during the shutdown process. At time t10, the internal ON/
KILL pin high within the specified 400ms time window, OFF signal transitions low. When this happens, the DC/DC
the LTC2952 pulls the EN pin low (thus turning off the converter providing power to the system will be shut off
DC/DC converter) and as a side effect resets the internal in 400ms unless the WDE pin is toggled.
ON/OFF signal.
When the WDE pin transitions at t11, the LTC2952 resets
KILL Power Turn-Off During Normal Operation the 400ms KILL Off Wait timer. Before this second 400ms
wait time expires, the WDE pin transitions again (this time
Once the system has powered on and is operating nor- from high to low) at t12, causing the 400ms timer to reset
mally, the system can turn off power by setting KILL low, again. Finally, the third 400ms timer which starts at t12
as shown in the timing diagram in Figure 12. At t9, KILL is expires without any further extension at t13 causing the
set low and this immediately causes the LTC2952 to pull EN pin to go low, shutting down the DC/DC converter.
EN low, turning off the DC/DC converter.

INTERNAL INTERNAL
ON/OFF SIGNAL ON/OFF SIGNAL

KILL DON'T CARE KILL DON'T CARE

EN EN

t7 t8 t9

tKILL, ON BLANKING tEN, LOCKOUT 2952 F11 tKILL, ON BLANKING 2952 F12

Figure 11. Aborted Power-On Sequence Figure 12. KILL Initiated Shutdown

EXTENDED HOUSE KEEPING TIME

INTERNAL
ON/OFF SIGNAL

KILL DON'T CARE DON'T CARE

EN

WDE

t10 t11 t12 t13

tKILL, ON BLANKING < tKILL, OFF WAIT tKILL, OFF WAIT tEN, LOCKOUT 2952 F13

< tKILL, OFF WAIT

Figure 13. Power-On/Power-Off Sequence with Extended Shutdown/Housekeeping Wait Time

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21
LTC2952
APPLICATIONS INFORMATION
Setting Up Different Configurations In modes 4 and 5 both of the ideal diodes are disabled
The various configurations discussed previously are sum- and the input to the PB pin is ignored. Note that mode 5
marized in Table 2, including the ideal diode PowerPath is a transitional mode. If there is no change at the M1 and
state (ID1-primary, ID2-secondary). Note that an input M2 pin while in mode 5, the mode eventually transitions
above 0.515V (typical rising threshold) on the M1 and into mode 4 after a proper shutdown sequence.
M2 pins is indicated with a 1 and an input below 0.500V A rising edge at M1 in mode 1 or a falling edge at M2 in
(typical falling threshold) is represented by a 0. Also, mode 7 is recognized as a digital off command, which
an enabled ideal diode driver is indicated with a 1 and a causes a transition to mode 5. When a digital off com-
disabled driver is indicated with a 0. mand is received, the EN pin is driven low and the ideal
diodes are disabled after a proper shutdown sequence
Table 2. Mode Table
involving the interrupt alert to the μP (INT pin driven
MODE DESCRIPTION M1 M2 EN ID1 ID2
low)—refer to the earlier sections for details on the
0 Both Diodes Enabled 0 0 0 1 1
shutdown sequence.
1 Both Diodes Enabled 0 0 1 1 1
2 Primary Diode Off, Secondary 0 1 0 0 1
Note that since the PB input is ignored in both mode 4 and
Diode On 5, the only way to turn on the PowerPath from these two
3 Primary Diode Off, Secondary 0 1 1 0 1 modes is a transition from 0 to 1 at the M2 pin. A transition
Diode On from 0 to 1 at the M2 pin in modes 4 or 5 is interpreted as
4 PowerPath Off, PB Overwrite 1 0 0 0 0 a digital on command. This digital on command causes
5 Transitional PowerPath Off, 1 0 1 1 1 the mode to transition from mode 4 or 5 to mode 7. In
PB Overwrite
mode 7, both of the ideal diodes are enabled and the EN
6 Pushbutton PowerPath Off 1 1 0 0 0 pin goes high impedance. Modes 4, 5 and 7 are used in
7 Pushbutton PowerPath On 1 1 1 1 1 configuration D (Figure 6).
Notice that in mode 7, both the M2 pin and the PB pin
In addition to the mode table, the mode transition diagram have direct control over the EN pin. A transition from 1
in Figure 14 shows all possible interactions between the to 0 at the M2 pin in mode 7 is recognized as a digital off
events on the pins (PB, M1 and M2) and the different command. This digital off command causes a transition to
modes of the LTC2952 PowerPath behavior. Using Table 2 mode 4 after a proper shutdown sequence. On the other
and Figure 14, it is possible to configure the LTC2952 in hand, a valid pushbutton off mode 7 transitions the part to
many different ways beyond the four discussed in the mode 6 after a proper shutdown sequence. In both mode 4
Operation and Applications Information sections. and mode 6 the EN pin is driven low. Modes 6 and 7 are
In modes 0 and 1, both of the ideal diode drivers are enabled used in configuration C (Figure 5).
all the time. A valid pushbutton toggles the mode between In mode 4 the ideal diode driver circuitry is disabled, the
0 and 1 (changing the state of the EN pin) without ever EN pin is driven low, and the PB input is ignored. On the
turning off of the ideal diodes. These modes are used in other hand, in mode 6, although both of the primary and
configuration A and B (Figures 3 and 4). secondary ideal diodes are disabled and the EN pin is set
In modes 2 and 3, only V2 provides power to the load low, the PB input is not ignored. A valid pushbutton tran-
connected at VS because the primary ideal diode driver is sitions the part from mode 6 to mode 7, turning on both
disabled and only the secondary ideal diode driver is en- the ideal diodes and setting the EN pin high impedance
abled. These modes are used in configuration B (Figure 4). (turning on the DC/DC converter).

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22
 LTC2952
APPLICATIONS INFORMATION

MODE 0 VALID PB MODE 1

M1 = 0 M1 = 0
M2 = 0 M2 = 0
EN = 0 EN = 1
G1 = ON VALID PB G1 = ON
G2 = ON G2 = ON
M1
M1
M1 M1 M2 M2 M2 M2 PB CONTROL
DIGITAL OFF OF EN PIN
COMMAND

MODE 2 VALID PB MODE 3

M1 = 0 M1 = 0
M2 = 1 M2 = 1
EN = 0 EN = 1
G1 = OFF VALID PB G1 = OFF
G2 = ON G2 = ON

MODE 4 MODE 5
M1 = 1 M1 = 1
M2 = 0 M2 = 0
EN = 0 EN = 1
G1 = OFF G1 = OFF
G2 = OFF G2 = OFF
(PB IGNORE) (PB IGNORE) M1 M1

M2 M2 AND PB CONTROL
DIGITAL ON M2 M2 OF EN PIN AND IDEAL
M1 M1 M2 COMMAND DIGITAL OFF DIGITAL ON DIODES FUNCTION
COMMAND COMMAND

MODE 6 VALID PB MODE 7

M1 = 1 M1 = 1
M2 = 1 M2 = 1
EN = 0 EN = 1
G1 = OFF VALID PB G1 = ON
G2 = OFF G2 = ON
2952 F14

Figure 14. Mode Transition Diagram

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23
LTC2952
TYPICAL APPLICATIONS
Wall Adapter and Battery Automatic Load Switchover with Simple On/Off Pushbutton
Control and Voltage Monitors for System Power without μP
WALL ADAPTER
5V TO 20V 2.5V
VIN VOUT
Q2 Q1 R6
Si7913DN Si7913DN LT1767-2.5
1k
SHDN** R7

INDICATOR
1k

BAT LOW
R5
4.2V R3 R1 1k

INDICATOR
SINGLE 511k 365k

BAT OFF
CELL

POWER LOW
INDICATOR
R8
Li-Ion R4
G1 VS 10k
BATTERY 100k
G2 PFI D3
R2
V1 EN
100k D2
V2 VM
D1

LTC2952 INT
M1 KILL
M2 RST
G1STAT
PB PFO
WDE
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL 2952 TA02
**SHDN INTERNALLY PULLED UP BY THE LT1767-2.5

Wall Adapter and Battery Automatic Load Switchover with Pushbutton Control, Voltage Monitors and Watchdog
WALL ADAPTER
12V TO 25V 3.3V
VIN VOUT
Q2 Q1
Si6993DQ Si6993DQ LT1767-3.3
R6
SHDN** 10k

R3 R1 R7
9V BATTERY 1.3M 511k 10k
R8
R4 10k
G1 VS 100k
G2 PFI R5
10k
R2
V1 EN
100k
V2 VM

LTC2952 RST
M1 INT
M2 G1STAT μP
PFO
PB KILL
WDE
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL 2952 TA03

**SHDN INTERNALLY PULLED UP BY THE LT1767-3.3

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24
 LTC2952
TYPICAL APPLICATIONS
Uninterruptible Power Supply with Preferential Wall Adapter Operation and Automatic Load
Switchover to Battery with Pushbutton Control, Voltage Monitors and Watchdog

WALL ADAPTER
5V TO 30V 3.3V
VIN VOUT
Q2 CVS
Si7421DN Si7941DP LTC1625
0.1μF R6
RUN/SS** 10k
R3 R1 R7
Q1 Q3 1.78M 511k 10k
5V TO 30V
R8
BATTERY R4
G1 VS 10k
100k
G2 PFI R5
10k
R2
V1 EN
100k
V2 VM

LTC2952 RST
R9
845k M1 INT
G1STAT μP
M2 PFO
PB KILL
R10
WDE
100k
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL
2952 TA04
**RUN/SS INTERNALLY PULLED UP BY THE LTC1625

Direct PowerPath Control with Pushbutton Control, Voltage Monitors and Watchdog
Si7925DN
WALL ADAPTER
5V

Q4 CVS
Q2 R11
Si7925DN 0.1μF R6
1k
10k
POWER ON/OFF

R7
INDICATOR

R1
511k 10k
4.2V
SINGLE R8
Q1 Q3
CELL 10k
Li-Ion
G1 VS R5
BATTERY
G2 10k
D4
R2
V1 EN
100k
V2 VM

LTC2952 RST
R3
845k M1 INT
M2 G1STAT μP
PFI PFO
PB KILL
R4
WDE
100k
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL
2952 TA05

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25
LTC2952
TYPICAL APPLICATIONS
Critical System with Primary Supply and Temporary Battery Backup with
Pushbutton Control, Voltage Monitors and Watchdog

PRIMARY POWER
12V TO 30V 3.3V
VIN VOUT
Q2 Q1
SUB75P03-07 SUB75P03-07 LTC3728
R6
RUN/SS** 10k

R3 R1 R7
12V BATTERY 1.82M 511k 10k
R8
R4 10k
G1 VS 100k
G2 PFI R5
10k
R2
V1 EN
100k
V2 VM

R9
LTC2952 RST
2.15M
M1 INT
M2 G1STAT μP
R10 C2 PFO
100k 0.1nF
PB KILL
WDE
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL 2952 TA06
**RUN/SS INTERNALLY PULLED UP BY THE LTC3728

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26
 LTC2952
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

F Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)

6.40 – 6.60*
(.252 – .260)
1.05 ±0.10 20 19 18 17 16 15 14 13 12 11

6.60 ±0.10 4.50 ±0.10 6.40

(.252)
BSC

0.45 ±0.05 0.65 BSC

RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10

1.10
4.30 – 4.50**
(.0433)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.19 – 0.30
NOTE: (.0075 – .0118) F20 TSSOP 0204

1. CONTROLLING DIMENSION: MILLIMETERS TYP

MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

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27
LTC2952
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UF Package
20-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)

0.70 0.05

4.50 0.05
3.10 0.05
2.45 0.05
2.00 REF

2.45 0.05

PACKAGE OUTLINE

0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN 1 NOTCH
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.20 TYP
BOTTOM VIEW—EXPOSED PAD OR 0.35 ¥ 45
0.75 0.05 R = 0.05 R = 0.115 CHAMFER
4.00 0.10 TYP TYP
19 20

PIN 1 0.40 0.10

TOP MARK
(NOTE 6) 1

2.45 0.10 2
4.00 0.10 2.00 REF

2.45 0.10

(UF20) QFN 01-07 REV A

0.200 REF 0.25 0.05

0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

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28
 LTC2952
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 02/10 Revised Configuration B of Figure 1 14
B 09/11 Added information to Typical Applications drawings 1, 24, 25, 26, 30
Revised conditions for tONT, OFFT in Electrical Characteristics 4
Revised EN, KILL, and WDE pin pin descriptions in Pin Functions 10, 11
Added information to Figures 1, 3, 4, 6, 7 and 8 14 to 18
Updated values in Applications Information 20, 21

2952fb

29
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2952
TYPICAL APPLICATION
Wall Adapter and Battery Automatic Load Switchover with Reverse Battery Protection

WALL ADAPTER
12V TO 25V 3.3V
VIN VOUT
Q2 Q1
Si6993DQ Si6993DQ LT1767-3.3
R6
SHDN** 10k

R3 R1 R7
9V BATTERY 1.3M 511k 10k
R8
1k R4
G1 VS 10k
100k
G2 PFI R5
10k
V1 R2
EN
100k
VM

V2 LTC2952 RST
M1 INT
M2 G1STAT μP
PFO
PB KILL
WDE
ONT GND OFFT
S1
CONT* COFFT*
22nF 68nF *OPTIONAL 2952 TA07
**SHDN INTERNALLY PULLED UP BY THE LT1767-3.3

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PART NUMBER DESCRIPTION COMMENTS
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LTC2905
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LT 0911 REV B • PRINTED IN USA

Linear Technology Corporation
30 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010