A B C D E

Vinafix.com
1 1

Compal Confidential
YOGA 730 15"
DIS M/B Schematics Document
2 2

Intel KabyLake R Processor with DDR4

N17P-G0-A1 (29x29mm)

2017-12-5
LA-F661P
3 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 Deciphered Date 2017/6/2 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 06, 2017 Sheet 1 of 61
A B C D E
 1 2 3 4 5

Compal Confidential
Pluto 5A (15")
GPU Vinafix.com
Kabylake-R
A
N17P-G0-A1 35W PEG x4 DDR4 2400MHz DDR4-SO-DIMM 1 A

+VGA_CORE +1.2V, +0.6VS

VRAM 256MX32 +1.5VGS
GDDR5 x 4 (2GB/4GB) +1.0VGS
+1.8VGS

Panel FHD/UHD
eDP x1 DDR4-on board RAM
4 Lanes (4 DRAM Devices per channel) 8G
IPS

USB3.1/TBT

I2C DDI1
Type-C Type-C
Conn TI TPS 65988CE Intel
Alpine Ridge USB2.0 x1
AUX/TBT AR-LP Intel KBL-R U 15W FingerPrint
SBU Mux PCIE x2 USB2.0 x1
TS3D10224 1356pin BGA Camera 1.0M HD
USB2.0 x1
B B

USB2.0 x1 USB Charger

TPS2546
HDMI Re-driver USB3.0 x1 USB 3.0 conn x1
PS8407A(Option)
USB3.0 x1
HDMI2.0 Converter DDI2
HDMI Conn USB 3.0 conn x1
PS175 (Option) USB2.0 x1
By pass for HDMI 1.4x
I2C
Touch Panel
PCIE x1
NGFF (TYPE E)
2230 Conn. USB2.0 x1 Combo Jack
WLAN/BT4.0
HDA Audio Codec
PCIE x 4 Int. Speaker
NGFF (TYPE M) or Realtek ALC3240
C M.2 PCIE SSD(Gen3)
SATA x 1 C

Int. Array Mic *2

SPI ROM SPI

W25Q64FVSSIQ MIC/Sensor FPC
8MB I2C I2C ALS
+1.0VS
+3VS

AL3010
+3V_PCH
+RTCVCC

Power, Novo Button I2C G Sensor x1

LPC BUS BMA250E
Power Circuit MIC/Sensor FPC G Sensor x1
PS2 Hall Sensor x1 BMA250E
MIC/Sensor FPC
Touch Pad CONN. ENE TCS20DLR
(Panel side MIC x2, G sensor x1, KB9022
ALS x1, Hall sensor x1) Int. KBD +3VLP Hall Sensor x1
TCS20DLR
+3VALW
D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2016/4/19 Deciphered Date 2017/4/19 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 17, 2017 Sheet 2 of 61
1 2 3 4 5
 A B C D E

Vinafix.com
1 1

UC1A @ SKL-U
Rev_1.0
E55 C47
38 CPU_DP1_N0 F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXN0 29
38 CPU_DP1_P0 DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 29
E58 D46
38 CPU_DP1_N1 F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXN1 29
38 CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 29
38 CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 EDP_TXN2 29
38 CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47 EDP_TXP2 29
38 CPU_DP1_N3 DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 29
G56 B47
38 CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3] EDP_TXP3 29
C50 E45 EDP_AUXN 29
31 CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45
31 CPU_DP2_P0 DDI2_TXP[0] EDP_AUXP EDP_AUXP 29
C52
31 CPU_DP2_N1 DDI2_TXN[1]
D52 B52
31 CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
31 CPU_DP2_N2 B50 DDI2_TXN[2] G50
31 CPU_DP2_P2 DDI2_TXP[2] DDI1_AUXN DDI1_AUX_DN 38
D51 F50
31 CPU_DP2_N3 DDI2_TXN[3] DDI1_AUXP DDI1_AUX_DP 38
C51 E48
31 CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN DDI2_AUX_DN 30
F48 DDI2_AUX_DP 30
DDI2_AUXP G46
DISPLAY SIDEBANDS RSVD F46
L13 RSVD
CPU_DDPB_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 CPU_DP1_HPD 38
L7 CPU_DP2_HPD 30,31,32
N7 GPP_E14/DDPC_HPD1 L6
31,32 HDMICLK_NB N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
31,32 HDMIDAT_NB GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EC_SCI# 10,45
GPP_E17/EDP_HPD EDP_HPD 29
N11
N12 GPP_E22 R12
2 29 TS_I2C_RST# GPP_E23 EDP_BKLTEN R11 ENBKL 29,45 2
EDP_COMP E52 EDP_BKLTCTL U13 INVPWM 29
1 OF 20
EDP_RCOMP EDP_VDDEN PCH_ENVDD 29
SKL-U_BGA1356

+3VS

+1.0VS_VCCIO
RC218 2 TBT@ 1 2.2K_0201_5% CPU_DDPB_CTRL_DATA

+1.0VS_VCCIO
1

RC4 UC1D @ SKL-U

1K_0402_5% Rev_1.0
CATERR# D63 SOC_XDP_TMS RC11 1 CMC@ 2 51_0402_5%
H_PECI A54 CATERR#
45 H_PECI H_PROCHOT#_R PECI SOC_XDP_TDI
45 H_PROCHOT# 1 2 C65 RC12 1 CMC@ 2 51_0402_5%
PROCHOT#
2

JTAG
RC6 499_0402_1% H_THERMTRIP# C63
A65 THERMTRIP# SOC_XDP_TDO RC13 1 DCI@ 2 51_0402_5%
SKTOCC# B61 CPU_XDP_TCK0
C55
CPU MISC PROC_TCK D60 SOC_XDP_TDI
D55 BPM#[0] PROC_TDI A61 SOC_XDP_TDO
B54 BPM#[1] PROC_TDO C60 SOC_XDP_TMS CPU_XDP_TCK0 RC14 1 DCI@ 2 51_0402_5%
C56 BPM#[2] PROC_TMS B59
+1.0VS_VCCIO BPM#[3] PROC_TRST#
A6 B56
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 SOC_XDP_TDI
RC3 1 2 EDP_COMP BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 SOC_XDP_TDO
24.9_0402_1% AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 SOC_XDP_TMS
39 TBT_FORCE_PWR GPP_B4/CPU_GP3 PCH_JTAG_TMS C61
3 RC7 2 1 49.9_0402_1% CPU_POPIRCOMP AT16 PCH_TRST# A59 CPU_XDP_TCK0 3
RC8 2 1 49.9_0402_1% PCH_OPIRCOMP AU16 PROC_POPIRCOMP JTAGX
RC9 2 @ 1 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC10 2 @ 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
+1.0V_VCCST 4 OF 20
SKL-U_BGA1356

1 2 H_THERMTRIP#
RC5 1K_0402_5%

@
2 1 CATERR#
RC19 49.9_0402_1%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/6/2
SKL-U(1/12)DDI,EDP,MISC,CMC
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 6 of 61
A B C D E
 5 4 3 2 1

D
Vinafix.com D

SKL-U
UC1B SKL-U UC1C
Rev_1.0 Rev_1.0
18 DDR_A_D[0..15] DDR_A_D0 DDR_A_CLK#0
AL71 AU53 DDR_A_CLK#0 18
DDR_A_D1 DDR0_DQ[0] DDR0_CKN[0] DDR_A_CLK0 20 DDR_B_D[0..15] DDR_B_D0 Interleave / Non-Interleaved DDR_B_CLK#0
AL68 AT53 DDR_A_CLK0 18 AF65 AN45 DDR_B_CLK#0 20
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR_A_D3 DDR0_DQ[2] DDR0_CKN[1] DDR_A_CLK1 TP@ T186 DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 20
AN69 AT55 TP@ T189 AK65 AP45 DDR_B_CLK0 20
DDR_A_D4 AL70 DDR0_DQ[3] DDR0_CKP[1] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR_A_D5 DDR0_DQ[4] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 20
AL69 BA56 DDR_A_CKE0 18,19
AF66
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D7 DDR0_DQ[6] DDR0_CKE[1] TP@ T190 DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 20
AN71 AW 56 AK67 AP55 DDR_B_CKE1 20
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] DDR_B_D8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D11 DDR0_DQ[10] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 18,19 DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU68 AU43 TP@ T187 AH71 BB42 DDR_B_CS#0 20
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1
DDR_A_D13 DDR0_DQ[12] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 18,19 DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 20
AR69 AT43 TP@ T188 AF71 BA42 DDR_B_ODT0 20
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW 42 DDR_B_ODT1
DDR_A_D15 DDR0_DQ[14] DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 20
AU69 AH70
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR_A_MA9 DDR_A_MA5 18,19 20 DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4 DDR_B_MA5
BB54 DDR_A_MA9 18,19
AT66 AY48 DDR_B_MA5 20
18 DDR_A_D[16..31] DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_B_D17 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9
BB65 BA52 DDR_A_MA6 18,19 AU66 AP50 DDR_B_MA9 20
DDR_A_D17 AW 65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_B_D18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 18,19 DDR_B_D19 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 20
AW 63 AW 52 DDR_A_MA7 18,19
AN65 BB48 DDR_B_MA8 20
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 DDR_B_D20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BG0 18,19 DDR_B_D21 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BG0 DDR_B_MA7 20
BA65 AW 54 DDR_A_MA12 18,19
AP66 AP52 DDR_B_BG0 20
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_A_ACT# DDR_A_MA11 18,19 DDR_B_D23 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 20
BA63 BA55 M_A_ACT# 18,19 AU65 AN48 DDR_B_MA11 20
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_B_D24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_ACT#
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA13 DDR_A_BG1 18 DDR_B_D25 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_BG1 DDR_B_ACT# 20
BA61 AU46 DDR_A_MA13 18,19 AU61 AN52 DDR_B_BG1 20
C DDR_A_D25 AW 61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 DDR_B_D26 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43 DDR_B_MA13 C
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR_A_MA14 DDR_A_MA15 18,19 DDR_B_D27 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR_B_MA15 DDR_B_MA13 20
BB59 AT46 DDR_A_MA14 18,19 AN60 AY43 DDR_B_MA15 20
DDR_A_D27 AW 59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 DDR_B_D28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDR_B_MA14
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR_A_BA0 DDR_A_MA16 18,19 DDR_B_D29 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR_B_MA16 DDR_B_MA14 20
BB61 AU52 DDR_A_BA0 18,19
AP61 AW 44 DDR_B_MA16 20
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_B_D30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDR_B_BA0
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR_A_BA1 DDR_A_MA2 18,19 DDR_B_D31 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR_B_MA2 DDR_B_BA0 20
BA59 AT48 DDR_A_BA1 18,19
AU60 AY47 DDR_B_MA2 20
DDR_A_D31 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 20 DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BA1
AY59 AT50 DDR_A_MA10 18,19 AU40 BA44 DDR_B_BA1 20
18 DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR_A_MA1 DDR_B_D33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR_B_MA10
AY39 BB50 DDR_A_MA1 18,19 AT40 AW 46 DDR_B_MA10 20
DDR_A_D33 AW 39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 DDR_B_D34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDR_B_MA1
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR_A_MA0 18,19 DDR_B_D35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR_B_MA0 DDR_B_MA1 20
AY37 AU37 BA46 DDR_B_MA0 20
DDR_A_D35 AW 37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 DDR_B_D36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 18,19 DDR_B_D37 DDR1_DQ[36]/DDR1_DQ[20] DDR_B_MA3
BB39 BB52 DDR_A_MA4 18,19 AP40 BB46 DDR_B_MA3 20
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 DDR_B_D38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47 DDR_B_MA4
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS0 DDR_A_DQS#0 18 DDR_B_D39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4] DDR_B_MA4 20
BA37 AM69 DDR_A_DQS0 18
AR37
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] AT69 DDR_A_DQS#1 DDR_B_D40 AT33 DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] DDR_A_DQS1 DDR_A_DQS#1 18 DDR_B_D41 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved DDR_B_DQS#0
AY35 AT70 DDR_A_DQS1 18
AU33 AH66 DDR_B_DQS#0 20
DDR_A_D41 AW 35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] DDR_B_D42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDR_B_DQS0
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR_B_D43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] DDR_B_DQS#1 DDR_B_DQS0 20
AY33 AT30 AG69 DDR_B_DQS#1 20
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#2 DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1
AW 33 BA64 DDR_A_DQS#2 18
AR33 AG70 DDR_B_DQS1 20
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_A_D45 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 18 DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 20
BA35 AY60 DDR_A_DQS#3 18
AR30 AR65 DDR_B_DQS2 20
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_A_D47 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 18 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 20
BB33 BA38 DDR_A_DQS#4 18 AR60 DDR_B_DQS3 20
18 DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] DDR_A_DQS4 20 DDR_B_D[48..63] DDR_B_D48 DDR1_DQSP[3]/DDR0_DQSP[7] DDR_B_DQS#4
AY31 AY38 DDR_A_DQS4 18
AU27 AT38 DDR_B_DQS#4 20
DDR_A_D49 AW 31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDR_B_DQS4
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] DDR_A_DQS5 DDR_A_DQS#5 18 DDR_B_D50 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] DDR_B_DQS#5 DDR_B_DQS4 20
AY29 BA34 DDR_A_DQS5 18
AT25 AT32 DDR_B_DQS#5 20
DDR_A_D51 AW 29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDR_B_DQS5
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] DDR_A_DQS6 DDR_A_DQS#6 18 DDR_B_D52 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3] DDR_B_DQS5 20
BB31 AY30 DDR_A_DQS6 18 AP27
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 DDR_B_D53 AN27 DDR1_DQ[52] AR25 DDR_B_DQS#6
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] DDR_A_DQS7 DDR_A_DQS#7 18 DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 20
BA29 BA26 DDR_A_DQS7 18 AN25 AR27 DDR_B_DQS6 20
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_A_D56 DDR0_DQ[55]/DDR1_DQ[39] DDR_A_ALERT# DDR_B_D56 DDR1_DQ[55] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 20
AY27 AW 50 AT22 AR21 DDR_B_DQS7 20
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# DDR_A_PARITY DDR_A_ALERT# 18 DDR_B_D57 DDR1_DQ[56] DDR1_DQSP[7] DDR_B_ALERT#
AW 27 AT52 DDR_A_PARITY 18,19 AU22 AN43
DDR_A_D58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_B_D58 DDR1_DQ[57] DDR1_ALERT# DDR_B_PARITY DDR_B_ALERT# 20
AY25 AU21 AP43 DDR_B_PARITY 20
DDR_A_D59 AW 25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 +0.6V_A_VREFCA DDR_B_D59 AT21 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST#
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +0.6V_A_VREFCA 18 DDR_B_D60 DDR1_DQ[59] DRAM_RESET# DDR_DRAMRST# 18,20
B BB27 AY68 AN22 DDR CH - B AR18 B
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 +0.6V_B_VREFDQ DDR_B_D61 AP22 DDR1_DQ[60] DDR_RCOMP[0] AT18
DDR_A_D62 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ +0.6V_B_VREFDQ 20 DDR_B_D62 DDR1_DQ[61] DDR_RCOMP[1] SM_RCOMP0
BA25 AP21 AU18 RC16 1 SDP@ 2 200_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW 67 DDR_PG_CTRL DDR_B_D63 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2] SM_RCOMP1 RC17 1 2 80.6_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL DDR1_DQ[63] SM_RCOMP2 RC18 1 2 100_0402_1%
SKL-U_BGA1356 SKL-U_BGA1356
@ @
DDP@
RC16
SD034121090
121_0402_1%

+1.2V +3VS
+1.2V

1
1

CC1

1
RC20
100K_0402_5%
RC132

0.1U_0201_10V6K
470_0402_5%
@
UC2 2
1 5
2

NC VCC

2
DDR_DRAMRST#
DDR_PG_CTRL 2
A 4
Y DDR_VTT_PG_CTRL 49
3 1
GND
74AUP1G07GW_TSSOP5 CC96
SA00007WE00 100P_0201_25V8J
2 ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/6/2 Title

SKL-U(2/12)DDR4
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Dat e: Wednesday, October 18, 2017 Sheet 7 of 61
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D UC1E @ SKL-U D
Rev_1.0
SPI - FLASH
SMBUS, SMLINK
SOC_SPI_CLK AV2 R7 PCH_SMB_CLK
SOC_SPI_SO SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA PCH_SMB_CLK 20
AW3 R8 PCH_SMB_DATA 20
SOC_SPI_SI AV3 SPI0_MISO GPP_C1/SMBDATA R10
SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
SOC_SPI_IO3 AU4 SPI0_IO2 R9 SOC_SML0CLK
SOC_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SOC_SML0DATA
AU2 SPI0_CS0# GPP_C4/SML0DATA W1
AU1 SPI0_CS1# GPP_C5/SML0ALERT#
SPI0_CS2# W3 EC_SMB_CK2
GPP_C6/SML1CLK EC_SMB_DA2 EC_SMB_CK2 21,35,45
V3 EC_SMB_DA2 21,35,45
SPI - TOUCH GPP_C7/SML1DATA AM7 SOC_SML1ALERT#
M2 GPP_B23/SML1ALERT#/PCHHOT#
M3 GPP_D1/SPI1_CLK
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
RC56 V2 GPP_D21/SPI1_IO2 AY13 LPC_AD0
GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 LPC_AD0 45
39 TBT_CIO_PLUG_EVENT# 1 2 TBT_CIO_PLUG_EVENT#_R1 M1 LPC BA13 LPC_AD1
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 45
BB13
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 45
0_0402_5% AY12
GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3 45
+3VS C LINK BA12
GPP_A5/LFRAME#/ESPI_CS# LPC_FRAME# 45
G3 BA11
G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET#
RC25 1 2 8.2K_0402_5% SERIRQ G1 CL_DATA
CL_RST# AW9 LPC_CLK0 RC26 1 EMI@ 2 22_0402_5%
GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_EC 45
AY9
KB_RST# AW13 GPP_A10/CLKOUT_LPC1 AW11 PM_CLKRUN#
C GPP_A0/RCIN# GPP_A8/CLKRUN# PM_CLKRUN# 45 C
+3VS SERIRQ AY11
45 SERIRQ GPP_A6/SERIRQ 5 OF 20

SKL-U_BGA1356
RC112 1 2 10K_0402_5% KB_RST#
+3VS

RPC1
SOC_SPI_SO 1 8 SOC_SPI_SO_0_R EC_SMB_CK2 RC28 1 2 1K_0402_5%
SOC_SPI_CLK 2 7 SOC_SPI_CLK_0_R
SOC_SPI_SI 3 6 SOC_SPI_SI_0_R EC_SMB_DA2 RC29 1 2 1K_0402_5%
SOC_SPI_IO3 4 5 SOC_SPI_IO3_0_R

33_0804_8P4R_5% SOC_SML1ALERT# 1 @ 2
EMI@ RC113 150K_0402_5%

SOC_SPI_IO2 1 2 SOC_SPI_IO2_0_R RPC2

RC30 EMI@ 33_0402_5% PCH_SMB_CLK 1 8
PCH_SMB_DATA 2 7
SOC_SML0CLK 3 6
SOC_SML0DATA 4 5
RPC3
EC_SPI_CLK 1 8 SOC_SPI_CLK_0_R 1K_0804_8P4R_5%
45 EC_SPI_CLK EC_SPI_MOSI SOC_SPI_SI_0_R
B 2 7 B
45 EC_SPI_MOSI EC_SPI_CS0# SOC_SPI_CS#0
3 6
45 EC_SPI_CS0# EC_SPI_MISO SOC_SPI_SO_0_R
4 5 +3VS
45 EC_SPI_MISO
33_0804_8P4R_5%
PM_CLKRUN# 1 2
EMI@
RC31 8.2K_0402_5%

+3VALW
@
UC3 CC2 1 2 0.1U_0201_10V K X5R
SOC_SPI_CS#0 1 8
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R
GND DI(IO0)
1
W 25Q64FVSSIQ_SO8
SA000039A40 CC3
10P_0402_50V8J
2 @EMI@

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(3/12)SPI,SMB,LPC,ESPI
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 8 of 61
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

RPC4
1 8 HDA_BIT_CLK
33 HDA_BITCLK_AUDIO HDA_SYNC
33 HDA_SYNC_AUDIO 2 7 UC1G @ SKL-U
3 6 HDA_SDOUT Rev_1.0
33 HDA_SDOUT_AUDIO
4 5 AUDIO

33_0804_8P4R_5% HDA_SYNC BA22

EMI@ HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
SDIO / SDXC
BA21 HDA_SDO/I2S0_TXD
33 HDA_SDIN0 HDA_SDI0/I2S0_RXD
AY21 AB11
AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
I2S1_TXD GPP_G4/SD_DATA3 W10
AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7
RC116 2 1 0_0402_5% HDA_SDOUT D7 GPP_D19/DMIC_CLK0 SD_RCOMP
45 ME_EN GPP_D20/DMIC_DATA0
D8 AF13
C C8 GPP_D17/DMIC_CLK1 GPP_F23 C
GPP_D18/DMIC_DATA1
HDA_SPKR AW5
33 HDA_SPKR GPP_B14/SPKR
7 OF 20

SKL-U_BGA1356

UC1I @ SKL-U
Rev_1.0
+3VS CSI-2

A36 C37
RC33 1 @ 2 2.2K_0402_5% HDA_SPKR B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
B C33 CSI2_DP4 GPP_D4/FLASHTRIG B
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
9 OF 20 AT1
EMMC_RCOMP
SKL-U_BGA1356

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 9 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS

UC1J @ SKL-U
Rev_1.0
CLOCK SIGNALS

D42
RPC6 40 CLK_PCIE_TBT# C42 CLKOUT_PCIE_N0
40 CLK_PCIE_TBT TBTCLK_REQ# CLKOUT_PCIE_P0
8
7
6
1
2
3
TBTCLK_REQ#
WLANCLK_REQ#
EC_SCI# 6,45 Vinafix.com 40 TBTCLK_REQ#
AR10

B42
GPP_B5/SRCCLKREQ0#

SSDCLK_REQ# 21 CLK_PEG_VGA# CLKOUT_PCIE_N1

5 4 A42 F43
D 21 CLK_PEG_VGA VGA_CLKREQ# AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43
D
21 VGA_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
10K_0804_8P4R_5%
D41 BA17 SUSCLK
34 CLK_PCIE_WLAN# C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 34
34 CLK_PCIE_WLAN WLANCLK_REQ# CLKOUT_PCIE_P2
34 WLANCLK_REQ#
AT8 E37
GPP_B7/SRCCLKREQ2# XTAL24_IN E35
1 DIS@ 2 VGA_CLKREQ# D40 XTAL24_OUT
RC34 10K_0402_5% C40 CLKOUT_PCIE_N3 E42 XCLK_BIASREF
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
1 @ 2 GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1
RC140 10K_0402_5% B40 RTCX1 AM20 SOC_RTCX2
34 CLK_PCIE_SSD# A40 CLKOUT_PCIE_N4 RTCX2
34 CLK_PCIE_SSD SSDCLK_REQ# AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST#
34 SSDCLK_REQ# GPP_B9/SRCCLKREQ4# SRTCRST# EC_CLEAR_CMOS#
AM16
E40 RTCRST#
E38 CLKOUT_PCIE_N5
+3VL_RTC AU7 CLKOUT_PCIE_P5
GPP_B10/SRCCLKREQ5#

RC36 1 2 20K_0402_5% SOC_SRTCRST# 10 OF 20

CC6 1 2 1U_0402_6.3V6K SKL-U_BGA1356

+1.0VALW

XCLK_BIASREF 1 2
RC37 1 2 20K_0402_5% EC_CLEAR_CMOS# 45 RC35 2.7K_0402_1%
1 @ 2
CC7 1 2 1U_0402_6.3V6K RC110 60.4_0402_1%

CLRP2 1 2 SHORT PADS

RC55 1 2 0_0402_5%
RC39 1 2 1M_0402_5% SM_INTRUDER#

C +3VS C

+3VALW UC4

5
SOC_PLTRST# 1
B 4

P
Y PCI_RST# 21,34,40,45
2
A

G
TC7SH08FUF_SSOP5 SOC_RTCX2

1
3
@

1
RC44
100K_0402_5%
CC8
100P_0402_50V8J
ESD@ SOC_RTCX1
RPC7

2
2
8 1 PCH_PWROK 1 2
7 2 EC_RSMRST# RC41 10M_0402_5%
6 3 SYS_RESET#
5 4

10K_0804_8P4R_5% YC2
1 2

32.768KHZ 9PF 20PPM 9H03280012

UC1K @ SKL-U
ESD@ 1 2 SYS_RESET# Rev_1.0
CC97 100P_0402_50V8J SYSTEM POWER MANAGEMENT
1 1
ESD@ 1 2 EC_RSMRST# AT11
CC94 100P_0402_50V8J GPP_B12/SLP_S0# AP15 PM_SLP_S3# CC9 CC10
SYS_PWROK SOC_PLTRST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# 45
ESD@ 1 2 AN10 BA16 6.8P_0402_50V8C 6.8P_0402_50V8C
SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# 45,47,49 2 2
CC95 100P_0402_50V8J B5 AY16 TP@T131
EC_RSMRST# AY17 SYS_RESET# GPD10/SLP_S5#
45 EC_RSMRST# RSMRST# AN15
T31 TP@ A68 SLP_SUS# AW15
B EC_VCCST_PG B65 PROCPWRGD SLP_LAN# BB17 B
VCCST_PWRGD GPD9/SLP_WLAN# AN16
SYS_PWROK B6 GPD6/SLP_A#
+3VALW 45 SYS_PWROK PCH_PWROK SYS_PWROK PBTN_OUT#
BA20 BA15
45 PCH_PWROK EC_RSMRST# PCH_PWROK GPD3/PWRBTN# AC_PRESENT_R PBTN_OUT# 45
BB20 AY15 RC103 1 2 0_0402_5% AC_PRESENT 21,45
DSW_PWROK GPD1/ACPRESENT AU13 PM_BATLOW#
RC54 GPD0/BATLOW# PM_BATLOW# 39
AR13
1 2 WAKE# AP11 GPP_A13/SUSWARN#/SUSPWRDNACK +3VALW
GPP_A15/SUSACK# AU11
WAKE# BB15 GPP_A11/PME# AP16 SM_INTRUDER#
1K_0402_5% AM15 WAKE# INTRUDER# PM_BATLOW# 1 2
AW17 GPD2/LAN_WAKE# AM10 RC46 8.2K_0402_5%
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 SOC_VRALERT# AC_PRESENT_R 1 @ 2
GPD7/RSVD 11 OF 20 GPP_B2/VRALERT# RC48 10K_0402_5%
SOC_VRALERT# 1 @ 2
+1.0V_VCCST SKL-U_BGA1356 RC50 10K_0402_5%
1

RC52
1K_0402_5%

RC53 1 2 60.4_0402_1% EC_VCCST_PG

45 VCCST_PWRGD
2

1
100P_0402_50V8J
CC126 ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 2017/6/2 Title

SKL-U(5/12)CLK,PM,GPIO
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 10 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS

Vinafix.com

1
RC135 RC133 RC137
D 10K_0402_5% 10K_0402_5% 10K_0402_5% D
X76RAM@ X76RAM@ X76RAM@
OBRAM_ID0 OBRAM_ID1 OBRAM_ID2

2
1

1
RC136 RC134 RC138
10K_0402_5% 10K_0402_5% 10K_0402_5%
X76RAM@ X76RAM@ X76RAM@

2
+3VS

RC59 1 @ 2 4.7K_0402_5% GSPI0_MOSI

RC60 1 @ 2 150K_0402_5% GSPI1_MOSI

+3VS

C C
RPC5
8 1 DGPU_HOLD_RST#
7 2 WLBT_OFF#
6 3 DGPU_PWR_EN
5 4

10K_0804_8P4R_5%

RC83 1 2 49.9K_0402_1% UART0_RX

RC84 1 2 49.9K_0402_1% UART0_TX

UC1F @ SKL-U
Rev_1.0
LPSS ISH

RC27 1 2 499_0402_1% I2C1_SDA_TS GC6_FB_EN3V3 AN8 P2

21 GC6_FB_EN3V3 GPP_B15/GSPI0_CS# GPP_D9
AP7 P3
RC32 1 2 499_0402_1% I2C1_SCL_TS SENSOR_EC_INT AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
45 SENSOR_EC_INT GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11
AR7 P1
RC42 1 2 2.2K_0402_5% I2C0_SDA_TP GPP_B18/GSPI0_MOSI GPP_D12
OBRAM_ID0 AM5 M4
RC43 1 2 2.2K_0402_5% I2C0_SCL_TP OBRAM_ID1 AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
OBRAM_ID2 AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
AB1 GPP_D8/ISH_I2C1_SCL
36 TP_INT# GPP_C8/UART0_RXD
AB2 AD11
W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12
21 GPU_EVENT# WLBT_OFF# GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AB3
34 WLBT_OFF# GPP_C11/UART0_CTS#
34 UART0_RX AD1 U1
AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
34 UART0_TX GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
AD3 U3
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
B GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# +3VS B
AC1 DGPU_PWR_EN
GPP_C12/UART1_RXD/ISH_UART1_RXD DGPU_HOLD_RST# DGPU_PWR_EN 21,28,45
U7 AC2
36 I2C0_SDA_TP GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD GPU_ALL_PGOOD DGPU_HOLD_RST# 21
U6 AC3
36 I2C0_SCL_TP GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# DGPU_PRSNT# GPU_ALL_PGOOD 21
AB4
GPP_C15/UART1_CTS#/ISH_UART1_CTS# RC64
U8
29 I2C1_SDA_TS GPP_C18/I2C1_SDA TS_INT#
U9 AY8 2 1
29 I2C1_SCL_TS GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 TS_INT# 29
BA8
AH9 GPP_A19/ISH_GP1 BB7 4.7K_0402_5%
45 I2C2_SDA_SEN GPP_F4/I2C2_SDA GPP_A20/ISH_GP2
AH10 BA7
45 I2C2_SCL_SEN GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7
AH11 GPP_A22/ISH_GP4 AW7
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL 6 OF 20

SKL-U_BGA1356

+3VS

DGPU_PRSNT# 10K_0402_5% 2 UMA@ 1 R73

10K_0402_5% 2 DIS@ 1 R74

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 2017/6/2 Title

SKL-U(6/12)GPIO,I2C,GSPI
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 11 of 61
5 4 3 2 1
 5 4 3 2 1

SKL-U
UC1H @
Rev_1.0
Vinafix.com SSIC / USB3
PCIE / USB3 / SATA
D H8 USB3_RX1_N 37 D
USB3_1_RXN G8
USB3_1_RXP USB3_RX1_P 37
40 PCIE_PRX_DTX_N1 H13 C13
PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_TX1_N 37
40 PCIE_PRX_DTX_P1 G13 D13
PCIE_PTX_DRX_N1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_TX1_P 37
CC114 1 2 0.22U_0201_6.3V6M B17
40 PCIE_PTX_C_DRX_N1 PCIE_PTX_DRX_P1 PCIE1_TXN/USB3_5_TXN
CC115 1 2 0.22U_0201_6.3V6M A17 J6 USB3_RX2_N 37
40 PCIE_PTX_C_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6 USB3_RX2_P 37
G11 USB3_2_RXP / SSIC_RXP B13
40 PCIE_PRX_DTX_N2 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN USB3_TX2_N 37
F11 A13
40 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_TX2_P 37
CC116 1 2 0.22U_0201_6.3V6M D16
40 PCIE_PTX_C_DRX_N2 CC117 1 2 0.22U_0201_6.3V6M PCIE_PTX_DRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
40 PCIE_PTX_C_DRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN H10
H16 USB3_3_RXP B15
G16 PCIE3_RXN USB3_3_TXN A15
D17 PCIE3_RXP USB3_3_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
34 PCIE_PRX_DTX_N4 PCIE4_RXN USB3_4_TXN
34 PCIE_PRX_DTX_P4 F15 D15
CC136 1 2 0.1U_0201_10V K X5R PCIE_PTX_DRX_N4 B19 PCIE4_RXP USB3_4_TXP
34 PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PCIE4_TXN USB20_N1
CC137 1 2 0.1U_0201_10V K X5R A19 AB9 USB20_N1 37
34 PCIE_PTX_C_DRX_P4 PCIE4_TXP USB2N_1 USB20_P1
AB10 USB20_P1 37
F16 USB2P_1
21 PCIE_PRX_DTX_N5 PCIE5_RXN USB20_N2
21 PCIE_PRX_DTX_P5 E16 AD6
PCIE_PTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 37
CC142 1 2 0.22U_0201_6.3V6M C19 AD7
21 PCIE_PTX_C_DRX_N5 PCIE_PTX_DRX_P5 PCIE5_TXN USB2P_2 USB20_P2 37
CC143 1 2 0.22U_0201_6.3V6M D19
21 PCIE_PTX_C_DRX_P5 PCIE5_TXP USB20_N3
AH3
USB2N_3 USB20_P3 USB20_N3 43
21 PCIE_PRX_DTX_N6 G18 AJ3
PCIE6_RXN USB2P_3 USB20_P3 43
21 PCIE_PRX_DTX_P6 F18
C CC148 1 2 0.22U_0201_6.3V6M PCIE_PTX_DRX_N6 D20 PCIE6_RXP AD9 C
21 PCIE_PTX_C_DRX_N6 PCIE_PTX_DRX_P6 PCIE6_TXN USB2N_4
CC149 1 2 0.22U_0201_6.3V6M C20 AD10
21 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
21 PCIE_PRX_DTX_N7 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 29
21 PCIE_PRX_DTX_P7 E20 AJ2
PCIE_PTX_DRX_N7 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 29
CC144 1 2 0.22U_0201_6.3V6M B21 USB2
21 PCIE_PTX_C_DRX_N7 PCIE_PTX_DRX_P7 PCIE7_TXN/SATA0_TXN USB20_N6
CC145 1 2 0.22U_0201_6.3V6M A21 AF6
21 PCIE_PTX_C_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 36
AF7
USB2P_6 USB20_P6 36
21 PCIE_PRX_DTX_N8 G21
F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
21 PCIE_PRX_DTX_P8 PCIE_PTX_DRX_N8 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 34
CC146 1 2 0.22U_0201_6.3V6M D21 AH2
21 PCIE_PTX_C_DRX_N8 PCIE_PTX_DRX_P8 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 34
CC147 1 2 0.22U_0201_6.3V6M C21
21 PCIE_PTX_C_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
34 PCIE_PRX_DTX_N9 PCIE9_RXN USB2P_8
34 PCIE_PRX_DTX_P9 E23
B23 PCIE9_RXP AG1
34 PCIE_PTX_DRX_N9 PCIE9_TXN USB2N_9
A23 AG2
34 PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9
34 PCIE_PRX_DTX_N10 F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
34 PCIE_PRX_DTX_P10 PCIE10_RXP USB2P_10
D23
34 PCIE_PTX_DRX_N10 PCIE10_TXN USB2_COMP
C23 AB6 RC70 1 2 113_0402_1%
34 PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP USB2_ID
AG3 RC104 1 2 1K_0402_5%
RC71 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_SENSE RC105 1 2 1K_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
D56 GPP_E9/USB2_OC0# C9 USB_OC1#
D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2#
BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3#
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1
34 PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 W L_OFF#
34 PCIE_PRX_DTX_P11 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 W L_OFF# 34
D24 J3 DEVSLP2
34 PCIE_PTX_DRX_N11 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 DEVSLP2 34
C24
34 PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2
34 SATA_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
34 SATA_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 NGFF_SSD_PEDET
34 SATA_PTX_DRX_N12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 NGFF_SSD_PEDET 34
B25
34 SATA_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1
8 OF 20 GPP_E8/SATALED# +3VALW

SKL-U_BGA1356
RPC9
USB_OC2# 8 1
USB_OC0# 7 2
USB_OC3# 6 3
USB_OC1# 5 4

10K_0804_8P4R_5%

+3VS

SSD_DET@
NGFF_SSD_PEDET RC130 1 2 10K_0402_5%

@
W L_OFF# RC131 1 2 10K_0402_5%
A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(7/12)PCIE,USB,SATA
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 12 of 61
5 4 3 2 1
 5 4 3 2 1

+VL +1.2V +1.0VS_VCCIO

UC1N @ SKL-U
Rev_1.0
+1.0V_VCCST CPU POWER 3 OF 4
AU23 AK28
AU28 VDDQ_AU23 VCCIO AK30
1 VDDQ_AU28 VCCIO

1U_0402_6.3V6K
CC150
RC214 1 2 0_0402_5% AU35 AL30
Vinafix.com AU42 VDDQ_AU35
VDDQ_AU42
VCCIO
VCCIO
AL42
1 BB23 AM28
2 VDDQ_BB23 VCCIO

0.1U_0201_10V6K
CC151 @
D UC7 BB32 AM30 D
1 14 BB41 VDDQ_BB32 VCCIO AM42 +VCC_SA
+1.0VALW VIN1 VOUT1 +1.0VS_VCCIO VDDQ_BB41 VCCIO
2 13 BB47
VIN1 VOUT1 2 BB51 VDDQ_BB47 AK23
RC215 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 VDDQ_BB51 VCCSA AK25
45,49 SYSON ON1 CT1 CC152 VCCSA G23
4 11 8200P_0402_25V7K +1.0V_VCCST AM40 VCCSA G25
VBIAS GND VDDQC VCCSA G27
RC216 1 2 0_0402_5% EN_1.8VS 5 10 1 2 A18 VCCSA G28
39,44,45,49 SUSP# ON2 CT2 CC153 VCCST VCCSA J22
6 9 1000P_0402_50V7K A22 VCCSA J23
7 VIN2 VOUT2 8 VCCSTG_A22 VCCSA J27
+1.8VALW VIN2 VOUT2 VCCSA
AL23 K23
15 +1.8VS VCCPLL_OC VCCSA K25
GPAD K20 VCCSA K27
EM5209VF_DFN14_3X2 K21 VCCPLL_K20 VCCSA K28
RC217 1 2 0_0402_5% VCCPLL_K21 VCCSA K30
VCCSA
1 AM23
VCCIO_SENSE

0.1U_0201_10V6K
CC154 @
AM22
VSSIO_SENSE
H21 VSSSA_SENSE
2 VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE 52
H20
VCCSA_SENSE VCCSA_SENSE 52
14 OF 20

SKL-U_BGA1356

C C

+1.0V_VCCST +1.0VS_VCCIO
+VL +1.0VALW

1 1
0.1U_0201_10V K X5R

1U_0402_6.3V6K
CC30

CC32

UC6
@ 1 +1.0VS_VCCIO
2 2 VIN1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2
VIN2 RC79
+1.0VS_VCCIO_STG

CC28

CC34

CC35
7 6 1 2 @
VIN thermal VOUT 2 2 2
1
3 0_0805_5%
VBIAS CC33
SUSP# 4 5 @ 0.1U_0201_10V K X5R
ON GND 2
B B
TPS22961DNYR_W SON8

+1.0VS_VCCIO +1.2V
10U_0603_6.3V6M

1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M
CC36

CC37

CC38

CC39

CC40

CC41

CC42

CC29

CC43

CC44

CC45

CC128

CC46

CC47

CC48

CC49

CC50
@ @ @ @ @ @ @ @ @ @
2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(8/12)Power
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 13 of 61
5 4 3 2 1
 5 4 3 2 1

+3VALW

Vinafix.com
D
+1.0VALW +1.8VALW 1 1 D

1U_0402_6.3V6K

0.1U_0201_10V K X5R
UC1O SKL-U
Rev_1.0 +3VALW

CC81

CC79
CPU POWER 4 OF 4
AB19 2 2
AB20 VCCPRIM_1P0 AK15
P18 VCCPRIM_1P0 VCCPGPPA AG15
VCCPRIM_1P0 VCCPGPPB Y16
AF18 VCCPGPPC Y15
AF19 VCCPRIM_CORE VCCPGPPD T16
V20 VCCPRIM_CORE VCCPGPPE AF16
V21 VCCPRIM_CORE VCCPGPPF AD15
VCCPRIM_CORE VCCPGPPG
CC55 1 2 1U_0402_6.3V6K DCPDSW AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19
K17 T1 +1.0VALW
CC56 1 2 1U_0402_6.3V6K L1 VCCMPHYAON_1P0 VCCPRIM_1P0_T1
VCCMPHYAON_1P0 AA1 CC57 1 2 1U_0402_6.3V6K
N15 VCCATS_1P8
N16 VCCMPHYGT_1P0_N15 AK17 +3VL_RTC +RTCVCC
N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
CC66 1 2 1U_0402_6.3V6K P15 VCCMPHYGT_1P0_N17 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19 +3VL_RTC
P16 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 RC90 1 2 0_0402_5%
CC59 1 @ 2 1U_0402_6.3V6K K15 BB10 DCPRTC CC62 1 2 0.1U_0201_10V K X5R
L15 VCCAMPHYPLL_1P0 DCPRTC
VCCAMPHYPLL_1P0 1
A14 +1.0VALW CC82
V15 VCCCLK1 1U_0402_6.3V6K
+1.0V_APLL VCCAPLL_1P0 K19
AB17 VCCCLK2 2
Y18 VCCPRIM_1P0_AB17 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_APLL

+3VALW AD17 N20 +1.0VALW

VCCDSW_3P3_AD17 VCCCLK4
AD18
VCCDSW_3P3_AD18 Saf t y s ugges t i on r emove EE s i de , Keep PW
R s i de
AJ17 L19
VCCDSW_3P3_AJ17 VCCCLK5 +1.0VALW
C
+3V_1.8V_HDA AJ19 A10 +1.0VALW
C
+3VALW RF@ +3V_1.8V_HDA VCCHDA VCCCLK6
AJ16 AN11
+3VALW VCCSPI GPP_B0/CORE_VID0 +1.0VALW
LC4 AN13
1 2 AF20 GPP_B1/CORE_VID1
BLM15EG221SN1D_2P AF21 VCCSRAM_1P0
T19 VCCSRAM_1P0
T20 VCCSRAM_1P0
1 VCCSRAM_1P0
RF@
CC52 +3VALW AJ21
0.1U_0402_25V6 VCCPRIM_3P3_AJ21
2 1

1U_0402_6.3V6K
AK20
VCCPRIM_1P0_AK20

CC155
1 2 N18 @
CC68 1U_0402_6.3V6K VCCAPLLEBB_1P0 15 OF 20 2

SKL-U_BGA1356
@

+1.0V_APLL

LC100
1 2
RF@
BLM15EG221SN1D_2P 2
RF@
CC156
B 0.1U_0402_25V6 B
1
Close to L21

1U_0402_6.3V6K
CC157
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 2017/6/2 Title

SKL-U(9/12)Power
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 14 of 61
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT

+VCC_CORE UC1M SKL-U
UC1L SKL-U Rev_1.0
Rev_1.0 CPU POWER 2 OF 4
CPU POWER 1 OF 4
N70
A30 Vinafix.com
VCC_A30 VCC_G32
G32 A48
VCCGT
VCCGT
VCCGT
N71
A34 G33 A53 R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
D D
A44 VCC_A39 VCC_G35 G37 A62 VCCGT VCCGT R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
G30 VCC_AM38 VCC_K42 K43 AC69 VCCGT VCCGT W66
VCC_G30 VCC_K43 AC70 VCCGT VCCGT W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD VCC_SENSE VCCCORE_SENSE 52 VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSCORE_SENSE 52 VCCGT VCCGT
AK32 J45 W70 +VCC_CORE
RSVD B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
AB62 VIDALERT# A63 VR_SVID_CLK J48 VCCGT VCCGT Y62
VCCOPC_AB62 VIDSCK VR_SVID_DATA VR_SVID_CLK 52 VCCGT VCCGT
P62 D64 J50
V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 J53 VCCGT AK42
H63 VCCSTG_G20 J55 VCCGT VCCGTX_AK42 AK43
VCC_OPC_1P8_H63 +1.0VS_VCCIO J56 VCCGT VCCGTX_AK43 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 J60 VCCGT VCCGTX_AK46 AK48
C AC63 K48 VCCGT VCCGTX_AK48 AK50 C
AE63 VCCOPC_SENSE K50 VCCGT VCCGTX_AK50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
AL63 K58 VCCGT VCCGTX_AK58 AK60
AJ62 VCCEOPIO_SENSE K60 VCCGT VCCGTX_AK60 AK70
VSSEOPIO_SENSE 12 OF 20 L62 VCCGT VCCGTX_AK70 AL43
L63 VCCGT VCCGTX_AL43 AL46
SKL-U_BGA1356 L64 VCCGT VCCGTX_AL46 AL50
@ L65 VCCGT VCCGTX_AL50 AL53
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
+1.0V_VCCST N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
VCCGT VCCGTX_BB66
VCCGT_SENSE J70 AK62
52 VCCGT_SENSE VSSGT_SENSE VCCGT_SENSE VCCGTX_SENSE
J69 AL61
52 VSSGT_SENSE VSSGT_SENSE 13 OF 20VSSGTX_SENSE
1

RC94
56_0402_5%
B SKL-U_BGA1356 B
@
2

SOC_SVID_ALERT# 1 2
VR_ALERT# 52
RC95 220_0402_5%

+1.0V_VCCST
1

RC96
100_0402_1%
2

VR_SVID_DATA
VR_SVID_DATA 52

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(10/12)Power,SVID
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 15 of 61
5 4 3 2 1
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D D
SKL-U SKL-U
UC1P UC1Q
Rev_1.0 Rev_1.0 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3 Rev_1.0
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
C AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10 C
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
B AK27 VSS VSS AR5 B58 VSS VSS F1 B
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(11/12)GND
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 17, 2017 Sheet 16 of 61
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Vinafix.com UC1T SKL-U

Rev_1.0
SPARE
D D

+1.8VALW AW69 F6
SKL-U AW68 RSVD_AW69 RSVD_F6 E3 42E_SOC_XTAL24_IN_R
UC1S RSVD_AW68 RSVD_E3
Rev_1.0 AU56 C11
RESERVED SIGNALS-1 RC98 AW48 RSVD_AU56 RSVD_C11 B11
0_0402_5% 42E_SOC_XTAL24_OUT_R C7 RSVD_AW48 RSVD_B11 A11
E68 BB68 1 @ 2 RSVD1 U12 RSVD_C7 RSVD_A11 D12
B67 CFG[0] RSVD_TP_BB68 BB69 U11 RSVD_U12 RSVD_D12 C12
D65 CFG[1] RSVD_TP_BB69 H11 RSVD_U11 RSVD_C12 F52
CFG[2] 1 RSVD_H11 RSVD_F52

1U_0402_6.3V6K
D67 AK13
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 20 OF 20
CFG[4] RSVD_TP_AK12

CC98
C68 @
D68 CFG[5] BB2 2 SKL-U_BGA1356
C67 CFG[6] RSVD_BB2 BA3 @
F71 CFG[7] RSVD_BA3
G69 CFG[8]
F70 CFG[9] AU5
G68 CFG[10] TP5 AT5
H70 CFG[11] TP6
G71 CFG[12]
H69 CFG[13] D5
G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2 42E_SOC_XTAL24_IN_R 1 2 33E_SOC_XTAL24_IN
E63 RSVD_B2 C2 RC58 EMI@ 33_0201_5%
F63 CFG[16] RSVD_C2
CFG[17] B3
E66 RSVD_B3 A3 LC99 @EMI@
F66 CFG[18] RSVD_A3 1 2
C CFG[19] AW1 1 2 C
CFG_RCOMP E60 RSVD_AW1 1 2
CFG_RCOMP E1 4 3 RC38 1M_0402_5%
E8 RSVD_E1 E2 4 3
ITP_PMODE RSVD_E2 DLM0NSN900HY2D_4P
AY2 BA4 YC3 SJ10000UJ00
AY1 RSVD_AY2 RSVD_BA4 BB4 42E_SOC_XTAL24_OUT_R 1 2 33E_SOC_XTAL24_OUT
24MHZ_18PF_XRCGB24M000F2P51R0
RSVD_AY1 RSVD_BB4 RC63 EMI@ 33_0201_5%
D1 A4 3 1
D3 RSVD_D1 RSVD_A4 C4 3 1
RSVD_D3 RSVD_C4 NC NC
1 1

27P_0402_50V8J
CC19

27P_0402_50V8J
CC20
K46 BB5
K45 RSVD_K46 TP4 4 2
RSVD_K45 A69
AL25 RSVD_A69 B69 2 2
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC97 1 @ 2 0_0402_5%
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 RC213 1 2 0_0402_5%
J68 RSVD_J71 VSS_AY71 AR56
B RSVD_J68 ZVM# B
F65 AW71
G65 VSS_F65 RSVD_TP AW70
VSS_G65 RSVD_TP
F61 AP56
E61 RSVD_F61 MSM# C64 SKL_CNL# +1.0V_VCCST
RSVD_E61 PROC_SELECT#
19 OF 20 1 @ 2
RC99 100K_0402_5%
1 2 CFG_RCOMP SKL-U_BGA1356
RC100 49.9_0402_1% @

1 2 CFG4
RC101 1K_0402_5%

A A

Security Classification
2017/5/3
Compal Secret Data
2017/6/2 Title
Compal Electronics, Inc.
SKL-U(12/12)CFG,RSVD
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 17 of 61
5 4 3 2 1
 A B C D E

+DDR_VREF_CA +DDR_VREF_CA +DDR_VREF_CA

+DDR_VREF_CA

U4 U2 U3
U1
M1 G2 DDR_A_D3 M1 G2 DDR_A_D17 M1 G2 DDR_A_D33
VREFCA DQL0 F7 DDR_A_D2 VREFCA DQL0 F7 DDR_A_D18 VREFCA DQL0 F7 DDR_A_D35 M1 G2 DDR_A_D50
DQL1 DDR_A_D5 DQL1 DDR_A_D16 DQL1 DDR_A_D32 VREFCA DQL0 DDR_A_D51
0.047U_0402_25V7K

0.047U_0402_25V7K

0.047U_0402_25V7K
H3 H3 H3 F7
DDR_A_MA0 DQL2 DDR_A_D7 DDR_A_MA0 DQL2 DDR_A_D22 DDR_A_MA0 DQL2 DDR_A_D39 DQL1 DDR_A_D48

0.047U_0402_25V7K
P3 H7 P3 H7 P3 H7 H3
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D4 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D20 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D36 DDR_A_MA0 P3 DQL2 H7 DDR_A_D55
A1 DQL4 A1 DQL4 A1 DQL4 A0 DQL3
1

1
DDR_A_MA2 R3 H8 DDR_A_D6 DDR_A_MA2 R3 H8 DDR_A_D23 DDR_A_MA2 R3 H8 DDR_A_D38 DDR_A_MA1 P7 H2 DDR_A_D52
CD271

CD125

CD126
A2 DQL5 A2 DQL5 A2 DQL5 A1 DQL4

1
DDR_A_MA3 N7 J3 DDR_A_D0 DDR_A_MA3 N7 J3 DDR_A_D21 DDR_A_MA3 N7 J3 DDR_A_D34 DDR_A_MA2 R3 H8 DDR_A_D54

CD127
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D1 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D19 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D37 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D49

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2

2
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D53

2
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D9 DDR_A_MA7 R8 A6 A3 DDR_A_D28 DDR_A_MA7 R8 A6 A3 DDR_A_D44 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D11 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D31 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D43 DDR_A_MA7 R8 A6 A3 DDR_A_D60
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D12 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D29 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D41 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D63
1 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D15 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D30 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D47 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D57 1
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D13 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D25 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D40 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D62
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D10 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D26 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D42 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D56
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D8 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D24 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D45 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D58
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D14 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D27 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D46 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D61
A14/WE DQU7 A14/WE DQU7 A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D59
DDR_A_BA0 N2 DDR_A_BA0 N2 DDR_A_BA0 N2 A14/WE DQU7
7,18,19 DDR_A_BA0 DDR_A_BA1 BA0 7,18,19 DDR_A_BA0 DDR_A_BA1 BA0 7,18,19 DDR_A_BA0 DDR_A_BA1 BA0 DDR_A_BA0
N8 B3 +1.2V N8 B3 +1.2V N8 B3 +1.2V N2
7,18,19 DDR_A_BA1 BA1 VDD 7,18,19 DDR_A_BA1 BA1 VDD 7,18,19 DDR_A_BA1 BA1 VDD 7,18,19 DDR_A_BA0 DDR_A_BA1 BA0
B9 B9 B9 N8 B3 +1.2V
VDD VDD VDD 7,18,19 DDR_A_BA1 BA1 VDD
+1.2V E2 D1 +1.2V E2 D1 +1.2V E2 D1 B9
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 E2 VDD D1
DML/DBIL VDD DML/DBIL VDD DML/DBIL VDD +1.2V DMU/DBIU VDD
J1 J1 J1 E7 G7
VDD J9 VDD J9 VDD J9 DML/DBIL VDD J1
VDD L1 VDD L1 VDD L1 VDD J9
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 VDD L1
7,18 DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD 7,18 DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD 7,18 DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
K8 R1 K8 R1 K8 R1 K7 L9
7,18 DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD 7,18 DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD 7,18 DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD 7,18 DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD
K2 T9 K2 T9 K2 T9 K8 R1
7,18,19 DDR_A_CKE0 CKE VDD 7,18,19 DDR_A_CKE0 CKE VDD 7,18,19 DDR_A_CKE0 CKE VDD 7,18 DDR_A_CLK#0 DDR_A_CKE0 CK_c VDD
K2 T9
7,18,19 DDR_A_CKE0 CKE VDD
A1 A1 A1
VDDQ A9 VDDQ A9 VDDQ A9 A1
VDDQ C1 VDDQ C1 VDDQ C1 VDDQ A9
VDDQ D9 VDDQ D9 VDDQ D9 VDDQ C1
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ D9
VDDQ F8 VDDQ F8 VDDQ F8 VDDQ F2
DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 DDR_A_ODT0 K3 VDDQ G1 VDDQ F8
7,19 DDR_A_ODT0 DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_CS#0 ODT VDDQ DDR_A_ODT0 VDDQ
L7 G9 L7 G9 L7 G9 K3 G1
7,18,19 DDR_A_CS#0 DDR_A_MA16 CS VDDQ 7,18,19 DDR_A_CS#0 DDR_A_MA16 CS VDDQ 7,18,19 DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_CS#0 ODT VDDQ
L8 J2 L8 J2 L8 J2 L7 G9
DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ DDR_A_MA15 RAS VDDQ 7,18,19 DDR_A_CS#0 DDR_A_MA16 CS VDDQ
M8 J8 M8 J8 M8 J8 L8 J2
CAS VDDQ CAS VDDQ CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
B2 B2 B2 CAS VDDQ
VSS E1 DDP@ VSS E1 DDP@ VSS E1 DDP@ B2
VSS E9 RD200 1 2 240_0402_1% VSS E9 RD201 1 2 240_0402_1% VSS E9 RD202 1 2 240_0402_1% VSS E1 DDP@
VSS G8 VSS G8 VSS G8 VSS E9 RD203 1 2 240_0402_1%
DDR_A_DQS#1 A7 VSS K1 DDR_A_DQS#3 A7 VSS K1 DDR_A_DQS#5 A7 VSS K1 VSS G8
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS3 B7 DQSU_c VSS K9 DDR_A_DQS5 B7 DQSU_c VSS K9 DDR_A_DQS#7 A7 VSS K1
DDR_A_DQS#0 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS#2 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS#4 F3 DQSU_t VSS M9 DDR_A_BG1_R DDR_A_DQS7 B7 DQSU_c VSS K9
DDR_A_DQS0 DQSL_c VSS DDR_A_BG1_R 19 DDR_A_DQS2 DQSL_c VSS DDR_A_DQS4 DQSL_c VSS DDR_A_DQS#6 DQSU_t VSS DDR_A_BG1_R
G3 N1 G3 N1 G3 N1 F3 M9
DQSL_t VSS T1 DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_DQS6 G3 DQSL_c VSS N1
MEMRST# P1 VSS MEMRST# P1 VSS MEMRST# P1 VSS DQSL_t VSS T1
RESET RESET RESET MEMRST# P1 VSS
1 2 RU160 F9 1 2 RU161 F9 1 2 RU162 F9 RESET
240_0402_1% ZQ 240_0402_1% ZQ 240_0402_1% ZQ 1 2 RU163 F9
240_0402_1% ZQ
M_A_ACT# L3 A2 M_A_ACT# L3 A2 M_A_ACT# L3 A2
2 7,19 M_A_ACT# DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ DDR_A_BG0 ACT VSSQ M_A_ACT# 2
7,19 DDR_A_BG0 M2 A8 M2 A8 M2 A8 L3 A2
N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 N9 BG0 VSSQ C9 DDR_A_BG0 M2 ACT VSSQ A8
DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2 N9 BG0 VSSQ C9
7 DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ DDR_A_ALERT# TEN VSSQ
7,19 DDR_A_PARITY T3 D8 T3 D8 T3 D8 P9 D2
PAR VSSQ E3 PAR VSSQ E3 PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8
T7 VSSQ E8 T7 VSSQ E8 T7 VSSQ E8 PAR VSSQ E3
B1 NC VSSQ F1 B1 NC VSSQ F1 B1 NC VSSQ F1 T7 VSSQ E8
+2.5V VPP VSSQ +2.5V VPP VSSQ +2.5V VPP VSSQ NC VSSQ
R9 H1 R9 H1 R9 H1 +2.5V B1 F1
VPP VSSQ H9 VPP VSSQ H9 VPP VSSQ H9 R9 VPP VSSQ H1
96-BALL VSSQ 96-BALL VSSQ 96-BALL VSSQ VPP VSSQ H9
SDRAM DDR4 SDRAM DDR4 SDRAM DDR4 96-BALL VSSQ
K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 K4AAG165WB-MCRC C38 SDRAM DDR4
X76RAM@ X76RAM@ X76RAM@ K4AAG165WB-MCRC C38
X76RAM@

7,19 DDR_A_MA[0..16]

7 DDR_A_DQS#[0..7]

7 DDR_A_DQS[0..7]
DDP@
7 DDR_A_D[0..63] DDR_A_BG1_R RD204 1 2 0_0402_5% DDR_A_BG1 7

SDP@
RD205 1 2 0_0402_5%

+0.6VS

DDR_A_CLK0 RU166 1 2 36_0402_1%

3 DDR_A_CLK#0 3
RU167 1 2 36_0402_1%
DDR_A_CLK0
1
@
CD273
3300P_0402_50V7K
DDR_A_CLK#0 2
+1.2V

DDR_A_ALERT# RD41 2 1 49.9_0402_1%

DDR_DRAMRST# RD46 1 2 0_0402_5% MEMRST#

7,20 DDR_DRAMRST#

1
CD36
100P_0201_25V8J
2 @ +1.2V
2

RD195
1.8K_0402_1%
RD11 +DDR_VREF_CA
2.7_0402_1%
2 1
7 +0.6V_A_VREFCA
1

4
CD24 4
0.022U_0402_16V7K
2
1

RD13 RD206
24.9_0402_1% 1.8K_0402_1%
2

Compal Secret Data

LA-F661P
Security Classification
2014/02/14 2015/02/14 Title

DDR4 ON BOARD CHIPS

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 18 of 61
A B C D E
 5 4 3 2 1

7,18 DDR_A_MA[0..16]

+0.6VS

Vinafix.com RP17
D
1 8 D
2 7
DDR_A_MA0 3 6
DDR_A_MA6 4 5
+1.2V
36_0804_8P4R_5%

CU198

CU195

CU197

CU200

CU199

CU196

CU201

CD211

CD210

CD212

CD213

CD214

CD215

CD216

CD217

CD218
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

@ @ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP18
DDR_A_BG0 1 8
7,18 DDR_A_BG0 DDR_A_MA10 2 7
DDR_A_MA4 3 6
DDR_A_BA0 4 5
7,18 DDR_A_BA0
36_0804_8P4R_5%

RP19
M_A_ACT# 1 8
7,18 M_A_ACT# DDR_A_CS#0 2 7
7,18 DDR_A_CS#0 DDR_A_MA15 3 6
4 5

1 36_0804_8P4R_5%
1 1 1 1 1 DDR_A_BG1_R
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
+ CU89 18 DDR_A_BG1_R 1 2
CD25

CD26

CD27

CD39

CD40
330U_D2_2V_Y RD211 36_0402_1%
@
2 2 2@ 2 2 2 RP20
DDR_A_CKE0 1 8
7,18 DDR_A_CKE0 DDR_A_ODT0
7,18 DDR_A_ODT0 2 7
DDR_A_MA16 3 6
DDR_A_MA14 4 5

36_0804_8P4R_5%

RP21
DDR_A_MA13 1 8
C DDR_A_MA8 C
2 7
DDR_A_PARITY 3 6
7,18 DDR_A_PARITY DDR_A_MA11 4 5

36_0804_8P4R_5%

RP22
DDR_A_MA12 1 8
DDR_A_MA3 2 7
DDR_A_BA1 3 6
7,18 DDR_A_BA1 DDR_A_MA1
+2.5V +0.6VS 4 5

36_0804_8P4R_5%
CU206

CU203

CU205

CU208

CU207

CU204

CU209

CU210

CU216

CU212

CU213

CU218

CU215

CU214

CU217

CU211
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 @ 1

@ @ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RP24
DDR_A_MA5 1 8
DDR_A_MA7 2 7
DDR_A_MA9 3 6
DDR_A_MA2 4 5

36_0804_8P4R_5%

1 1 1 1 1 1@ 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
CD41

10U_0402_6.3V6M

CD220

10U_0402_6.3V6M

CD219

CD42

CD43

CD47

CD46

B 2 2 2 2 2 2 2 B

@ @

A A

Compal Secret Data

LA-F661P
Security Classification
2014/02/14 2015/02/14 Title

DDR4 ON BOARD CHIPS

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 19 of 61
5 4 3 2 1
 A B C D E

7 DDR_B_DQS#[0..7]

7 DDR_B_D[0..63]

7 DDR_B_DQS[0..7]

7 DDR_B_MA[0..16] +1.2V +1.2V

DDR_B_BA0 JDIMM1
7 DDR_B_BA0 DDR_B_BA1
7 DDR_B_BA1 DDR_B_BG0 1 2
7 DDR_B_BG0 DDR_B_BG1 DDR_B_D10 VSS1 VSS2 DDR_B_D15
3 4
7 DDR_B_BG1 DQ5 DQ4
5 6
DDR_B_D11 7 VSS3 VSS4 8 DDR_B_D14

7 DDR_B_CLK0
DDR_B_CLK0
DDR_B_CLK#0
Vinafix.com DDR_B_DQS#1
DDR_B_DQS1
9
11
13
15
DQ1
VSS5
DQS0_c
DQS0_t
DQ0
VSS6
DM0_n/DBI0_n
VSS7
10
12
14
16 DDR_B_D12 +1.2V
7 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_D8 VSS8 DQ6
1 17 18 1
7 DDR_B_CLK1 DDR_B_CLK#1 DQ7 VSS9 DDR_B_D13
19 20
7 DDR_B_CLK#1 DDR_B_D9 VSS10 DQ2
21 22
23 DQ3 VSS11 24 DDR_B_D4
DDR_B_CKE0 DDR_B_D0 25 VSS12 DQ12 26 +DIMM_VREF_DQ
7 DDR_B_CKE0 DDR_B_CKE1 DQ13 VSS13 DDR_B_D5
27 28
7 DDR_B_CKE1 DDR_B_CS#0 DDR_B_D1 VSS14 DQ8
29 30
7 DDR_B_CS#0 DQ9 VSS15

2
DDR_B_CS#1 31 32 DDR_B_DQS#0 RD194
7 DDR_B_CS#1 VSS16 DQS1_c DDR_B_DQS0
33 34 1K_0402_1%
35 DM1_n/DBI_n DQS1_t 36 RD10
PCH_SMB_DATA DDR_B_D7 37 VSS17 VSS18 38 DDR_B_D2 2_0402_1%
8 PCH_SMB_DATA PCH_SMB_CLK DQ15 DQ14
39 40 2 1
8 PCH_SMB_CLK 7 +0.6V_B_VREFDQ

1
DDR_B_D6 41 VSS19 VSS20 42 DDR_B_D3
43 DQ10 DQ11 44
DDR_B_ODT0 DDR_B_D17 45 VSS21 VSS22 46 DDR_B_D20
7 DDR_B_ODT0 DDR_B_ODT1 DQ21 DQ20 1
47 48
7 DDR_B_ODT1 DDR_B_D16 VSS23 VSS24 DDR_B_D21
49 50 CD21
51 DQ17 DQ16 52 0.022U_0402_16V7K
DDR_B_DQS#2 53 VSS25 VSS26 54 2
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
57 DQS2_t VSS27 58 DDR_B_D23
VSS28 DQ22

2
DDR_B_D19 59 60 RD12 RD199
61 DQ23 VSS29 62 DDR_B_D22
VSS30 DQ18 24.9_0402_1% 1K_0402_1%
DDR_B_D18 63 64
65 DQ19 VSS31 66 DDR_B_D29
DDR_B_D25 67 VSS32 DQ28 68

1
69 DQ29 VSS33 70 DDR_B_D28
DDR_B_D24 71 VSS34 DQ24 72
+1.2V 73 DQ25 VSS35 74 DDR_B_DQS#3
75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
DDR_B_D31 79 VSS37 VSS38 80 DDR_B_D30
81 DQ30 DQ31 82
DDR_B_D26 VSS39 VSS40 DDR_B_D27
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 83 84
85 DQ26 DQ27 86 +1.2V
87 VSS41 VSS42 88
CB5/NC CB4/NC
CD4

CD5

CD6

CD7

CD8

CD9

CD17

CD18

89 90
2 2 2 2 2 2 2 2 91 VSS43 VSS44 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
97 DQS8_c DM8_n/DBI_n/NC 98
99 DQS8_t VSS47 100
VSS48 CB6/NC

1
101 102 RD43
103 CB2/NC VSS49 104
VSS50 CB7/NC 470_0402_1%
105 106 @
2 +1.2V 107 CB3/NC VSS51 108 DDR_DRAMRST#_R 2
DDR_B_CKE0 109 VSS52 RESET_n 110 DDR_B_CKE1

2
111 CKE0 CKE1 112 DDR_DRAMRST#_R RD45 1 2 0_0402_5%
DDR_B_BG1 VDD1 VDD2 1 DDR_DRAMRST# 7,18
113 114
DDR_B_BG0 BG1 ACT_n DDR_B_ACT# 7
10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

115 116 CD34

BG0 ALERT_n DDR_B_ALERT# 7 100P_0201_25V8J
117 118
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11 2 @
1 1 1 1 1 1 1 1 DDR_B_MA9 A12 A11 DDR_B_MA7
121 122
A9 A7
CD10

CD11

CD12

CD13

CD14

CD19

CD15

CD20

123 124
DDR_B_MA8 125 VDD5 VDD6 126 DDR_B_MA5
2 2 2 2 2 2 2 2 DDR_B_MA6 127 A8 A5 128 DDR_B_MA4 +3VS +3VS +3VS
@ @ @ 129 A6 A4 130
DDR_B_MA3 131 VDD7 VDD8 132 DDR_B_MA2
DDR_B_MA1 133 A3 A2 134 DDR_B_EVENT# 1 @ 2 RD165

2
1

1
135 A1 EVENT_n/NF 136 240_0402_1% RD207 RD108 @ RD208
DDR_B_CLK0 137 VDD9 VDD10 138 DDR_B_CLK1 @ 0_0402_5% 0_0402_5% 0_0402_5%
DDR_B_CLK#0 139 CK0_t CK1_t/NF 140 DDR_B_CLK#1
141 CK0_c CK1_c/NF 142
143 VDD11 VDD12 144 DDR_B_MA0 DDR_B_SA2 DDR_B_SA1 DDR_B_SA0

2
7 DDR_B_PARITY PARITY A0

DDR_B_BA1 145 146 DDR_B_MA10

2
+0.6VS 147 BA1 A10/AP 148 RD209 RD138 RD210
DDR_B_CS#0 149 VDD13 VDD14 150 DDR_B_BA0 0_0402_5% @ 0_0402_5% 0_0402_5%
DDR_B_MA14 151 CS0_n BA0 152 DDR_B_MA16
153 WE_n/A14 RAS_n/A16 154
DDR_B_ODT0 155 VDD15 VDD16 156 DDR_B_MA15

1
1

1
DDR_B_CS#1 157 ODT0 CAS_n/A15 158 DDR_B_MA13
1 1 1 1 1 1 CS1_n A13 +DIMM_VREF_DQ
10U_0603_6.3V6M

10U_0603_6.3V6M

CD30 CD31 CD32 CD33 159 160

DDR_B_ODT1 VDD17 VDD18
CD22

CD23

161 162
163 ODT1 C0/CS2_n/NC 164
2 2 2 @ 2 2@ 2 VDD19 VREFCA DDR_B_SA2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

165 166
167 C1, CS3_n,NC SA2 168
DDR_B_D36 169 VSS53 VSS54 170 DDR_B_D33
171 DQ37 DQ36 172
DDR_B_D37 173 VSS55 VSS56 174 DDR_B_D32
175 DQ33 DQ32 176
DDR_B_DQS#4 177 VSS57 VSS58 178
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180
181 DQS4_t VSS59 182 DDR_B_D35
DDR_B_D38 183 VSS60 DQ39 184
+3VS 185 DQ38 VSS61 186 DDR_B_D39
DDR_B_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D44
DDR_B_D40 191 VSS64 DQ45 192
3 3
193 DQ44 VSS65 194 DDR_B_D45
DDR_B_D41 195 VSS66 DQ41 196
+3VS_DIMM 197 DQ40 VSS67 198 DDR_B_DQS#5
199 VSS68 DQS5_c 200 DDR_B_DQS5
201 DM5_n/DBI5_n DQS5_t 202
DDR_B_D46 203 VSS69 VSS70 204 DDR_B_D43
1 1 DQ46 DQ47
CD28 @ 205 206
CD35 0.1U_0201_10V6K DDR_B_D42 207 VSS71 VSS72 208 DDR_B_D47
2.2U_0402_6.3V6M 209 DQ42 DQ43 210
2 2 DDR_B_D52 211 VSS73 VSS74 212 DDR_B_D48
213 DQ52 DQ53 214
DDR_B_D53 215 VSS75 VSS76 216 DDR_B_D49
217 DQ49 DQ48 218
DDR_B_DQS#6 VSS77 VSS78
close to DIMM DDR_B_DQS6
219
DQS6_c DM6_n/DBI6_n
220
221 222
223 DQS6_t VSS79 224 DDR_B_D54
DDR_B_D51 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D50
DDR_B_D55 229 VSS82 DQ50 230
+2.5V 231 DQ51 VSS83 232 DDR_B_D61
DDR_B_D56 233 VSS84 DQ60 234
235 DQ61 VSS85 236 DDR_B_D60
DDR_B_D57 237 VSS86 DQ57 238
239 DQ56 VSS87 240 DDR_B_DQS#7
+2.5V 241 VSS88 DQS7_c 242 DDR_B_DQS7 +0.6VS
243 DM7_n/DBI7_n DQS7_t 244
DDR_B_D59 245 VSS89 VSS90 246 DDR_B_D58
247 DQ62 DQ63 248
DDR_B_D63 249 VSS91 VSS92 250 DDR_B_D62
1 1 DQ58 DQ59
10U_0402_6.3V6M

CD37 CD29 251 252

PCH_SMB_CLK 253 VSS93 VSS94 254 PCH_SMB_DATA
+3VS_DIMM 255 SCL SDA 256 DDR_B_SA0
2 2 VDDSPD SA0
1U_0402_6.3V6K

257 258
259 VPP1 VTT 260 DDR_B_SA1
261 VPP2 SA1 262
GND1 GND2

LOTES_ADDR0205-P002A
ME@

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10
Compal Electronics, Inc.
DDR4_DIMM
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 20 of 61
A B C D E
 A B C D E

+1.8VSDGPU_AON
RVP1
UV1A DIS@ 10K_0804_8P4R_5%
VGA_OVERT# 8 1
AN12 Part 1 of 7 VGA_ALERT 7 2
12 PCIE_PTX_C_DRX_P5 PEX_RX0 DGPU_VID FRM_LCK#
AM12 P6 6 3
12 PCIE_PTX_C_DRX_N5 PEX_RX0_N GPIO0 GC6_FB_EN1V8 DGPU_VID 55 ACIN_BUF
AN14 M3 DIS@ 5 4
12 PCIE_PTX_C_DRX_P6 PEX_RX1 GPIO1 GPU_EVENT#_1
AM14 L6 DV1 2 1
12 PCIE_PTX_C_DRX_N6 PEX_RX1_N GPIO2 DGPU_S_VID GPU_EVENT# 11
AP14 P5 DIS@
12 PCIE_PTX_C_DRX_P7 PEX_RX2 GPIO3 1.8VSDGPU_MAIN_EN
AP15 P7 RB751S-40 SOD-523
12 PCIE_PTX_C_DRX_N7 PEX_RX2_N GPIO4 FRM_LCK# 1.8VSDGPU_MAIN_EN 28
AN15 L7 RVP2
12 PCIE_PTX_C_DRX_P8 PEX_RX3 GPIO5 DGPU_PSI
AM15 M7 10K_0804_8P4R_5%
12 PCIE_PTX_C_DRX_N8
AN17
AM17
Vinafix.com
PEX_RX3_N
PEX_RX4
PEX_RX4_N
GPIO6
GPIO7
GPIO8
N8
L3 VRAM_VDD_CTL
VGA_ALERT
DGPU_PSI

VRAM_VDD_CTL
55

58
2
RV253
1 @ +3VS
GPU_EVENT#_1
VRAM_VREF_CTL
GC6_FB_EN1V8
8
7
1
2
AP17 M2 10K_0402_5% 6 3
1
AP18 PEX_RX5 GPIO9 L1 VRAM_VREF_CTL 1.8VSDGPU_MAIN_EN 5 4
1

AN18 PEX_RX5_N GPIO10 M5 VRAM_VREF_CTL 26,27

PEX_RX6 GPIO11 ACIN_BUF DIS@
AM18 N3 DV2 2 1 DIS@
PEX_RX6_N GPIO12 AC_PRESENT 10,45
AN20 M4

GPIO
AM20 PEX_RX7 GPIO13 N4 RB751S-40 SOD-523 SYS_PEX_RST_MON# RV1 2 @ 1 10K_0402_5%
AP20 PEX_RX7_N GPIO14 P2 VGA_I2CS_SDA RV2 1 DIS@ 2 1.8K_0402_1%
AP21 PEX_RX8 GPIO15 R8 SYS_PEX_RST_MON# VGA_I2CS_SCL RV3 1 DIS@ 2 1.8K_0402_1%
AN21 PEX_RX8_N GPIO16 M6 DGPU_PSI RV4 2 DIS@ 1 10K_0402_5%
AM21 PEX_RX9 GPIO17 R1 RV247 GPU_PEX_RST_HOLD# RV82 2 @ 1 10K_0402_5%
AN23 PEX_RX9_N GPIO18 P3 2 1 @ PLTRST_VGA#_1V8 DGPU_S_VID RV264 2 DIS@ 1 10K_0402_5%
AM23 PEX_RX10 GPIO19 P4 10K_0402_5%
AP23 PEX_RX10_N GPIO20 P1 RV248
AP24 PEX_RX11 GPIO21 P8 DIS@ 2 1 DIS@ PLTRST_VGA#_1V8
AN24 PEX_RX11_N GPIO22 T8 GPU_PEX_RST_HOLD# QV1A 10K_0402_5%
PEX_RX12 GPIO23

5
AM24 L2 PJT138KA 2N SOT363-6 DIS@
AN26 PEX_RX12_N GPIO24 R4 VGA_OVERT# 2 RV260 1 VGA_OVERT#_R 4 3 GPU_OVERT# TP12 @ QV2A

G
PEX_RX13 GPIO25 23 VGA_OVERT#

5
AM26 R5 PJT138KA 2N SOT363-6
PEX_RX13_N GPIO26 VGA_I2CS_SCL

D
AP26 U3 0_0402_5% 4 3

G
PEX_RX14 GPIO27 EC_SMB_CK2 8,35,45
AP27 @ RV249
PEX_RX14_N PLTRST_VGA#_1V8

D
AN27 2 1 RV250
AM27 PEX_RX15 AK9 DIS@ 10K_0402_5% 2 1 DIS@ PLTRST_VGA#_1V8
PEX_RX15_N NC AL10 10K_0402_5%
NC AL9 DIS@ DIS@
CV210 1DIS@ 20.22U_0201_6.3V6K PCIE_PRX_C_DTX_P5AK14 NC AM9 QV1B QV2B
12 PCIE_PRX_DTX_P5 PEX_TX0 NC

2
CV211 1DIS@ 20.22U_0201_6.3V6K PCIE_PRX_C_DTX_N5 AJ14 AN9 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
12 PCIE_PRX_DTX_N5 PCIE_PRX_C_DTX_P6AH14 PEX_TX0_N NC VGA_ALERT VGA_I2CS_SDA
CV212 1DIS@ 20.22U_0201_6.3V6K AG10 1 6 1 6

G
12 PCIE_PRX_DTX_P6 PCIE_PRX_C_DTX_N6AG14 PEX_TX1 NC GPU_PROHOT 35,45,47 EC_SMB_DA2 8,35,45
CV213 1DIS@ 20.22U_0201_6.3V6K AP8
12 PCIE_PRX_DTX_N6 PCIE_PRX_C_DTX_P7AK15 PEX_TX1_N NC

D
CV214 1DIS@ 20.22U_0201_6.3V6K AK26
12 PCIE_PRX_DTX_P7 PCIE_PRX_C_DTX_N7 AJ15 PEX_TX2 NC
CV215 1DIS@ 20.22U_0201_6.3V6K AJ26
12 PCIE_PRX_DTX_N7 PCIE_PRX_C_DTX_P8 AL16 PEX_TX2_N NC
CV216 1DIS@ 20.22U_0201_6.3V6K XV1 DIS@
12 PCIE_PRX_DTX_P8 PCIE_PRX_C_DTX_N8AK16 PEX_TX3
CV217 1DIS@ 20.22U_0201_6.3V6K 27MHZ_10PF_XRCGB27M000F2P18R0

PCI EXPRESS
12 PCIE_PRX_DTX_N8 PEX_TX3_N
AK17 RV80
AJ17 PEX_TX4 XTALOUT 1 2 XTALOUT_R 3 1 XTALIN +3VS +3VS
2 AH17 PEX_TX4_N AP9 470_0402_5% 3 1 2
AG17 PEX_TX5 TS_VREF NC NC
PEX_TX5_N 1 1

2
AK18 DIS@ UV11 RV83

18P_0402_50V8J

18P_0402_50V8J
AJ18 PEX_TX6 DIS@ 4 2 DIS@
PEX_TX6_N 10K_0402_5%
AL19 MC74VHC1G09DFT2G_SC70-5 DIS@
PEX_TX7

5
AK19 +1.8VSDGPU_AON CV1 2 CV2 2 VGA_CORE_PG 1
AK20 PEX_TX7_N B 4

G VCC
GPU_ALL_PGOOD 11

1
AJ20 PEX_TX8 2 Y
PEX_TX8_N VGA_I2CB_SCL 58 1.5VS_DGPU_PG A
AH20 R7 RV86 1 DIS@ 2 2K_0402_5%
AG20 PEX_TX9 I2CB_SCL R6 VGA_I2CB_SDA RV85 1 DIS@ 2 2K_0402_5%
AK21 PEX_TX9_N I2CB_SDA

3
AJ21 PEX_TX10 R2 VGA_I2CC_SCL RV5 1 DIS@ 2 2K_0402_5% +1.8VSDGPU_MAIN
PEX_TX10_N I2CC_SCL VGA_I2CC_SDA
I2C

AL22 R3 RV6 1 DIS@ 2 2K_0402_5%

AK22 PEX_TX11 I2CC_SDA +5VALW
AK23 PEX_TX11_N T4 VGA_I2CS_SCL +GPU_PLLVDD
AJ23 PEX_TX12 I2CS_SCL T3 VGA_I2CS_SDA 1 RV261 2
PEX_TX12_N I2CS_SDA +1.8VSDGPU_MAIN
AH23 DIS@ Level shift 10K_0402_5%
AG23 PEX_TX13 +GPU_PLLVDD LV1 1 2 DIS@
PEX_TX13_N

1
AK24 CHILISIN PBY160808T-330Y-N RV265 VGA_ALERT 21
PEX_TX14

5
4.7U_0402_6.3V6M
AJ24 1 1 1 1 1 PCH side 100K_0402_5%
PEX_TX14_N DGPU_CLKREQ# 4

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

22U_0603_6.3V6M
AL25 CV42 CV4 3 DIS@

G
PEX_TX15 VGA_CLKREQ# 10
AK25 CV5 CV6 CV3 D
PEX_TX15_N

3
GPU_PROHOT# 5

D
DIS@ DIS@ @ DIS@ DIS@ QV5A DIS@ DIS@

2
AD8 2 2 2 2 2 PJT138KA 2N SOT363-6 G QV11B
AJ11 XS_PLLVDD +1.8VSDGPU_AON 2N7002KDW_SOT363-6
NC AE8 S
AL13 SP_PLLVDD +3VS D
10 CLK_PEG_VGA

4
PEX_REFCLK

6
AK13 AD7 2 DIS@
10 CLK_PEG_VGA# PEX_REFCLK_N VID_PLLVDD 21,35,45,47 GPU_PROHOT
2
DGPU_CLKREQ# AK12 RV251 G QV11A
PEX_CLKREQ_N +3VS 2N7002KDW_SOT363-6
10K_0402_5%
RV7 1 DIS@ 2 10K_0402_5% H3 XTALIN @
CLK

S
+1.8VSDGPU_AON XTAL_IN

1
H2 XTALOUT RV9 RV106 RV108

1
XTAL_OUT 10K_0402_5% 10K_0402_5% 10K_0402_5%
1

3 PLTRST_VGA#_1V8 AJ12 J4 XTAL_OUTBUFF 1 2 DIS@ DIS@ DIS@ DIS@ 3

PEX_RST_N XTAL_OUTBUFF

5
1 2 PEX_TERMP AP29 H1 XTAL_SSIN 1 2 DIS@
RV10 PEX_TERMP XTAL_SSIN RV11 1.8VSDGPU_MAIN 1

VCC
2

2
10K_0402_5% IN B 4GPUCORE_EN
2.49K_0402_1% 2 OUT Y @
IN A

3
DIS@ 5

GND
PJT138KA 2N SOT363-6
D

1 2DV4
G

GP107-ES-A1_BGA908

6
1.8VSDGPU_MAIN_EN 2 QV7A UV10 RV254
S

2
D

QV7B DIS@ NL17SZ08DFT2G_SC70-5 RB751S-40 SOD-523

100K_0402_5%
G

3
PJT138KA 2N SOT363-6 @
S

+3VS DIS@ RV105 1 DIS@ 2

DGPU_PWR_EN 11,28,45

1
DV3 2
GC6_FB_EN3V3 2 +1.8VSDGPU_AON 20K_0402_5% CV197

1
1 1.5VSDGPU_PWR_EN 58 +1.8VSDGPU_AON DIS@
VGA_CORE_PG VGA_CORE_EN 55
3 DIS@ 0.1U_0402_25V6
1

RV113 1
2
10K_0402_5% BAV70W_SOT323-3 CV199
1

RV111 DIS@ RV12 DIS@ @ DIS@

1

10K_0402_5% 68K_0402_5% RV102 0.1U_0402_25V6 GPU_OVERT# 1 2DV7 1 2DV5

GC6_FB_EN3V3 1 1.0VS_DGPU_EN 28
DIS@ GC6_FB_EN3V3 11 DIS@ 10K_0402_5%
3 2

DIS@ RB751S-40 SOD-523 RB751S-40 SOD-523

5 DIS@
6 2

5
D

PJT138KA 2N SOT363-6 RV103 1 DIS@ 2

G
2

2
GC6_FB_EN1V8 2 QV8A PLTRST_VGA#_1V8 1 RV255
S

VCC
IN B

3
D

QV8B DIS@ 4 5 QV6A 28K_0402_1%

G

2 28K_0402_1%
4

GC6_FB_EN1V8# OUT Y
D

PJT138KA 2N SOT363-6 +1.8VS 2 CV196 DIS@

G

PJT138KA 2N SOT363-6
S

DIS@ IN A DIS@
S
GND
1

UV2 DIS@ RV104 0.1U_0402_25V6

1
NL17SZ08DFT2G_SC70-5 UV9 1 2 1
+3VS
5

DIS@ NL17SZ08DFT2G_SC70-5 10K_0402_5%

3
6

PCI_RST# 1 GC6_FB_EN1V8 2 QV6B DIS@

VCC

10,34,40,45 PCI_RST# IN B SYS_PEX_RST_MON#

D

4 2 RV99 @ 1 PJT138KA 2N SOT363-6

G

DGPU_HOLD_RST# 2 OUT Y DIS@

0_0402_5% DV6 2 1
S

11 DGPU_HOLD_RST# IN A VGA_CORE_PG 55
DIS@
GND

4 4
1
1

+1.8VSDGPU_AON RV15 RB751S-40 SOD-523

10K_0402_5%
2

+1.8VSDGPU_AON RV14 DIS@

3

0_0402_5%
1

UV3 RV100
2

@ NL17SZ08DFT2G_SC70-5 10K_0402_5%
5

@
Compal Electronics, Inc.
1

SYS_PEX_RST_MON#
Compal Secret Data
1
Security Classification
VCC

IN B 4 PLTRST_VGA#_1V8
2

GPU_PEX_RST_HOLD# OUT Y
2 2013/10/01 2014/05/24 Title

N17P PEG 1/7

IN A Issued Date Deciphered Date
RV16
GND

100K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 2 Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DIS@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 06, 2017 Sheet 21 of 61
A B C D E
 A B C D E

UV1B DIS@ UV1C DIS@

26 FBA_D[63..0] FBA_CMD[31..0] 26 27 FBB_D[63..0] FBB_CMD[31..0] 27
Part 2 of 7 Part 3 of 7
FBA_D0 L28 U30 FBA_CMD0 FBB_D0 G9 D13 FBB_CMD0
FBA_D1 M29 FBA_D0 FBA_CMD0 T31 FBA_CMD1 FBB_D1 E9 FBB_D0 FBB_CMD0 E14 FBB_CMD1
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_CMD2 FBB_D2 G8 FBB_D1 FBB_CMD1 F14 FBB_CMD2
FBA_D3 M28 FBA_D2 FBA_CMD2 R34 FBA_CMD3 FBB_D3 F9 FBB_D2 FBB_CMD2 A12 FBB_CMD3
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_CMD4 FBB_D4 F11 FBB_D3 FBB_CMD3 B12 FBB_CMD4
FBA_D5 P29 FBA_D4 FBA_CMD4 U32 FBA_CMD5 FBB_D5 G11 FBB_D4 FBB_CMD4 C14 FBB_CMD5
FBA_D6 FBA_D5 FBA_CMD5 FBA_CMD6 FBB_D6 FBB_D5 FBB_CMD5 FBB_CMD6
FBA_D7
FBA_D8
R29
P28
J28
FBA_D6
FBA_D7
Vinafix.com
FBA_CMD6
FBA_CMD7
U33
U28
V28
FBA_CMD7
FBA_CMD8
FBB_D7
FBB_D8
F12
G12
G6
FBB_D6
FBB_D7
FBB_CMD6
FBB_CMD7
B14
G15
F15
FBB_CMD7
FBB_CMD8
FBA_D9 H29 FBA_D8 FBA_CMD8 V29 FBA_CMD9 FBB_D9 F5 FBB_D8 FBB_CMD8 E15 FBB_CMD9
1 FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_CMD10 FBB_D10 E6 FBB_D9 FBB_CMD9 D15 FBB_CMD10 1
FBA_D11 H28 FBA_D10 FBA_CMD10 U34 FBA_CMD11 FBB_D11 F6 FBB_D10 FBB_CMD10 A14 FBB_CMD11
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_CMD12 FBB_D12 F4 FBB_D11 FBB_CMD11 D14 FBB_CMD12
FBA_D13 E31 FBA_D12 FBA_CMD12 V34 FBA_CMD13 FBB_D13 G4 FBB_D12 FBB_CMD12 A15 FBB_CMD13
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CMD14 FBB_D14 E2 FBB_D13 FBB_CMD13 B15 FBB_CMD14
FBA_D15 F30 FBA_D14 FBA_CMD14 Y32 FBA_CMD15 FBB_D15 F3 FBB_D14 FBB_CMD14 C17 FBB_CMD15
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CMD16 FBB_D16 C2 FBB_D15 FBB_CMD15 D18 FBB_CMD16
FBA_D17 D32 FBA_D16 FBA_CMD16 AA29 FBA_CMD17 FBB_D17 D4 FBB_D16 FBB_CMD16 E18 FBB_CMD17
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_CMD18 FBB_D18 D3 FBB_D17 FBB_CMD17 F18 FBB_CMD18
FBA_D19 C33 FBA_D18 FBA_CMD18 AC34 FBA_CMD19 FBB_D19 C1 FBB_D18 FBB_CMD18 A20 FBB_CMD19
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_CMD20 FBB_D20 B3 FBB_D19 FBB_CMD19 B20 FBB_CMD20
FBA_D21 F32 FBA_D20 FBA_CMD20 AA32 FBA_CMD21 FBB_D21 C4 FBB_D20 FBB_CMD20 C18 FBB_CMD21
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_CMD22 FBB_D22 B5 FBB_D21 FBB_CMD21 B18 FBB_CMD22
FBA_D23 H32 FBA_D22 FBA_CMD22 Y28 FBA_CMD23 FBB_D23 C5 FBB_D22 FBB_CMD22 G18 FBB_CMD23
FBA_D24 P34 FBA_D23 FBA_CMD23 Y29 FBA_CMD24 FBB_D24 A11 FBB_D23 FBB_CMD23 G17 FBB_CMD24
FBA_D25 P32 FBA_D24 FBA_CMD24 W31 FBA_CMD25 FBB_D25 C11 FBB_D24 FBB_CMD24 F17 FBB_CMD25
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_CMD26 FBB_D26 D11 FBB_D25 FBB_CMD25 D16 FBB_CMD26
FBA_D27 P33 FBA_D26 FBA_CMD26 AA34 FBA_CMD27 FBB_D27 B11 FBB_D26 FBB_CMD26 A18 FBB_CMD27
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_CMD28 FBB_D28 D8 FBB_D27 FBB_CMD27 D17 FBB_CMD28

MEMORY INTERFACE B
FBA_D29 L34 FBA_D28 FBA_CMD28 Y34 FBA_CMD29 FBB_D29 A8 FBB_D28 FBB_CMD28 A17 FBB_CMD29
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CMD30 FBB_D30 C8 FBB_D29 FBB_CMD29 B17 FBB_CMD30
FBA_D31 L33 FBA_D30 FBA_CMD30 V31 FBA_CMD31 FBB_D31 B8 FBB_D30 FBB_CMD30 E17 FBB_CMD31
FBA_D32 AG28 FBA_D31 FBA_CMD31 R28 FBB_D32 F24 FBB_D31 FBB_CMD31 G14
FBA_D33 AF29 FBA_D32 FBA_CMD32 AC28 FBB_D33 G23 FBB_D32 FBB_CMD32 G20
FBA_D34 AG29 FBA_D33 FBA_CMD33 R32 FBA_DEBUG0 @TV1 FBB_D34 E24 FBB_D33 FBB_CMD33 C12 FBB_DEBUG0 @TV2
FBA_D35 FBA_D34 FBA_CMD34 FBA_DEBUG1 FBB_D35 FBB_D34 FBB_CMD34 FBB_DEBUG1
MEMORY INTERFACE

AF28 AC32 @TV3 G24 C20 @TV4

FBA_D36 AD30 FBA_D35 FBA_CMD35 FBB_D36 D21 FBB_D35 FBB_CMD35
FBA_D37 AD29 FBA_D36 FBB_D37 E21 FBB_D36
FBA_D38 AC29 FBA_D37 FBB_D38 G21 FBB_D37
FBA_D39 AD28 FBA_D38 FBB_D39 F21 FBB_D38
FBA_D40 AJ29 FBA_D39 FBB_D40 G27 FBB_D39
FBA_D41 AK29 FBA_D40 FBB_D41 D27 FBB_D40
FBA_D42 AJ30 FBA_D41 FBB_D42 G26 FBB_D41
2 FBA_D43 AK28 FBA_D42 FBB_D43 E27 FBB_D42 2
FBA_D44 AM29 FBA_D43 FBB_D44 E29 FBB_D43
FBA_D45 AM31 FBA_D44 R30 FBB_D45 F29 FBB_D44 D12
FBA_D46 FBA_D45 FBA_CLK0 FBA_CLKA0 26 FBB_D46 FBB_D45 FBB_CLK0 FBB_CLKA0 27
AN29 R31 E30 E12
FBA_D47 FBA_D46 FBA_CLK0_N FBA_CLKA0# 26 FBB_D47 FBB_D46 FBB_CLK0_N FBB_CLKA0# 27
AM30 AB31 D30 E20
FBA_D48 FBA_D47 FBA_CLK1 FBA_CLKA1 26 FBB_D48 FBB_D47 FBB_CLK1 FBB_CLKA1 27
AN31 AC31 A32 F20
FBA_D49 FBA_D48 FBA_CLK1_N FBA_CLKA1# 26 FBB_D49 FBB_D48 FBB_CLK1_N FBB_CLKA1# 27
AN32 C31
FBA_D50 AP30 FBA_D49 FBB_D50 C32 FBB_D49
A

FBA_D51 AP32 FBA_D50 FBB_D51 B32 FBB_D50

FBA_D52 AM33 FBA_D51 K31 FBB_D52 D29 FBB_D51 F8
FBA_D53 FBA_D52 FBA_WCK01 FBA_WCK01 26 FBB_D53 FBB_D52 FBB_WCK01 FBB_WCK01 27
AL31 L30 A29 E8
FBA_D54 FBA_D53 FBA_WCK01_N FBA_WCK01# 26 FBB_D54 FBB_D53 FBB_WCK01_N FBB_WCK01# 27
AK33 H34 C29 A5
FBA_D55 FBA_D54 FBA_WCK23 FBA_WCK23 26 FBB_D55 FBB_D54 FBB_WCK23 FBB_WCK23 27
AK32 J34 B29 A6
FBA_D56 FBA_D55 FBA_WCK23_N FBA_WCK23# 26 FBB_D56 FBB_D55 FBB_WCK23_N FBB_WCK23# 27
AD34 AG30 B21 D24
FBA_D57 FBA_D56 FBA_WCK45 FBA_WCK45 26 FBB_D57 FBB_D56 FBB_WCK45 FBB_WCK45 27
AD32 AG31 C23 D25
FBA_D58 FBA_D57 FBA_WCK45_N FBA_WCK45# 26 FBB_D58 FBB_D57 FBB_WCK45_N FBB_WCK45# 27
AC30 AJ34 A21 B27
FBA_D59 FBA_D58 FBA_WCK67 FBA_WCK67 26 FBB_D59 FBB_D58 FBB_WCK67 FBB_WCK67 27
AD33 AK34 C21 C27
FBA_D60 FBA_D59 FBA_WCK67_N FBA_WCK67# 26 FBB_D60 FBB_D59 FBB_WCK67_N FBB_WCK67# 27
AF31 B24
FBA_D61 AG34 FBA_D60 FBB_D61 C24 FBB_D60
FBA_D62 AG32 FBA_D61 FBB_D62 B26 FBB_D61
FBA_D63 AG33 FBA_D62 J30 FBB_D63 C26 FBB_D62 D6
FBA_D63 FBA_WCKB01 J31 FBB_D63 FBB_WCKB01 D7
26 FBA_DBI[7..0] FBA_DBI0 FBA_WCKB01_N 27 FBB_DBI[7..0] FBB_DBI0 FBB_WCKB01_N
P30 J32 E11 C6
FBA_DBI1 F31 FBA_DQM0 FBA_WCKB23 J33 FBB_DBI1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DBI2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBB_DBI2 A3 FBB_DQM1 FBB_WCKB23_N F26
FBA_DBI3 M32 FBA_DQM2 FBA_WCKB45 AJ31 FBB_DBI3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DBI4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 FBB_DBI4 F23 FBB_DQM3 FBB_WCKB45_N A26
FBA_DBI5 AL29 FBA_DQM4 FBA_WCKB67 AJ33 FBB_DBI5 F27 FBB_DQM4 FBB_WCKB67 A27
FBA_DBI6 AM32 FBA_DQM5 FBA_WCKB67_N FBB_DBI6 C30 FBB_DQM5 FBB_WCKB67_N
FBA_DBI7 AF34 FBA_DQM6 FBB_DBI7 A24 FBB_DQM6
FBA_DQM7 +1.8VSDGPU_MAIN FBB_DQM7
26 FBA_EDC[7..0] FBA_EDC0 GPU_BUFRST# 27 FBB_EDC[7..0] FBB_EDC0
M31 E1 @TV9 D10
FBA_EDC1 G31 FBA_DQS_WP0 BUFRST_N FBB_EDC1 D5 FBB_DQS_WP0
3 FBA_EDC2 E33 FBA_DQS_WP1 FBB_EDC2 C3 FBB_DQS_WP1 3
FBA_EDC3 M33 FBA_DQS_WP2 DIS@ FBB_EDC3 B9 FBB_DQS_WP2
FBA_EDC4 AE31 FBA_DQS_WP3 K27 +FB_PLLAVDD 2 1 LV3 FBB_EDC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
FBA_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD CHILISIN PBY160808T-330Y-N FBB_EDC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD
FBA_EDC6 FBA_DQS_WP5 1 1 1 FBB_EDC6 FBB_DQS_WP5 1 1
AN33 B30
FBA_EDC7 FBA_DQS_WP6 FBB_EDC7 FBB_DQS_WP6
0.1U_0402_25V6

0.1U_0402_25V6

22U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6
AF33 CV9 CV10 CV11 A23 CV12 CV7
FBA_DQS_WP7 U27 DIS@ DIS@ DIS@ FBB_DQS_WP7 DIS@ DIS@
M30 FBA_PLL_AVDD 2 2 2 D9 2 2
H30 FBA_DQS_RN0 +GPU_PLLVDD E4 FBB_DQS_RN0
E34 FBA_DQS_RN1 B2 FBB_DQS_RN1
M34 FBA_DQS_RN2 H26 A9 FBB_DQS_RN2
AF30 FBA_DQS_RN3 GPCPLL_AVDD D22 FBB_DQS_RN3
AK31 FBA_DQS_RN4 D28 FBB_DQS_RN4
FBA_DQS_RN5 FBB_DQS_RN5
AM34
FBA_DQS_RN6
A30
FBB_DQS_RN6 Near H17
AF32 B23
FBA_DQS_RN7 FBB_DQS_RN7

GP107-ES-A1_BGA908 GP107-ES-A1_BGA908

+GPU_PLLVDD
+1.5VGS
+1.5VGS

FBA_CMD14 2 DIS@ 1
RV87 10K_0402_5% FBB_CMD14 2 DIS@ 1
FBA_CMD30
CV195

1 2 DIS@ 1 RV91 10K_0402_5%

RV88 10K_0402_5% FBB_CMD30 2 DIS@ 1
0.1U_0402_25V6

RV92 10K_0402_5%

2 FBA_CMD13
DIS@

2 DIS@ 1
RV89 10K_0402_5% FBB_CMD13 2 DIS@ 1
FBA_CMD29 2 DIS@ 1 RV93 10K_0402_5%
4 4
RV90 10K_0402_5% FBB_CMD29 2 DIS@ 1
RV94 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

2013/10/01 2014/05/24
N17P VRAM 2/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 22 of 61
A B C D E
 A B C D E

+1.8VSDGPU_AON

UV1D DIS@

Part 4 of 7 strap0 strap1 strap2 strap3 strap4 strap5

AL6 RV26 RV27 RV28 RV29 RV25 RV78 RV24 RV32 RV33
IFPA_L0

2
AK6 AC6 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
AN5 IFPA_L0_N NC AJ28 X76@ X76@ X76@ @ @ @ DIS@ DIS@ DIS@
AM5 IFPA_L1 NC AJ4
IFPA_L1_N NC
AP3
AN3 IFPA_L2 NC
AJ5
AL11
Vinafix.com

1
AM6 IFPA_L2_N NC C15
AN6 IFPA_L3 NC D19 STRAP0
1 IFPA_L3_N NC D20 STRAP1 ROM_SI 1
NC D23 STRAP2 ROM_SO

NC
AN8 NC D26 STRAP3 ROM_SCLK
AM8 IFPB_L0 NC V32 STRAP4
AM7 IFPB_L0_N NC STRAP5
AL7 IFPB_L1
AP6 IFPB_L1_N
IFPB_L2

2
AP5 RV34 RV35 RV36 RV37 RV38 RV79 RV39 RV40 RV41
IFPB_L2_N

2
AJ9 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
AH9 IFPB_L3 X76@ X76@ X76@ DIS@ DIS@ DIS@ @ @ DIS@
IFPB_L3_N
H31

1
AK1 FB_VREF

1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L4 VCCSENSE_VGA
AJ2 IFPC_L1 VDD_SENSE VCCSENSE_VGA 25,55
AH3 IFPC_L1_N
AH4 IFPC_L2 L5 VSSSENSE_VGA
IFPC_L2_N GND_SENSE VSSSENSE_VGA 25,55
AG5
AG4 IFPC_L3
IFPC_L3_N

AM1
TEST
AM2 IFPD_L0
AM3 IFPD_L0_N
AM4 IFPD_L1 AK11 TESTMODE RV42 1 DIS@ 2 10K_0402_5%
AL3 IFPD_L1_N NVJTAG_SEL
AL4 IFPD_L2 AM10 JTAG_TCK_VGA @ TV5
AK4 IFPD_L2_N JTAG_TCK AM11 JTAG_TDI @TV6
AK5 IFPD_L3 JTAG_TDI AP12 JTAG_TDO @TV7
IFPD_L3_N JTAG_TDO AP11 JTAG_TMS @ TV8
JTAG_TMS AN11 JTAG_RST RV43 1 DIS@ 210K_0402_5%
AD2 JTAG_TRST_N
2 AD3 IFPE_L0 2
IFPE_L0_N
LVDS/TMDS

AD1
AC1 IFPE_L1
AC2 IFPE_L1_N

SERIAL
AC3 IFPE_L2
AC4 IFPE_L2_N
AC5 IFPE_L3 H6
IFPE_L3_N ROM_CS_N H4 ROM_SCLK
ROM_SCLK H5 ROM_SI
AE3 ROM_SI H7 ROM_SO
AE4 IFPF_L0 ROM_SO
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N
AD5 IFPF_L2

GENERAL
AG1 IFPF_L2_N
AF1 IFPF_L3
IFPF_L3_N

AJ6 M1 VGA_OVERT#
IFPA_AUX_SCL OVERT VGA_OVERT# 21
AH6
IFPA_AUX_SDA_N
AK8
AL8 IFPB_AUX_SCL
IFPB_AUX_SCL_N
AG3 J2 STRAP0
AG2 IFPC_AUX_SCL STRAP0 J7 STRAP1
IFPC_AUX_SDA_N STRAP1 J6 STRAP2
AK3 STRAP2 J5 STRAP3
AK2 IFPD_AUX_SCL STRAP3 J3 STRAP4
IFPD_AUX_SDA_N STRAP4 J1 STRAP5
AB3 STRAP5
AB4 IFPE_AUX_SCL
3 IFPE_AUX_SDA_N K3 3
AF3 THERMDP K4
AF2 IFPF_AUX_SCL THERMDN
IFPF_AUX_SDA_N

GP107-ES-A1_BGA908

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2013/10/01 2014/05/24
N17P STRAP 3/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 23 of 61
A B C D E
 A B C D E

+1.0VS_DGPU

1 1 1 1 1 1 1 1 1
Vinafix.com CV134 CV13 CV14 CV33 CV29 CV16 CV28 CV204 CV34

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

4.7U_0402_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

22U_0402_6.3V6M
DIS@ DIS@ DIS@ DIS@ @ DIS@ DIS@ DIS@ DIS@
2 2 2 2 2 2 2 2 2
1 1

+1.5VGS UV1E DIS@

Part 5 of 7

AA27 AG19
AA30 FBVDDQ_0 PEX_DVDD AG21
AB27 FBVDDQ_1 PEX_DVDD AG22
1 1 1 1 1 1 1 1 FBVDDQ_2 PEX_DVDD
AB33 AG24
CV18 CV19 CV20 CV21 CV22 CV23 CV24 CV26 AC27 FBVDDQ_3 PEX_DVDD AH21
FBVDDQ_4 PEX_DVDD
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ AD27 AH25
2 2 2 2 2 2 2 2 AE27 FBVDDQ_5 PEX_DVDD
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
FBVDDQ_8 PEX_HVDD +1.8VSDGPU_MAIN
B13 AG15
B19 FBVDDQ_9 PEX_HVDD AG16
FBVDDQ_11 PEX_HVDD 1 1 1 1 1 1 1 1 1
E13 AG18 CV137 CV136 CV25 CV15 CV30 CV27 CV31
FBVDDQ_12 PEX_HVDD

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

22U_0603_6.3V6M
E19 AG25 CV17 CV32
FBVDDQ_14 PEX_HVDD

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0402_6.3V6M
H10 AH15 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
H11 FBVDDQ_15 PEX_HVDD AH18 2 2 2 2 2 2 2 2 2
H12 FBVDDQ_16 PEX_HVDD AH26
H13 FBVDDQ_17 PEX_HVDD AH27
H14 FBVDDQ_18 PEX_HVDD AJ27
1 1 1 1 1 1 1 1 FBVDDQ_19 PEX_HVDD
H18 AK27
CV126 CV127 CV128 CV129 CV130 CV131 CV132 CV133 H19 FBVDDQ_22 PEX_HVDD AL27
FBVDDQ_23 PEX_HVDD
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0402_6.3V6M
DIS@ DIS@ DIS@ DIS@ @ DIS@ DIS@ @ H20 AM28
2 2 2 2 2 2 2 2 H21 FBVDDQ_24 PEX_HVDD AN28

POWER
H22 FBVDDQ_25 PEX_HVDD
H23 FBVDDQ_26
H24 FBVDDQ_27
H8 FBVDDQ_28 AH12
FBVDDQ_29 PEX_PLL_HVDD +1.8VSDGPU_MAIN
H9 1
2 L27 FBVDDQ_30 CV43 2
M27 FBVDDQ_31
FBVDDQ_32

0.1U_0402_25V6
N27 AG12 DIS@
P27 FBVDDQ_33 NC AG26 2
R27 FBVDDQ_34 NC AG7
T27 FBVDDQ_35 NC AN2
T30 FBVDDQ_36 NC
T33 FBVDDQ_37
1 1 1 1 1 1 1 FBVDDQ_38
Y27
CV37 CV38 CV35 CV36 CV39 CV40 CV218 FBVDDQ_43
10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M

22U_0402_6.3V6M

DIS@ DIS@ DIS@ @ @ DIS@ @ J8

2 2 2 2 2 2 2 1V8_AON K8
1V8_AON L8
B16 VDD18 M8
E16 FBVDDQ VDD18
H15 FBVDDQ
H16 FBVDDQ
V27 FBVDDQ AH8
+1.5VGS W27 FBVDDQ IFPAB_PLLVDD AJ8
W30 FBVDDQ IFPAB_RSET
W33 FBVDDQ
FBVDDQ AF7
IFPCD_PLLVDD +1.8VSDGPU_AON
2

RV45 AF8
0_0402_5% IFPCD_RSET
1 1 1 1
AB8 CV135 CV49 CV51 CV50
IFPEF_PLLVDD

0.1U_0402_25V6

0.1U_0402_25V6

1U_0402_6.3V6K

4.7U_0402_6.3V6M
AD6 @ DIS@ DIS@ DIS@
IFPEF_RSET
1

FB_VDDQ_SENSE F1 2 2 2 2
58 FB_VDDQ_SENSE FB_VDDQ_SENSE

TP@ TV10 FB_GND_SENSE F2

PROBE_FB_GND
AG8
3 RV47 1 DIS@ 2 40.2_0402_1% FB_CAL_PD_VDDQ J27 IFP_IOVDD AG9 3
+1.5VGS FB_CAL_PD_VDDQ IFP_IOVDD AG6
IFP_IOVDD AF6
FB_CAL_PU_GND IFP_IOVDD +1.8VSDGPU_MAIN
RV48 1 DIS@ 2 40.2_0402_1% H27 AC7
FB_CAL_PU_GND IFP_IOVDD AC8
IFP_IOVDD 1 1 1 1
1 DIS@ 2 FB_CAL_TERM_GND H25 CV52 CV53 CV54 CV55
FB_CAL_TERM_GND

0.1U_0402_25V6

0.1U_0402_25V6

1U_0402_6.3V6K

4.7U_0402_6.3V6M
RV49 60.4_0402_1% DIS@ @ DIS@ DIS@
2 2 2 2

GP107-ES-A1_BGA908

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2013/10/01 2014/05/24
N17P POWER 4/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 24 of 61
A B C D E
 A B C D E

UV1F DIS@

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
UV1G DIS@ AA22 GND_3 GND_103 E22
GND_4 GND_104
+VGA_CORE

AA14
Vinafix.comPart 7 of 7 P23
+VGA_CORE AB12
AB14
AB16
GND_5
GND_6
GND_105
GND_106
E25
E5
E7
AA21 VDD_1 VDDS P19 AB19 GND_7 GND_107 F28
1
AB13 VDD_4 VDDS AA12 AB2 GND_8 GND_108 F7
1

AB15 VDD_6 VDDS AA16 AB21 GND_9 GND_109 G10

AB17 VDD_7 VDDS AA19 A33 GND_10 GND_110 G13
AB18 VDD_8 VDDS AA23 AB23 GND_11 GND_111 G16
AB20 VDD_9 VDDS AC14 AB28 GND_12 GND_112 G19
AB22 VDD_10 VDDS AC21 AB30 GND_13 GND_113 G2
AC12 VDD_11 VDDS M14 AB32 GND_14 GND_114 G22
AC16 VDD_12 VDDS M21 AB5 GND_15 GND_115 G25
AC19 VDD_14 VDDS P12 AB7 GND_16 GND_116 G28
AC23 VDD_15 VDDS P16 AC13 GND_17 GND_117 G3
M12 VDD_17 VDDS W21 AC15 GND_18 GND_118 G30
M16 VDD_18 VDDS W14 AC17 GND_19 GND_119 G32
M19 VDD_20 VDDS V18 AC18 GND_20 GND_120 G33
M23 VDD_21 VDDS U17 AA13 GND_21 GND_121 G5
N13 VDD_23 VDDS T21 AC20 GND_22 GND_122 G7
N15 VDD_24 VDDS T14 AC22 GND_23 GND_123 K2
N17 VDD_25 VDDS AE2 GND_24 GND_124 K28
N18 VDD_26 AE28 GND_25 GND_125 K30
N20 VDD_27 U1 VCCSENSE_VGA_S RV115 1 @DIS@ 2 0_0402_5% AE30 GND_26 GND_126 K32
N22 VDD_28 VDDS_SENSE U2 VSSSENSE_VGA_S RV116 1 @DIS@ 2 0_0402_5% VCCSENSE_VGA 23,55 AE32 GND_27 GND_127 K33
VDD_29 GNDS_SENSE VSSSENSE_VGA 23,55 GND_28 GND_128
P14 AE33 K5

POWER
P21 VDD_31 +VGA_CORE AE5 GND_29 GND_129 K7
R13 VDD_34 AE7 GND_30 GND_130 M13
R15 VDD_36 U4 AH10 GND_31 GND_131 M15
R17 VDD_37 XVDD U5 AA15 GND_32 GND_132 M17
R18 VDD_38 XVDD U6 AH13 GND_33 GND_133 M18
R20 VDD_39 XVDD U7 AH16 GND_34 GND_134 M20
R22 VDD_40 XVDD U8 AH19 GND_35 GND_135 M22
T12 VDD_41 XVDD V1 AH2 GND_36 GND_136 N12
T16 VDD_42 XVDD V2 AH22 GND_37 GND_137 N14
T19 VDD_44 XVDD V3 AH24 GND_38 GND_138 N16
T23 VDD_45 XVDD V4 AH28 GND_39 GND_139 N19
U13 VDD_47 XVDD V5 AH29 GND_40 GND_140 N2
2 U15 VDD_48 XVDD V6 AH30 GND_41 GND_141 N21 2
U18 VDD_49 XVDD V7 AH32 GND_42 GND_142 N23
U20 VDD_51 XVDD V8 AH33 GND_43 GND_143 N28
U22 VDD_52 XVDD W2 AH5 GND_44 GND_144 N30

GND
V13 VDD_53 XVDD W3 AH7 GND_45 GND_145 N32
V15 VDD_54 XVDD W4 AJ7 GND_46 GND_146 N33
V17 VDD_55 XVDD W5 AK10 GND_47 GND_147 N5
V20 VDD_56 XVDD W7 AK7 GND_48 GND_148 N7
V22 VDD_58 XVDD W8 AL12 GND_49 GND_149 P13
W12 VDD_59 XVDD AL14 GND_50 GND_150 P15
W16 VDD_60 AL15 GND_51 GND_151 P17
W19 VDD_62 Y1 AL17 GND_52 GND_152 P18
W23 VDD_63 XVDD Y2 AL18 GND_53 GND_153 P20
Y13 VDD_65 XVDD Y3 AL2 GND_54 GND_154 P22
Y15 VDD_66 XVDD Y4 AL20 GND_55 GND_155 R12
Y17 VDD_67 XVDD Y5 AL21 GND_56 GND_156 R14
Y18 VDD_68 XVDD Y6 AL23 GND_57 GND_157 R16
Y20 VDD_69 XVDD Y7 AL24 GND_58 GND_158 R19
Y22 VDD_70 XVDD Y8 AL26 GND_59 GND_159 R21
VDD_71 XVDD AL28 GND_60 GND_160 R23
AL30 GND_61 GND_161 T13
AA1 AL32 GND_62 GND_162 T15
XVDD AA2 AL33 GND_63 GND_163 T17
XVDD AA3 AL5 GND_64 GND_164 T18
XVDD AA4 AM13 GND_65 GND_165 T2
XVDD AA5 AM16 GND_66 GND_166 T20
XVDD AA6 AM19 GND_67 GND_167 T22
XVDD AA7 AM22 GND_68 GND_168 AG11
XVDD AA8 AM25 GND_69 GND_169 T28
XVDD AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
AN13 GND_72 GND_172 T7
GP107-ES-A1_BGA908 AN16 GND_73 GND_173 U12
3 AN19 GND_74 GND_174 U14 3
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
GND_OPT

GP107-ES-A1_BGA908

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2013/10/01 2014/05/24
N17P POWER & GND 5/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 25 of 61
A B C D E
 A B C D E

22 FBA_D[63:0]
UV4B @ 2 OF 2 UV5B @ 2 OF 2

K4 A4 FBA_D0 K4 A4 FBA_D56
22 FBA_CMD6 A8/A7 DQ0 FBA_D1 22 FBA_CMD26 A8/A7 DQ0 FBA_D57
H5 A2 H5 A2
22 FBA_CMD11 A9/A1 DQ1 FBA_D2 22 FBA_CMD23 A9/A1 DQ1 FBA_D58
H4 B4 H4 B4
22 FBA_CMD10 A10/A0 DQ2 FBA_D3 22 FBA_CMD22 A10/A0 DQ2 FBA_D59
22
22
FBA_CMD7
FBA_CMD9
K5
J5 A11/A6
A12/RFU#J5/NC#J5
Vinafix.com DQ3
DQ4
B2
E4
E2
FBA_D4
FBA_D5
22
22
FBA_CMD27
FBA_CMD25
K5
J5 A11/A6
A12/RFU#J5/NC#J5
DQ3
DQ4
B2
E4
E2
FBA_D60
FBA_D61
H11 DQ5 F4 FBA_D6 +1.5VGS H11 DQ5 F4 FBA_D62
1 22 FBA_CMD2 BA0/A2 DQ6 FBA_D7 22 FBA_CMD19 BA0/A2 DQ6 FBA_D63 1
K10 F2 K10 F2
22 FBA_CMD4 BA1/A5 DQ7 FBA_D8 22 FBA_CMD17 BA1/A5 DQ7 FBA_D48
K11 A11 K11 A11
22 FBA_CMD3 BA2/A4 DQ8 FBA_D9 22 FBA_CMD18 BA2/A4 DQ8 FBA_D49
H10 A13 H10 A13
22 FBA_CMD1 BA3/A3 DQ9 22 FBA_CMD20 BA3/A3 DQ9

1
B11 FBA_D10 RV50 B11 FBA_D50
J4 DQ10 B13 FBA_D11 549_0402_1% J4 DQ10 B13 FBA_D51
22 FBA_CMD8 ABI# DQ11 FBA_D12 22 FBA_CMD24 ABI# DQ11 FBA_D52
G3 E11 DIS@ G3 E11
22 FBA_CMD12 RAS# DQ12 FBA_D13 22 FBA_CMD31 RAS# DQ12 FBA_D53
G12 E13 RV51 G12 E13
22 FBA_CMD0 CS# DQ13 FBA_D14 22 FBA_CMD21 CS# DQ13 FBA_D54
L3 F11 931_0402_1% L3 F11
22 FBA_CMD15 22 FBA_CMD28

2
L12 CAS# DQ14 F13 FBA_D15 FBA_VREFC_R 1 2 FBA0_VREFC L12 CAS# DQ14 F13 FBA_D55
22 FBA_CMD5 WE# DQ15 FBA_D16 22 FBA_CMD16 WE# DQ15 FBA_D40
U11 U11
J12 DQ16 U13 FBA_D17 DIS@ J12 DQ16 U13 FBA_D41
22 FBA_CLKA0 CK DQ17 FBA_D18 22 FBA_CLKA1 CK DQ17 FBA_D42
J11 T11 1 J11 T11
22 FBA_CLKA0# CK# DQ18 22 FBA_CLKA1# CK# DQ18

1
J3 T13 FBA_D19 RV52 CV89 J3 T13 FBA_D43
22 FBA_CMD14 CKE# DQ19 FBA_D20 22 FBA_CMD30 CKE# DQ19 FBA_D44
N11 1.33K_0402_1% 820P_0402_50V7K N11
D2 DQ20 N13 FBA_D21 D DIS@ DIS@ D2 DQ20 N13 FBA_D45
22 FBA_DBI0 DBI0# DQ21 22 FBA_DBI7 DBI0# DQ21

1
D13 M11 FBA_D22 2 2 D13 M11 FBA_D46
22 FBA_DBI1 DBI1# DQ22 FBA_D23 21,27 VRAM_VREF_CTL 22 FBA_DBI6 DBI1# DQ22 FBA_D47
P13 M13 G QV3 P13 M13
22 FBA_DBI2 22 FBA_DBI5

2
P2 DBI2# DQ23 U4 FBA_D24 L2N7002SWT1G 1N SC-70-3 P2 DBI2# DQ23 U4 FBA_D32
S
22 FBA_DBI3 DBI3# DQ24 FBA_D25 22 FBA_DBI4 DBI3# DQ24 FBA_D33
U2 DIS@ U2

3
J2 DQ25 T4 FBA_D26 J2 DQ25 T4 FBA_D34
22 FBA_CMD13 RESET# DQ26 FBA_D27 22 FBA_CMD29 RESET# DQ26 FBA_D35
T2 T2
J10 DQ27 N4 FBA_D28 RV55 DIS@ J10 DQ27 N4 FBA_D36
FBA0_ZQ1 J13 SEN DQ28 N2 FBA_D29 1K_0402_5% FBA1_ZQ3 J13 SEN DQ28 N2 FBA_D37
J1 ZQ DQ29 M4 FBA_D30 1 2 J1 ZQ DQ29 M4 FBA_D38
MF DQ30 FBA_D31 +1.5VGS MF DQ30 FBA_D39
M2 M2
D4 DQ31 D4 DQ31
22 FBA_WCK01 WCK01 22 FBA_WCK67 WCK01
D5 C2 D5 C2
22 FBA_WCK01# WCK01# EDC0 FBA_EDC0 22 22 FBA_WCK67# WCK01# EDC0 FBA_EDC7 22
C13 C13
EDC1 FBA_EDC1 22 EDC1 FBA_EDC6 22
P4 R13 P4 R13
22 FBA_WCK23 WCK23 EDC2 FBA_EDC2 22 22 FBA_WCK45 WCK23 EDC2 FBA_EDC5 22
P5 R2 P5 R2
22 FBA_WCK23# WCK23# EDC3 FBA_EDC3 22 22 FBA_WCK45# WCK23# EDC3 FBA_EDC4 22

H5GC4H24AJR-R0C C38 H5GC4H24AJR-R0C C38

1

1
2 DIS@ DIS@ DIS@ 2
RV58 RV59 RV61
121_0402_1% 1K_0402_5% 121_0402_1%
2

2
+1.5VGS
UV4A @ 1 OF 2 +1.5VGS
UV5A @ 1 OF 2
C5 B5
C10 VDD VSS B10 C5 B5
D11 VDD VSS D10 C10 VDD VSS B10
G1 VDD VSS G5 D11 VDD VSS D10
VDD VSS FBA_CLKA0 FBA_CLKA0# +1.5VGS VDD VSS
G4 G10 G1 G5
G11 VDD VSS H1 G4 VDD VSS G10
G14 VDD VSS H14 G11 VDD VSS H1
+1.5VGS VDD VSS VDD VSS

1
L1 K1 RV63 RV95 G14 H14
L4 VDD VSS K14 40.2_0402_1% 40.2_0402_1% L1 VDD VSS K1
VDD VSS 1 1 1 1 1 1 1 VDD VSS
L11 L5 DIS@ DIS@ L4 K14
L14 VDD VSS L10 CV61 CV62 CV63 CV64 CV65 CV66 CV69 L11 VDD VSS L5
VDD VSS VDD VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 P11 P10 DIS@ DIS@ DIS@ DIS@ @ DIS@ DIS@ L14 L10

2
R5 VDD VSS T5 2 2 2 2 2 2 2 P11 VDD VSS P10
VDD VSS 1 VDD VSS
CV58 CV59 CV67 CV56 CV57 CV60 CV68 R10 T10 DIS@ R5 T5
VDD VSS VDD VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.01U_0402_16V7K
DIS@ DIS@ DIS@ @ DIS@ DIS@ DIS@ R10 T10
2 2 2 2 2 2 2 VDD VSS

CV190
B1 A1
B3 VDDQ VSSQ A3 2 B1 A1
B12 VDDQ VSSQ A12 B3 VDDQ VSSQ A3
B14 VDDQ VSSQ A14 B12 VDDQ VSSQ A12
D1 VDDQ VSSQ C1 B14 VDDQ VSSQ A14
D3 VDDQ VSSQ C3 D1 VDDQ VSSQ C1
D12 VDDQ VSSQ C4 D3 VDDQ VSSQ C3
D14 VDDQ VSSQ C11 D12 VDDQ VSSQ C4
VDDQ VSSQ 1 1 1 1 1 1 1 VDDQ VSSQ
E5 C12 D14 C11
3 E10 VDDQ VSSQ C14 CV77 CV78 CV79 CV80 CV81 CV82 CV83 E5 VDDQ VSSQ C12 3
VDDQ VSSQ VDDQ VSSQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 F1 E1 DIS@ @ DIS@ @ @ DIS@ @ E10 C14
F3 VDDQ VSSQ E3 2 2 2 2 2 2 2 F1 VDDQ VSSQ E1
CV141 CV142 CV140 CV73 CV74 CV75 CV76 F12 VDDQ VSSQ E12 F3 VDDQ VSSQ E3
VDDQ VSSQ FBA_CLKA1 FBA_CLKA1# VDDQ VSSQ
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

DIS@ @ DIS@ DIS@ @ DIS@ DIS@ F14 E14 F12 E12

2 2 2 2 2 2 2 G2 VDDQ VSSQ F5 F14 VDDQ VSSQ E14
G13 VDDQ VSSQ F10 G2 VDDQ VSSQ F5
VDDQ VSSQ VDDQ VSSQ
1

H3 H2 RV96 1 RV62 G13 F10

H12 VDDQ VSSQ H13 40.2_0402_1% 40.2_0402_1% H3 VDDQ VSSQ H2
K3 VDDQ VSSQ K2 DIS@ DIS@ H12 VDDQ VSSQ H13
K12 VDDQ VSSQ K13 K3 VDDQ VSSQ K2
L2 VDDQ VSSQ M5 K12 VDDQ VSSQ K13
2

L13 VDDQ VSSQ M10 L2 VDDQ VSSQ M5

VDDQ VSSQ 1 VDDQ VSSQ
M1 N1 DIS@ 1 1 1 1 1 1 1 L13 M10
VDDQ VSSQ VDDQ VSSQ
0.01U_0402_16V7K

M3 N3 M1 N1
VDDQ VSSQ VDDQ VSSQ
CV191

M12 N12 CV86 CV87 CV143 CV144 CV145 CV147 CV146 M3 N3

VDDQ VSSQ 2 VDDQ VSSQ

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 1 1 1 1 1 1 M14 N14 DIS@ @ DIS@ DIS@ DIS@ DIS@ DIS@ M12 N12
N5 VDDQ VSSQ R1 2 2 2 2 2 2 2 M14 VDDQ VSSQ N14
CV84 CV85 CV70 CV71 CV72 CV138 CV139 N10 VDDQ VSSQ R3 N5 VDDQ VSSQ R1
VDDQ VSSQ VDDQ VSSQ
10U_0603_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

@ @ DIS@ DIS@ DIS@ DIS@ @ P1 R4 N10 R3

2 2 2 2 2 2 2 P3 VDDQ VSSQ R11 P1 VDDQ VSSQ R4
P12 VDDQ VSSQ R12 P3 VDDQ VSSQ R11
P14 VDDQ VSSQ R14 P12 VDDQ VSSQ R12
T1 VDDQ VSSQ U1 P14 VDDQ VSSQ R14
T3 VDDQ VSSQ U3 T1 VDDQ VSSQ U1
T12 VDDQ VSSQ U12 T3 VDDQ VSSQ U3
T14 VDDQ VSSQ U14 T12 VDDQ VSSQ U12
VDDQ VSSQ T14 VDDQ VSSQ U14
FBA0_VREFC J14 A5 VDDQ VSSQ
VREFC VPP/NC#A5 U5 FBA0_VREFC J14 A5
VPP/NC#U5 1 1 1 1 1 1 1 1 VREFC VPP/NC#A5
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 A10 U5
VREFD VPP/NC#U5
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

U10 CV166 CV168 CV167 CV170 CV169 CV172 CV171 CV173 A10
CV161 CV160 CV158 CV162 CV163 CV164 CV159 CV165 VREFD DIS@ DIS@ @ DIS@ @ DIS@ DIS@ @ U10 VREFD
DIS@ DIS@ DIS@ DIS@ @ @ @ @ 2 2 2 2 2 2 2 2 VREFD
4 4
2 2 2 2 2 2 2 2 H5GC4H24AJR-R0C C38
H5GC4H24AJR-R0C C38

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/01/29 2017/01/10
N17P GDDR5 CHA 6/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 26 of 61
A B C D E
 A B C D E

UV7B @ 2 OF 2
22 FBB_D[63:0]
UV6B @ 2 OF 2 K4 A4 FBB_D56
22 FBB_CMD26 A8/A7 DQ0 FBB_D57
H5 A2
FBB_D0 22 FBB_CMD23 A9/A1 DQ1 FBB_D58
K4 A4 H4 B4
22 FBB_CMD6 A8/A7 DQ0 FBB_D1 22 FBB_CMD22 A10/A0 DQ2 FBB_D59
22
22
FBB_CMD11
FBB_CMD10
H5
H4
K5
A9/A1
A10/A0
Vinafix.com DQ1
DQ2
A2
B4
B2
FBB_D2
FBB_D3
22
22
FBB_CMD27
FBB_CMD25
K5
J5 A11/A6
A12/RFU#J5/NC#J5
DQ3
DQ4
B2
E4
E2
FBB_D60
FBB_D61
22 FBB_CMD7 A11/A6 DQ3 FBB_D4 DQ5 FBB_D62
J5 E4 H11 F4
1 22 FBB_CMD9 A12/RFU#J5/NC#J5 DQ4 FBB_D5 22 FBB_CMD19 BA0/A2 DQ6 FBB_D63 1
E2 K10 F2
DQ5 FBB_D6 22 FBB_CMD17 BA1/A5 DQ7 FBB_D48
H11 F4 K11 A11
22 FBB_CMD2 BA0/A2 DQ6 FBB_D7 22 FBB_CMD18 BA2/A4 DQ8 FBB_D49
K10 F2 +1.5VGS H10 A13
22 FBB_CMD4 BA1/A5 DQ7 FBB_D8 22 FBB_CMD20 BA3/A3 DQ9 FBB_D50
K11 A11 B11
22 FBB_CMD3 BA2/A4 DQ8 FBB_D9 DQ10 FBB_D51
H10 A13 J4 B13
22 FBB_CMD1 BA3/A3 DQ9 FBB_D10 22 FBB_CMD24 ABI# DQ11 FBB_D52
B11 G3 E11
DQ10 22 FBB_CMD31 RAS# DQ12

1
J4 B13 FBB_D11 RV64 G12 E13 FBB_D53
22 FBB_CMD8 ABI# DQ11 FBB_D12 22 FBB_CMD21 CS# DQ13 FBB_D54
G3 E11 549_0402_1% L3 F11
22 FBB_CMD12 RAS# DQ12 FBB_D13 22 FBB_CMD28 CAS# DQ14 FBB_D55
G12 E13 DIS@ L12 F13
22 FBB_CMD0 CS# DQ13 FBB_D14 22 FBB_CMD16 WE# DQ15 FBB_D40
L3 F11 RV65 U11
22 FBB_CMD15 CAS# DQ14 FBB_D15 DQ16 FBB_D41
L12 F13 931_0402_1% J12 U13
22 FBB_CMD5 22 FBB_CLKA1

2
WE# DQ15 U11 FBB_D16 FBB_VREFC_R 1 2 FBB0_VREFC J11 CK DQ17 T11 FBB_D42
DQ16 FBB_D17 22 FBB_CLKA1# CK# DQ18 FBB_D43
J12 U13 J3 T13
22 FBB_CLKA0 CK DQ17 FBB_D18 22 FBB_CMD30 CKE# DQ19 FBB_D44
J11 T11 DIS@ N11
22 FBB_CLKA0# CK# DQ18 FBB_D19 DQ20 FBB_D45
J3 T13 D2 N13
22 FBB_CMD14 CKE# DQ19 22 FBB_DBI7 DBI0# DQ21

1
N11 FBB_D20 RV66 D13 M11 FBB_D46
DQ20 FBB_D21
1 22 FBB_DBI6 DBI1# DQ22 FBB_D47
D2 N13 1.33K_0402_1% CV123 P13 M13
22 FBB_DBI0 DBI0# DQ21 FBB_D22 D 22 FBB_DBI5 DBI2# DQ23 FBB_D32
D13 M11 820P_0402_50V7K P2 U4
22 FBB_DBI1 DBI1# DQ22 22 FBB_DBI4 DBI3# DQ24

1
P13 M13 FBB_D23 2 QV4 DIS@ DIS@ U2 FBB_D33
22 FBB_DBI2 DBI2# DQ23 FBB_D24 21,26 VRAM_VREF_CTL 2 DQ25 FBB_D34
P2 U4 G DIS@ J2 T4
22 FBB_DBI3 22 FBB_CMD29

2
DBI3# DQ24 U2 FBB_D25 L2N7002SWT1G 1N SC-70-3 RESET# DQ26 T2 FBB_D35
S
J2 DQ25 T4 FBB_D26 RV69 J10 DQ27 N4 FBB_D36
22 FBB_CMD13

3
RESET# DQ26 T2 FBB_D27 1K_0402_5% FBB1_ZQ3 J13 SEN DQ28 N2 FBB_D37
J10 DQ27 N4 FBB_D28 1 2 J1 ZQ DQ29 M4 FBB_D38
FBB0_ZQ1 SEN DQ28 FBB_D29 +1.5VGS MF DQ30 FBB_D39
J13 N2 M2
J1 ZQ DQ29 M4 FBB_D30 D4 DQ31
22 FBB_WCK67 DIS@
MF DQ30 M2 FBB_D31 D5 WCK01 C2
DQ31 22 FBB_WCK67# WCK01# EDC0 FBB_EDC7 22
D4 C13
22 FBB_WCK01 WCK01 EDC1 FBB_EDC6 22
D5 C2 P4 R13
22 FBB_WCK01# WCK01# EDC0 FBB_EDC0 22 22 FBB_WCK45 WCK23 EDC2 FBB_EDC5 22
C13 P5 R2
EDC1 FBB_EDC1 22 22 FBB_WCK45# WCK23# EDC3 FBB_EDC4 22
P4 R13
22 FBB_WCK23 WCK23 EDC2 FBB_EDC2 22
P5 R2
22 FBB_WCK23# WCK23# EDC3 FBB_EDC3 22 H5GC4H24AJR-R0C C38

1
2 DIS@ 2
H5GC4H24AJR-R0C C38 RV72
1

DIS@ DIS@ 121_0402_1%

RV74 RV75
121_0402_1% 1K_0402_5%

2
+1.5VGS
2

UV7A @ 1 OF 2

+1.5VGS C5 B5
+1.5VGS VDD VSS
UV6A @ 1 OF 2 C10 B10
D11 VDD VSS D10
+1.5VGS VDD VSS
C5 B5 G1 G5
C10 VDD VSS B10 G4 VDD VSS G10
D11 VDD VSS D10 G11 VDD VSS H1
VDD VSS 1 1 1 1 1 1 1 VDD VSS
G1 G5 G14 H14
G4 VDD VSS G10 CV90 CV94 CV96 CV97 CV91 CV95 CV98 L1 VDD VSS K1
1 1 1 1 1 1 1 VDD VSS VDD VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
G11 H1 @ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ L4 K14
CV99 CV100 CV101 CV92 CV93 CV102 CV103 G14 VDD VSS H14 FBB_CLKA0 FBB_CLKA0# 2 2 2 2 2 2 2 L11 VDD VSS L5
VDD VSS VDD VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

DIS@ DIS@ @ @ @ DIS@ DIS@ L1 K1 L14 L10

2 2 2 2 2 2 2 L4 VDD VSS K14 P11 VDD VSS P10
VDD VSS VDD VSS

1
L11 L5 RV76 RV77 R5 T5
L14 VDD VSS L10 40.2_0402_1% 40.2_0402_1% R10 VDD VSS T10
P11 VDD VSS P10 DIS@ DIS@ VDD VSS
R5 VDD VSS T5 B1 A1
R10 VDD VSS T10 B3 VDDQ VSSQ A3

2
VDD VSS B12 VDDQ VSSQ A12
1 VDDQ VSSQ
B1 A1 B14 A14
VDDQ VSSQ VDDQ VSSQ

0.01U_0402_16V7K
B3 A3 1 1 1 1 1 1 1 D1 C1
VDDQ VSSQ VDDQ VSSQ

CV193
B12 A12 D3 C3
B14 VDDQ VSSQ A14 2 CV104 CV105 CV106 CV174 CV108 CV109 CV110 D12 VDDQ VSSQ C4
1 1 1 1 1 1 1 VDDQ VSSQ VDDQ VSSQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
D1 C1 @ @ DIS@ DIS@ DIS@ DIS@ DIS@ D14 C11
CV111 CV112 CV113 CV114 CV115 CV116 CV117 D3 VDDQ VSSQ C3 2 2 2 2 2 2 2 E5 VDDQ VSSQ C12
VDDQ VSSQ VDDQ VSSQ
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

3 DIS@ DIS@ DIS@ @ DIS@ DIS@ DIS@ D12 C4 E10 C14 3

2 2 2 2 2 2 2 D14 VDDQ VSSQ C11 F1 VDDQ VSSQ E1
E5 VDDQ VSSQ C12 F3 VDDQ VSSQ E3
VDDQ VSSQ DIS@ VDDQ VSSQ
E10 C14 F12 E12
F1 VDDQ VSSQ E1 F14 VDDQ VSSQ E14
F3 VDDQ VSSQ E3 FBB_CLKA1 FBB_CLKA1# G2 VDDQ VSSQ F5
F12 VDDQ VSSQ E12 G13 VDDQ VSSQ F10
F14 VDDQ VSSQ E14 H3 VDDQ VSSQ H2
VDDQ VSSQ VDDQ VSSQ
1

G2 F5 RV97 1 RV98 H12 H13

G13 VDDQ VSSQ F10 40.2_0402_1% 40.2_0402_1% K3 VDDQ VSSQ K2
H3 VDDQ VSSQ H2 DIS@ DIS@ K12 VDDQ VSSQ K13
VDDQ VSSQ 1 1 1 1 1 1 1 VDDQ VSSQ
H12 H13 L2 M5
K3 VDDQ VSSQ K2 CV118 CV119 CV153 CV155 CV154 CV156 CV157 L13 VDDQ VSSQ M10
1 1 1 1 1 1 1
2

VDDQ VSSQ VDDQ VSSQ

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
K12 K13 1 DIS@ DIS@ DIS@ @ @ @ @ M1 N1
CV120 CV121 CV148 CV149 CV150 CV152 CV151 L2 VDDQ VSSQ M5 2 2 2 2 2 2 2 M3 VDDQ VSSQ N3
VDDQ VSSQ VDDQ VSSQ
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

0.01U_0402_16V7K

DIS@ @ DIS@ DIS@ DIS@ @ @ L13 M10 M12 N12

2 2 2 2 2 2 2 VDDQ VSSQ VDDQ VSSQ
CV192

M1 N1 M14 N14
M3 VDDQ VSSQ N3 2 N5 VDDQ VSSQ R1
M12 VDDQ VSSQ N12 N10 VDDQ VSSQ R3
M14 VDDQ VSSQ N14 P1 VDDQ VSSQ R4
N5 VDDQ VSSQ R1 P3 VDDQ VSSQ R11
N10 VDDQ VSSQ R3 P12 VDDQ VSSQ R12
P1 VDDQ VSSQ R4 P14 VDDQ VSSQ R14
VDDQ VSSQ DIS@ VDDQ VSSQ
P3 R11 T1 U1
P12 VDDQ VSSQ R12 T3 VDDQ VSSQ U3
P14 VDDQ VSSQ R14 T12 VDDQ VSSQ U12
T1 VDDQ VSSQ U1 T14 VDDQ VSSQ U14
VDDQ VSSQ 1 1U_0402_6.3V6K 1 1 1 1 1 1 1 VDDQ VSSQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
T3 U3
T12 VDDQ VSSQ U12 CV182 CV184 CV183 CV185 CV186 CV188 CV187 CV189 FBB0_VREFC J14 A5
T14 VDDQ VSSQ U14 @ DIS@ @ @ @ @ @ @ VREFC VPP/NC#A5 U5
1 1 1 1 1 1 1 1 VDDQ VSSQ VPP/NC#U5
2 2 2 2 2 2 2 2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

A10
CV107 CV176 CV175 CV177 CV178 CV180 CV179 CV181 FBB0_VREFC J14 A5 U10 VREFD
DIS@ @ DIS@ DIS@ @ DIS@ DIS@ DIS@ VREFC VPP/NC#A5 U5 VREFD
2 2 2 2 2 2 2 2 A10 VPP/NC#U5
4 4
U10 VREFD H5GC4H24AJR-R0C C38
VREFD

H5GC4H24AJR-R0C C38

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/01/29 2017/01/10
N17P GDDR5 CHB 7/7
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 27 of 61
A B C D E
 5 4 3 2 1

+1.0VS_DGPU
@ +5VALW
PJP505 UV12 DIS@
+VL +1.8VALW +1.8VSDGPU_AON 1 2 1 6
+1.0VALW 1 2 IN OUT
UG1 DIS@ 2
DV10 1 14 JUMP_43X39 3 IN 7
DIS@ VIN1 VOUT1 1.0VS_DGPU_EN_R VBIASVCC_PAD
2 1 2 13 RV256 1 2 0_0402_5% 4 5
VIN1 VOUT1 21 1.0VS_DGPU_EN ON GND
CG1 220P_0402_50V8J 1 1
DGPU_PW R_EN_18ON

10U_0603_6.3V6M
RB751S-40 SOD-523 3 12 1 2 1 1 AOZ1334DI-02_DFN8-7_3X3 CV206
Vinafix.com ON1 CT1 CV205 CV207 1U_0402_6.3V6K

CG2 DIS@
DV8 DIS@ DGPU_PW R_EN_18ON 4 11 DIS@ 0.1U_0402_25V6 0.1U_0402_25V6 DIS@
DGPU_PW R_EN 2 1 VBIAS GND DIS@ DIS@ 2 2
11,21,45 DGPU_PW R_EN 1.8VSDGPU_MAIN_EN_R 2 2
RG1 1 @ 2 0_0402_5% 5 10 CG31 2 DIS@
21 1.8VSDGPU_MAIN_EN ON2 CT2 +1.8VSDGPU_MAIN
D RB751S-40 SOD-523 1200P_0402_50V8J D

1 1 6 9
1 2 RV257 7 VIN2 VOUT2 8

2
RV245 RV252 CG4 CG5 100K_0402_5% VIN2 VOUT2
2

10U_0603_6.3V6M
1K_0402_5% CV203 200K_0402_1% 0.1U_0402_25V6 0.1U_0402_25V6 DIS@ 15 1
@ DIS@ @ 2 2 DIS@ GPAD
DIS@

CG6 DIS@
0.1U_0402_25V6 EM5209VF_DFN14_2X3
1

1
2

+5VALW +1.0VS_DGPU
+1.8VSDGPU_MAIN

+5VALW

1
RV262 DIS@ RV263 DIS@

2
RV242 100K_0402_5% 10_0603_5%
1_0805_5%
DIS@

1
RV258

2
100K_0402_5%

1
DIS@ D

3
C 1.0VS_DGPU_EN#_R 5 DIS@
C

D G QV10B

3
1.8VSDGPU_MAIN_EN#_R 5 DIS@ 2N7002KDW_SOT363-6
G QV9B D S

6
2N7002KDW_SOT363-6 1.0VS_DGPU_EN_R 2 DIS@

4
S G QV10A
D 2N7002KDW_SOT363-6

4
6
1.8VSDGPU_MAIN_EN_R 2 DIS@ S
G QV9A

1
2N7002KDW_SOT363-6
S

1
B B

A A

Security Classification
2016/4/19
Compal Secret Data
2017/4/19
Compal Electronics, Inc.
DGPU_DC/DC Interface
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 06, 2017 Sheet 28 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS
Vinafix.com +LCDVDD_CONN
D D
U10 R311
5 1 +LCDVDD 1 2
IN OUT +3VS
2 0_0805_5% 1
GND

C128
1

4.7U_0402_6.3V6K
C456 4 3
1U_0402_6.3V6K EN OC
2 1
G5016KD1U SOT23
2 C130
10U_0402_6.3V6M
2
6 PCH_ENVDD

1
R120
100K_0402_5%

2
R121
1 2 +LEDVDD
B+
0_0805_5%

10U_0603_25V6M
1
C133
@

2
JEDP1
R211 1 @ 2 0_0402_5% 1
6,45 ENBKL 1
2
R123 1 2 0_0402_5% DISPOFF# 3 2
45 BKOFF# 3
C 4 C
5 4
6 INVPWM 5
DISPOFF# 6
6
2

2
R218 R124 EDP_HPD_R 7
W=60mils
100K_0402_5% @ 100K_0402_5% 8 7
+LCDVDD_CONN 8
9
C134 1 2 0.1U_0201_10V K X5R EDP_AUXN_C 10 9
6 EDP_AUXN EDP_AUXP_C 10
C135 1 2 0.1U_0201_10V K X5R 11
6 EDP_AUXP
1

1
C136 1 2 0.1U_0201_10V K X5R EDP_TXP0_C 12 11
6 EDP_TXP0 1 2 EDP_TXN0_C 13 12
C137 0.1U_0201_10V K X5R
6 EDP_TXN0 EDP_TXP1_C 13
C138 1 2 0.1U_0201_10V K X5R 14
6 EDP_TXP1 1 2 EDP_TXN1_C 15 14
C139 0.1U_0201_10V K X5R
6 EDP_TXN1 EDP_TXP2_C 15
C141 UHD@ 1 2 0.1U_0201_10V K X5R 16
6 EDP_TXP2 EDP_TXN2_C 16
C140 UHD@ 1 2 0.1U_0201_10V K X5R 17
6 EDP_TXN2 1 2 EDP_TXP3_C 18 17
C142 UHD@ 0.1U_0201_10V K X5R
6 EDP_TXP3 EDP_TXN3_C 18
C143 UHD@ 1 2 0.1U_0201_10V K X5R 19
6 EDP_TXN3
W=20mils 20 19
R126 1 2 0_0402_5% EDP_HPD_R 21 20
6 EDP_HPD 12 USB20_P5 21
22
12 USB20_N5 23 22
23
1

24
35,45 EC_SMB_DA4 25 24
R128
35,45 EC_SMB_CK4 25
100K_0402_5% +3VS 26
27 26
+3VALW 27
28
2

29 28
45 TAB_SW# 30 29
33 DMIC_CLK 30
31
33 DMIC_DAT 31
32
33 32
34 33
35 34
DMIC_CLK 6 TS_I2C_RST# 35
36 41
11 TS_INT# 36 G1
37 42
11 I2C1_SDA_TS 37 G2
38 43
11 I2C1_SCL_TS 38 G3
1 39 44

10P_0402_50V8J
45 TS_DISABLE# 40 39 G4 45

@EMI@
+3VS 40 G5
C455
B B
ACES_50398-04041-001
2 SP010013I00

2
D27 ME@
YSLC05CH_SOT23-3
ESD@

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/6/2
eDP / Camera
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 29 of 61
5 4 3 2 1
 5 4 3 2 1

+5VALW
+1.2V +1.2V_DTH_OUT +1.2V_DTH
UM2 HDMI20@
RM1
+3VS +DTH_VDD33 1 8 2 1
2 VIN VOUT 7 0_0603_5%
LM1 1 2 VIN VOUT
DTH_VDD12_ON HDMI20@
PBY160808T-300Y-N_2P 3 6
CM2 CM3 CM4 CM5 CM6 EN CT
1 HDMI20@ 1 1 1 1
4 5 1
VBIAS GND

1
HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ 9 HDMI20@ HDMI20@
Vinafix.com GND

1
RM7 CM7 CM1
2 2 2 2 2
0.47U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
10K_0402_5% APE8937GN2_DFN8_2X2 2200P_0402_50V7K 0.1U_0402_25V6
SA000070L00
2

2
D D

2
HDMI20@
HDMI_CEC_R RM6 1 2 HDMI_CEC
HDMI_CEC 32
0_0402_5%

UM1
+1.2V_DTH +DTH_VDD12

LM2 1 2 D6 G4
PBY160808T-300Y-N_2P
+DTH_VDD12 F5 VDD12 VDD33 G2 +DTH_VDD33
CM10 1 CM11 1 CM12 1 CM13 1 CM56 1 CM14 1 F4 VDD12 VDD33 B2
HDMI20@ +DTH_VDDA12 VDDA12 VDD33
HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ G7 G8 DTH_VDD12_ON
+DTH_VDDTX12 G5 VDDTX12 VDD12_ON
2 2 2 2 2 2 VDDTX12
0.47U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

0.01U_0402_16V7K

0.01U_0402_16V7K
B7
+DTH_VDDRX12 B5 VDDRX12 H8 HDMI1_TX2+
B4 VDDRX12 HDMID2P H7 HDMI1_TX2- HDMI1_TX2+ 32
VDDRX12 HDMID2N HDMI1_TX2- 32
HDMI20@ H6 HDMI1_TX1+
2 0_0402_5% CPU_DP2_P0_RR CPU_DP2_P0_C A8 HDMID1P H5 HDMI1_TX1- HDMI1_TX1+ 32
HDMI20@ RM60 1 CM15 1 2 0.1U_0201_10V K X5R
31,32 HDMI_LS_TX2+ 2 0_0402_5% CPU_DP2_N0_RR CPU_DP2_N0_C A7 DRX0P HDMID1N HDMI1_TX1- 32
HDMI20@ RM61 1 CM16 1 2 0.1U_0201_10V K X5R
31,32 HDMI_LS_TX2- DRX0N H4 HDMI1_TX0+
HDMI20@ HDMI20@
HDMID0P HDMI1_TX0+ 32
HDMI20@ RM62 1 2 0_0402_5% CPU_DP2_P1_RR CM17 1 2 0.1U_0201_10V K X5R CPU_DP2_P1_C A6 H3 HDMI1_TX0-
31,32 HDMI_LS_TX1+ DRX1P HDMID0N HDMI1_TX0- 32
HDMI20@ RM63 1 2 0_0402_5% CPU_DP2_N1_RR CM18 1 2 0.1U_0201_10V K X5R CPU_DP2_N1_C A5
31,32 HDMI_LS_TX1- DRX1N H2 HDMI1_CLK+
HDMI20@ HDMI20@
+1.2V_DTH +DTH_VDDA12 HDMI20@ RM64 1 2 0_0402_5% CPU_DP2_P2_RR CM19 1 2 0.1U_0201_10V K X5R CPU_DP2_P2_C A4 HDMICKP H1 HDMI1_CLK- HDMI1_CLK+ 32
31,32 HDMI_LS_TX0+ CPU_DP2_N2_RR CPU_DP2_N2_C A3 DRX2P HDMICKN HDMI1_CLK- 32
HDMI20@ RM65 1 2 0_0402_5% CM20 1 2 0.1U_0201_10V K X5R
31,32 HDMI_LS_TX0- DRX2N F2 HDMI_CEC_R
LM3 1 2 HDMI20@ HDMI20@
HDMI_CEC DDC_SCL_HDMI 31,32
PBY160808T-300Y-N_2P HDMI20@ RM66 1 2 0_0402_5% CPU_DP2_P3_RR CM21 1 2 0.1U_0201_10V K X5R CPU_DP3_P3_C A2
31,32 HDMI_LS_CLK+ DRX3P
C CM25 1 HDMI20@ CM26 1 CM27 1 CM28 1 HDMI20@ RM67 1 2 0_0402_5% CPU_DP2_N3_RR CM22 1 2 0.1U_0201_10V K X5R CPU_DP3_N3_C A1 E1 DDC_SCL_HDMI20_R RM76 1HDMI20@ 2 0_0201_5% C
31,32 HDMI_LS_CLK- DRX3N DDC_SCL F1 DDC_SDA_HDMI20_R RM77 1HDMI20@ 2 0_0201_5%
HDMI20@
HDMI20@ HDMI20@ HDMI20@ HDMI20@ DDI2_AUXP_M HDMI20@ CM23 1 2 0.1U_0201_10V K X5R DDI2_AUXP_C C7 DDC_SDA
DDI2_AUXN_M HDMI20@ CM24 1 2 0.1U_0201_10V K X5R DDI2_AUXN_C C8 AUXP G1 HDMI_HPD DDC_SDA_HDMI 31,32
2 2 2 2 AUXN HDMI_HPD HDMI_HPD 31,32
0.47U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_25V6

0.01U_0402_16V7K

DTH_SPI_CS C1 B1 CPU_DP2_HPD_R RM10 1HDMI20@ 2

DTH_SPI_D_IN C2 SPI_CS DP_HPD CPU_DP2_HPD 6,31,32
1K_0402_5%
DTH_SPI_D_OUT D1 SPI_D_IN
DTH_SPI_CK_OUT_R RM30 1 2 15_0402_5% DTH_SPI_CK_OUT D2 SPI_D_OUT C6 REXT_PS175 RM13 1 2 4.99K_0402_1%~D
HDMI20@ DTH_SPI_WR_PROT E2 SPI_CK_OUT REXT C3 DTH_PDB HDMI20@
SPI_WR_PROT PDB B8 DTH_RST#
RESETB C5
+3VS DTH_GPIO0 C4 TESTMODEB
D3 GPIO0 +3VS
DTH_GPIO2 E3 GIPIO1 F7 HDMI20@
+1.2V_DTH +DTH_VDDRX12 F3 GPIO2 NC DTH_PDB RM16 1 2
DTH_GPIO4 E7 CONFG1/GPIO3 G6 10K_0402_5%
CEC_EN/GPIO4 GND

1
LM4 1 2 HDMI20@ HDMI20@ D7 E5 HDMI_HPD RM17 1 2
PBY160808T-300Y-N_2P RM11 RM12 HDMI_ID D8 I2C_ADDR/GPIO5 GND B3 HDMI20@ 20K_0402_5%
CM31 1 HDMI_ID/GPIO6 GND G3
HDMI20@ CM32 1 CM33 1 CM34 1 CM35 1 CM36 1 CM37 1 CM38 1 4.7K_0402_5% 4.7K_0402_5%
DTH_CSCL GND
E6 E4
HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ DTH_CSDA F6 CSCL GND D5

2
DTH_CSDA CSDA GND D4
2 2 2 2 2 2 2 2 DTH_CSCL DTH_XTI GND +3VS
0.47U_0402_6.3V6K

10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

E8 B6
DTH_XTO F8 XTLI GND
XTLO

1
HDMI20@ HDMI20@
YM1 RM20
Crystal 10K_0402_5%
4 3 DTH_XTO
PS175HDMBGA64GTR2-B1_TFBGA64
SA000088320
GND OUT DTH_RST#

2
B DTH_XTI 1 2 B
IN GND HDMI20@
+1.2V_DTH +DTH_VDDTX12 HDMI20@

1
27MHZ_10PF_7V27000023 CM39
SJ10000G300
LM5 1 2 1U_0402_6.3V6K
PBY160808T-300Y-N_2P

2
CM41 1 HDMI20@
CM42 1 CM43 1 CM44 1 CM45 1 CM46 1 HDMI20@ HDMI20@
1

HDMI20@ CM29 CM30

HDMI20@ HDMI20@ HDMI20@ HDMI20@ HDMI20@ 12P_0402_50V8J 12P_0402_50V8J
2
0.47U_0402_6.3V6K

2 2 2 2 2 DDI2_AUX_DP DDI2_AUXP_M
10U_0603_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

0.01U_0402_16V7K

0.01U_0402_16V7K

HDMI20@ CM8 1 2 0.1U_0402_25V6

6 DDI2_AUX_DP DDI2_AUX_DN HDMI20@ CM9 1 2 0.1U_0402_25V6 DDI2_AUXN_M
6 DDI2_AUX_DN
+3VS +3VS HDMI20@ RM8 1 2 68_0402_5%
HDMI20@ RM9 1 2 68_0402_5%
1

RM18 RM19
@ @
10K_0402_5% 4.7K_0402_5%
DTH_GPIO0 DTH_GPIO2 HDMI_ID DTH_GPIO4
+3VS +3VS
2

2
1

RM24 RM25 RM21 RM29 DTH_SPI_CS HDMI20@ RM26 1 2

@ @ @ @ UM3 4.7K_0402_5%
4.7K_0402_5% 4.7K_0402_5% 10K_0402_5% 4.7K_0402_5% DTH_SPI_CS 1 8 DTH_SPI_HOLD# HDMI20@ RM23 1 2
DTH_SPI_D_IN CS# VCC DTH_SPI_HOLD# 1
2 7 HDMI20@ 4.7K_0402_5%
DTH_SPI_WR_PROT 3 DO HOLD# 6 DTH_SPI_CK_OUT_R CM40
2

4 WP# CLK 5 DTH_SPI_D_OUT 0.1U_0402_16V7K

GND DI 2
A W25X20CLSNIG_SO8 A
DTH_SPI_CK_OUT
SA00003GM30
HDMI20@ RM27 1 2
4.7K_0402_5%
HDMI20@ DTH_SPI_WR_PROT HDMI20@ RM28 1 2
4.7K_0402_5%

Title
HDMI2.0 PS175
Size Document Number R ev
LA-F661P 0.3

Date: Wednesday, October 18, 2017 Sheet 30 of 61

5 4 3 2 1
 5 4 3 2 1

+3VS +1.2V_HDMI

+1.2V +1.2V_HDMI
1

RLS1
LS@ 4.7K_0402_5%

0.01U_0201_6.3V7K
CLS1

0.01U_0201_6.3V7K
CLS2

0.1U_0201_10V6K
CLS3

0.1U_0201_10V6K
CLS4

0.1U_0201_10V6K
CLS5

0.1U_0201_10V6K
CLS6
2 2 2 2 2 2 RLS2
2 1
DDCBUF 0_0603_5%
Vinafix.com
2

1 1 1 1 1 1 LS@
+3VS
1

LS@

LS@

LS@

LS@

LS@

LS@
D RLS3 D
@ 4.7K_0402_5%

ULS1 LS@
19 11
2

20 VDDTA VDD33 37
31 VDDTX VDD33
12 VDDTX
VDDRX HDMI_LS_TX2+

0.01U_0201_6.3V7K
CLS8

0.1U_0201_10V6K
CLS9
40 30 HDMI_LS_TX2+ 30,32 2 2
VDDRX OUT_D2p 29 HDMI_LS_TX2-
OUT_D2n HDMI_LS_TX2- 30,32
+3VS CLS7 LS@ 1 2 0.1U_0201_10V6K HDMI_TX2+_C 1 27 HDMI_LS_TX1+
6 CPU_DP2_P0 HDMI_TX2-_C IN_D2p OUT_D1p HDMI_LS_TX1- HDMI_LS_TX1+ 30,32 1 1
CLS10 LS@ 1 2 0.1U_0201_10V6K 2 26 HDMI_LS_TX1- 30,32
6 CPU_DP2_N0 IN_D2n OUT_D1n

LS@

LS@
CLS11 LS@ 1 2 0.1U_0201_10V6K HDMI_TX1+_C 4 25 HDMI_LS_TX0+
6 CPU_DP2_P1 IN_D1p OUT_D0p HDMI_LS_TX0+ 30,32
1

RLS4 CLS12 LS@ 1 2 0.1U_0201_10V6K HDMI_TX1-_C 5 24 HDMI_LS_TX0-

6 CPU_DP2_N1 IN_D1n OUT_D0n HDMI_LS_TX0- 30,32
@ 4.7K_0402_5%
CLS13 LS@ 1 2 0.1U_0201_10V6K HDMI_TX0+_C 6 22 HDMI_LS_CLK+
6 CPU_DP2_P2 HDMI_TX0-_C IN_D0p OUT_CKp HDMI_LS_CLK- HDMI_LS_CLK+ 30,32
CLS14 LS@ 1 2 0.1U_0201_10V6K 7 21 HDMI_LS_CLK- 30,32
6 CPU_DP2_N2 IN_D0n OUT_CKn
EQ
2

CLS15 LS@ 1 2 0.1U_0201_10V6K HDMI_CLK+_C 9 39 HDMIDAT_NB

6 CPU_DP2_P3 HDMI_CLK-_C IN_CKp SDA_SRC HDMICLK_NB HDMIDAT_NB 6,32
CLS16 LS@ 1 2 0.1U_0201_10V6K 10 38 HDMICLK_NB 6,32
6 CPU_DP2_N3 IN_CKn SCL_SRC
1

RLS5 33 DDC_SDA_HDMI_R RLS15 1 LS@ 2 0_0201_5%

SDA_SNK DDC_SCL_HDMI_R DDC_SDA_HDMI 30,32
@ 4.7K_0402_5% 32 RLS16 1 LS@ 2 0_0201_5% DDC_SCL_HDMI 30,32
SCL_SNK
+3VS
DDCBUF 14
2

RLS6 1 LS@ 2 4.7K_0402_5% 13 DDCBUF/SDA_CTL 3 CPU_DP2_HPD

DCIN_EN/SCL_CTL HPD_SRC CPU_DP2_HPD 6,30,32
EQ 17 34 ISET
C I2C_CTL_EN_LS 8 EQ/I2C_ADDR0 ISET 28 HDMI_HPD C
I2C_CTL_EN HPD_SNK HDMI_HPD 30,32

RLS7 1 LS@ 2 4.99K_0402_1% 18

+3VS 36 REXT
RLS8 1 @ 2 4.7K_0402_5% 23 PD# 15
PRE 16 CFG / I2C_ADDR1 GND 35
PRE GND 41
EPAD
1

RLS9
@ 4.7K_0402_5% PS8407ATQFN40GTR2A1_TQFN40_5X5

I2C_CTL_EN_LS
2
1

RLS10
@ 4.7K_0402_5%
2

+3VS
B B
1

RLS11
@ 4.7K_0402_5%

PRE
2
1

RLS12
@ 4.7K_0402_5%

RPH1 HDMI14_20@ RPH2 HDMI14_20@

CPU_DP2_P0 4 5 HDMI_TX2+_R 4 5 HDMI_LS_TX2+
2

CPU_DP2_N0 3 6 HDMI_TX2-_R 3 6 HDMI_LS_TX2-

CPU_DP2_P1 2 7 HDMI_TX1+_R 2 7 HDMI_LS_TX1+
CPU_DP2_N1 1 8 HDMI_TX1-_R 1 8 HDMI_LS_TX1-

0_0804_8P4R_5% 0_0804_8P4R_5%

RPH3 HDMI14_20@ RPH4 HDMI14_20@

+3VS CPU_DP2_P2 4 5 HDMI_TX0+_R 4 5 HDMI_LS_TX0+
CPU_DP2_N2 3 6 HDMI_TX0-_R 3 6 HDMI_LS_TX0-
CPU_DP2_P3 2 7 HDMI_CLK+_R 2 7 HDMI_LS_CLK+
CPU_DP2_N3 1 8 HDMI_CLK-_R 1 8 HDMI_LS_CLK-
1

RLS13
@ 4.7K_0402_5% 0_0804_8P4R_5% 0_0804_8P4R_5%

A A
ISET
2
1

RLS14
@ 4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2016/06.23 2017/06/23 Title

HDMI Level shifter_PS8407A

Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 31 of 61

5 4 3 2 1
 5 4 3 2 1

+5V_Display

+5VS UM4 JHDMI1

HDMI20@ HDMI_HPD 19
HDMI1_CLK+ HDMI1_CLK+_R 30,31 HDMI_HPD HOT_Plug_Detect/HEAC-
RM68 1 2 0_0402_5% 3 18
30 HDMI1_CLK+ HDMI1_CLK- HDMI1_CLK-_R OUT +5V_Power
RM69 1 2 0_0402_5% 2 17
30 HDMI1_CLK- DDC_SDA_HDMI DDC/CEC_Ground/HEAC_Shield
HDMI20@ 1 16
HDMI20@ IN CM47 30,31 DDC_SDA_HDMI DDC_SCL_HDMI 15 SDA
HDMI1_TX2+ HDMI1_TX2+_R 30,31 DDC_SCL_HDMI SCL
RM70 1 2 0_0402_5% 2 14
30 HDMI1_TX2+
30 HDMI1_TX2-
Vinafix.com
HDMI1_TX2- RM71 1 2 0_0402_5% HDMI1_TX2-_R GND 1
0.1U_0201_10V K X5R
30 HDMI_CEC
HDMI_CEC
HDMI_CLK-_CONN
13 Utility/HEAC+
CEC
HDMI20@ 12 20
HDMI20@ AP2330W -7_SC59-3 11 TMDS_Clock- GND1 21
D D
SA00004ZA00
HDMI1_TX0+ RM72 1 2 0_0402_5% HDMI1_TX0+_R HDMI_CLK+_CONN 10 TMDS_Clock+_shield GND2 22
30 HDMI1_TX0+ HDMI1_TX0- HDMI1_TX0-_R HDMI_TX0-_CONN TMDS_Clock+ GND3
RM73 1 2 0_0402_5% 9 23
30 HDMI1_TX0- TMDS_Data0- GND4
HDMI20@ 8
HDMI20@ HDMI_TX0+_CONN 7 TMDS_Data0_shield
HDMI1_TX1+ RM74 1 2 0_0402_5% HDMI1_TX1+_R HDMI_TX1-_CONN 6 TMDS_Data0+
30 HDMI1_TX1+ HDMI1_TX1- HDMI1_TX1-_R +3VS TMDS_Data1-
RM75 1 2 0_0402_5% 5
30 HDMI1_TX1- HDMI_TX1+_CONN TMDS_Data1_shield
HDMI20@ 4
HDMI_TX2-_CONN 3 TMDS_Data1+
2 TMDS_Data2-
HDMI_TX2+_CONN 1 TMDS_Data2_shield
TMDS_Data2+

2
RM58
1M_0402_5% ACON_HMRB8-A3120C
HDMI14@ DC231709272

2
HDMI_CLK+_CONN 2 300_0402_1% HDMI_CLK-_CONN

G
RM39 1 EMI@ ME@
3 1 HDMI_HPD
6,30,31 CPU_DP2_HPD

1
HDMI_TX2+_CONN RM40 1 EMI@ 2 300_0402_1% HDMI_TX2-_CONN

2
HDMI_TX0+_CONN RM41 1 EMI@ 2 300_0402_1% HDMI_TX0-_CONN QM2 RM59
L2N7002SW T1G 1N SC-70-3 20K_0402_5%
HDMI_TX1+_CONN RM42 1 EMI@ 2 300_0402_1% HDMI_TX1-_CONN HDMI14@
HDMI14@

1
HDMI14@
C CM48 1 2 0.1U_0201_10V K X5R HDMI1_TX1+_R RM45 1 EMI@ 2 8.2_0402_1% HDMI_TX1+_CONN C
30,31 HDMI_LS_TX1+ HDMI1_TX1-_R
CM49 1 2 0.1U_0201_10V K X5R RM46 1 EMI@ 2 8.2_0402_1% HDMI_TX1-_CONN
30,31 HDMI_LS_TX1-
HDMI14@ HDMI14@
CM50 1 2 0.1U_0201_10V K X5R HDMI1_TX0+_R RM47 1 EMI@ 2 8.2_0402_1% HDMI_TX0+_CONN
30,31 HDMI_LS_TX0+ HDMI1_TX0-_R
CM51 1 2 0.1U_0201_10V K X5R RM48 1 EMI@ 2 8.2_0402_1% HDMI_TX0-_CONN
30,31 HDMI_LS_TX0-
HDMI14@ HDMI14@
CM52 1 2 0.1U_0201_10V K X5R HDMI1_TX2+_R RM49 1 EMI@ 2 8.2_0402_1% HDMI_TX2+_CONN
30,31 HDMI_LS_TX2+ HDMI1_TX2-_R
CM53 1 2 0.1U_0201_10V K X5R RM50 1 EMI@ 2 8.2_0402_1% HDMI_TX2-_CONN
30,31 HDMI_LS_TX2-
HDMI14@ HDMI14@
CM54 1 2 0.1U_0201_10V K X5R HDMI1_CLK+_R RM52 1 EMI@ 2 8.2_0402_1% HDMI_CLK+_CONN
30,31 HDMI_LS_CLK+ HDMI1_CLK-_R
CM55 1 2 0.1U_0201_10V K X5R RM54 1 EMI@ 2 8.2_0402_1% HDMI_CLK-_CONN
30,31 HDMI_LS_CLK-
HDMI14@
RPM1
5 4
6 3 +3VS +3VS +5V_Display
7 2
8 1

470 +-5% 8P4R HDMI14@

1
HDMI14@ RM55 RM56 HDMI14@ RM3 RM4
2.2K_0201_5% 2.2K_0201_5% QH1A 2.2K_0201_5% 2.2K_0201_5%
RPM2 HDMI14@ 2N7002KDW 2N SC88-6 HDMI14@

2
5 4
6 3 1 6 DDC_SCL_HDMI
6,31 HDMICLK_NB

2
7 2
8 1 +3VS

5
470 +-5% 8P4R D 4 3 DDC_SDA_HDMI
6,31 HDMIDAT_NB

1
HDMI14@ 2
B QM1 G QH1B B
L2N7002SW T1G 1N SC-70-3
S 2N7002KDW 2N SC88-6
HDMI14@ HDMI14@

DM4 @ESD@ 3 DM5 @ESD@ DM6 @ESD@

HDMI_HPD 9 1 HDMI_HPD HDMI_TX0+_CONN 9 1 HDMI_TX0+_CONN HDMI_TX1+_CONN 9 1 HDMI_TX1+_CONN

+5V_Display 8 2 +5V_Display HDMI_TX0-_CONN 8 2 HDMI_TX0-_CONN HDMI_TX1-_CONN 8 2 HDMI_TX1-_CONN

DDC_SDA_HDMI 7 4 DDC_SDA_HDMI HDMI_CLK+_CONN 7 4 HDMI_CLK+_CONN HDMI_TX2+_CONN 7 4 HDMI_TX2+_CONN

DDC_SCL_HDMI 6 5 DDC_SCL_HDMI HDMI_CLK-_CONN 6 5 HDMI_CLK-_CONN HDMI_TX2-_CONN 6 5 HDMI_TX2-_CONN

3 3 3

L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9

TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/01/06 2018/01/06 Title

HDMI
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 32 of 61
5 4 3 2 1
 A B C D E

+5VS

+5VS_PVDD RA1 1 2 0_0805_5%

+3VDD_CODEC +3VDD_CODEC
2 1 2 1

0.1U_0201_10V K X5R
0.1U_0201_10V K X5R
+1.8VS

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
CA3
CA1

CA2
CA32

2
1 2 1 2
2
RA38
CA17 100K_0402_1%
4.7U_0402_6.3V6M
@ 1 PLUG_IN_R RA13 1 2 200K_0402_1% PLUG_IN

1
UA1
Vinafix.com

29

34
39
1
33_0402_5% 2 1 RA12 HDA_SDIN0_AUDIO 7

PVDD1
PVDD2
CPVDD
DVDD
1 9 HDA_SDIN0 SDATA-IN HP_OUTL EXT_MIC_SLEEVE 1
4 25 EMI@ RA19 1 2 BLM15BD121SN1D_2P HGNDB
9 HDA_SDOUT_AUDIO SDATA-OUT HPOUT-L(PORT-I-L) HP_OUTR EXT_MIC_RING2
26 EMI@ RA20 1 2 BLM15BD121SN1D_2P HGNDA
HPOUT-R(PORT-I-R) HP_OUTL EMI@ RA22 1 2 47_0402_5% HPOUT_L
PC_BEEP 11 CA27 1 2 1U_0402_6.3V6K HP_OUTR EMI@ RA23 1 2 47_0402_5% HPOUT_R
PCBEEP AGND
22 SD028470A80
5 VREF 27 CPVEE 2 1 SD028470A80
9 HDA_BITCLK_AUDIO BCLK CPVEE
22P_0402_50V8J EMI@ CA12 33_0402_5% 2 EMI@ 1 RA10 CA20 1U_0402_6.3V6K
1 1

470P_0402_50V7K

470P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
2

2
RA6 1 2 2.2K_0402_5% EXT_MIC_RING2 13 17 LINE1-R LINE1-L CA21 2 1 1U_0402_6.3V6K
MIC2-L(PORT-F-L)/RING LINE1-R(PORT-C-R)

2
1 2 2.2K_0402_5% EXT_MIC_SLEEVE 14 18 LINE1-L @ @

RA26

RA27

EMI@ CA33

EMI@ CA34

EMI@ CA35

EMI@ CA36
10K_0402_5%

10K_0402_5%
RA7 CA19 2 1 2.2U_0402_6.3V6M 15 MIC2-R(PORT-F-R)/SLEEVE LINE1-L(PORT-C-L) 24 LINE1-R CA22 2 1 1U_0402_6.3V6K
MIC2-CAP LINE1-VREFO-L PLUG_IN_R +LINE1-VREFO-R 2 2
AGND

+MIC2-VREFO 23 12

1
MIC2-VREFO HP/ LINE1-JD(JD1) SM01000NY00

1
SPK_L2+ 35 2
SPK_L1- 36 SPK-OUT-LP GPIO0/DMIC-DATA12 3 DMIC_CLK_R 220_0402_5% 2 1 LA1 DMIC_DAT 29 RA29 1 2 4.7K_0402_5% AGND AGND AGND AGND AGND AGND
SPK_R1- 37 SPK-OUT-LN GPIO1/DMIC-CLK EMI@ DMIC_CLK 29
SPK_R2+ 38 SPK-OUT-RN 8 RA32 1 2 4.7K_0402_5%
SPK-OUT-RP DVDD-IO +IOVDD_CODEC +LINE1-VREFO-R
AGND AGND

2.2U_0402_6.3V6M 1 2 CA26 1
LDO1 21 28
2.2U_0402_6.3V6M 1 2 CA16 LDO2 32 LDO1-CAP CBN 30 CA15
LDO3 6 LDO2-CAP CBP
LDO3-CAP 1U_0402_6.3V6K
2.2U_0402_6.3V6M 1 2 CA13 2
40 1 2 EC_MUTE# 45
10 PDB 0_0402_5% RA11 2 1
9 DC DET 41

VD33STB
9 HDA_SYNC_AUDIO SYNC THERMAL PAD RA8 10K_0402_5%

AVDD1
AVDD2
AVSS1
AVSS2
@ DA2 DA1 JHP1
HGNDB 2 HPOUT_L 2 HGNDA 3
1 1 HPOUT_L 1
HGNDA 3 HPOUT_R 3

20
33
19
31

16
S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23 ESD S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23 ESD PLUG_IN 5
ESD@ @ESD@
6

2
HPOUT_R 2 2

AGND +3VALW HGNDB 4 7

+5VDDA_CODEC +1.8VS

RA5 1 2 YUQIU_PJ567-F07M1BE-G
0_0402_5% DC231709260
ME@
CA8 1 2 1U_0402_6.3V6K
AGND

JP11
6
5 GND2
GND1
SPK_R1- LA8 2 1 0_0603_5% SPK_R1-_CONN 4
SPK_R2+ LA7 2 1 0_0603_5% SPK_R2+_CONN 3 4
SPK_L1- LA6 2 1 0_0603_5% SPK_L1-_CONN 2 3
SPK_L2+ LA5 2 1 0_0603_5% SPK_L2+_CONN 1 2
1
+5VS +5VDDA_CODEC SP02000TS00
ACES_50271-0040N-001

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
RA4 2 1 0_0603_5% 1 1 1 1 ME@

EMI@ CA28

EMI@ CA29

EMI@ CA30

EMI@ CA31
1 1
0.1U_0201_10V K X5R

2 2 2 2
1U_0402_6.3V6K

CA7
CA11

2 2

3 3

AGND

SPK_R2+_CONN

SPK_L2+_CONN
SPK_R1-_CONN

SPK_L1-_CONN
3

2
L03ESDL5V0CC3-2_SOT23-3
DA4 @ESD@ SCA00002900

L03ESDL5V0CC3-2_SOT23-3
DA3 @ESD@ SCA00002900
1

1
+3VS +IOVDD_CODEC +3VS +3VDD_CODEC

RA40 1 2 47K_0402_5% BEEP_N CA37 2 1 1U_0402_6.3V6K PC_BEEP RA44 1 2 0_0402_5%

45 BEEP#
RA3 2 1 0_0603_5% RA2 2 1 0_0603_5% RA41 1 2 47K_0402_5%
9 HDA_SPKR
RA42 1 2 0_0402_5%
1 1
1U_0402_6.3V6K
0.1U_0201_10V K X5R

100P_0402_50V8J
CA40 @ESD@

1
0.1U_0201_10V K X5R

RA43 1 2 0_0402_5%
CA4

CA5

4 RA39 4
CA6

27K_0402_5%
2 2
2

2 RA45 1 2 0_0402_5%
2

GND AGND
AGND

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/07/27 Deciphered Date 2016/07/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC3240
Size Document Number Rev
LA-E552P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 33 of 61
A B C D E
 A B C D E F G H

+3VS_SSD

+3VS +3VS_SSD

0.01U_0402_16V7K

0.1U_0201_10V6K

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 +3VS_SSD
R17

C220

C221

C222

C223
1 2
2 2 2 @ 2
0_0805_5% R134 1 @ 2 0_0402_5%
NGFF_SSD_PEDET 12
Vinafix.com SSD_DET@

2
R133
1 10K_0402_5% 1
JSSD1
1 2
3 GND 3P3VAUX 4

1
5 GND 3P3VAUX 6
12 PCIE_PRX_DTX_N9 PERn3 NC D
7 8
12 PCIE_PRX_DTX_P9 PERp3 NC

1
9 10 NGFF_SSD_PEDET# 2 Q32
CC118 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N9 11 GND DAS/DSS# 12
12 PCIE_PTX_DRX_N9 PETn3 3P3VAUX
G L2N7002SWT1G 1N SC-70-3
CC119 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P9 13 14 S SSD_DET@
12 PCIE_PTX_DRX_P9 15 PETp3 3P3VAUX 16

3
17 GND 3P3VAUX 18
12 PCIE_PRX_DTX_N10 PERn2 3P3VAUX
19 20
12 PCIE_PRX_DTX_P10 21 PERp2 NC 22
CC120 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N10 23 GND NC 24
12 PCIE_PTX_DRX_N10 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P10 25 PETn2 NC 26
CC121
12 PCIE_PTX_DRX_P10 PETp2 NC
27 28
29 GND NC 30
12 PCIE_PRX_DTX_N11 PERn1 NC
31 32
12 PCIE_PRX_DTX_P11 PERp1 NC
33 34
CC102 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N11 35 GND NC 36
12 PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 NC
CC103 1 2 0.22U_0201_6.3V6M 37 38
12 PCIE_PTX_DRX_P11 PETp1 DEVSLP DEVSLP2 12
39 40
41 GND NC 42
12 SATA_PRX_DTX_P12 PERn0/SATA-B+ NC
43 44
12 SATA_PRX_DTX_N12 45 PERp0/SATA-B- NC 46
CC125 1 2 0.22U_0201_6.3V6M SATA_PTX_C_DRX_N12 47 GND NC 48
12 SATA_PTX_DRX_N12 SATA_PTX_C_DRX_P12 PETn0/SATA-A- NC PCI_RST#
CC158 1 2 0.22U_0201_6.3V6M 49 50
12 SATA_PTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52
GND CLKREQ# SSDCLK_REQ# 10
53 54
10 CLK_PCIE_SSD# 55 REFCLKN PEWake# 56
10 CLK_PCIE_SSD REFCLKP NC
57 58
GND NC

67 68
NGFF_SSD_PEDET# 69 NC SUSCLK(32kHz) 70
71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 72
73 GND 3P3VAUX 74
2 2
75 GND 3P3VAUX
GND 76
GND1 77
GND2
LOTES_APCI0079-P005A
SP07001EZ00
ME@

+3VS +3VS_WLAN

RWL153 1 2 0_0603_5%

+3VS_WLAN

JWLAN1
1 2 1
3 GND 3.3VAUX 4 @
12 USB20_P7 USB_D+ 3.3VAUX
5 6 CWL157 1 1
12 USB20_N7 7 USB_D- LED1# 8 4.7U_0402_6.3V6K CWL155 CWL156
9 GND PCM_CLK 10 2
11 SIDO_CLK PCM_SYNC 12 4.7U_0402_6.3V6K 0.1U_0201_10V K X5R
13 SDIO_CMD PCM_IN 14 2 2
3
15 SDO_DAT0 PCM_OUT 16 3
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
21 SDO_DAT3 UART_WAKE# 22 WL_UART_RX R135 1 @ 2 0_0402_5%
SDIO_WAKE# UART_RX UART0_RX 11
23
SDIO_RESET#

32 WL_UART_TX R136 1 @ 2 0_0402_5%

UART_TX UART0_TX 11
33 34
35 GND UART_CTS 36
12 PCIE_PTX_C_DRX_P4 37 PETP0 UART_RTS 38
12 PCIE_PTX_C_DRX_N4 PETN0 RESERVED EC_TX 45
39 40
41 GND RESERVED 42 EC_RX 45
12 PCIE_PRX_DTX_P4 PERP0 RESERVED
43 44
12 PCIE_PRX_DTX_N4 PERN0 COEX3
45 46
47 GND COEX2 48
10 CLK_PCIE_WLAN REFCLKP0 COEX1
49 50
10 CLK_PCIE_WLAN# 51 REFCLKN0 SUSCLK 52 SUSCLK 10
WLANCLK_REQ#_R GND PERST0# PCI_RST# 10,21,40,45
10 WLANCLK_REQ# RWL158 1 2 0_0402_5% 53 54
WAKE#_R CLKEQ0# W_DISABLE2# WLBT_OFF# 11
39,45 EC_PCIE_WAKE# RWL162 1 @ 2 0_0402_5% 55 56
57 PEWAKE0# W_DISABLE1# 58 WL_OFF# 12
59 GND I2C_DATA 60
61 RSRVD/PETP1 I2C_CLK 62
63 RSRVD/PETN1 ALERT 64
65 GND RESERVED 66
67 RSRVD/PERP1 RESERVED 68
69 RSRVD/PERN1 RESERVED 70
71 GND RESERVED 72
RESERVED 3.3VAUX
2

73 74 RWL507
75 RESERVED 3.3VAUX 100K_0402_5%
GND

77 76
1

MTG77 MTG76

LOTES_APCI0128-P005A
4 SP070011H00 4
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/6/2
NGFF SSD/WLAN
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 34 of 61
A B C D E F G H
 5 4 3 2 1

+3VS

2
R390
0_0402_5%

UTS1 EX_THM@

1
+3V_Thermal 1 8 EC_SMB_CK2
1 VDD SCL EC_SMB_CK2 8,21,45
EX_THM@
CTS1 REMOTE1+ 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 8,21,45
2200P_0402_50V7K
2

RTS340 1 2 4.7K_0402_5%
REMOTE1- 3

4
Vinafix.com
D- ALERT#
6

5
GPU_PROHOT 21,45,47
+3VS

UGS2
+3VS_GS_R
+3V_Thermal T_CRIT# GND
EX_THM@ RGS2 1 2 0_0402_5% +3VS_GS_R 7 3
D
10 VDD VDDIO 11 D
CSB PS

0.1U_0201_10V K X5R
NCT7718W_MSOP8
2 5 4
6 INT1 NC
INT2 1
SDO

CGS3
2 9
1 29,45 EC_SMB_DA4 12 SDx GND 8
29,45 EC_SMB_CK4 SCx GNDIO
BMA250E_LGA12
SA00005BP10

REMOTE1+
1
C
1

EX_THM@ CTS2 2 QTS1 EX_THM@

100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 E
REMOTE1-
3

+3VALW

LID_SW#
+EC_VCCA +EC_VCCA +EC_VCCA LID_SW# 45
C C

3
1

1
RTS336 RTS334 RTS341
16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1% 1 2

VCC

VOUT
CHS1 CHS2
0.1U_0201_10V6K 10P_0402_50V8J

GND
2

2
2 1
UHS1
45 CUST_TEMP1 45 CUST_TEMP2 45 CUST_TEMP3
TCS40DPR_SOT23F3

1
SA00009G000
1

1
RTS338 RTS335 RTS339
100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K 100K +-1% 0402 B25/50 4250K
2

ECAGND ECAGND ECAGND

JFAN1 H1 H3 H6 H2 H4 H8 H23
B +5VS 6 FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA CLIP4 CLIP5 CLIP6 CLIP8
B
5 GND2 HOLEA HOLEA HOLEA HOLEA
GND1
RF168 2 1 0_0603_5% +5VS_FAN1 4
3 4 @ @ @ @
45 EC_FAN_SPEED1
1

1
2 3

1
1 2
45 EC_FAN_PWM1 1
2 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P5
ACES_50271-0040N-001
CF162 SP02000TS00
10U_0603_6.3V6M ME@
1
CLIP1 CLIP2 CLIP3 CLIP7 CLIP11 CLIP12 CLIP13 CLIP14 CLIP15 CLIP16 CLIP20
H20 H19 H5 H7 H9 H18 H10 H11 H12 H17 H14 H15 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @ @ @ @ @ @ @

1
1

1
JFAN2 H_3P2 H_3P2 H_3P3 H_3P3 H_3P3 H_6P0 H_2P5 H_2P5 H_2P5 H_2P5 H_2P5 H_2P5
+5VS 6
5 GND2
GND1
RF169 2 1 0_0603_5% +5VS_FAN2 4 H13 H21 H22 H24
3 4 HOLEA HOLEA HOLEA HOLEA
45 EC_FAN_SPEED2 3
2
1 2 CLIP9 CLIP10 CLIP19 CLIP21 CLIP22 CLIP23
45 EC_FAN_PWM2 1
2 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
ACES_50271-0040N-001
1

CF163 SP02000TS00
10U_0603_6.3V6M ME@ @ @ @ @ @ @
1 H_2P5 H_3P3X2P8 H_7P0X6P0 H_2P8X2P3
1

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 Deciphered Date 2017/6/2 Title
FAN / Thermal Senser
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 35 of 61
5 4 3 2 1
 JFP1 +5VS
1
2 1 KSI[0..7] JKB1
3 2 KSI[0..7] 45
4 3 KSO[0..15] R263 2 1 866_0402_5% CAPS_LED#_R 32
5 4 KSO[0..15] 45 31 32
5 45 CAPS_LED# 31
6 9 KSO15 30
12 USB20_P6 6 G1 30
7 10 KSO10 29
12 USB20_N6 1 2 8 7 G2 28 29 34
+3VS RFP2 KSO11
Vinafix.com 8 28 GND

C229
0_0402_5% 1 KSO14 27 33
RFP1 1 @ 2 SP01001AE00 KSO13 26 27 GND
+3VALW 26
0_0402_5% ACES_51522-00801-001 ESD@ KSO12 25
KSO3 24 25
ME@ 24
2

0.1U_0201_10V K X5R
KSO6 23
KSO8 22 23
KSO7 21 22
CFP1 KSO4 20 21
0.1U_0201_10V K X5R KSO2 19 20
KSI0 18 19
18

2
KSO1 17
ESD@ KSO5 16 17
DFP6 KSI3 15 16
PSOT24C_SOT23-3 KSI2 14 15
KSO0 13 14
KSI5 12 13

1
KSI4 11 12
KSO9 10 11
KSI6 9 10
KSI7 8 9
KSI1 7 8
6 7
5 6
4 5
3 4
2 3
45 KB_MUTLI_KEY 1 2
1
JXT_FP257H-032S10M
+3VS +3VS
SP01002FA00
RTP2
1 2 ME@

0_0402_5% @
CTP1
0.1U_0201_10V K X5R +3VL
1

RTP1
4.7K_0402_5%

JTP1

2
R170
2

+TP_VCC 1 SW2
1 100K_0402_5%
2
11 I2C0_SCL_TP 2
3 TBF312KQR_5P
11 I2C0_SDA_TP 4 3
11 TP_INT#

1
1 2 TP_DISABLE#_R 5 4 ON/OFF# 1 3
45 TP_DISABLE# 6 5 45 ON/OFF# 2 4
RTP3 7 6
0_0402_5% 8 G1
G2

5
3

2
SP01002DQ00
1 1 JXT_FP201CH-006G10M D24
100P_0402_50V8J

100P_0402_50V8J

ME@ ESD@
3

2
CTP2

CTP3

@ @ESD@ L03ESDL5V0CC3-2_SOT23-3
2 2
@

DTP1

1
PSOT24C_SOT23-3
1

+3VL

2
R172
100K_0402_5%
SW1

1
NOVO# 1 2
45 NOVO#

3 4

2
+5VS +5VS_KBL
D23 TCHC2QR_2P
+5VALW ESD@ SN10000BW00
KBL@
QKBL1 JKBL1 L03ESDL5V0CC3-2_SOT23-3
4 6

1
4 GND
1

KBL@ 3 1 3 5
3 GND
S

RKBL2 2
10K_0402_5% ME2301DC-G_SOT23-3 1 2
1
CKBL2

CKBL3

1 2
10U_0603_6.3V6M

0.1U_0201_10V K X5R

RKBL1 JXT_FP202DH-004M10M
G
2

45 KB_BL_PWM 1 2 SP010022U00
ME@
30K_0402_1% 2 1
1
@

KBL@

KBL@ KBL@
CKBL1
0.01U_0402_16V7K
2

LED1

White
LED2 RS175
BATT_CHG_LED# 1 2 2
45 BATT_CHG_LED#
White 412_0402_1%
RS178 RS176 1 RS177 1 2 0_0402_5% +VL
PWR_LED# 1 2 2 BATT_LOW_LED# 1 2 3
45 PWR_LED# 45 BATT_LOW_LED#
806_0402_1% 523_0402_1%
RS179 1 RS180 1 2 0_0402_5%
PWR_BATT_LOW# +VL
1 2 3 Amber
45 PWR_BATT_LOW#
523_0402_1% SC50000FV10
HT-210UD5-BP5_AMBER-WHITE
Amber
SC50000FV10
HT-210UD5-BP5_AMBER-WHITE
LED3

White
RS181
PWR_LED#

Compal Electronics, Inc.

1 2 2
Compal Secret Data
806_0402_1%
RS182 1 RS183 1 2 0_0402_5% Security Classification

KBL/KBD/LED/TP/HS Conn.
PWR_BATT_LOW# +VL
1 2 3
Issued Date 2017/5/3 Deciphered Date 2017/6/2 Title
523_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amber Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SC50000FV10 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
HT-210UD5-BP5_AMBER-WHITE MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 06, 2017 Sheet 36 of 61
 5 4 3 2 1

ESD@ D7
U3RXDN2 9 10 1 1 U3RXDN2 ESD@ D8
U2DP2 3 6
I/O2 I/O4
U3RXDP2 8 9 2 2 U3RXDP2
+3VL +5VALW_USBCH +5V_CHGUSB U3TXDN2 7 7 4 4 U3TXDN2
2 5 +5V_CHGUSB
GND VDD
U3TXDP2 6 6 5 5 U3TXDP2

3 3

8
7
6
5
1 4 U2DN2
RPBC1 8 I/O1 I/O3
10K_0804_8P4R_5%
Vinafix.com
U12 L05ESDL5V0NA-4 SLP2510P8 ESD
L30ESDL5V0C6-4 SOT23

1
2
3
4
D 1 12 D
USB_CHG_STATUS# 9 IN OUT 10 USB20_CH_P2
45 USB_CHG_STATUS# STATUS# DP_IN 11 USB20_CH_N2
13
4 FAULT# DM_IN 2 USB20_N2
45 USB_CHG_ILIM_SEL USB_CHG_EN ILIM_SELDM_OUT 3 USB20_P2 USB20_N2 12
45 USB_CHG_EN 5
USB_CHG_CTL1 EN DP_OUT 15 USB20_P2 12
45 USB_CHG_CTL1 6 R183 1 2 2.7M_0402_1%
USB_CHG_CTL2 7 CTL1 ILIM_LO 16 R197 1 2 24.9K_0402_1%
45 USB_CHG_CTL2 USB_CHG_CTL3 CTL2 ILIM_HI 14
45 USB_CHG_CTL3 8
CTL3 GND 17
T-PAD
1

150U_B2_6.3VM_R35M
TPS2546RTER QFN 16P PWR SW

22U_0603_6.3V6M

22U_0603_6.3V6M
1 SA000064O00 + L12 EMI@
USB20_CH_N2

C195
1 2 U2DN2
1 2

1
C194
2

C457

C458
0.1U_0201_10V K X5R
2 USB20_CH_P2 4 3 U2DP2

2
@ 4 3
DLM0NSN900HY2D_4P

+5VALW_USBCH +5VALW
+5VALW
+VL

150U_B2_6.3VM_R35M
+5VALW +
CMF-2012-2G45-32T_6P +5V_CHGUSB

C461
L59
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 R215 2 2 1 3 1

5
2

D
1 0_0603_5% BLM15PX331SN1D_2P Q28 1 GND
1

C454 L60 C453 JUSB1

@

ME2301DC-G_SOT23-3
C224

C225

C226

C227

C239

C238

C228

4.7U_0402_6.3V6K 2 1 4.7U_0402_6.3V6K 1
2 2 BLM15PX331SN1D_2P USB3_RX2_N 4 6 U3RXDN2 U2DN2 2 VBUS

G
12 USB3_RX2_N
2

2
2 2 4 6 U2DP2 3 D-
4 D+
@ @ @ @ @ @ @ USB3_RX2_P 3 1 U3RXDP2 U3RXDN2 5 GND
+VL 12 USB3_RX2_P 3 1 U3RXDP2 6 SSRX- 10
R130 7 SSRX+ GND 11
C 1 2 U3TXDN2 8 GND GND 12 C
GND U3TXDP2 9 SSTX- GND 13
100K_0402_5% L15 SSTX+ GND
RF@ ACON_TAR2G-9R1393

2
D 1 @ DC231709280
C90
ME@

1
R396 1 2 0_0402_5% 3V/5VALW_PG_R 2 Q29 0.1U_0201_10V K X5R
44,45,48,50 3V/5VALW_PG
G L2N7002SWT1G 1N SC-70-3
S 2
2

3
C462 CMF-2012-2G45-32T_6P
0.1U_0201_10V K X5R

5
1 @ GND
C168
0.1U_0201_10V K X5R
1 2 U3TXDN2_L 4 6 U3TXDN2
12 USB3_TX2_N 4 6
C169
0.1U_0201_10V K X5R
1 2 U3TXDP2_L 3 1 U3TXDP2
12 USB3_TX2_P 3 1

GND
L16
RF@

2
ESD@ D9 ESD@ D10
B U3RXDN1 9 10 1 1 U3RXDN1 U2DP1 3 6 B
I/O2 I/O4
L24 EMI@ U3RXDP1 8 9 2 2 U3RXDP1
USB20_N1 1 2 U2DN1
12 USB20_N1 1 2 U3TXDN1 7 7 4 4 U3TXDN1 2 5 +USB3_VCCA
GND VDD
USB20_P1
12 USB20_P1
4 3 U2DP1 U3TXDP1 6 6 5 5 U3TXDP1
4 3
DLM0NSN900HY2D_4P 3 3 1 4 U2DN1
I/O1 I/O3
8
L30ESDL5V0C6-4 SOT23
+USB3_VCCA
L05ESDL5V0NA-4 SLP2510P8 ESD
JUSB2
+5VALW +USB3_VCCA 1
U20 U2DN1 2 VBUS
1 U2DP1 3 D-
5 OUT L22 RF@ 4 D+
IN 2 5 GND U3RXDN1 5 GND
USB_EN# 4 GND U3RXDP1 6 SSRX- 10
45 USB_EN# EN SSRX+ GND 11
3 7
OCB 4 6 U3RXDN1 U3TXDN1 8 GND GND 12
1 12 USB3_RX1_N 4 6 SSTX- GND 13
C196 SY6288D20AAC_SOT23-5 U3TXDP1 9
SSTX+ GND
6.8P_0402_50V_NPO

0.1U_0201_10V K X5R 1
150U_B2_6.3VM_R35M

@ 1 3 1 U3RXDP1 ACON_TAR2G-9R1393
2 + 12 USB3_RX1_P 3 1
DC231709280
C178

C177

RF@

ME@
2 2 GND

CMF-2012-2G45-32T_6P
2

L23 RF@
5

GND
A A
C459
0.1U_0201_10V K X5R
1 2 U3TXDN1_L 4 6 U3TXDN1
12 USB3_TX1_N 4 6
C460
0.1U_0201_10V K X5R
1 2 U3TXDP1_L 3 1 U3TXDP1
12 USB3_TX1_P 3 1

GND

CMF-2012-2G45-32T_6P
Security Classification Compal Secret Data Compal Electronics, Inc.
2

2017/5/3 2017/6/2 Title

USB2 / USB3 / FP / IO Board

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Dat e: Wednesday, October 18, 2017 Sheet 37 of 61
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

TBT PORTS DP
UT1E TBT@

43 USB3_A_TRX_DTX_P0 B21
A21 PA_RX0_P AB7 CPU_DP1_P0_C 0.1U_0201_6.3V6K 2 1 TBT@ CT156
43 USB3_A_TRX_DTX_N0 PA_RX0_N DPSNK0_ML0_P CPU_DP1_N0_C CPU_DP1_P0 6
AC7 0.1U_0201_6.3V6K 2 1 TBT@ CT155 CPU_DP1_N0 6
CT41 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P0 A19 DPSNK0_ML0_N
43 USB3_A_TTX_C_DRX_P0 USB3_A_TTX_DRX_N0 PA_TX0_P CPU_DP1_P1_C
43 USB3_A_TTX_C_DRX_N0 CT42 TBT@ 2 1 0.22U_0201_6.3V6M B19 AB9 0.1U_0201_6.3V6K 2 1 TBT@ CT157 CPU_DP1_P1 6
PA_TX0_N DPSNK0_ML1_P AC9 CPU_DP1_N1_C 0.1U_0201_6.3V6K 2 1 TBT@ CT158
DPSNK0_ML1_N CPU_DP1_N1 6
A15 AB11 CPU_DP1_P2_C 0.1U_0201_6.3V6K 2 1 TBT@ CT160

Sink Port 0
43 USB3_A_TRX_DTX_P1 PA_RX1_P DPSNK0_ML2_P CPU_DP1_N2_C CPU_DP1_P2 6
43 USB3_A_TRX_DTX_N1 B15 AC11 0.1U_0201_6.3V6K 2 1 TBT@ CT159 CPU_DP1_N2 6
PA_RX1_N DPSNK0_ML2_N
CT39 TBT@ 2 1 0.22U_0201_6.3V6M USB3_A_TTX_DRX_P1 A17 AB13 CPU_DP1_P3_C 0.1U_0201_6.3V6K 2 1 TBT@ CT161

Port A
43 USB3_A_TTX_C_DRX_P1 USB3_A_TTX_DRX_N1 PA_TX1_P DPSNK0_ML3_P CPU_DP1_N3_C CPU_DP1_P3 6
43 USB3_A_TTX_C_DRX_N1 CT40 TBT@ 2 1 0.22U_0201_6.3V6M B17 AC13 0.1U_0201_6.3V6K 2 1 TBT@ CT162 CPU_DP1_N3 6
PA_TX1_N DPSNK0_ML3_N
CT43 TBT@ 2 1 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y11 CPU_DP1_AUXP_C 0.1U_0201_6.3V6K 2 1 TBT@ CT163
43 TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P DPSNK0_AUX_P CPU_DP1_AUXN_C DDI1_AUX_DP 6
43 TBT_A_AUX_N_C CT44 TBT@ 2 1 0.1U_0201_6.3V6K W15 W11 0.1U_0201_6.3V6K 2 1 TBT@ CT164
PA_DPSRC_AUX_N DPSNK0_AUX_N DDI1_AUX_DN 6
E20 AA2 CPU_DP1_HPD
PA_USB2_D_P DPSNK0_HPD CPU_DP1_HPD 6
D20
PA_USB2_D_N Y5
DPSNK0_DDC_CLK R4
TBTA_LSTX A5 NC_R4
43 TBTA_LSTX TBTA_LSRX PA_LSTX
43 TBTA_LSRX A4
PA_LSRX

1
TBTA_HPD M4 AB15 RT59
42 TBTA_HPD PA_DPSRC_HPD NC_AB15 AC15 100K_0402_5%
NC_AC15
C 2 TBT@ 1 PA_USB2_RBIAS H19 AB17 TBT@ C
RT43 499_0201_1% PA_USB2_RBIAS NC_AB17 AC17

2
NC_AC17
A13 AB19
B13 NC_A13 NC_AB19 AC19
NC_B13 NC_AC19
A11 AB21
B11 NC_A11 NC_AB21 AC21
NC_B11 NC_AC21
Y12
B7 NC_Y12 W12
A7 PB_RX0_N NC_W12
PB_RX0_P Y6
A9 RSV_Y6 Y8
B9 PB_TX0_P NC_Y8 N4
PB_TX0_N NC_N4 Y18 DPSNK_RBIAS 1 TBT@ 2
DPSNK_RBIAS 14K_0402_1% RT5
Y16
100K_0402_1% 2 TBT@ 1 RT41 TBTA_HPD W16 NC_Y16 R2
NC_W16 NC_R2 R1
NC_R1
E19 N2
D19 NC_E19 NC_N2 N1
NC_D19 NC_N1
L2
B4 NC_L2 L1
1M_0201_1% 2 TBT@ 1 RT42 TBTA_LSTX B5 NC_B4 NC_L1
1M_0201_1% 2 TBT@ 1 RT120 TBTA_LSRX G2 NC_B5 J2
NC_G2 NC_J2 J1
B F19 NC_J1 B
NC_F19 W19
NC_W19 Y19
NC_Y19
G1
NC_G1
N6
NC_N6

JHL6240-QSXA-A1_BGA337

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/06.23 2017/06/23 Title

Thunderbolt AR-LP(1/4)
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 38 of 61

5 4 3 2 1
 5 4 3 2 1

UT1A TBT@
TBT_EE_DI AB3 U1 TBT_I2C_SDA
42 TBT_EE_DI TBT_EE_DO EE_DI GPIO_0_I2C_DATA TBT_I2C_SDA 42
42 TBT_EE_DO AC4
TBT_EE_CS_N AC3 EE_DO U2 TBT_I2C_SCL
42 TBT_EE_CS_N TBT_EE_CLKVinafix.com
AB4 EE_CS_N GPIO_1_I2C_CLK TBT_I2C_SCL 42

EE
42 TBT_EE_CLK EE_CLK TBT_EE_W P_N
V1
TBT_TDI Y4 GPIO_2_EE_WP#

LC GPIO
D D

DEBUG
TBT_TMS V4 TDI V2 TBT_TMU_CLK_OUT

MISC &
TBT_TCK T4 TMS GPIO_3_Reserved
TBT_TDO W4 TCK W1 TBT_PCIE_W AKE# RT77 1 2 0_0402_5%

JTAG
TDO GPIO_4_PEWAKE# EC_PCIE_WAKE# 34,45
TBT_XTAL_25_IN D22 W2 TBT_CIO_PLUG_EVENT#
XTAL_25_IN GPIO_5_CIO_PLUG_EVENT TBT_CIO_PLUG_EVENT# 8
TBT_XTAL_25_OUT D23 Y1 TBT_HDMI_DDC_DATA
XTAL_25_OUT GPIO_6_SRC0_DDC_DATA
Y2 TBT_HDMI_DDC_CLK
TBT_RSENSE J6 GPIO_7_SRC0_DDC_CLK
2 1 TBT_RBIAS H6 RSENSE AA1 TBT_SRC_CFG1
RT25 TBT@ 4.75K_0402_0.5% RBIAS GPIO_8_SRC0_CFG1
J4 TBTA_I2C_INT
POC_GPIO_0_PA_PPS_INT_N TBTA_I2C_INT 42
AC23
AB23 THERMDA1 E2 TBTA_I2C1_INT
AC1 THERMDA2 POC_GPIO_1_PB_PPS_INT_N
L15 TEST_EDM D4 RTD3_USB_PWR_EN_R
N15 FUSE_VQPS_64 POC_GPIO_2_RTD3_PWR_EN
NC_N15 H4 TBT_FORCE_PW R
POC_GPIO_3_FORCE_PWR TBT_FORCE_PW R 6
C23
C22 MONDC_CIO_0 F2 BATLOW # DT246 1 2 RB521CM-30T2R_SOD923-2

POC GPIO
PM_BATLOW # 10

DEBUG
NC_C22 POC_GPIO_4_BATLOW# @
D6 D2 SUSP#_R DT247 1 2 RB521CM-30T2R_SOD923-2
MONDC_SVR POC_GPIO_5_DG_SLP_S3# SUSP# 13,44,45,49
W13 @
W18 MONDC_DPSNK_0 F1 RTD3_CIO_PWR_EN_R
AB2 NC_W18 POC_GPIO_6_RTD3_CIO_PWR_EN
NC_AB2 AB5 TBT_TEST_PWG
A23 TEST_PWR_GOOD
C B23 ATEST_P E1 TBT_TEST_EN C
E18 ATEST_N TEST_EN
V18 USB2_ATEST F4 TBT_RESET_N
PCIE_ATEST RESET_N TBT_RESET_N 42
JHL6240-QSXA-A1_BGA337
BATLOW # RT167 1 2 0_0402_5% PM_BATLOW #

SUSP#_R RT168 1 2 0_0402_5% SUSP#

+3.3V_FLASH +3.3V_LC

RT21
2

2
+3.3V_TBT_SX RT105 RT106 TBT_XTAL_25_IN 1 2 TBT_XTAL_25_IN_R
0_0402_5% 0_0402_5%
RTD3_CIO_PWR_EN_R RT117 2 TBT@ 1 10K_0201_5% @ 33_0201_5%
TBT_FORCE_PW R RT125 2 @ 1 10K_0201_5% EMI@
1 UT2 TBT@
1

8 1 TBT_EE_CS_N
TBT_HOLD_N 7 VCC CS# 2 TBT_EE_DO LC101 @EMI@
TBT_RESET_N RT80 2 @ 1 10K_0201_5% TBT_EE_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_EE_W P_N 1 2
TBT_PCIE_W AKE# RT20 2 TBT@ 1 10K_0201_5% TBT_EE_DI 5 CLK WP#(IO2) 4 1 2
TBT_CIO_PLUG_EVENT# RT108 2 TBT@ 1 10K_0201_5% DI(IO0) GND
TBT_SRC_CFG1 RT126 2 @ 1 10K_0201_5% W 25Q80DVSSIG_SO8 4 3
RT50 1 TBT@ 2 2.2K_0402_5% TBT_EE_CS_N 4 3
RT51 1 TBT@ 2 3.3K_0402_5% TBT_HOLD_N DLM0NSN900HY2D_4P
RT48 1 TBT@ 2 3.3K_0402_5% TBT_EE_W P_N YT1 TBT@
+3.3V_TBT_SX RT49 2 TBT@ 1 2.2K_0402_5% TBT_EE_DO 25MHZ_20PF_XRCGB25M000F2P18R0
RT22
TBT_I2C_SDA RT138 2 TBT@ 1 2.2K_0201_5% TBT_XTAL_25_OUT 1 2 TBT_XTAL_25_OUT_R 3 1
1 3 1
B TBT_I2C_SCL RT139 2 TBT@ 1 2.2K_0201_5% B
TBTA_I2C_INT RT111 2 TBT@ 1 10K_0201_5% CT45 33_0201_5% NC NC
1 1
TBTA_I2C1_INT RT187 2 TBT@ 1 10K_0201_5% 0.1U_0402_25V6 EMI@ TBT@ TBT@
2 TBT@ CT37 4 2 CT38
27P_0402_50V8J 27P_0402_50V8J
2 2

TBT_SRC_CFG1 RT135 1 TBT@ 2 1M_0201_1%

+3.3V_LC

TBT_HDMI_DDC_DATA RT109 1 TBT@ 2 100K_0201_5%

TBT_HDMI_DDC_CLK RT110 1 TBT@ 2 100K_0201_5%
TBT_TMU_CLK_OUT RT38 1 TBT@ 2 100K_0201_5%
TBT_FORCE_PW R RT127 2 TBT@ 1 100K_0201_5% RT6 RT7 RT8 RT9

1
10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
@ @ @ @

TBT_TEST_PWG RT136 1 TBT@ 2 100_0201_5% JTAG1

TBT_TEST_EN RT137 1 TBT@ 2 100_0201_5% 1

2
TBT_TDI 2 1
TBT_TMS 3 2
TBT_TCK 4 3
RTD3_CIO_PWR_EN_R RT116 2 @ 1 10K_0201_5% TBT_TDO 5 4
RTD3_USB_PWR_EN_R RT115 1 TBT@ 2 10K_0201_5% 6 5
BATLOW # RT31 2 @ 1 10K_0201_5% 6
SUSP#_R RT30 2 @ 1 10K_0201_5% 7
8 GND
A GND A

ACES_50228-0067N-001
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/06.23 2017/06/23 Title

Thunderbolt AR-LP(2/4)
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 39 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS_TBT

+3VALW +3VS_TBT +3VALW +3.3V_TBT_SX

Vinafix.com

1
SHI0000N600 TBT@ LT1
D 1UH +-20% LQM18PN1R0MFHD D
RT146 1 2 0_0805_5% RT147 1 2 0_0402_5%
+3VS_TBT

2
CT129 CT130 CT137 CT138 CT139 CT140 CT123 CT141 CT142

1 1 1 1 1 1 1

1U_0201_6.3V6M

1U_0402_6.3V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
UT1C TBT@

1
+0.9V_DP L8 A2
CT108 CT109 CT110 CT111 CT112 CT124 L11 VCC0P9_DP VCC3P3_SVR A3 TBT@ TBT@ TBT@ TBT@ @ TBT@ TBT@ TBT@ TBT@
L12 NC_L11 VCC3P3_SVR B3 2 2 2 2 2 2 2

MAIN PWRSVR 3.3V

1 1 1 1 1 1

2
NC_L12 VCC3P3_SVR
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0402_6.3V6K

1U_0201_6.3V6M

1U_0402_6.3V6K
M8 H9
T11 VCC0P9_DP VCC3P3A
TBT@ TBT@ TBT@ TBT@ TBT@ TBT@ T12 VCC0P9_DP
2 2 2 2 2 2 VCC0P9_DP R13 +3.3V_LC +3.3V_TBT_SX
L6 VCC3P3_S0
M6 NC_L6 F8 +3.3V_TBT_SX
V11 NC_M6 VCC3P3_SX CT132 CT131
V12 VCC0P9_ANA_DPSNK R6 +3.3V_LC
V13 VCC0P9_ANA_DPSNK VCC3P3_LC
VCC0P9_ANA_DPSNK 1 1
+0.9V_SVR

LC

1U_0402_6.3V6K

1U_0402_6.3V6K
L9
+0.9V_PCIE M13 VCC0P9_SVR M9 CT54 CT125 CT126 CT127 CT128
CT118 CT119 CT120 CT121 CT122 M15 VCC0P9_PCIE VCC0P9_SVR E12 TBT@ TBT@
VCC0P9_PCIE VCC0P9_SVR_ANA 1 1 1 1 1 2 2
1 1 1 1 1 M16 E13
VCC0P9_PCIE VCC0P9_SVR_ANA
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L19 F11

SVR 0.9V
N19 NC_L19 VCC0P9_SVR_ANA F12 TBT@ TBT@ TBT@ TBT@ TBT@
@ @ TBT@ TBT@ TBT@ L18 VCC0P9_ANA_PCIE_1 VCC0P9_SVR_ANA F13 2 2 2 2 2
2 2 2 2 2 M18 VCC0P9_ANA_PCIE_2 VCC0P9_SVR_ANA F15

PWR OUT 0.9V

C N18 VCC0P9_ANA_PCIE_2 VCC0P9_SVR_ANA J9 C
VCC0P9_ANA_PCIE_2 VCC0P9_SVR_SENSE
R15 LT2 TBT@
+0.9V_USB R16 VCC0P9_USB C1 TBT_SVR_IND 1 2
CT115 VCC0P9_USB SVR_IND C2 0.6UH_MND-04ABIR60M-XGL_20% CT143 CT144 CT145 CT272
+0.9V_CIO R8 SVR_IND D1
1 VCC0P9_CIO SVR_IND

1
CT117 CT116 R9
VCC0P9_CIO
1U_0201_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
R11 A1 TBT@ TBT@ TBT@ TBT@
TBT@ R12 VCC0P9_CIO SVR_VSS B1

2
2 VCC0P9_CIO SVR_VSS
1U_0201_6.3V6M

1U_0201_6.3V6M

1 1 B2
+0.9V_LVR_OUT F18 SVR_VSS
CT113 CT114 CT135 CT136 CT146 CT273 H18 VCC0P9_LVR J16 +3.3V_ANA_USB2
TBT@ TBT@ J11 VCC0P9_LVR VCC3P3_ANA_USB2 L16 +3.3V_ANA_PCIE
2 2 1 1 1 1 1 VCC0P9_LVR VCC3P3_ANA_PCIE
H11 CT134 CT133
VCC0P9_LVR_SENSE
1
1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

TBT@ TBT@ TBT@ @ TBT@ TBT@ JHL6240-QSXA-A1_BGA337 1 1

2 2 2 2 2

1U_0201_6.3V6M

1U_0201_6.3V6M
2

1
RT183
10K_0201_1% TBT@ TBT@
TBT@ 2 2

2
B B

UT1B TBT@
CT14 TBT@ 1 2 0.22U_0201_6.3V6M PCIE_PRX_C_DTX_P1 V23 Y23 PCIE_PTX_C_DRX_P1
12 PCIE_PRX_DTX_P1 PCIE_PRX_C_DTX_N1 PCIE_TX0_P PCIE_RX0_P PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 12
CT16 TBT@ 1 2 0.22U_0201_6.3V6M V22 Y22

PCIe
12 PCIE_PRX_DTX_N1 PCIE_TX0_N PCIE_RX0_N PCIE_PTX_C_DRX_N1 12
CT12 TBT@ 1 2 0.22U_0201_6.3V6M PCIE_PRX_C_DTX_P2 P23 T23 PCIE_PTX_C_DRX_P2
12 PCIE_PRX_DTX_P2 PCIE_PRX_C_DTX_N2 PCIE_TX1_P PCIE_RX1_P PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 12
CT2 TBT@ 1 2 0.22U_0201_6.3V6M P22 T22
12 PCIE_PRX_DTX_N2 PCIE_TX1_N PCIE_RX1_N PCIE_PTX_C_DRX_N2 12
K23 M23
K22 NC_K23 NC_M23 M22
NC_K22 NC_M22 +3VS_TBT
F23 H23
F22 NC_F23 NC_H23 H22
NC_F22 NC_H22 TBTCLK_R_REQ# RT148 1 @ 2 10K_0201_5%
PCI_RST# L4 AC5 RT141 1 2 0_0201_5%
10,21,34,45 PCI_RST# PERST_N PCIE_CLKREQ_N TBTCLK_REQ# 10
CLK_PCIE_TBT V19 N16 PCIE_RBIAS RT140 1 TBT@ 2 3.01K_0201_1%
10 CLK_PCIE_TBT REFCLK_100_IN_P PCIE_RBIAS
CLK_PCIE_TBT# T19
10 CLK_PCIE_TBT# REFCLK_100_IN_N

JHL6240-QSXA-A1_BGA337
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/06.23 2017/06/23 Title

Thunderbolt AR-LP(3/4)
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, October 18, 2017 Sheet 40 of 61

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
UT1D TBT@
D A6 V5 D
A8 VSS_ANA VSS_ANA V6
A10 VSS_ANA VSS_ANA V8
A12 VSS_ANA VSS_ANA V9
A14 VSS_ANA VSS_ANA V15
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
VSS_ANA VSS_ANA

GND
D9 AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
C E15 VSS_ANA VSS_ANA AC8 C
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA P1
H1 VSS_ANA VSS_ANA P2
H2 VSS_ANA VSS_ANA R5
H12 VSS_ANA VSS_ANA R18
H13 VSS_ANA VSS_ANA R19
H15 VSS_ANA VSS_ANA R20
H16 VSS_ANA VSS_ANA R22
H20 VSS_ANA VSS_ANA R23
J5 VSS_ANA VSS_ANA T1
J18 VSS_ANA VSS_ANA T2
J19 VSS_ANA VSS_ANA T5
J20 VSS_ANA VSS_ANA U22
J22 VSS_ANA VSS_ANA N23
J23 VSS_ANA VSS_ANA N22
K1 VSS_ANA VSS_ANA N20
K2 VSS_ANA VSS_ANA N5
L5 VSS_ANA VSS_ANA M20
L20 VSS_ANA VSS_ANA M19
L22 VSS_ANA VSS_ANA M5
L23 VSS_ANA VSS_ANA M2
M1 VSS_ANA VSS_ANA T20
B VSS_ANA VSS_ANA U23 B
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E6 JHL6240-QSXA-A1_BGA337
E5
E4
J12

H8
H5

D5

M11
M12
J13
J15

N8
N9
L13

T13
T15
T16
T18
AB1
J8

F6
F5

N11
N12
T8
T9

AC2
T6
N13

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2016/06.23 2017/06/23 Title

Thunderbolt AR-LP(4/4)
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 17, 2017 Sheet 41 of 61

5 4 3 2 1
 5 4 3 2 1

+5VALW +5VALW_PD Vinafix.com +3VALW +3VALW_PD

D J1 J6 D
2 1 2 1
2 1 2 1
JUMP_43X79 JUMP_43X79

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

TBT@

TBT@

TBT@

TBT@
1 1 1 1
CT22
4.7U_0402_6.3V6K
2
2 2 2 2 TBT@

CT90

CT91

CT92

CT93
+TBTA_VBUS

+5VALW_PD

2 TBT@
TBT@ CT222 TBT@

1
CT260 0.1U_0402_25V6 DT248
1U_0603_25V6K NSR20F30NXT5G_DSN2-2
1

2
+3VALW

C C
+3VALW_PD UT10
PT1

2
G
7 8 DMP3056L-7_SOT23-3
PP_HV1 VBUS1 3 1 @ TBTA_CC1 CT265 1 2 220P_0201_25V7K
2

RT171
3.3K_0201_5%

3.3K_0201_5%

@ @ 10K_0201_5% 1 2 TBT_VBUS2 TBT@

D
TBT@ +3VALW_PD PP_HV2 VBUS2 +LDO_1V8_PD +3.3V_FLASH TBTA_CC2 CT269 1 2 220P_0201_25V7K

TBT@
1

5 TBT_LDO_3V3 RT188 1 2 0_0402_5%

1 LDO_3V3
3 26
RT170

RT169

CT263 VIN_3V3 LDO_1V8

2
10U_0402_6.3V6M
TBTA_CC1 2 10U_0402_6.3V6M
2 TBT@ 15
C1_CC1 TBTA_CC2 TBTA_CC1 43 10U_0402_6.3V6M CT270
17 CT262 TBT@
C1_CC2 TBTA_CC2 43 1
18 TBT@
45,46,47 EC_SMB_CK1 I2C1_SCL TBTB_CC1 1
19 36
45,46,47 EC_SMB_DA1 I2C1_SDA C2_CC1 TBTB_CC2
20 38
45 PD_IRQ# I2C1_IRQ C2_CC2
23
39 TBT_I2C_SCL I2C2_SCL
24 4 ADCIN1
39 TBT_I2C_SDA I2C2_SDA ADCIN1 +5VALW_PD
25 6 ADCIN2
39 TBTA_I2C_INT I2C2_IRQ ADCIN2 +3.3V_FLASH
16
PP1_CABLE 37
TBT_EE_DO PP2_CABLE 1
27
39 TBT_EE_DO TBT_EE_DI SPI_MISO(GPIO8)
28 41 TP2 @ CT271
39 TBT_EE_DI TBT_EE_CLK SPI_MOSI(GPIO9) C1_USB_P(GPIO18)
39 TBT_EE_CLK 29 42 TP3 @ 4.7U_0402_6.3V6K

1
TBT_EE_CS_N 30 SPI_CLK(GPIO10) C1_USB_N(GPIO19) 2 RT172 RT173
39 TBT_EE_CS_N SPI_SS(GPIO11) TBT@
43 TP4 @ 10K_0201_1% 10K_0201_1%
C2_USB_P(GPIO20) 44 TP5 @ TBT@ TBT@
C2_USB_N(GPIO21)

2
9 TBT_RESET_N_R RT186 1 2 0_0402_5% ADCIN1
RT174 1 2 0_0402_5% HRESET 35 GPIO0 10 TBT_GPIO1 TBT_RESET_N 39 ADCIN2
45 PD_RESET HRESET GPIO1 TBT_GPIO2
11 TP1 @
GPIO2 21
HPD1(GPIO3) TBT_GPIO4 TBTA_HPD 38
22 TP6 @

1
45 HPD2(GPIO4) 12 TBTA_DP_MODE RT175 RT176
NC GPIO5 TBTA_POL TBTA_DP_MODE 43
46 13 100K_0201_1% 100K_0201_1%
NC GPIO6 TBTA_TBT_MODE TBTA_POL 43
14 TBT@ TBT@
B
GPIO7 TBT_GPIO7 TBTA_TBT_MODE 43 B
47 31 TP7 @
G-Pad GPIO12 32 TBT_GPIO8 TP8 @

2
+3VALW_PD GPIO13 33 TBT_GPIO9 TP9 @
A1 GPIO14(PWM) 34 TBT_GPIO10 TP10 @ +5VALW_PD
A2 NC1 GPIO15(PWM) 39 TBTA_PPEXT_EN 100K_0201_5% 2 TBT@ 1 RT177
A3 NC2 GPIO16(PP_EXT1) 40 TBT_GPIO17 TP11 @
RT178 1 @ 2 100K_0201_5% HRESET A4 NC3 GPIO17(PP_EXT2)
NC4 TBT_GPIO1 1 2 RT179
RT180 1 @ 2 1M_0201_5% 1M_0402_5% TBT@
TBT@ SN1701012RSLR_VQFN48_6X6
@ SA0000BAN00 TBT_VBUS2 1 2 RT189

4.7U_0402_6.3V6K

4.7U_0402_6.3V6K
2 2
0.01U_0201_6.3V7K 2 1 CT231 1M_0402_5% TBT@

CT225

CT268
TBTB_CC1 1 2 RT190
1M_0402_5% TBT@ 1 1

TBTB_CC2 1 2 RT191 TBT@ TBT@

1M_0402_5% TBT@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/06/23
CC_TPS65988CE
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 42 of 61
5 4 3 2 1
 5 4 3 2 1

UT5 TBT@

7
RPD_G1
DT232 ESD@ 6
RPD_G2
USB3_A_TTX_C_DRX_P0 1 2
38 USB3_A_TTX_C_DRX_P0 TBTA_CC1 TBTA_CC1_CONN
42 TBTA_CC1 12 4
DT233 ESD@ CC1 C_CC1
PESD5V0H1BSF_SOD962-2-2 TBTA_CC2 11 TPD8S300 5 TBTA_CC2_CONN
USB3_A_TTX_C_DRX_N0 42 TBTA_CC2 CC2 C_CC2
1 2
38 USB3_A_TTX_C_DRX_N0
DT234
Vinafix.com
ESD@
TBTA_SBU1 15
SBU1 C_SBU1
1 TBTA_SBU1_CONN

PESD5V0H1BSF_SOD962-2-2 TBTA_SBU2 14 2 TBTA_SBU2_CONN

D USB3_A_TRX_DTX_P0 1 2 SBU2 C_SBU2 D
38 USB3_A_TRX_DTX_P0
DT235 ESD@
PESD5V0H1BSF_SOD962-2-2 20
USB3_A_TRX_DTX_N0 1 2 D1
38 USB3_A_TRX_DTX_N0 +3.3V_FLASH 19
DT236 ESD@ 3 D2
PESD5V0H1BSF_SOD962-2-2 VBIAS 17
USB3_A_TTX_C_DRX_P1 1 2 10 D3
38 USB3_A_TTX_C_DRX_P1 VPWR 16
DT237 ESD@ D4
PESD5V0H1BSF_SOD962-2-2
USB3_A_TTX_C_DRX_N1 1 2 RT134 2 TBT@ 1 100K_0402_5% 9 18
38 USB3_A_TTX_C_DRX_N1 FLT GND1 8
DT238 ESD@ GND2 13
PESD5V0H1BSF_SOD962-2-2 GND3 21
USB3_A_TRX_DTX_P1 1 1 PAD

1U_0201_6.3V6M
CT153

1U_0603_50V6K
CT154
38 USB3_A_TRX_DTX_P1 1 2

DT239 ESD@ TPD8S300_QFN20_3X3

PESD5V0H1BSF_SOD962-2-2 2 2
USB3_A_TRX_DTX_N1

TBT@

TBT@
38 USB3_A_TRX_DTX_N1 1 2

PESD5V0H1BSF_SOD962-2-2

LT3 EMI@
USB20_N3 4 3 TBT_A_USB20_N3
12 USB20_N3 4 3

C USB20_P3 1 2 TBT_A_USB20_P3 C
+3.3V_TBT_SX 12 USB20_P3 1 2
1 DLM0NSN900HY2D_4P

1
RT184 RT185
100K_0402_5% 100K_0402_5%
+3VALW_PD TBT@ TBT@
ESD@ D26
2

UT9 TBT@ 2 3 6 TBT_A_USB20_N3

13 20 TBT_A_AUX_N_C I/O2 I/O4 DT242 ESD@
VCC A1_OUTp TBT_A_AUX_P_C +5VALW_PD TBTA_CC2_CONN 1 1 TBTA_CC2_CONN
A1_OUTn
19 10 9
TBTA_SBU1 1
TBTA_SBU2 A_INp TBT_A_AUX_P_C TBTA_CC1_CONN
2 18
TBT_A_AUX_P_C 38
2 5 2 2 9 8 TBTA_CC1_CONN
A_INn A0_OUTp 17 TBT_A_AUX_N_C GND VDD
A0_OUTn TBT_A_AUX_N_C 38 TBTA_SBU2_CONN
RT181 1 2 0_0201_5% 14 4 4 7 7 TBTA_SBU2_CONN
16 SAI 15 TBTA_POL
EN_A SAO TBT_A_USB20_P3 TBTA_SBU1_CONN
42 TBTA_DP_MODE TBTA_POL 42 1 4 5 5 6 6 TBTA_SBU1_CONN
I/O1 I/O3
3 6 TBTA_LSRX AZC099-04S.R7G_SOT23-6 3 3
4 B_INp B1_OUTp 7 TBTA_LSTX
B_INn B1_OUTn 8
12 8 TBTA_LSTX
10 SBI B0_OUTp 9 TBTA_LSRX TBTA_LSTX 38 L05ESDL5V0NA-4_SLP2510P8-10-9
42 TBTA_TBT_MODE EN_B B0_OUTn TBTA_LSRX 38
5 11
21 GND SBO
Thermal pad
2

RT182
0_0201_5% TS3DS10224RUKR_WQFN20_3X3
+TBTA_VBUS +TBTA_VBUS
B B
1

JTYPEC1
A1 B12
GND_A1 GND_B12
USB3_A_TTX_C_DRX_P1 A2 B11 USB3_A_TRX_DTX_P1
USB3_A_TTX_C_DRX_N1 A3 SSTXP1 SSRXP1 B10 USB3_A_TRX_DTX_N1
SSTXN1 SSRXN1
TBT@ CT94 1 2 0.47U_0402_25V6K A4 B9 CT96 1 2 0.47U_0402_25V6K
VBUS_A4 VBUS_B9
TBTA_CC2_CONN A5 B8 TBTA_SBU1_CONN TBT@
CC1 SBU2
TBT_A_USB20_P3 A6 B7 TBT_A_USB20_N3
TBT_A_USB20_N3 A7 DP1 DN2 B6 TBT_A_USB20_P3
DN1 DP2

Bottom
TBTA_SBU2_CONN A8 B5 TBTA_CC1_CONN

TOP
SBU1 CC2
TBT@ CT95 1 2 0.47U_0402_25V6K A9 B4 1 2
VBUS_A9 VBUS_B4 CT97 0.47U_0402_25V6K
USB3_A_TRX_DTX_N0 A10 B3 USB3_A_TTX_C_DRX_N0 TBT@
USB3_A_TRX_DTX_P0 A11 SSRXN2 SSTXN2 B2 USB3_A_TTX_C_DRX_P0
SSRXP2 SSTXP2
A12 B1
GND_A12 GND_B1

1 2
GND1 GND2

3
3 4 ESD@ DT245
5 GND3 GND4 6
GND5 GND6 L30ESD24VC3-2_SOT23-3
A A

1
DRAPH_UB11246-0500B-1H
ME@
SP061708250

Security Classification Compal Secret Data Compal Electronics, Inc.

2017/5/3 2017/06/23 Title

USB3.1 TypeC
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev

LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 43 of 61
5 4 3 2 1
 A B C D E

+3VS
+3VALW J4

+VL
Vinafix.com 2
2
JUMP_43X79
1
1

10U_0603_6.3V6M
1 1

10U_0603_6.3V6M

0.1U_0201_10V K X5R
1 1
1 1
0.1U_0201_10V K X5R

C211

C212
@ @
C205

C206
@ @
2 2
2 2
U13
1 14
2 VIN1 VOUT1 13 +3VALW_3VS
VIN1 VOUT1
3 12 C207 1 2
ON1 CT1 470P_0402_50V7K
4 11
13,39,45,49 SUSP# VBIAS GND
5 10 1 2 220P_0402_50V7K +5VS
+5VALW ON2 CT2 C213 J5
6 9 +5VALW_5VS 2 1
7 VIN2 VOUT2 8 2 1
VIN2 VOUT2 JUMP_43X79
10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 15 1 1
GPAD
0.1U_0201_10V K X5R

0.1U_0201_10V K X5R
C214

C215

C217

C218
@ @ EM5209VF_DFN14_2X3 @ @
2 2 2 2

2 2

3 3

+1.8VALW

+0.6VS
+5VALW
+5VALW
1

R394
1

22_0603_5% R228
@
1

R393 470_0402_5%
1

100K_0402_5% R230
2

@
2

100K_0402_5%
D D
2

1.8VALW_PWR_EN# 5 SUSP 5 @
2

G Q143B G Q144B
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
D D
4

4
6

2 SUSP# 2 @
37,45,48,50 3V/5VALW_PG G Q143A G Q144A
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/5/3 Deciphered Date 2017/6/2 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC to DC
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 44 of 61
A B C D E
 +3VL +3VL

R189 1 @ 2 0_0603_5% 1@
Vinafix.com +3VALW_EC
C179
100P_0402_50V8J
1 1 1 1 2

0.1U_0201_10V K X5R
C180

0.1U_0201_10V K X5R
C181

1000P_0402_50V7K
C182

1000P_0402_50V7K
C183
L20
BLM15AX601SN1D_2P +5VALW
1 2 2 2 @ 2 @ 2 +EC_VCCA
+3VALW_EC SM01000KL00 1 1
+EC_VCCA
C184 C185 @ USB_EN# R194 1 2 10K_0402_5%
0.1U_0201_10V K X5R
L21 1000P_0402_50V7K
U11

111
125
1 2 2 ECAGND 2

22
33
96

67
9
BLM15AX601SN1D_2P
SM01000KL00

VCC_LPC
VCC
VCC
VCC
VCC0
VCC

AVCC
ECAGND
1 21
42 PD_IRQ# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F VCCST_PWRGD 10
2 23 BEEP#
48 5VLDO_EN KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 33
3 26 1
8 SERIRQ SERIRQ EC_FAN_PWM/GPIO12 EC_FAN_PWM2 EC_FAN_PWM1 35
PWM Output

100P_0402_50V8J
C124 @ESD@
4 27
8 LPC_FRAME# LPC_FRAME# AC_OFF/GPIO13 EC_FAN_PWM2 35
5
8 LPC_AD3 7 LPC_AD3
8 LPC_AD2 LPC_AD2 2
8 63
8 LPC_AD1 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_TEMP 46,47
LPC_AD0LPC & MISC
@EMI@ @EMI@ 10 64
2 1 8 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 DCHG_I 47
R190 2 1 10_0402_1% 65
ADP_I/AD2/GPIO3A ADP_I 47
C186 22P_0402_50V8J
8 CLK_LPC_EC
12
CLK_PCI_EC AD Input AD_BID/AD3/GPIO3B
66
CUST_TEMP3 35
13 75
10,21,34,40 PCI_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 ADP_ID 46
1 2 37 76
+3VALW_EC R192 @ 47K_0402_5% EC_SCI# 20 EC_RST# AD5/GPIO43 CUST_TEMP2 35
6,10 EC_SCI#
1 2 PM_CLKRUN#_R 38 EC_SCI#/GPIO0E
2 8 PM_CLKRUN# CLKRUN#/GPIO1D
@ RC219 0_0402_5%
C187 68 NOVO# +1.8VS
DA0/GPIO3C NOVO# 36 VCIN1_BATT_TEMP
0.1U_0201_10V K X5R
1 1 DA Output EN_DFAN1/DA1/GPIO3D 70
TP_DISABLE# 36
1 2
@ESD@ KSI0 55 71 C189 100P_0402_50V8J
56 KSI0/GPIO30 DA2/GPIO3E 72 DGPU_PWR_EN 11,21,28 I2C2_SCL_SEN VCIN1_AC_IN
C188 KSI1 R222 1 2 1K_0402_5% 1 2
0.1U_0402_25V6 KSI1/GPIO31 DA3/GPIO3F USB_EN# 37 I2C2_SDA_SEN
KSI2 57 R223 1 2 1K_0402_5% C190 100P_0402_50V8J
2 KSI3 58 KSI2/GPIO32 83 I2C2_SCL_SEN
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A I2C2_SDA_SEN I2C2_SCL_SEN 11
KSI4 59 84
KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B EC_SMB_CK4 I2C2_SDA_SEN 11 +3VS
KSI5 60 85
KSI5/GPIO35 PSCLK2/GPIO4C EC_SMB_DA4 EC_SMB_CK4 29,35
KSI6 61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
EC_SMB_DA4 29,35 EC_SMB_CK4
KSI7 62 87 R220 1 2 1K_0402_5%
39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TAB_SW# USB_CHG_ILIM_SEL 37 EC_SMB_DA4
KSO0 R221 1 2 1K_0402_5%
KSO0/GPIO20 TP_DATA/GPIO4F TAB_SW# 29
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97
KSO3/GPIO23 ENKBL/GPXIOA00 ENBKL 6,29
KSO4 43 98
KSO4/GPIO24 WOL_EN/GPXIOA01 SYS_PWROK 10
KSO5/GPIO25 Int. K/B
KSO5 44 99
ME_EN/GPXIOA02 ME_EN 9
KSO6/GPIO26 Matrix
KSO6 45 109
VCIN0_PH1/GPXIOD00 VCIN0_PH1 46
KSO7 46
KSO7/GPIO27
KSO8 47
KSO8/GPIO28 SPI Device Interface
KSO9 48 119
KSO[0..15] 49 KSO9/GPIO29 MISO/GPIO5B 120 EC_SPI_MISO 8
KSO10
KSO[0..15] 36 KSO10/GPIO2A MOSI/GPIO5C EC_SPI_MOSI 8
KSO11 50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126
EC_SPI_CLK 8
KSI[0..7] KSO12 51 128
KSI[0..7] 36 52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# 8
KSO13
KSO13/GPIO2D
KSO14 53
KSO14/GPIO2E +3VALW
+3VALW_EC KSO15 54
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40
73
CUST_TEMP1 35 EC_MUTE#
81 74 R198 1 2 10K_0402_5%
36 KB_MUTLI_KEY GPU_PROHOT KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 SENSOR_EC_INT 11
R201 82 89
1 2 EC_SMB_CK1 21,35,47 GPU_PROHOT KSO17/GPIO49 GPIO50 90 EC_MUTE# 33
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# 36
2.2K_0402_5% 91
EC_SMB_CK1 CAPS_LED#/GPIO53 CAPS_LED# 36
R202
EC_SMB_DA1 42,46,47 EC_SMB_CK1 EC_SMB_DA1
77
EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54
92
PWR_LED# 36
1 2 78 93
42,46,47 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# 36
2.2K_0402_5% 79 95 SYSON
8,21,35 EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 SYSON 13,49
8,21,35 EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 VR_ON 52 KB_BL_PWM
+3VALW DPWROK_EC/GPIO59
127
AC_PRESENT 10,21
SM Bus

1
6 100 R325
KB_MUTLI_KEY 10 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 10
R217 1 2 10K_0402_5% 14 101 10K_0402_5%
37 USB_CHG_CTL1 GPIO07 GPXIOA04 3V/5VALW_PG 37,44,48,50
15 102 NOKBL@
10 EC_CLEAR_CMOS# 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103
PBTN_OUT# 37 USB_CHG_CTL3 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 VCOUT1_PROCHOT# 47
R395 1 @ 2 10K_0402_5% 17 104
37 USB_CHG_EN VCOUT0_MAIN_PWR_ON 48

2
18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 BKOFF# TBT@
37 USB_CHG_CTL2 GPIO0C BKOFF#/GPXIOA08 BKOFF# 29 PD_RESET
37 USB_CHG_STATUS#
19
AC_PRESENT/GPIO0D GPIO GPO GPXIOA09
106
PD_RESET 42
2 R219 1
25 107
36 KB_BL_PWM 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 EC_PCIE_WAKE# TS_DISABLE# 29
10K_0402_5%
35 EC_FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 EC_PCIE_WAKE# 34,39
29
35 EC_FAN_SPEED2 EC_TX FANFB1/GPIO15
30
34 EC_TX EC_RX 31 EC_TX/GPIO16 110 VCIN1_AC_IN @
34 EC_RX PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON VCIN1_AC_IN 47
32 112 R391
10 PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON 48 1 2
ON/OFF# 36 SUSP#
36 PWR_BATT_LOW# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW#
1 52 VR_PWRGD
36
NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04
115
LID_SW# 35
100P_0402_50V8J
C125 ESD@

116 SUSP# 100K_0402_5%

SUSP#/GPXIOD05 117 SUSP# 13,39,44,49
1 GPXIOD06
C123 ESD@
100P_0402_50V8J

118 PECI 1 2
2 PBTN_OUT# 122 PECI/GPXIOD07 H_PECI 6
R208 43_0402_1%
10 PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D
123 124 +V18R R209 1 2 0_0402_5% +3VALW_EC
2 10,47,49 PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2
1
+3VALW
AGND

C192
GND
GND
GND
GND
GND

4.7U_0402_6.3V6K

VCOUT1_PROCHOT# R204 1 2 0_0402_5%

2
+3VALW KB9022QD_LQFP128_14X14
113
11
24
35
94

69

SA000075S30 RHS1 R205 1 2 0_0402_5%

LID_SW# 52 VR_HOT# H_PROCHOT# 6
1 2
100K_0402_5%
ECAGND

R212 R392 1
1 @ 2 EC_PCIE_WAKE# TAB_SW# 1 2 @
1K_0402_5% C191
100K_0402_5% 47P_0402_50V8J
2
1
@ESD@ SYSON
C197
0.1U_0201_10V K X5R
2 @ESD@
C193
0.1U_0201_10V K X5R

+3VS

1 2 EC_FAN_SPEED1
R214 10K_0402_5%
1 2 EC_FAN_SPEED2
R213 10K_0402_5%

Compal Electronics, Inc.

GPU_PROHOT
Compal Secret Data
R389 1 DIS@ 2
10K_0402_5%
Security Classification
2017/5/3 2017/6/2
EC KB9022QD
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
LA-F661P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 45 of 61
 5 4 3 2 1

VMB
VMB2 EMI@ PL201 5A_Z80_0805_2P
1 2
JBAT201 PF201
1 1 2
1 2 +12.6V_BATT+
2 3 EC_SMCA 10A_24V_F1206HB10V024TM EMI@ PL202
3 4 EC_SMDA 1 2
4 5
5 6 5A_Z80_0805_2P
6 7
7 8
Vinafix.com

1
8 9

1
100_0402_1%

100_0402_1%
PC201 EMI@ PC202 EMI@
D GND 10 1000P_0402_50V7K 0.01U_0402_25V7K D
GND 11

2
GND 12

PR201

PR202
2

2
GND
SUYIN_125022HB008M200ZL
@CONN@

EC_SMB_CK1 42,45,47

EC_SMB_DA1 42,45,47
1 2
+3VLP
PR203
200K_0402_1%

1 2
VCIN1_BATT_TEMP 45,47
PR204
10K_0402_5%

@CONN@ +RTCBATT

ACES_50299-00501-003
7 EMI@ PL203
VIN
GND 6 5A_Z80_0805_2P
GND 1 2
+EC_VCCA

2
5 APDIN PF202 PR209
+CHGRTC
5 4 1 2 APDIN1 45.3K_0603_1%
4 3 EMI@
3 2 0437007.WR 7A 32V UL FAST PL204
2 1

16.5K_0402_1%
1 2 PR208

1
1

1
1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
C 1.5K_0603_5% C
JDCIN1
+3VLP

PR205
5A_Z80_0805_2P 1 2
PD201
1

1
EMI@ PC203

EMI@ PC204

EMI@ PC205

EMI@ PC206
S SCH DIO BAS40CW SOT-323
2

2
1 45 VCIN0_PH1
+RTCVCC
2

2
PR210 3
1K_0603_5%
+RTCBATT 2 1

1
100P_0402_50V8J
@ PR206 0_0402_5% PH201
ADP_ID_R 1 2 100K +-1% 0402 B25/50 4250K

PC209

2
2
ECAGND

1 2
+3VALW ADP_ID 45
680P_0603_50V7K

PR207
0.1U_0402_16V7K

750_0402_1%
1

1
PC207

PC208
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/07/27 2016/07/27
PWR- BATTERY CONN/OTP
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
SKL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 46 of 61
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D D

1
2 PQ301
G L2N7002WT1G_SC70-3
S B+

3
1 2 1 2

PR301 PR302
1M_0402_1% 3M_0402_5%
PQ302 +19V_P1 PQ303
EMB04N03H 1N EDFN5X6-8 AON7506_DFN33-8-5 PR303
1 1 +19V_P2 0.01_1206_1% +19VB_CHG
2 2
5 3 3 5 1 4
VIN

PC305 @EMI@

EMI@
2 3

2200P_0402_25V7K
10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V7K
CSIP_CHG_R
4

1
CSIN_CHG_R

PC302

PC303

PC304
@ PJP1
1 2

2
1 2
JUMP_43X118

1
2_0402_5%
1
0_0402_5%

PR305
1
287K_0402_1%

PR304
@
PR306

ASGATE_CHG_R

2
2
PC306
2

1 2 PQ304

4.02K_0402_1%

4.02K_0402_1%
AON7506_DFN33-8-5
1
0.1U_0402_25V6 2

1
5 3

C PR309 C
100_0402_1%

PC307 0.22U_0603_25V7K
2
+12.6V_BATT+

4
PR307

PR308
1 2

CMSRC_CHG @ PC308
1

2200P_0402_50V7K
49.9K_0402_1%

ASGATE_CHG
PR310

PC301

1 2

1
2

0.1U_0402_25V7K

BGATE_CHG
2

OPCN_CHG 2
CSIN_CHG
CSIP_CHG

OPCP_CHG

VBAT_CHG
1 VDD_CHG

5
PQ305
100K_0402_1%

PU301

30

29

25
32

31

28

27

26
AON7408L_DFN8-5
PR311

@ PR312 PC309 4

ASGATE

QPCP

BGATE
CSIP

CMSRC

OPCN

VBAT
CSIN
0_0603_5% 0.22U_0603_25V7K
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R
1 2
ACIN BOOT PR315
PL2
2

UG_CHG
+12.6V_BATT+
2 23 0.005_1206_1%
45 VCIN1_AC_IN @ ACOK UGATE 4.7UH_5.5A_20%_7X7X3_M

3
2
1
PR314 1 2 0_0402_5% 3 22 LX_CHG 1 2 +17.4V_BATT_CHG 1 4
42,45,46 EC_SMB_DA1 SDA PHASE
1
158K_0402_1%

@
LG_CHG
PR313

PR316 1 2 0_0402_5% 4 21 2 3
42,45,46 EC_SMB_CK1 SCL LGATE

10U_0603_25V6M
680P_0603_50V7K 4.7_1206_5%
@

1
VDDP_CHG

10U_0603_25V6M

10U_0603_25V6M
RF@ PR320

PC310
PR317 1 2 0_0402_5% 5 20 PQ306
PROCHOT# VDDP

5
45 VCOUT1_PROCHOT#
2

2 1K_0402_1%AMON_ISL95520 6 VDD_CHG

AON7752_DFN3X3EP8-5
PR318 1 19 1 2
45 ADP_I AMON VDD

1
PC311

PC312
PR321 1 2 1K_0402_1%BMON_ISL95520 7 18 PR319 4.7_0402_5%
45 DCHG_I

2
+3VS
BMON DCIN 4

2
1

1
Close to EC. 8 17 PC313 PC314
52 PSYS_MON NC NTC

BATGONE
1U_0402_16V6K 1U_0402_16V6K

RF@ PC315
B B
PR323
CCLIM

2
ACLIM
COMP
PROG
AGND

CSON

CSOP
FSET 100K_0402_1%

1
PC316 PC317 @

3
2
1

2
1

0_0402_5%

0.1U_0402_25V6 0.1U_0402_25V6 PD1

PR322

PR324 10_1206_5% 3
ISL88739AHRZ-T_QFN32_4X4
VIN
33

10

11

12

13

14

15

16
1

PR338 PR339 1 2 1
2

10K_0402_5% 10K_0402_5% Close to 2 PQ307

3
@VGA@ @VGA@
EC.
VF = 0.38V
2

2
FSET_CHG

PC318
1U_0603_25V6
S SCH DIO BAS40CW SOT-323 LMUN5113T1G_SOT323-3
PR326 2
2

21,35,45 GPU_PROHOT PR325 @ 0_0603_5%

1
1 2
VDD_CHG 10K_0402_1% +12.6V_BATT+
VDD=5V

1
@VGA@ @ PR327
VCOUT1_PROCHOT#

PQ315A D 1 2
BA
2
6

2 CCLIM_CHG

1
G 0_0603_5% 10,45,49 PM_SLP_S4# 2
ACLIM_CHG
200K_0402_1%

@VGA@ 2N7002KDW_SOT363-6
1

1
VCIN1_AC_IN

PQ314 S PR329
PROG_CHG CSOP_CHG CSOP_CHG_R
PR328

RUM001L02_VMT3 200K_0402_1% 1 2 PQ308

1
1

@VGA@

BA
PQ315B D COMP_CHG PR330 2_0402_5% LTC015EUBFS8TL_UMT3F

3
3

2 5
2

1
G PC319 BA
38.3K_0402_1%

2N7002KDW_SOT363-6 0.1U_0402_25V6
1

2 PR333 1
100_0402_1%

2
CSON_CHG CSON_CHG_R
PR332

1 2
4

560P_0402_50V7K
255K_0402_1%

PR334 0_0402_5%
3

1
PR335

@
PC320

2
1
169K_0402_1%

90W@ PR337
2
1

VCIN1_BATT_TEMP 45,46
0.015U_0402_25V7K

255K_0402_1% @
2

1
PR336

PC321
2

PC322
2

10P_0402_25V8J
2

A A

PR336 65W@
88.7K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/05 Deciphered Date 2014/12/15 Title
PWR_CHARGER
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 47 of 61
5 4 3 2 1
 A B C D E

Vinafix.com
1 1

B+ PU501
SY8286BRAC_QFN20_3X3 @ PR502 PC504
@ PJ505 0_0402_5% 0.1U_0201_10V6K
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2
1 2

2200P_0402_50V7K
JUMP_43X118

10U_0603_25V6M

10U_0603_25V6M
EMI@ PC501

EMI@ PC502
0.1U_0402_25V6
PL501

1
1.5UH_6A_20%_5X5X3_M

PC528

PC503

IN

IN

IN

IN

BS
LX_3V6 20 LX_3V 1 4
+3VALWP

2
LX LX
7 19 2 3
GND LX

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
4.7_1206_5%
8 18
+3VLP GND GND

1
PR503
RF@

PC505

PC506

PC507

PC508
9 17
PG LDO +3VLP

2
10 16
NC NC

1
PC509

3V_SN2
1
21 4.7U_0603_6.3V6M

OUT
EN2

EN1
GND

NC
PR501

FF

680P_0603_50V7K
100K_0402_5%

11

12

13

14

15

1
3.3V LDO 150mA~300mA

RF@
37,44,45,50 3V/5VALW_PG

PC510
2
2 ENLDO_3V5V PC511 PR504 2
1000P_0402_25V8J 1K_0402_1%
5V_3V_EN 3V_FB 1 2 3V_FB_1 1 2

@ PJ502
+3VALWP 1
1 2
2
+3VALW
JUMP_43X118

PJP502 @
JUMP_43X39
+3VLP 2
2 1
1
+3VL
@ PR505 PC512
0_0402_5% 0.1U_0201_10V6K
BST_5V 1 2 BST_5V_R 1 2
B+ +19VB_5V
EMI@
PL504
1 2 +19VB_5V

5A_Z80_0805_2P PU502
5

1
LX_5V

SY8288CRAC_QFN20_3X3
PL502

BS
IN

IN

IN

IN
6 20 3.3UH_6.3A_20%_7X7X3_M
LX LX
2200P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6

LX_5V
7
GND LX
19 1 4 +5VALWP
1

1
PC513

PC514

EMI@ PC515

@EMI@ PC516

8 18 2 3
3 GND GND PC517 3
VCC_5V 1

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
9 17 2
2

PG VCC

1
PR506

1
PR507

PC519

PC520

PC518

PC521

PC522

PC523
4.7_1206_5%
499K_0402_1% 10 16
5V_PGD

ENLDO_3V5V NC NC 2.2U_0402_6.3V6M
B+ 1 2

RF@

2
21 @
OUT

LDO
EN2

EN1

GND
1

@ PR509
FF
1

PR508 0_0402_5%

2
1

499K_0402_1% PC529 5V LDO 150mA~300mA

11

12

13

14

15

1U_0402_16V6K
3V/5VALW_PG

15V_SN
+5VLP
2

4.7U_0603_6.3V6M
2

680P_0603_50V7K
@ PR514
1

ENLDO_3V5V 1
PC524

PC525
RF@
0_0402_5%
5V_3V_EN
2

2
PR510 1 PR515 2
2.2K_0402_5% @ 0_0402_5%

45 EC_ON
1 2

@ 5VLDO_EN 45 PC526
1000P_0402_25V8J
PR512
1K_0402_1%

45 VCOUT0_MAIN_PWR_ON
PR511 1 2 0_0402_5% 5V_FB 1 2 5V_FB_1 1 2

5V_3V_EN
@ PJ504
+5VALWP 1
1 2
2
+5VALW
1M_0402_1%

4.7U_0402_6.3V6M
1

JUMP_43X118
1
PR513

PC527

4 @ PJP504 4
JUMP_43X39
+5VLP +VL
2

1 2
2

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/15 2012/07/11
+3VALW/+5VALW
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 48 of 61
A B C D E
 5 4 3 2 1

B+
EMI@
PL601
1 2 +12.6VB_DDR PR601
2.2_0603_5%

+1.2VP
5A_Z80_0805_2P BST_DDR_R 1 2 BST_DDR

10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6

10U_0603_25V6M
1

1
+0.6VSP

PC604
Vinafix.com UG_DDR

@EMI@ PC601

EMI@ PC602

PC603
2

2
D D
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
1
PC605

1
0.1U_0603_25V7K

5
PU601

PC606

PC607
16

17

18

19

20
2

2
21

VLDOIN
PHASE

VTT
UGATE

BOOT
PAD
PQ601 4 LG_DDR 15 1
LGATE VTTGND
AON7408L_DFN8-5
PL603 14 2
1UH_11A_20%_7X7X3_M PR602 PGND VTTSNS
11.8K_0402_1%

1
2
3
+1.2VP
1 4 1 2 CS_DDR 13 3
PC608 CS RT8207PGQW _W QFN20_3X3 GND
2 3 1U_0402_10V6K

1
1 2 12 4 VTTREF_DDR
VDDP VTTREF

5
RF@ PR603 PQ602 PR604
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

4.7_1206_5% AON7506_DFN33-8-5 5.1_0603_5%

1

+5VALW +1.2VP
1 2 VDD_DDR 11 5
PC609

PC610

PC611

PC612

PC613

PC614

VDD VDDQ

1 2

1
+5VALW PR605

PGOOD
4 PC616
2

RF@ PC615 0.033U_0402_16V7K

TON
1
680P_0402_50V7K PC617 1 2

FB
S5

S3

2
1U_0402_10V6K 5.1_0603_5%

6
10
VFB= 0.75v

1
2
3
C C
ILimit : 7.4A

EN_0.675VSP

FB_DDR
EN_DDR
TON_DDR
PR607
464Kohm-->540KHz 1 2 +1.2VP
PR608
+12.6VB_DDR1 2
6.04K_0402_1%
464K_0402_1%

1
PR609
@ PR610 10K_0402_1%
1 2
13,45 SYSON

2
0_0402_5%
@ PC618

1
0.1U_0402_10V7K

2
@ PR611
0_0402_5%
1 2 @ PJ601
13,39,44,45 SUSP# +1.2VP 1 2 +1.2V
1 2
+3VALW +5VALW @ PR606 JUMP_43X118
1 2
7 DDR_VTT_PG_CTRL
0_0402_5%

1
@ PC619
B 0.1U_0402_10V7K B
1

PC620 PJ604 @

2
1

1U_0402_6.3V6K 1 2
+0.6VSP +0.6VS
1

JUMP_43X79 1 2
@ PJ603 JUMP_43X39
2
2
2

PC621
1

4.7U_0603_6.3V6K G9661MF11U_SO8
4 5
VPP NC
+2.5VP
@ PR612 3 6
2

VIN VO PJ605
1 2 2 7 @
10,45,47 PM_SLP_S4# VEN ADJ
1 8 +2.5VP 1 2 +2.5V
GND

POK GND 1 2
1

0_0402_5%
3.4K_0402_1%

0.01U_0402_25V7K
1

PU602 JUMP_43X79
Rup
1

PR615
PR614

PC622

22U_0603_6.3V6M
0.1U_0402_16V7K

47K_0402_5%
PC623

1
2

PC624
2

2
1

1.6K_0402_1%

Rdown
PR616

A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

2012/12/31 Title

RT8207P
Issued Date 2010/07/20 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 49 of 61
5 4 3 2 1
 5 4 3 2 1

D
Vinafix.com D

+3VALW +5VALW

1
PC701

1
1U_0402_6.3V6K

1
JUMP_43X79
@ PJ701

2
2
2
C PC702 C

1
4.7U_0603_6.3V6K G9661MF11U_SO8
4 5 PJ702
PR701 @
VPP NC
+1.8VALWP
@ 0_0402_5% 3 6 +1.8VALWP 1 2 +1.8VALW

2
1 2 2 VIN VO 7 1 2
37,44,45,48 3V/5VALW_PG VEN ADJ
1 2 1 8 JUMP_43X79

GND
POK GND

12.7K_0402_1%
PR706

0.01U_0402_25V7K
1
PU701
Rup
1 100K_0402_5%

PR703

PC703

22U_0603_6.3V6M
@ PR704

0.1U_0402_16V7K

9
PC704
47K_0402_5%

1
2

2
+3VALW

PC705
@
2

2
1

10K_0402_1%
Rdown

PR705
51 +1.8VALW_PG

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/13 2012/06/13 Title
APL5930
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 50 of 61
5 4 3 2 1
 A B C D E

+3VALW @ PJ802
JUMP_43X118
1 2
+1.0VALWP 1 2 +1.0VALW
+19VB_1V
Vinafix.com

1
@ PR803 RF@ PR802 RF@ PC802
10K_0402_5% 4.7_1206_5% 680P_0603_50V7K
1 2 SNUB_1V 1 2
@ PJ804

B+
1 1
JUMP_43X118 PU801

2
1 2 +19VB_1V 2 9 @ PR804 PC805 Use 7x7x3 size when the layout space is enough.
1 2 IN PG 0_0402_5% 0.1U_0201_10V6K
3 1 BST_1V 1 2 BST_1V_R 1 2 PL801

+1.0VALWP

10U_0603_25V6M
0.1U_0402_25V6
IN BS 1UH_11A_20%_7X7X3_M

2200P_0402_50V7K
1

1
4 6 LX_1V 1 2

EMI@ PC801

EMI@ PC803

PC804
IN LX
5 19

2
IN LX

14K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1
7 20
R1
GND LX

1
PR805

PC806

PC807

PC808

PC809

PC810

@ PC827

@ PC828
8 14 FB_1V
GND FB

2
@ PR801 18 17 LDO_1V

2
0_0402_5% GND VCC
1 2 EN_1V 11 10
50 +1.8VALW_PG EN NC

1
ILMT_1V
PC811 FB=0.6V
13 12 2.2U_0402_6.3V6M
ILMT NC

1
@ PC812
R2

2
1

PR806
1M_0402_1%
0.1U_0402_25V6 +3VALW 15
BYP NC
16 PR807
20K_0402_1%
21
+3VALW
2

PAD

2
SY8288RAC_QFN20_3X3
2

1
PC813
1U_0402_6.3V6K
1

@ PR808

2
0_0402_5%
2
1

@ PR809
0_0402_5%

2 2
2

3 3

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10
Compal Electronics, Inc.
SY8286
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 51 of 61
A B C D E
 5 4 3 2 1

Vinafix.com
D D

PC901
PR901 100_0402_1% 1000P_0402_50V7K

+VCC_SA
1 2 1 2 PC902
0.01U_0402_25V7K PR902
1.5K_0402_1%
RDRPSP 1 2 1 2
COMP_1b
@ PR903 PR904
0_0402_5% 1.69K_0402_1% 1 2
1 2 VSPP_1b 1 2VSP_1b
13 VCCSA_SENSE PC903
100P_0402_50V8J

PC904

1
1000P_0402_50V7K
PR906
@ 1K_0402_1% PC905

2
1 2 VSNN_1b 1 2
13 VSSSA_SENSE 2200P_0402_50V7K

1
PR905 0_0402_5%
1 2
PR907 100_0402_1% PR908

2
1 2 10_0402_1%
PC906
2200P_0402_50V7K 1 2

1000P_0402_50V7K
47 PSYS_MON CSN_1b 53
PR911

19.6K_0402_1%
1

2
20K_0402_1%

+VCC_CORE

1
1 2 1 2

PR909

PC907
PH901
PR910 100_0402_1% 100K_0402_1%_NCP15WF104F03RC

0.01U_0402_25V7K
1

2200P_0402_50V7K
place close to SA chock

2
ILIM_1b
@

1 2
VSP_2ph

1
1 2

PC908

PC909
15 VCCCORE_SENSE
PR912 0_0402_5% PR913
12K_0402_1%
+3VS

2
PR914

1
PC910 PR918 54.9K_0402_1% 2 1 SW_1b 53 PR916

2
@ PR917 1000P_0402_50V7K 806_0402_1% 2 1 PR915 10K_0402_1%
1 2 VSNN_2ph 1 2
15 VSSCORE_SENSE PC911 7.5K_0603_1%

2
VSN_2ph

Iout_1b
0_0402_5% 470P_0402_50V7K
1 2
1 2 1 2
VR_PWRGD 45

1
PR919 PR920 PC912 @ PR921

+1.0V_VCCST
100_0402_1% 49.9_0402_1% 3300P_0402_50V7-K 1 2 VR_ON 45
0_0402_5%
close to the longer distance phase(81208 or 81210)
PWM_1b_SA 53

1K_0402_1%
C C

1
Alert,Data,Clk.

1 2
place close to IA chock

PR922
PH902 PC913
THERM_ 220K 5% 0402 470P_0402_50V7K
1 2 DRVON 53

110_0402_1%

100_0402_1%
45.3_0402_1%

0.1U_0402_16V7K
2

1
PR925
PU901

110_0402_1%
4.75K_0402_1%

470P_0402_50V7K

1
PR929

PC914

PR931
PR934

22.6K_0402_1%
2

1
PR932 PR928 NCP81218DMNTXG_QFN48_6X6 7.5K_0603_1%
1 2

PC915
88.7K_0603_1% 165K_0402_1% PC916 @

49

37
46
48
47

45
44

42
41
40
43

39
38
SWN_GT1 53

2
SW_1a 1 2 1 2 1 2 15P_0402_50V8J PR938
VR_HOT# 45

2
PR926

PR927

PR930
PR935 12K_0402_1%

TAB

PSYS

EN
CSP_1b
VSN_2ph

VSP_1b
VSN_1b
VSP_2ph

CSN_1b

IOUT_1b
VR_RDY
COMP_1b
ILIM_1b
1
PR933 49.9_0402_1% 1 2

1 1

1
IOUT_2ph 1 36 1 2
PR936 75K_0402_1% @ PC920

1000P_0402_50V7K
IOUT_2ph PW M_1b VR_SVID_CLK 15
88.7K_0603_1% 2 35 470P_0402_50V7K

2200P_0402_50V7K

0.022U_0402_25V7K
2
SW_2a DIFFOUT_2ph DRVON

1
1 2 3 34 1 2 1 2

PC918
PC917 PC919 SCLK PR939 VR_ALERT# 15
4 FB_2ph SCLK 33 0_0402_5%

PC921
820PF_0402_50V7K PR940 2200P_0402_50V7K ALERT# PR941

2
COMP_2ph ALERT#

1
1 2 5 32 110_0402_1%2

PC922
@ 16.9K_0402_1% SDIO VR_SVID_DATA 15 PR943 PH903
2

2
ILIM_2ph SDIO

1
PR942 6 31 1 2 69.8K_0402_1% 100K_0402_1%_NCP15WF104F03RC
10_0402_1% 7 CSCOMP_2ph VR_HOT# 30 IOUT_1a
PR944 100_0402_1% 2 1
1 2 8 CSSUM_2ph IOUT_1a 29 CSP_1a
53 CSN_1a

2
9 CSREF_2ph CSP_1a 28 1 2 CSN_GT1 53

2
10 CSP2_2ph CSN_1a 27 ILIM_1a
PR945
1 2 11 CSP1_2ph ILIM_1a 26 COMP_1a
PC925

PR947 10_0402_1%
0.1U_0402_16V7K
0.22U_0402_16V7K

TSENSE_2ph COMP_1a

ROSC_COREGT
1 2 0_0402_5% 1 2 12 25
0.1U_0402_16V7K

0.015U_0402_25V7K
53 CSN_2a

ADDR_VBOOT
VRMP VSN_1a
1

+19VB_CPU
100K_0402_1%_NCP15WF104F03RC

TSENSE_1ph
PC923

PC928
PR949 PC929

RSOC_SAUS

ICCMAX_2ph
ICCMAX_1a
ICCMAX_1b

1
PWM1_2ph
PWM2_2ph
PC924

PR946 1K_0402_1% PC930 2200P_0402_50V7K

36.5K_0402_1%
1

1
PWM_1a
10_0402_1% PC927 3300P_0402_50V7-K

VSP_1a
2

1
1 2
PH904

PR951
1000P_0402_50V7K PR954 PC926
61.9K_0402_1%

VCC

1 2

2
PC931 @ PR953 100_0402_1% 150P_0402_50V8J PC932
2

2
1 2 VSN_1a 1 2 1 2 2 1
53 SW_1a 0.01U_0402_50V7K 1000P_0402_50V7K

2
0_0402_5% place close to GTchock

13
14
15
16
17
18
19
20
21
22
23
24
2

1
PR950

PR948 PR952 VSSGT_SENSE 15 PR955

1
1.62K_0402_1% 499_0402_1% PC933 1000P_0402_50V7K 2.15K_0402_1%

2
53 SW_2a
1 2 PR958 3.32K_0402_1% @ PR959 OCP for GT

2
100度 place close to IA MOS

1 2 1 2 VCCGT_SENSE 15
PR956 0_0402_5%

+VCC_GT
VSP_1a 1 2 1 2 2 1
1.62K_0402_1%
PR962 PC934 PR960 PR961

+5VALW
1 2 1000P_0402_50V7K 3.09K_0402_1% 100_0402_1%

24K_0402_1%
1
2_0402_1%

29.4K_0402_1%
1

PR965
1 2

PR964
PR966
0_0402_5%

1
PC935

1
1U_0603_10V6K

1000P_0402_50V7K
2

PC936
PWM_1a_GT 53

61.9K_0402_1%
2

1
PH905

2
100K_0402_1%_NCP15WF104F03RC

place

PR967
FSW FOR GT AND IA close

2
FSW FOR SA
to GT high side

100K_0402_1%

97.6K_0402_1%

19.1K_0402_1%

35.7K_0402_1%
1

1
PR968

PR969

PR970

PR971
B B

2
PR857=97.6K in all platform
VBOOT PR858=19.1K in all platform

PWM2_2ph_IA 53

PWM1_2ph_IA 53

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NCP81205 H42
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Tuesday, October 17, 2017 Sheet 52 of 61
5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

EMI@
PL1005

B+
5A_Z80_0805_2P
1 2

+19VB_CPU
EMI@
1 2

+19VB_CPU
PL1006
PR1002 5A_Z80_0805_2P InputCapacitor:
0_0603_5% <BOM Structure>
10uF_0805_X5R_25V
HG1_VCORE_R InputCapacitor: PR1003
1 2 1 2HG2_VCORE_R
10uF_0805_X5R_25V 0_0603_5%

@EMI@ PC1004
2200P_0402_50V7K
PC1003

EMI@ PC1009

PC1005
<BOM Structure>
PR1004 <BOM Structure>
PC1002

0.1U_0402_25V6
2.2_0603_5% 0.22U_0603_16V7K PQ1002

10U_0603_25V6M

10U_0603_25V6M
2200P_0402_50V7K

1
1

2
1 2 1 2

EMI@ PC1006

@EMI@PC1007
PQ1001 1

0.1U_0402_25V6
1

PC1010

PC1008
PR1001 PC1001

10U_0603_25V6M

10U_0603_25V6M

D1
G1

AON6962_DFN5X6D-8-7
1

1
2.2_0603_5% 0.22U_0603_16V7K + PC1011

D1
G1

AON6962_DFN5X6D-8-7

2
1 2 1 2 33U_D1_25VM_R6M 7
7 D2/S1

2
D2/S1 2 <BOM Structure>
PU1002

(Common Part) +VCC_CORE

PU1001 1 9

G2

S2

S2

S2
BST FLAG
NCP81151MNTBG_DFN8_2X2
SH00001EF00 7*7*3

G2

S2

S2

S2
2 8 HG2_VCORE
52 PWM2_2ph_IA PL1002

3
PW M DRVH
(Common Part) +VCC_CORE
1 9 0.15UH_NA__35A_20%

3
BST FLAG 3 7 SW2_VCORE 1 4
2 8 HG1_VCORE SH00001EF00
PL1001 7*7*3 DRVON
EN SW
52 PWM1_2ph_IA
+5VALW
PW M DRVH 0.15UH_NA__35A_20% 4 6 2 3
3 7 SW1_VCORE 1 4 VCC GND
52 DRVON EN SW LG2_VCORE
5

RF@ PR1005
+5VALW
4 6 2 3 DRVL
VCC GND

4.7_1206_5%
LG1_VCORE

1
5 NCP81151MNTBG_DFN8_2X2 CSN_2a 52

<BOM Structure> PC1012

4.7U_0402_6.3V6M
DRVL
DCR=0.98m ohm +-5%

RF@ PR1006

2
1
Common part SH000011H00

4.7_1206_5%
1
CSN_1a 52

PC1013
4.7U_0402_6.3V6M
DCR=0.98m ohm +-5%

2
Common part SH000011H00 SW2_VCORE_SNB

680P_0402_50V7K
SW1_VCORE_SNB

1
SW_2a 52

RF@
680P_0402_50V7K

PC1014
1
RF@

2
SW_1a 52

PC1015
C C

2
+19VB_CPU
PR1007 PC1016
2.2_0603_5% 0.22U_0603_16V7K
1 2 1 2

@EMI@ PC1018

EMI@ PC1019
2200P_0402_50V7K
1

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6
33U_D1_25VM_R6M

PC1020

PC1021
1

1
PC1017
+

2
2

PU1003 PR1008
NCP81253MNTBG_DFN8_2X2 0_0603_5%
HG1_GT 2HG1_GT_R
1
BST DRVH
8 1 DCR=0.98m ohm +-5%
SW1_GT Common part SH000011H00
+VCC_GT
52 PWM_1a_GT
2 7
PW M SW
DRVON 3 6 PQ1003 PL1003
EN GND

2
0.15UH_NA__35A_20%

+5VALW
4 5 1 4 +VCC_GT

D1
G1

AON6962_DFN5X6D-8-7
VCC DRVL SW1_GT

PAD
7 2 3
D2/S1

1
CSN_GT1 52

9
PC1022
4.7U_0402_6.3V6M

G2

S2

S2

S2
2

RF@ PR1009
SWN_GT1 52

4.7_1206_5%
6

1
LG1_GT

+19VB_CPU

2
SW1_GT_SNB
2200P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

680P_0402_50V7K
EMI@ PC1026

1
RF@
@EMI@ PC1025
0.1U_0402_25V6
1

1
PC1023

PC1024

PC1027
PR1010 PC1028

2
2.2_0603_5% 0.22U_0603_16V7K
2

1 2 1 2

B HG_SA B

PU1004
NCP81253MNTBG_DFN8_2X2 PQ1005

+VCC_SA
PE642DT_PDFN8-10
4

1 8
BST DRVH
D1

D1

D1

G1

2 7 PL1004
52 PWM_1b_SA PW M SW SW_SA
10 9 1 4
DRVON 3 6 D1 D2/S1
EN GND 2 3
+5VALW
4 5
RF@ PR1011

VCC DRVL
G2

4.7_1206_5%
S2

S2

S2
PAD

0.47UH_NA__12.2A_20%
5

8
1

9
PC1029
4.7U_0402_6.3V6M

CSN_1b 52
2

SW_SA_SNB
SW_S A
680P_0402_50V7K

SW_1b 52
1
RF@

LG_SA
PC1030

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NCP81205_PowerStage
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Wednesday, October 18, 2017 Sheet 53 of 61
5 4 3 2 1
 D

0.1
Rev
PWR-PROCESSOR_DECOUPLING

61
of
54
Compal Electronics, Inc.

Sheet
+VCC_SA

PC11076
1U_0201_4V6M
Wednesday, October 18, 2017
1

1 2
+VCC_SA

PC11075
PC11049 1U_0201_4V6M
PC11023 22U_0603_6.3V6M
@

Document Number

22U_0603_6.3V6M 1 2
1 2 PC11074
1 2 PC11048 1U_0201_4V6M
22U_0603_6.3V6M
@

1 2
1 2 PC11073
PC11047 1U_0201_4V6M
22U_0603_6.3V6M
Date:
Title

1 2
Size

1 2 PC11072
PC11046 1U_0201_4V6M
C

22U_0603_6.3V6M
@

1 2
1 2 PC11071
PC11022 PC11045 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
1 2
PC11070
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

1 2 1 2
2016/07/27

PC11021 PC11044 1U_0201_4V6M

22U_0603_6.3V6M 22U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1 2
1 2 1 2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Deciphered Date
Compal Secret Data
2

2
+VCC_GT

2015/07/27
+VCC_GT

PC11020 PC11043 PC11069 PC11097 PC11109 PC11129 PC11153

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11019 PC11042 PC11068 PC11096 PC11108 PC11128 PC11152
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11018 PC11041 PC11067 PC11095 PC11107 PC11127 PC11151
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11017 PC11040 PC11066 PC11094 PC11106 PC11126 PC11150

Security Classification
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 0.47U_0201_4V6M 1U_0201_4V6M
@

Issued Date
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11016 PC11039 PC11065 PC11093 PC11125
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
PC11015 PC11038 PC11064 PC11092 PC11124
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
PC11014 PC11037 PC11063 PC11091 PC11123
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
3

3
1 2 1 2 1 2 1 2 1 2
PC11013 PC11036 PC11062 PC11090 PC11122
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
@

1 2 1 2 1 2 1 2 1 2
PC11012 PC11035 PC11061 PC11089 PC11121
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
@

1 2 1 2 1 2 1 2 1 2
PC11011 PC11034 PC11060 PC11088 PC11120
@

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC11105 0.47U_0201_4V6M

@

+
1

1 2 1 2 1 2 1 2 1 2
330U_D1_2VY_R9M
+VCC_CORE

Vinafix.com

PC11010 PC11033 PC11059 PC11087 PC11119 PC11139 PC11149 PC11155 PC11156 PC11166
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
+VCC_CORE
4

4
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11009 PC11032 PC11058 PC11086 PC11118 PC11138 PC11148 PC11154 PC11157 PC11167
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11008 PC11031 PC11057 PC11117 PC11137 PC11147 PC11158 PC11168
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC11079 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

@
1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11007 PC11030 PC11056 1 2 PC11116 PC11136 PC11146 PC11159 PC11169
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC11078 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

@
1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11006 PC11029 PC11055 1 2 PC11115 PC11135 PC11145 PC11160 PC11170
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PC11077 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

@
1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11005 PC11028 PC11054 1 2 PC11114 PC11134 PC11144 PC11161 PC11171
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

@
PC11099
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11004 PC11027 PC11053 PC11113 PC11133 PC11143 PC11162 PC11172

+
1

2
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 330U_D1_2VY_R9M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
@

@
1 2 1 2 1 2 PC11098 1 2 1 2 1 2 1 2 1 2
PC11003 PC11026 PC11052 PC11112 PC11132 PC11142 PC11163

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M

+
1

2
330U_D1_2VY_R9M
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11002 PC11025 PC11051 PC11111 PC11131 PC11141 PC11164
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M
@
1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC11001 PC11024 PC11050 PC11110 PC11130 PC11140 PC11165
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 10U_0402_6.3V6M

@
1 2 1 2 1 2 1 2 1 2 1 2 1 2
5

5
D

A
 5 4 3 2 1

+3VS +3VS

PSI pull high on HW side RV4 VGA@ VGA@

1
PR1202 PR1203 +5VS
+1.8VS 4.7K_0402_5% 4.7K_0402_5%
VGA@
Vinafix.com 1.8V EN is DGPU_PWR_EN PR1211
150K_0402_5%
VGA@
PR1206

PR1201 10K_0402_5%

1
1 2 2_0603_5%

1
PR1204

10K_0402_5%
D D
0_0402_5% VGA@
+3VS @VGA@ VGA@ PR1207

@VGA@
PR1205
PC1201
0_0402_5%

VGA@

2
1 2 1 2 VGA@ PR1208
21 VGA_CORE_EN

2
1
51_0402_5%
21 DGPU_PSI
@VGA@ PR1210 1 2
1 2 1U_0402_6.3V6K 1 2
VSSSENSE_VGA 23,25
0_0402_5%
21 VGA_CORE_PG
PR1209 0_0402_5% VGA@ VGA@ PC1202

2
1000P_0402_50V7K 1 2
+VGA_CORE

1
VGA@ PR1213 0_0402_5% @VGA@ PR1214 VGA@ PR1212 51_0402_5%
1 2 1 2
21 DGPU_VID VCCSENSE_VGA 23,25

2
R1
0_0402_5%
1 2 1 2
Place close to
PC1203 4700P_0402_50V7K
R3 PR1215 6.19K_0402_1%
GPU pins

276_VID_BUFF
@VGA@

R5 R4
VGA@
PR1216 PR1217 20.5K_0402_1%
4.32K_0402_1%1 2276_VREF VGA@ PC1204 47P_0402_50V8J VGA@ PC1205 VGA@ PR1220

R2 1 2 1 2276_DIFF_R
1 2

276_VCC
VGA@ PR1218 VGA@ PR1219 VGA@

276_VSN

276_VSP
1 2 1 2 VGA@

2
VGA@ 330P_0402_25V8J 49.9_0402_1%
309_0402_1% 16.5K_0402_1%

C1
VGA@ VGA@
PC1208
PU1201 PR1221
2 1 2 276_FB_R1 2 1 2

40

39

38

37

36

35

34

33

32

31
+19VB_GPU VGA@ PR1223
1K_0603_1% VGA@ PC1206 4700P_0402_50V7K 2200P_0402_25V7K 3.3K_0402_1% PR1222 1K_0402_0.5%

PWM_VID

PGOOD

PSI

EN

SCL

VSN
VCC
VID_BUFF

VSP
SDA
1 2 276_REFIN 1 30 276_COMP VGA@
VGA@ PC1207 0.01U_0402_16V7K REFIN COMP
VGA@ PC1209 1 2 276_VREF 2 29 276_FB
0.01U_0603_25V7K VREF FB
1 2 276_VRMP 3 28 276_DIFF
VRMP DIFF VGA@ PR1224 20K_0402_1%
276_SS 4 27 276_FSW 1 2 VGA@ PC1210 1000P_0402_25V8J
SS FSW 1 2
276_OCP 5 26 1 2
OCP LLTH/I2C_ADD VGA@ PR1225 23.2K_0402_1% VGA@ PR1226 24.9K_0402_1%
C C
276_LPC1 6 25 276_IOUT 1 2
LPC1 NCP81276MNTXG_QFN40_5X5 IOUT
276_LPC2 7 24 276_ILIM 1 2
LPC2 ILIM VGA@ PR1227 12.4K_0402_1%
8 23 276_CSCOMP
PWM4/PHTH1 CSCOMP
9 22 276_CSSUM

75K_0402_1%
56 276_PWM3 PWM3/PHTH2 CSSUM VGA@

1
10 21 PH1201

560P_0402_50V7K
PWM1/PHTH4

220P_0402_50V8J
56 276_PWM2 PWM2/PHTH3 CSREF

1
220K_0402_5%_B25/50 4700K
41
GND

DRON

CSP4

CSP3

CSP2

CSP1

2
1
276_CSSUM_R

VGA@
VGA@

NC

NC

NC

NC

PR1228
2
1

PC1211
Place close to
PR1235

P1 Inductor
VGA@

0.1U_0402_25V7K
PR1229

VGA@ PR1230

VGA@ PR1231

VGA@ PR1232

PR1233
10K_0402_5%

33K_0402_5%

2
11

12

13

14

15

16

17

18

19

20

1
26.1K_0402_1%

54.9K_0402_1%

54.9K_0402_1%

1K_0402_5%
1K_0402_5%

VGA@
PR1234

1
PC1212 0.068U_0402_16V7K PR1236
1 2
@VGA@

PC1213

PC1214
165K_0402_1%
2

2
276_CSP3

276_CSP2

276_CSP1
VGA@
@VGA@

PR1237 100K_0402_1% @VGA@

@VGA@

1 2 VGA@ VGA@
56 276_PWM1

2
VGA@ PC1215 0.068U_0402_16V7K VGA@
PR1238 1 2
1

1K_0402_1% VGA@ PR1239 200K_0603_1%

PR1240 100K_0402_1% @VGA@ 1 2
56 276_DRON 276_SWN1 56
1 2
VGA@ PR1241 200K_0603_1%
+5VS PC1216 0.068U_0402_16V7K VGA@ 1 2
276_SWN2 56
2

1 2
VGA@ PR1242 200K_0603_1%
PR1243 100K_0402_1% @VGA@ 1 2
1 2 276_SWN3 56

PR1245 2.32K_0402_1% VGA@

PR1246 2.32K_0402_1% VGA@

B B

1
PR1244 2.32K_0402_1%
1
VGA@

2
2

56
276_CSREF
276_SWN3

276_SWN2

276_SWN1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

VGA_CORE
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 55 of 61
5 4 3 2 1
 5 4 3 2 1

+19VB_GPU

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
VGA@ PC1304

VGA@ PC1305

VGA@ PC1306

VGA@ PC1307
2200P_0402_50V7K

0.1U_0402_25V7K
1

1
VGA_EMI@
PL1301
5A_Z80_0805_2P

2
1 2

PC1302

PC1303
B+
VGA_EMI@
1
PL1302
2

5A_Z80_0805_2P
+19VB_GPU
Vinafix.com VGA_EMI@ VGA_EMI@

D D

VGA@
PR1302

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
1 2HG_VGA2_R

VGA@ PC1309

VGA@ PC1310

VGA@ PC1311

VGA@ PC1312
2200P_0402_50V7K

0.1U_0402_25V7K
1

1
0_0603_5%

2
PC1301

PC1308
PQ1302

2
VGA_EMI@ VGA_EMI@ VGA@ PR1303 VGA@ PC1313 VGA@ VGA@ PL1303
2.2_0603_5% 0.22U_0603_16V7K

G1

D1

AON6962_DFN5X6D-8-7
BST_VGA2 1 2 1 2 0.15UH_NA__35A_20%
VGA@ PR1301 7
1 2HG_VGA1_R D2/S1 NVVDD_LX2 1 4
+VGA_CORE
0_0603_5% VGA@ PU1302 2 3
NCP81151MNTBG_DFN8_2X2

G2

S2

S2

S2
VGA_RF@ VGA@ PR1304

1
1 9 PR1306 1 2

3
BST FLAG 276_CSREF 55
4.7_1206_5%
PQ1301 VGA@ 2 8 HG_VGA2 10_0402_1%
55 276_PWM2 PWM DRVH
1

2
VGA@ PR1305 VGA@ PC1315 VGA@
PL1304 276_DRON 3 7 NVVDD_LX2
2.2_0603_5% 0.22U_0603_16V7K
G1

D1

2
EN SW

AON6962_DFN5X6D-8-7
BST_VGA1 1 2 1 2 NVVDD_LX1 1 4 NVVDD_LX2_SNB

+5VS
7 +VGA_CORE 4 6 276_SWN2 55
D2/S1 2 3 VCC GND

680P_0402_50V7K
VGA@ 5 LG_VGA2

VGA_RF@
DRVL

1
VGA@ PU1301 0.15UH_NA__35A_20% PR1307

PC1314
1
NCP81151MNTBG_DFN8_2X2 1 2 276_CSREF
G2

S2

S2

S2
VGA_RF@

PC1316
4.7U_0402_6.3V6M

2
1
1 9 PR1308 10_0402_1%
6

2
BST FLAG
4.7_1206_5%
2 8 HG_VGA1
55 276_PWM1 PWM DRVH
C C
3 7 NVVDD_LX1 276_SWN1 55

VGA@
55 276_DRON
2
EN SW NVVDD_LX1_SNB

+5VS 4
VCC GND
6
680P_0402_50V7K

5 LG_VGA1
DRVL
1
VGA_RF@
1

PC1317
PC1318
4.7U_0402_6.3V6M

2
2

VGA@

+19VB_GPU

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
VGA@ PC1321

VGA@ PC1322

VGA@ PC1323

VGA@ PC1324
2200P_0402_50V7K

0.1U_0402_25V7K
1

1
B B

2
PC1319

PC1320
VGA_EMI@ VGA_EMI@

VGA@ PR1309
1 2HG_VGA3_R

0_0603_5% used 0.15UH 7*7*3

PQ1303

2
VGA@ PR1310 VGA@ PC1325 VGA@
2.2_0603_5% 0.22U_0603_16V7K

G1

D1

AON6962_DFN5X6D-8-7
BST_VGA3 1 2 1 2 VGA@
7 0.15UH_NA__35A_20%
PL1305
D2/S1 NVVDD_LX3 1 4
+VGA_CORE
VGA@ PU1303 2 3
NCP81151MNTBG_DFN8_2X2

G2

S2

S2

S2
VGA_RF@ VGA@ PR1311

1
1 9 PR1312 1 2 276_CSREF
6

3
BST FLAG
4.7_1206_5%
2 8 HG_VGA3 10_0402_1%
55 276_PWM3 PWM DRVH
276_DRON 3 7 NVVDD_LX3

2
EN SW NVVDD_LX3_SNB

+5VS 4 6 276_SWN3 55
VCC GND
5 LG_VGA3
DRVL

1
PC1326
VGA_RF@

680P_0402_50V7K
1

PC1327

A A
4.7U_0402_6.3V6M

2
2

VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

VGA_CORE
Issued Date 2012/04/19 Deciphered Date 2015/04/19 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 56 of 61
5 4 3 2 1
 D

0.1
Rev

61
of
Compal Electronics, Inc.

57
VGA_CORE
Sheet
VGA DECOUPLING
1

1
W ednesday, October 18, 2017
Document Number

Date:
Title

Size
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2016/09/18

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2

2
Deciphered Date
Compal Secret Data
PC1461
VGA@
+
1

330U_D1_2VY_R9M
PC1460
VGA@
+
1

330U_D1_2VY_R9M

2015/09/18
PC1425
VGA@

PC1438
VGA@

1U_0402_6.3V6K
+
1

330U_D1_2VY_R9M
PC1424
VGA@

1 2
PC1437
VGA@
3

3
1U_0402_6.3V6K
+
1

330U_D1_2VY_R9M
PC1459

VGA@
1 2
PC1423 PC1436 10U_0603_6.3V6M
VGA@

4.7U_0603_6.3V6K 1U_0402_6.3V6K
VGA@

Security Classification
1 2
PC1448 PC1458

VGA@

VGA@
1 2 1 2
PC1422 PC1435 10U_0603_6.3V6M 10U_0603_6.3V6M
VGA@

Issued Date
PC1411 4.7U_0603_6.3V6K 1U_0402_6.3V6K
VGA@

10U_0603_6.3V6M
VGA@

1 2 1 2
1 2 1 2 PC1447 PC1457
PC1434 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@

VGA@
1 2
PC1410 PC1421 1U_0402_6.3V6K
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@

1 2 1 2
1 2 PC1446 PC1456
PC1433 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@

VGA@
1 2 1 2
PC1409 PC1420 1U_0402_6.3V6K
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@

1 2 1 2
1 2 PC1445 PC1455
PC1432 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1408 PC1419 1U_0402_6.3V6K

VGA@
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@

1 2 1 2
1 2 PC1444 PC1454
PC1431 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1407 1U_0402_6.3V6K

VGA@
PC1418
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@

1 2 1 2
1 2 PC1443 PC1453
PC1430 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1406 1U_0402_6.3V6K

VGA@
PC1417
Vinafix.com

10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@

1 2 1 2
1 2 PC1442 PC1452
PC1429 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
4

4
1 2 1 2
PC1405 1U_0402_6.3V6K

VGA@
PC1416
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@
1 2 1 2
1 2 PC1441 PC1451
PC1428 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1404 1U_0402_6.3V6K

VGA@
PC1415
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@
1 2 1 2
1 2 PC1440 PC1450
PC1427 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1403 1U_0402_6.3V6K

VGA@
PC1414
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@
1 2 1 2
1 2 PC1439 PC1449
PC1426 10U_0603_6.3V6M 10U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
PC1402 1U_0402_6.3V6K

VGA@
PC1413
10U_0603_6.3V6M 22U_0603_6.3V6M
VGA@

VGA@
1 2 1 2
1 2
1 2 1 2
PC1401 PC1412

+VGA_CORE
10U_0603_6.3V6M 22U_0603_6.3V6M

VGA@

VGA@
1 2 1 2
+VGA_CORE
5

5
D

A
 A B C D E

@ PJ1502
JUMP_43X118
1 2
+1.5VGSP 1 2 +1.5VGS

Vinafix.com
1 1

B+

PJ1501
+19VB_1.5VGSP 2 1
2 1

JUMP_43X79

10U_0603_25V6M
10U_0603_25V6M

10U_0603_25V6M

0.1U_0402_25V6
2200P_0402_50V7K
1

1
@

PC1513

PC1502

@VGA_EMI@ PC1504
21 1.5VS_DGPU_PG

PC1503

PC1505
VGA_EMI@
2

2
+3VS
VGA@ PR1501 VGA@ VGA@ VGA@
1 2
10K_0402_5%
@VGA@ PR1502 VGA@ PC1506
PD1501 VGA@ VGA@ 0_0603_5%
1 2 PU1501 0.1U_0603_25V7K
7*7*3

2
VGA@ PR1503 1 10 BST_1.5VGSP 1 2 1 2 PQ1501
RB751V-40_SOD323-2 48.7K_0402_1% PGOOD BOOT

G1

D1
PR1504 VGA@ 1 2ILMT_1.5VGSP 2 9 HGATE_1.5VGSP VGA@ PL1501

+1.5VGSP
CS UGATE

AON6994_DFN5X6D-8-7
12K_0402_5% 7 LX_1.5VGSP 0.82UH PCMC063T-R82MN 13A_20%
2 1 EN_1.5VGSP 3 8 LX_1.5VGSP D2/S1 1 2
21 1.5VSDGPU_PWR_EN EN PHASE

+5VALW
4 7
@VGA@ FB VCC
VGA@ PC1501

G2
S2

S2

S2
0.1U_0402_16V7K

330U_B2_2.5VM_R9M
1

5 6 LGATE_1.5VGSP
1 1

330U_B2_2.5VM_R9M
1M_0402_1% RF LGATE

1
PR1506

6
PR1505 11 + +

VGA@ PC1507
4.7_1206_5%
2

TP

VGA@ PC1511
VGA_RF@

1
RT8237EZQW2_WDFN10_3X3

LGATE_1.5VGSP
2

2 PR1507 VGA@ 2 2 2

2
1

SNB_1.5VGSP
470K_0402_1% PC1508 VGA@

1
VGA@ 1U_0603_6.3V6M VGA@ PR1508
100_0402_1%
2

2
PC1512 VGA@ PR1515 VGA@

2
680P_0402_50V7K 49.9_0402_1%

1
1 2 1 2 PC1509
680P_0603_50V7K
VGA_RF@

2
VGA@ PR1510
1

1.5VGSP_FB 2 1 1 2
PR1509 FB_VDDQ_SENSE 24
90.9K_0402_1% 18.2K_0402_1% @VGA@ PR1511 0_0402_5%
1

@VGA@
2

@VGA@ PR1512
D
PR1513 PQ1502 20K_0402_1%
1

1 2 2
21 VRAM_VDD_CTL G L2N7002WT1G_SC70-3 VGA@
2

0_0402_5% S
1

PR1514
3

10K_0402_1%
PC1510
0.1U_0402_16V7K
1

VGA@

@VGA@
2

VGA@

3 3

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10
Compal Electronics, Inc.
SY8286
Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 18, 2017 Sheet 58 of 61
A B C D E