INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

Unit 3
Introduction to Digital Systems

 Number System and Number Base Conversion

A number system represents quantities using specific symbols. The base (or radix) of a number system
indicates the number of unique digits or symbols used in that system. For example, the decimal system has a
base of 10 because it uses ten digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
1. Binary Number System:
A binary number system is a code that uses only two basic symbols. The digits can be any two distinct
characters, but it should be 0 or 1. The binary equivalent for some decimal numbers are given below
Decimal: 0 1 2 3 4 5 6 7 8 9 10 11
Binary: 0 1 10 11 100 101 110 111 1000 1001 1010 1011
Each digit in a binary number has a value or weight. The LSB (Least Significant Bit) has a value of 1. The
second from the right has a value of 2, the next 4 etc.
16 8 4 2 1
24 23 22 21 20
1.1 Binary to Decimal Conversion:
(1001)2 = 𝑋10
1001 = 1 × 23 + 0 × 22 + 0 × 21 + 1 × 20 = 8 + 0 + 0 + 1
(1001)2 = (9)10
Fractions: For fractions the weights of the digit positions are written from right of the binary point and weights
are given as follows. 2−1 2−2 2−3 2−4 2−5

Ex. (0.0110)2 = 𝑋10 = 0 × 2−1 + 1 × 2−2 + 1 × 2−3 + 0 × 2−4

= 0 × 0.5 + 1 × 0.25 + 1 × 0.125 + 0 × 0.0625 = (𝟎. 𝟑𝟕𝟓)𝟏𝟎
Ex. (1011.101)2 = 𝑋10 = 1 × 23 + 0 × 22 + 1 × 21 + 1 × 20 + 1 × 2−1 + 0 × 2−2 + 1 × 2−3.
= 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125 = (𝟏𝟏. 𝟔𝟐𝟓)𝟏𝟎
1.2 Decimal to Binary Conversion:
In this method, the decimal number is divided by 2 progressively and the remainder is written after each
division. Then the remainders are taken in the reverse order to form the binary number.
Ex. (12) 10 = 𝑋2 Ex. (21)10 = 𝑋2

Fractions:
The fraction is multiplied by 2 and the carry in the integer position is written after each multiplication. Then
they are written in the forward order to get the corresponding binary equivalent.
Ex. (0.4375)10 = 𝑋2

2. Octal Number System:

Octal number system has a base of 8 i.e., it has eight basic symbols. First eight decimal digits 0,1,2,3,4,5,6,7
are used in this system.
2.1 Octal to Decimal Conversion:
In the octal number system each digit corresponds to the powers of 8. The weight of digital position in
octal number is as follows:
84 83 82 81 80 8−1 8−2 8−3
To convert from octal to decimal, multiply each octal digit by its weight and add the resulting products.
Ex. (50)8 = 𝑋10

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50 = 5 × 81 + 0 × 80 = 40 + 0 = 40
(𝟓𝟎)𝟖 = (𝟒𝟎)𝟏𝟎
Ex. (22.34) 8 = 𝑋10
(22.34)8 = 2 × 81 + 2 × 80 + 3 × 8−1 + 4 × 8−2 = 16 + 2 + 3 × 1/8 + 4 × 1/64 = (18.4375)
(𝟐𝟐. 𝟑𝟒)𝟖 = (𝟏𝟖. 𝟒𝟑𝟕𝟓)𝟏𝟎
2.2 Decimal to Octal Conversion:
Here the number is divided by 8 progressively and each time the remainder is written and finally the
remainders are written in the reverse order to form the octal number. If the number has a fraction part, that
part is multiplied by 8 and carry in the integer part is taken. Finally, the carries are taken in the forward order.
Ex. (19.11) 10 = 𝑋8

(19.11)10 = (𝟐𝟑. 𝟎𝟕𝟎𝟐𝟒)𝟖

2.3 Octal to Binary Conversion:
Since the base of octal number is 8, i.e., the third power of 2, each octal number is converted into its
equivalent binary digit of length three.
Ex. (57.127)8 = 𝑋2

2.4 Binary to Octal Conversion:

The given binary number is grouped into a group of 3 bits, starting at the octal point and each group is
converted into its octal equivalent.
Ex.: (1101101.11101)2 = 𝑋8

3. Hexadecimal Number System:

The hexadecimal number system has a base of 16 . It has 16 symbols from 0 through 9 and A through F.
Decimal Hexadecimal Binary Decimal Hexadecimal Binary
0 0 0000 8 8 1000
1 1 0001 9 9 1001
2 2 0010 10 A 1010
3 3 0011 11 B 1011
4 4 0100 12 C 1100
5 5 0101 13 D 1101
6 6 0110 14 E 1110
7 7 0111 15 F 1111
3.1 Binary to Hexadecimal Conversion:
The binary number is grouped into bits of 4 from the binary point then the corresponding hexadecimal
equivalent is written. Ex. (100101110.11011)2 = 𝑋16
0001 0010 1110 . 1101 1000
1 2 E . D 8
(100101110.11011)2 = (𝟏𝟐E.D𝟖)𝟏𝟔
3.2 Hexadecimal to binary:
Since the base of hexadecimal number is 16, i.e., the fourth power of 2, each hexadecimal number is
converted into its equivalent binary digit of length four.
Ex. (5D.2A )16 = 𝑋2 5D.2A
01011101.00101010
(5D. 2 A)16 = (01011101.00101010)2

3.3 Decimal to hexadecimal:

The decimal number is divided by 16 and carries are taken after each division and then written in the reverse
order. The fractional part is multiplied by 16 and carry is taken in the forward order.
Ex. (2479.859)10 = 𝑋16

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3.4 Hexadecimal to decimal:

Each digit of the hexadecimal number is multiplied by its weight and then added.
Ex. (81.21)16 = 𝑋10 = 8 × 161 + 1 × 160 + 2 × 16−1 + 1 × 16−2.
1
= 8 × 16 + × 1 + 2/16 + 1/16 2 = (129.1289)10
2
(81.21)16 = (129.1289)10
Binary Arithmetic operations.
1. Binary Addition:
To perform the binary addition we have to follow the binary addition rule given below.
0+0 = 0 0+1 = 1
1+0 = 1 1 + 1 = 0 plus a carry-over of 1
Carry-overs are performed in the same manner as in decimal arithmetic. Since 1 the largest digit in the
binary system, any sum greater than 1 requires that a digit be considered over.
Ex. 111 1010 11.01
+110 +1101 +101.11
1101 10111 1001.00
2. Binary Subtraction:
To perform the binary subtraction the following binary subtraction rule should be followed.
0−0= 0 1−0 = 1
1−1= 0 0 − 1 = 1 with a borrow of 1
Ex. 111 110.01
− 010 − 100.10
101 001.11
3. Binary multiplication:
The rule for binary multiplication is given below
0×0 = 0 0×1 = 0
1×0 = 0 1×1 = 1
Ex. 1011 × 110 1011 × 110 Ex: 101.01 × 11.01 01.01 × 11.01
0000 10101
1011 00000
1011 10101
1000010 10101
4. Binary division: 10001.0001
The table for binary division is as follows. 0÷1 =0 1÷1= 1
As in the decimal system division by zero is undefined.
Ex

 Complements
Complements are used in digital computers to simplify subtraction and perform logical operations. Each
number system with base r has two types of complements. When the base r is specified, the complements
are named accordingly. The complements are classified as follows:
 Radix complement (or) r's complement - {N = rn – N}
 Diminished Radix complement (or) (r - 1) s complement – {N = (rn -1) – N}

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The table describes the types of complements used in different number systems:
Number Base Radix Complement (r's Diminished Radix Complement ((r-1)'s
System (𝒓) Complement) Complement)
Binary 𝑟=2 2's complement 1's complement
Octal 𝑟=8 8's complement 7's complement
Decimal 𝑟 =10 10's complement 9's complement
Hexadecimal 𝑟 =16 16's complement 15's complement
1's complement
To obtain 1's complement of a binary number, each bit of the number is subtracted from 1. Thus 1's
complement of a binary number is the number that results when we change each 0 to a 1 and each 1 to a 0.
Ex. Binary number 1's Complement
0101 1010
1001 0110
1101 0010
0001 1110
1's complement subtraction steps:
1. Write the first number (minuend) as such.
2. Write the 1's complement of second number (subtrahend).
3. Add the two numbers.
4. The carry that arises from the addition is said to be "end around carry".
5. End-around carry should be added with the sum to get the result.
6. If there is no end around carry array find out the 1's complement of the sum and put a negative sign in front
of the result as the result is negative.
Ex.

If there is no carry in the 1's complement subtraction, it indicates that the result is negative and number will
be in its 1's complement form. So complement it to get the final result.
2's complement
2's complement results when we add '1' to 1's complement of the given number i.e., 2’s complement = 1 's
complement +1
Ex. Binary Number 1's complement 2's complement
1010 0101 0110
0101 1010 1011
1001 0110 0111
0001 1110 1111
2's complement subtraction steps:
1. Write the first number (minuend) as such.
2. Write the 2 's complement of the second number (subtrahend).
3. Add the two numbers.
4. If there is a carry; discard it and the remaining part (sum) will be the result (positive).
5. If there is no carry, find out the 2 's complement of the sum and put negative sign in front the result as the
result is negative.
Ex. (i).

(ii).

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Question 01: Use the 2's complement and subtract i) 111012 -11012 ii) 11012 -111012
Solution:
Steps Solution i : 111012 − 11012 Solution ii : 11012 − 111012
Step 1: Minuend: 111012 (5 digits) Minuend: 11012 (4 digits) → Add leading 0
Equalizing Subtrahend: 11012 (4 digits) → Add leading 0 Subtrahend: 111012 (5 digits)
Digits Equation: 111012 − 011012 Equation: 011012 − 111012
Step 2: 2's 1's Complement of 011012 : 10010 1's Complement of 111012 : 00010
Complement of + 1 + 1
Subtrahend 2's Complement of 011012 : 10011 2's Complement of 111012 : 00011
Step 3: Add 111012 011012
Minuend and 2's + 100112 +000112
Complement = 1000002 = 100002
Step 4: Discard/ Since a carry is produced, discard it. No carry is produced ( M < S ). Find 2's
Carry Final Answer: 𝟏𝟎𝟎𝟎𝟎𝟐 Complement of result.
Step 5: Find 2's Not needed ( M > S ). 1's Complement of 100002 : 01111
Complement (If 2's Complement of 100002 : 10000
M < S) Final Answer: −𝟏𝟎𝟎𝟎𝟎 𝟐
Just as we calculated 1’s complement and 2’s complement for the binary number system, we can
determine complements for other number systems using the same approach. The diminished radix
complement (like 7’s, 9’s, and 15’s complement) is found by subtracting each digit from the highest
possible value in that base (i.e., r −1), similar to how 1’s complement is found by inverting the bits in
binary. The radix complement (like 8’s, 10’s, and 16’s complement) is obtained by adding 1 to the
diminished radix complement, just as 2’s complement is found by adding 1 to the 1’s complement in binary.
This method applies consistently across octal, decimal, and hexadecimal number systems, making
subtraction and logical operations more efficient.
Question 02: Find 8’s complement of i) (67123)8 ii) (235400)8
Solution: i) The 7’s complement of 67123 is found by subtracting each digit from 7, giving 10654.
The 8’s complement is simply the 7’s complement + 1, so 10654 + 1 = 10655. Ans.
ii) The 7’s complement of 235400 is found by subtracting each digit from 7, giving 542377.
The 8’s complement is simply the 7’s complement + 1, so 542377 + 1 = (542378)8. Ans.
Question 03: Using the 9’s complement, substrate (3250)10 – (72532)10
Solution: The 9’s complement of 72532 is found by subtracting each digit from 9, giving 27467.
Adding this to 3250 (written as 03250 for equal digits), we get 30717.
Since there is no carry, take the 9’s complement of 30717, which is 69282, and add a negative sign.
Hence (-69282)10 Ans.
Question 04: Find 10’s complement of i) (467)10 ii) (7892)10 iii) (70042)10
Solution: i) The 9’s complement of 467 is found by subtracting each digit from 9, giving 532.
The 10’s complement is simply the 9’s complement + 1, so 532 + 1 = (533)10. Ans.
ii) The 9’s complement of 7892 is found by subtracting each digit from 9, giving 2107.
The 10’s complement is simply the 9’s complement + 1, so 2107 + 1 = (2108)10. Ans.
iii) The 9’s complement of 70042 is found by subtracting each digit from 9, giving 29957.
The 10’s complement is simply the 9’s complement + 1, so 29957 + 1 = (29958)10. Ans.
Question 05: Using the 10’s complement, subtract (72532)10 – (3250)10.
Solution: The 9’s complement of 3250 is found by subtracting each digit from 9, giving 96749.
The 10’s complement is simply the 9’s complement + 1, so 96749 + 1 = 96750.
Adding this to 72532, we get 169282. Since there is a carry, we discard it, leaving (69282)10. Ans.
Question 06: Using the 16’s complement subtract (5D)16 – (3A)10.
Solution: The 15’s complement of (5D)₁₆ is found by subtracting each digit from F, giving A2.
The 16’s complement is simply the 15’s complement + 1, so A2 + 1 = A3.
Adding this to (3A)₁₆, we get DD₁₆. Since there is no carry, take the 16’s complement of DD, which
is 23, and add a negative sign. Hence (–23)16 Ans.

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

 Boolean Functions
Boolean Algebra was given by George Boole. It is a set of rules used to simplify a given logical expression
without changing its functionality. It is mainly used when several variables present are less. The algebraic
expression used in Boolean Algebra is known as a Boolean Expression, and it is used to describe a Boolean
Function. The Boolean expression generally consists of values 0 or 1, binary variables, and logical operations.
 A Boolean function of n variables is a mapping:
f :{0,1}ⁿ → {0,1}
where f (x₁, x₂, ..., xₙ) takes n binary inputs and returns a binary output.
For example, for n = 2, one possible Boolean function is: F (A, B) = A ⋅ B, (⋅) which represents the AND
operation.
 Number of Possible Boolean Functions For n input variables, there are 2ⁿ possible input combinations, and
each combination has two possible outputs (0 or 1). Thus, the total number of Boolean functions with n
inputs is:
2(2ⁿ)
For small values of n:
 n = 1: 2² = 4 Boolean functions
 n = 2: 2⁴ = 16 Boolean functions
 n = 3: 2⁸ = 256 Boolean functions
For larger n, the number of Boolean functions grows exponentially.
Truth Table Representation:
The truth table is a table that comprises all the possible outcomes of a Boolean function used in Boolean
algebra. It establishes a relationship between various variables that contribute to the Boolean function. 1 in
the truth table represents true/on, and 0 represents false/off.
Example for a 2-variable function: A B f (A, B)
0 0 0
0 1 1
1 0 1
1 1 0
Boolean algebra expression:
A Boolean function can be expressed as a combination of logic operations (AND, OR, NOT, etc.).
Example: f (A, B) = A ⊕ B = A B̅ + A̅ B
Boolean expressions can be simplified using Boolean algebra laws and theorem.
Types of Boolean Function:
1. Constant Function: Always outputs 0 or 1.
f (A, B) = 0 or f (A, B) = 1
2. Identity Function: Output is the same as the input.
f (A) = A
3. Self-Dual Function
f (A₁, A₂, ..., Aₙ) = f (A̅₁, A̅₂, ..., A̅ₙ)
4. Symmetric Function: Output depends only on the number of 1s in the input, not on their positions.
Example: Parity function, Majority function.
5. Linear Function: A function that can be written as a sum of variables modulo 2.
Example: f (A, B, C) = A ⊕ B ⊕ C
Applications of Boolean Functions:
1. Digital Circuits and Logic Design: Used in designing logic gates, combinational circuits (adders,
multiplexers, encoders, etc.).
2. Computer Science: Boolean logic is used in programming (conditional statements, bitwise operations).
3. Cryptography: Boolean functions play a role in encryption and error detection codes.
4. Artificial Intelligence (AI) and Machine Learning: Logic-based reasoning and decision-making systems.
5. Communication Systems: Used in error correction, coding theory, and digital modulation techniques.

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 Basic Theorems and Properties of Boolean algebra

Boolean Laws:
Boolean algebra follows a set of fundamental laws that help simplify logical expressions and design digital
circuits. These laws define how binary variables interact with logical operations such as AND, OR, and NOT.
Below are some of the essential laws of Boolean algebra:
S.No Law Expression S.No. Law Expression
˙
1. Complementation  0 = 1, 1 = 0 2. Commutative  𝐴+𝐵 = 𝐵+𝐴
Law Law  𝐴⋅𝐵 =𝐵⋅𝐴
3. Associative Law  (𝐴 + 𝐵) + 𝐶 = 𝐴 + (𝐵 + 𝐶) 4. Distributive  𝐴 ⋅ ( 𝐵 + 𝐶) = (𝐴 ⋅ 𝐵) + (𝐴 ⋅ 𝐶)
 (𝐴 ⋅ 𝐵) ⋅ 𝐶 = 𝐴 ⋅ (𝐵 ⋅ 𝐶) Law  𝐴 + (𝐵 ⋅ 𝐶) = (𝐴 + 𝐵) ⋅ (𝐴 + 𝐶)
 𝐴 + 𝐴𝐵 = 𝐴 + 𝐵
5. OR Law  0+0 =0 6. AND Law  0⋅0= 0
 0+1 =1  0⋅1= 0
 1+0 =1  1⋅0= 0
 1+1 =1  1⋅1= 1
 𝐴+0= 𝐴  𝐴⋅0=0
 𝐴+1= 1  A⋅1=A
 𝐴+𝐴 = 𝐴  A⋅A=A
 𝐴+𝐴 = 1  𝐴⋅ 𝐴 =0
Boolean Theorems
Boolean algebra relies on several theorems for simplifying and manipulating expressions. Two of the most
important theorems are Duality Theorem and De Morgan’s Theorem.
1. Duality Theorem:
The duality theorem states that every Boolean algebra expression remains valid if we:
 Change the OR operation ( + ) to AND operation ( ⋅ ) and vice versa.
 Complement any 0 or 1 in the expression by replacing 0 with 1 and 1 with 0.
Example:
S. No. Given Expression Dual form 7  𝐴⋅ 𝐴 =𝐴  𝐴+𝐴 = 𝐴
1  0=1  1=0 8  A⋅ 𝐴 = 0  𝐴+𝐴 = 1
2  0⋅1 = 0  1+0= 1 9  A⋅ B = B⋅ A  𝐴+𝐵 = 𝐵+𝐴
3  0⋅0 = 0  1+1= 1 10  A⋅ (B⋅C) = (𝐴 ⋅ 𝐵) ⋅ 𝐶  𝐴 + (𝐵 + 𝐶) = (𝐴 + 𝐵) + 𝐶
4  1⋅1 = 1  0+0= 0 11  𝐴 ⋅ (𝐵 + 𝐶) = 𝐴𝐵 + 𝐴𝐶  𝐴 + 𝐵𝐶 = (𝐴 + 𝐵)(𝐴 + 𝐶)
5  𝐴⋅0=0  𝐴+1= 1 12  𝐴(𝐴 + 𝐴‾) = 𝐴  𝐴 + 𝐴𝐴‾ = 𝐴
6  𝐴⋅𝑙 =𝐴  𝐴+0=𝐴 13  A⋅ (A⋅B) = A ⋅ B  𝐴+𝐴+𝐵 = 𝐴+𝐵
2. De Morgan’s Theorem:
De Morgan’s Theorems define the relationship between AND, OR, and NOT operations. They are useful
for simplifying expressions and designing digital circuits.
Theorem 1: It states that the complement of a product of variables is equal to the sum of the complements of
the variables. (𝑋. 𝑌. 𝑍) = 𝑋‾ + 𝑌‾ + 𝑍‾
Theorem 2: It states that the complement of a sum of variables is equal to the product of the complements of
the variables. (𝑋 + 𝑌 + 𝑍) = 𝑋‾ ⋅ 𝑌‾ ⋅ 𝑍‾
Proof of Theorem 1: Proof of Theorem 2:
𝑋 𝑌 𝑍 𝑋‾ 𝑌‾ 𝑍‾ 𝑋𝑌𝑍 𝑋𝑌𝑍 𝑌‾ + 𝑌‾ + 𝑍‾ 𝑋 𝑌 𝑍 𝑋‾ 𝑌‾ 𝑍‾ 𝑋 + 𝑌 + 𝑍 𝑋 + 𝑌 + 𝑍 𝑋‾𝑌‾𝑍‾
0 0 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 1 0 0
0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0
0 1 1 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0
1 0 0 0 1 1 0 1 1 1 0 0 0 1 1 1 0 0
1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 1 0 0
1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0
1 1 1 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0

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 Logic Gates
Logic gates are fundamental components of digital circuits that perform logical operations on binary inputs
to produce a single output. They are classified into three types: Basic Gates, including AND, OR, and NOT,
which perform elementary Boolean operations; Universal Gates, such as NAND and NOR, which can be used
to construct any other gate; and Exclusive Gates, like XOR and XNOR, which are commonly used in
arithmetic operations and error detection.
Gate Type Logic Gate Logical Diagram Truth Table Switch
Basic Gate 1. AND Gate A B A⋅ B
0 0 0
0 1 0
1 0 0
1 1 1
2. OR Gate A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
3. NOT Gate AA
0 1
1 0

Universal Gate 1. NAND Gate A B A .B

0 0 1
0 1 1
1 0 1
1 1 0
2. NOR Gate A B A+B
0 0 1
0 1 0
1 0 0
1 1 0
Exclusive Gate 2. XOR A B A+ B
0 0 0
0 1 1
1 0 1
1 1 0
3. XNOR Gate A B A⋅ B
0 0 1
0 1 0
1 0 0
1 1 1
Implementation of gates using universal gate
1) NOT Gate using NAND Gate
A NOT gate inverts the input, which can be done using a single NAND gate.

2) AND Gate using NAND Gate

The AND gate can be implemented using two NAND gates.

3) OR Gate using NAND Gate

To construct an AND gate, we first obtain A and B using NAND gates, then apply NAND again

4) NOT Gate using NOR Gate

A NOT gate inverts the input, which can be done using a single NOR gate.

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5) OR Gate using NOR Gate

An OR gate can be implemented using two NOR gates.

6) AND Gate using NOR Gate

To construct an AND gate, we first obtain A and B using NOR gates, then apply NOR again

7) XOR gate using NAND Gate:

8) XOR Gate using NOR Gate:

9) XNOR Gate using NAND Gate:

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10) XNOR Gate using NOR Gate:

 Logic Circuit Implementation Using Diodes and Transistors

Logic circuit implementation using diodes and transistors enables the design of fundamental logic gates by
leveraging diode logic (DL) and transistor-transistor logic (TTL) principles for efficient signal processing.
Diodes facilitate basic logic functions like AND and OR by allowing unidirectional current flow, though they
lack amplification. However, diodes alone cannot implement a NOT gate as they lack amplification, which is
essential for signal inversion. Transistors, acting as switches or amplifiers, enable complex logic operations,
ensuring signal amplification and reliability in digital circuits, forming the foundation of modern computing
systems
Logic Circuit Implementation Using Diodes
1) AND Gate: An AND gate is a basic digital logic gate that outputs HIGH (1) only when both inputs are
HIGH. A simple AND gate can be implemented using two diodes (D1, D2), a 470Ω resistor, and a 10kΩ pull-
up resistor. The circuit consists of two input terminals, A and B, connected to the cathodes of diodes D1 and
D2. The anodes of both diodes are joined together and connected to one end of a 10kΩ pull-up resistor, which
is also connected to the positive voltage supply (V+). The same junction is connected to one end of a 470Ω
resistor, with the other end connected to the anode of an LED bulb. The cathode of the LED is then connected
to the ground.
Working Principle: A B A⋅ B
Case 1: When both A and B are HIGH (5V) 0 0 0
 Both diodes (D1 and D2) are reverse biased and do 0 1 0
not conduct. 1 0 0
 The pull-up resistor (10kΩ) ensures that the output 1 1 1
remains HIGH.
 Current flows through the 470Ω resistor and LED, causing the
LED to turn ON (Output = 1).
Case 2: When either A or B (or both) are LOW (0V)
 The corresponding diode (D1 or D2) becomes forward biased,
creating a low-resistance path to ground.
 This pulls the output to LOW (0V), preventing current flow
through the LED.
 The LED remains OFF (Output = 0).
2) OR Gate: The OR gate logic circuit using only diodes consists of two input terminals, A and B, connected
to the anodes of two diodes, D1 and D2. The cathodes of both diodes are joined together and connected to one
end of a 470Ω resistor, with the other end of the resistor connected to the anode of an LED bulb. The cathode
of the LED is then connected to the ground. A power supply, typically 5V, is used to provide input signals.
Working Principle: A B A+B
Case 1: When both A and B are LOW (0V) 0 0 0
 Both diodes (D1 and D2) are in reverse bias 0 1 1
 No current flows through the circuit. 1 0 1
 The LED remains OFF (Output = 0). 1 1 1
Case 2: When A is HIGH (5V) and B is LOW (0V)
(or vice versa)
 The corresponding diode (D1 or D2) becomes forward biased
and conducts.
 Current flows through the LED and resistor.
 The LED turns ON (Output = 1).
Case 3: When both A and B are HIGH (5V)
 Both diodes are forward biased, allowing maximum current flow.
 The LED remains ON (Output = 1).

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

3) NAND Gate: A NAND gate (NOT AND) is a fundamental logic gate that outputs LOW (0) only when
both inputs are HIGH. Otherwise, it outputs HIGH (1). A NAND gate can be implemented using two diodes
(D1, D2) and three 1kΩ resistors. The circuit consists of two input terminals, A and B, connected to the
cathodes of diodes D1 and D2. The anodes of both diodes are connected together and then connected to one
1kΩ resistor, which is in turn connected to ground. This ensures that when both inputs are HIGH, current can
flow through the diodes to ground, pulling the output LOW. At the junction of the diode anodes, a 1kΩ pull-
up resistor is connected to the positive supply voltage (V+) to ensure the output remains HIGH when the
diodes are not conducting. The output is taken from this junction and connected to an LED bulb through a
1kΩ series resistor, which limits current and protects the LED.
Working Principle:
Case 1: When both A and B are LOW (0V)
 Both diodes (D1 and D2) are reverse biased and do not conduct.
 The pull-up resistor (1kΩ) keeps the output HIGH.
 Current flows through the LED and 1kΩ series resistor, turning
the LED ON (Output = 1).
Case 2: When either A or B (or both) are HIGH (5V)
 The corresponding diode (D1 or D2) becomes forward biased,
creating a low-resistance path to ground. A B A.B
 This pulls the output to LOW (0V), preventing current flow 0 0 1
through the LED. 0 1 1
 The LED remains OFF (Output = 0). 1 0 1
4) NOR Gate: A NOR gate (NOT OR) is a fundamental logic gate 1 1 0
that outputs HIGH (1) only when both inputs are LOW. If either
input is HIGH, the output becomes LOW. A NOR gate can be implemented using two diodes (D1, D2) and
one 1kΩ resistor. The circuit consists of two input terminals, A and B, connected to the anodes of diodes D1
and D2. The cathodes of both diodes are joined together, forming a common junction where the output is
taken. A 1kΩ resistor is connected from this junction to ground (GND), V+
ensuring that when both inputs are LOW, the output remains HIGH. An LED
bulb can be connected at this output node to indicate the logic state.
Working Principle:
Case 1: When both A and B are LOW (0V):
 Both diodes (D1x and D2) are reverse biased and do not conduct.
 Since no current flows through the 1kΩ resistor, the voltage at the output
remains HIGH (1).
 The LED connected at the output turns ON (indicating HIGH). A B A+B
Case 2: When either A or B (or both) are HIGH (5V):  0 0 1
 The corresponding diode (D1 or D2) becomes forward biased, creating a 0 1 0
low-resistance path to ground. 1 0 0
 This pulls the output to LOW (0V), preventing current flow through the 1 1 0
LED. The LED remains OFF (indicating LOW).
Logic Circuit Implementation Using Transistor
1) NOT Gate: A NOT gate (Inverter) outputs the opposite of the input signal. It can be built using a single
NPN transistor (e.g., BC547), a 1kΩ resistor, a 470Ω resistor, and an LED. The input (A) connects to the base
through a 1kΩ resistor, while the collector is linked to V+. A 470Ω resistor and LED are in series with the
collector, and the emitter is grounded.
Working Principle:
Case 1: When A is HIGH (5V or V+):
 The transistor turns ON, allowing current to flow from collector to emitter
(ground).
 Since most of the current is bypassed through the transistor, less current
flows through the LED, keeping it OFF (Output = 0).
Case 2: When A is LOW (0V):
 The transistor is turned OFF, meaning no conduction between collector
and emitter.

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

 The full supply voltage (V+) is applied across the LED and 470Ω resistor, causing current to flow through
the LED, turning it ON (Output = 1).
2) AND Gate: This AND gate is built using two NPN transistors (Q1 and Q2), where the inputs A and B
control the base terminals of each transistor. The output is taken from the emitter of the second transistor (Q2).
The circuit consists of two NPN transistors (Q1 and Q2) connected in series. The base of Q1 is connected to
input A, and the base of Q2 is connected to input B, both through 10kΩ resistors. The collector of Q1 is
connected to VCC (+5V), while its emitter is connected to the collector of Q2. The emitter of Q2 is the output
and is connected to a 470Ω resistor and LED, that are grounded
Working Principle:
Case 1: When A = 0 and B = 0 (Both LOW)
 Both transistors (Q1 and Q2) remain OFF since no base current is supplied.
 No current flows through the circuit, so the output remains LOW (0V).
 The LED stays OFF.
Case 2: When A = 1 and B = 0 (One HIGH, One LOW)
 Q1 turns ON, allowing current to flow through it.
 However, Q2 is still OFF, so the circuit remains incomplete.
 No current reaches the LED, keeping it OFF (Output = LOW).
Case 3: When A = 0 and B = 1 (One LOW, One HIGH) A B A⋅ B
 Q2 turns ON, but Q1 is still OFF. 0 0 0
 Since the circuit is still incomplete, no current flows to the LED. 0 1 0
 The LED remains OFF (Output = LOW). 1 0 0
Case 4: When A = 1 and B = 1 (Both HIGH) 1 1 1
 Both Q1 and Q2 turn ON, creating a complete path from VCC to ground.
 Current flows through the circuit, allowing the LED to turn ON.
 Output is HIGH, indicating an AND gate operation.
3) OR Gate: The circuit consists of two NPN transistors (Q1 and Q2) connected in parallel. The base of Q1
is connected to input A, and the base of Q2 is connected to input B, both through 10kΩ resistors. The collectors
of both transistors are connected to V+ (+5V), while their emitters are joined together, forming the output. A
470Ω resistor and an LED are connected in series from output to ground.
Working Principle:
Case 1: When A = 0 and B = 0 (Both LOW)
 Both transistors (Q1 and Q2) remain OFF since no base current is supplied.
 No current flows through the circuit, so the output remains LOW (0V).
 The LED stays OFF.
Case 2: When A = 1 and B = 0 (One HIGH, One LOW)
 Q1 turns ON, creating a path for current to flow from V+
to ground.
 Since current flows through the LED, it turns ON (output
= HIGH).
Case 3: When A = 0 and B = 1 (One LOW, One HIGH) A B A+B
 Q2 turns ON, allowing current to flow through the circuit. 0 0 0
 The LED turns ON, and output is HIGH. 0 1 1
Case 4: When A = 1 and B = 1 (Both HIGH) 1 0 1
 Both Q1 and Q2 turn ON, allowing a strong current flow. 1 1 1
 The LED remains ON, and output is HIGH.
4) NAND Gate: The NAND gate circuit consists of two NPN transistors (Q1 and Q2) connected in series.
The base of Q1 is connected to input A, and the base of Q2 is connected to input B, both through 10kΩ
resistors. The collector of Q1 is connected to V+, while the emitter of Q1 is connected to the collector of Q2.
The emitter of Q2 is connected to the output, where a 470Ω resistor and an LED are connected in series to
V+. This configuration ensures that the LED remains ON unless both transistors turn ON, following NAND
gate logic.

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

Working Principle: A B A.B

Case 1: When A = 0 and B = 0 (Both LOW) 0 0 1
 Both Q1 and Q2 remain OFF since no base current is supplied. 0 1 1
 No current flows through the transistors, so the output remains HIGH, and the 1 0 1
LED stays ON. 1 1 0
Case 2: When A = 1 and B = 0 (One HIGH, One LOW)
 Q1 turns ON, but Q2 remains OFF, so no current flows to ground.
 The output remains HIGH, and the LED stays ON.
Case 3: When A = 0 and B = 1 (One LOW, One HIGH)
 Q2 turns ON, but Q1 remains OFF, preventing current flow to ground.
 The output remains HIGH, and the LED stays ON.
Case 4: When A = 1 and B = 1 (Both HIGH)
 Both Q1 and Q2 turn ON, creating a complete path from V+ to ground.
 This causes the output to go LOW, turning the LED OFF.
5) NOR Gate: The NOR gate circuit consists of two NPN transistors (Q1 and
Q2) connected in parallel. The base of Q1 is connected to input A, and the base of Q2 is connected to input
B, both through 10kΩ resistors. The collectors of both transistors are connected to V+, while their emitters
are connected to the ground. A 470Ω resistor and an LED are connected in series from the output to ground.
Working Principle:
A B A+B
Case 1: When A = 0 and B = 0 (Both LOW)
 Both Q1 and Q2 remain OFF since no base current is 0 0 1
supplied. 0 1 0
 No current flows through the transistors, so the output 1 0 0
remains HIGH, and the LED turns ON. 1 1 0
Case 2: When A = 1 and B = 0 (One HIGH, One LOW)
 Q1 turns ON, creating a path for current to flow through it.
 This causes the output to go LOW, turning the LED OFF.
Case 3: When A = 0 and B = 1 (One LOW, One HIGH)
 Q2 turns ON, allowing current to flow through it.
 The output goes LOW, and the LED turns OFF.
Case 4: When A = 1 and B = 1 (Both HIGH)
 Both Q1 and Q2 turn ON, creating a complete path from V+ to ground.
 The output remains LOW, and the LED stays OFF.

 Reduction of Boolean Expression and implementation with Logic Gates

This topic focuses on simplifying Boolean expressions using techniques like Boolean algebra method to
minimize the number of logic gates in a circuit. Simplification reduces hardware complexity, cost, and power
consumption. Once reduced, the expression is implemented using basic logic gates (AND, OR, NOT) or
universal gates (NAND, NOR). This process optimizes digital circuit design for efficient performance.
Question 07: Using Boolean algebra, prove that
(i) AB + ABC +A 𝐵 =A (ii) (B + A)(B + D)(A + C)(C + D) = BC + AD
Solution 07: (i) AB + ABC + AB = AB(1 + C) + A B
= AB + A B [OR Law : 1+C=1]
= A( B + B) = 𝐀 [OR Law : 𝐵 + 𝐵‾ = 1 ]
(ii) (B + A)(B + D)(A + C)(C + D)
= (B + AD)(C + AD) [ Distributive Law : (𝐵 + 𝐴)(𝐵 + 𝐷) = 𝐵 + 𝐴𝐷]
= 𝐁𝐂 + 𝐀𝐃 [ Distributive Law : (𝐵 + 𝐴𝐷)(𝐶 + 𝐴𝐷) = 𝐵𝐶 + 𝐴𝐷]

literal is any variable appearing in the expression in complemented or uncomplemented form.

Question 08: Simplify in minimum number of literals:
(i) 𝑥𝑦𝑧 + 𝑥𝑦 + 𝑥𝑦𝑧‾ (ii) 𝑦(𝑤𝑧‾ + 𝑤𝑧) + 𝑥𝑦 (iii) (z𝑥 + z𝑥‾𝑦) (iv) (𝑥 + 𝑦)(𝑥 + 𝑦‾)
Solution 07: (i) 𝑥𝑦𝑧 + 𝑥‾𝑦 + 𝑥𝑦𝑧‾ [OR Law : 𝑧 + 𝑧‾ = 1]
= 𝑥𝑦(𝑧 + 𝑧‾) + 𝑥‾𝑦 = 𝑥𝑦 + 𝑥‾𝑦
= 𝑦(𝑥 + 𝑥‾) = 𝒚 [OR Law : 𝒙 + 𝑥‾ = 1

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

(ii) 𝑦(𝑤𝑧‾ + 𝑤𝑧) + 𝑥𝑦

= 𝑦𝑤(𝑧 + 𝑧‾) + 𝑥𝑦 [OR Law : 𝒛 + 𝑧‾ = 1]
= 𝑦𝑤 + 𝑥𝑦 = 𝒚(𝒘 + 𝒙)
(iii) (𝑧𝑥 + 𝑧𝑥𝑦)
= 𝑧(𝑥 + 𝑥‾𝑦)
= 𝑧(𝑥 + 𝑥‾)(𝑥 + 𝑦) [Distributive Law : 𝑥 + 𝑥‾𝑦 = (𝑥 + 𝑥‾)(𝑥 + 𝑦) ]
= 𝒛(𝒙 + 𝒚) [OR Law : 𝑥 + 𝑥‾ = 1 ]
(iv) (𝑥 + 𝑦)(𝑥 + 𝑦‾)
= 𝑥 + 𝑦𝑦 [AND Law : 𝑦‾𝑦‾ = 0]
=𝑥+0=𝑥
Question 09: Reduce the following expression to the required number of literals.
(i) 𝐴𝐵𝐶 + 𝐴‾ 𝐵‾ 𝐶 + 𝐴‾𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴‾ 𝐵‾ 𝐶‾ to five literals
(ii) 𝐵𝐶 + 𝐴𝐶‾ + 𝐴𝐵 + 𝐵𝐶𝐷 to four literals
(iii) (𝐶𝐷) + 𝐴) + 𝐴 + 𝐶𝐷 + 𝐴𝐵 to three literals
(iv) (𝐴 + 𝐶 + 𝐷)(𝐴 + 𝐶 + 𝐷‾)(𝐴 + 𝐶‾ + 𝐷)(𝐴 + 𝐵‾ ) to four literals
Solution 09: (i) 𝐴𝐵𝐶 + 𝐴‾ 𝐵‾ 𝐶 + 𝐴‾𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴‾ 𝐵‾ 𝐶‾ to five literals
= 𝐴𝐵(𝐶 + 𝐶‾) + 𝐴‾ 𝐵‾ (𝐶 + 𝐶‾) + 𝐴‾𝐵𝐶
= 𝐴𝐵 + 𝐴‾ 𝐵‾ + 𝐴‾𝐵𝐶 = 𝐵(𝐴 + 𝐴‾𝐶) + 𝐴‾ 𝐵‾
= 𝐵(𝐴 + 𝐴‾)(𝐴 + 𝐶) + 𝐴‾ 𝐵‾ = 𝑩(𝑨 + 𝑪) + 𝑨‾𝑩 ‾
(ii) 𝐵𝐶 + 𝐴𝐶‾ + 𝐴𝐵 + 𝐵𝐶𝐷 to four literals
= 𝐵𝐶(1 + 𝐷) + 𝐴𝐶‾ + 𝐴𝐵 = 𝐵𝐶 + 𝐴𝐶‾ + 𝐴𝐵
= 𝐵𝐶(𝐴 + 𝐴‾) + 𝐴𝐶‾(𝐵 + 𝐵‾ ) + 𝐴𝐵(𝐶 + 𝐶‾) = 𝐴𝐵𝐶 + 𝐴‾𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴 𝐵‾ 𝐶‾ + 𝐴𝐵𝐶 + 𝐴𝐵𝐶‾
= 𝐴𝐵𝐶 + 𝐴‾𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴 𝐵‾ 𝐶‾ = 𝐵𝐶(𝐴 + 𝐴‾) + 𝐴𝐶‾(𝐵 + 𝐵‾ ) = 𝑩𝑪 + 𝑨𝑪‾
(iii) ((𝐶𝐷) + 𝐴) + 𝐴 + 𝐶𝐷 + 𝐴𝐵 to three literals
= 𝐶𝐷 ⋅ 𝐴‾ + 𝐴 + 𝐶𝐷 + 𝐴𝐵 = 𝐶𝐷(1 + 𝐴‾) + 𝐴(1 + 𝐵)
= 𝐶𝐷 ⋅ 1 + 𝐴 ⋅ 1 = 𝑨 + 𝑪𝑫
(iv) (𝐴 + 𝐶 + 𝐷)(𝐴 + 𝐶 + 𝐷‾)(𝐴 + 𝐶‾ + 𝐷)(𝐴 + 𝐵‾ ) to four literals
= (𝐴 + 𝐶 + 𝐷 𝐷‾ )(𝐴 + 𝐶‾ + 𝐷)(𝐴 + 𝐵‾ ) = (𝐴 + 𝐶)(𝐴 + 𝐶‾ + 𝐷)(𝐴 + 𝐵‾ )
= (𝐴 + 𝐶(𝐶‾ + 𝐷))(𝐴 + 𝐵‾ ) = (𝐴 + 𝐶𝐶‾ + 𝐶𝐷)(𝐴 + 𝐵‾ )
= (𝐴 + 0 + 𝐶𝐷)(𝐴 + 𝐵‾ ) = (𝐴 + 𝐶𝐷)(𝐴 + 𝐵‾ ) = 𝐴 + 𝐵‾ 𝐶𝐷
Question 10: Simplify using Boolean Algebra.
(i) 𝑌 = 𝐴𝐵 + 𝐴(𝐵 + 𝐶) + 𝐵(𝐵 + 𝐶) (ii) 𝑌 = 𝐴𝐵 + 𝐴𝐵 ⋅ (𝐴𝐶)
Solution 09: i) 𝑌 = 𝐴𝐵 + 𝐴(𝐵 + 𝐶) + 𝐵(𝐵 + 𝐶)
= 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐵 + 𝐵𝐶 [OR Law : AB + AB = AB]
= 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐶 + 𝐵 + 𝐵𝐶
= 𝐴𝐵 + 𝐴𝐶 + 𝐵(1 + 𝐶)
= 𝐴𝐵 + 𝐴𝐶 + 𝐵 [OR Law: 1 + C = 1 ]
= 𝐵(1 + 𝐴) + 𝐴𝐶 [OR Law: 1 + A = 1 ]
= 𝑩 + 𝑨𝑪
(ii) 𝑌 = 𝐴𝐵 + 𝐴 𝐵‾ ⋅ (𝐴‾𝐶‾)
= 𝐴𝐵 + 𝐴 𝐵‾ ⋅ (𝐴 + 𝐶) [De Morgan's Law : (AB) = A + B ]
= 𝐴𝐵 + 𝐴𝐵‾ + 𝐴𝐵‾ 𝐶 [AND Law : AA = A]
= 𝐴(𝐵 + 𝐵‾ ) + 𝐴𝐵‾ 𝐶 [OR Law : B + B = 1 ]
= 𝐴 + 𝐴𝐵‾ 𝐶
= 𝐴(1 + 𝐵‾ 𝐶)
= 𝐴(1 + 𝐵‾ )(1 + 𝐶) [Distributive Law : 𝐴 + 𝐵𝐶 = (𝐴 + 𝐵)(𝐴 + 𝐶) ]
[OR Law : 𝐵 + 𝐵‾ = 1 ]
= 𝐴(𝐵 + 𝐵‾ + 𝐵‾ )(1 + 𝐶)
= 𝐴(𝐵 + 𝐵‾ )(1 + 𝐶)
[OR Law : 1 + 𝐶 = 1 and OR Law : 𝐵 + 𝐵‾ = 1 ]
=𝐀
Question 11: Reduce the expression by using Rule of Boolean Algebra- 𝐹 = 𝑥𝑧 + 𝑦𝑧 + 𝑦𝑧 + 𝑥𝑦𝑧.
Solution 11: 𝐹 = 𝑥‾𝑧‾ + 𝑦‾𝑧‾ + 𝑦𝑧‾ + 𝑥𝑦𝑧 = 𝑥‾𝑧‾ + 𝑧‾(𝑦 + 𝑦‾) + 𝑥𝑦
𝐹 = 𝑥‾𝑧‾ + 𝑧‾ + 𝑥𝑦𝑧 [OR Law: 𝑦 + 𝑦‾ = 1]
𝐹 = 𝑧‾(1 + 𝑥‾) + 𝑥𝑦𝑧 [OR Law: 𝑥 + 𝑥‾ = 1]

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𝐹 = 𝑧‾ + 𝑥𝑦𝑧 [Distribution Law: 𝑥 + 𝑦𝑧 = (𝑥 + 𝑦)(𝑥 + 𝑧) ]

F = (𝑥𝑦 + 𝑧‾)(𝑧 + 𝑧‾) [ORLaw: 𝑥 + 𝑥‾ = 1 ]
F = 𝑥𝑦 + 𝑧‾
Question 12: Simplify the Boolean expression and draw the logic diagram.

Solution 12:

Question 13: Implement the following function by using only NOR gates-
Solution 13:

Question 14: Show that 𝑨𝑩 + (𝑨 + 𝑩) is equivalent to 𝑨 ⊙ 𝑩. Also Constructs the corresponding logic
diagrams.
Solution 14: The truth table constructed below show that A ⊙ B = AB + (A + B). The corresponding logic
diagrams are also shown.
𝐀 𝐁 𝐀⋅𝐁 𝐀+𝐁 𝐀+𝐁 𝐀𝐁 + 𝐀 + 𝐁 𝐀⊙𝐁
0 0 0 0 1 1 1
0 1 0 1 0 0 0
1 0 0 1 0 0 0
1 1 1 1 0 1 1

 Karnaugh’s Map
Before delving into K-Map (Karnaugh Map), it is essential to first comprehend the standard terms of
Boolean expression:
SOP (Sum of Products):
 An expression formed by ORing multiple ANDed terms (minterms).
 Helps in representing 1s in the K-Map, Example: Z = AB + BC
POS (Product of Sums):
 An expression formed by ANDing multiple ORed terms (maxterms).
 Helps in representing 0s in the K-Map.
 Example: Z = (A+B) (B+C)
Minterm:
 A product term representing 1 in the truth table.

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INTRODUCTION TO ELECTRONICS AND COMMUNICATION Unit-3

 Used in SOP form to fill 1s in the K-Map.

Maxterm:
 A sum term representing 0 in the truth table.
 Used in POS form to fill 0s in the K-Map.
Min terms and max terms can be expressed for two-variable and three-variable Boolean functions as follows:
 For two- variable expression, the min-term and  For a three-variable expression, the min-terms
max-term are as follows: and max-terms are as follows :
X Y Z Min-term Max-term
𝐗 𝐘 Min-term Max-term
0 0 0 𝐗. Y. Z = m0 X + Y + Z = M0
0 0 𝑋‾. 𝑌‾ = 𝑚0 X + Y = M0
0 0 1 X. Y. Z = m1 X + Y + Z = M1
0 1 X. Y = m1 X + Y = M1
0 1 0 𝑋‾. 𝑌 V 𝑍‾ = m2 X + Y + Z = M2
1 0 X. Y = m2 X + Y = M2
0 1 1 X. Y. 𝑍 = m3 X + Y + Z = M3
1 1 X. Y = m3 X + Y = M3
1 0 0 𝐗. Y. Z = m4 X + Y + Z = M4
1 0 1 X. Y. Z = m5 X + Y + Z = M5
1 1 0 X.Y. 𝑍‾ = m6 X + Y + Z = M6
1 1 1 X.Y. 𝐙 = m7 𝐗 + Y + Z = M7
Question 15: Express the Boolean function 𝑭 = 𝑨 + 𝑩𝑪 in SOP and POS form.
Solution 15: SOP form :
𝐹 = 𝐴 + 𝐵‾ 𝐶
𝐹 = 𝐴(𝐵 + 𝐵‾ ) + 𝐵‾ 𝐶(𝐴 + 𝐴‾) [𝑂𝑅 𝐿𝑎𝑤: 𝑋 + 𝑋‾ = 1]
𝐹 = 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐵 𝐶 + 𝐴 𝐵 𝐶 = 𝐴𝐵(𝐶 + 𝐶 ) + 𝐴𝐵 (𝐶 + 𝐶‾) + 𝐴𝐵‾ 𝐶 + 𝐴‾ 𝐵‾ 𝐶
‾ ‾ ‾ ‾ ‾ ‾
𝐹 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴𝐵‾ 𝐶 + 𝐴𝐵‾ 𝐶‾ + 𝐴𝐵‾ 𝐶 + 𝐴‾ 𝐵‾ 𝐶 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶‾ + 𝐴𝐵‾ 𝐶 + 𝐴𝐵‾ 𝐶‾ + 𝐴‾ 𝐵‾ 𝐶
𝐹 = Σm(111,110,101,100,001) = Σm(7,6,5,4,1) = Σm(1,4,5,6,7)
POS form :
𝐹 = 𝐴 + 𝐵‾ 𝐶 = (𝐴 + 𝐵‾ )(𝐴 + 𝐶)
𝐹 = (𝐴 + 𝐵‾ + 𝐶𝐶‾)(𝐴 + 𝐶 + 𝐵 𝐵‾ ) [ANDLaw: X X = 0]
𝐹 = (𝐴 + 𝐵‾ + 𝐶)(𝐴 + 𝐵‾ + 𝐶‾)(𝐴 + 𝐶 + 𝐵)(𝐴 + 𝐶 + 𝐵‾ ) [Distributive Law :X + 𝑌𝑍 = (𝑋 + 𝑌)(𝑋 + 𝑍)]
𝐹 = (𝐴 + 𝐵‾ + 𝐶)(𝐴 + 𝐵‾ + 𝐶‾)(𝐴 + 𝐵 + 𝐶) = Π𝑀(010,011,000) = ΠM(2,3,0)
𝐹 = ΠM(0,2,3)
Karnaugh Map : The Karnaugh map or K-map is a method to simplify Boolean algebra expressions. The K-
map is also known as Veitch diagram. The basic of K-map is a graphical chart containing boxes called cells.
Each of the cell represents one of the 2" possible products that can be formed from n variables. Thus, a 2
variable map contains 2² = 4 cells, a 3 variable map contains 2³ = 8 cells and a 4 variable map contains 2 4 =
16 cells.
Two Variables K-map Two Variables K-map Four Variables K-map

Grouping of two adjacent 1’s (Pairs)

A group of two 1’s that are adjacent to one another is called pair.

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Grouping of four adjacent 1’s (Quad.)

A group of four 1’s that are adjacent to one another is called quad.

Grouping of eight adjacent 1’s (Octet.)

A group of eight 1’s that are adjacent to one another is called octet.

Question 16: Determine the minimized expression of logic function and implement through NAND logic.
𝑓 = ∑ 𝑚(2,3,5,7,9,11,12,13,14,15)
Solution: The maximum digit is 𝟏𝟓 i.e. four variables are required. Assume four variables are: A, B, C, D
𝑓 = ∑ 𝑚(2,3,5,7,9,11,12,13,14,15)

𝑓 = ∑ 𝑚(0010,0011,0101,0111,1001,1011,1100,1101,1110,1111)
𝑓 = 𝐴‾ 𝐵‾ 𝐶 𝐷‾ + 𝐴‾ 𝐵‾ 𝐶𝐷 + 𝐴‾𝐵𝐶‾𝐷 + 𝐴‾𝐵𝐶𝐷 + 𝐴𝐵‾ 𝐶‾𝐷 + 𝐴𝐵‾ 𝐶𝐷 + 𝐴𝐵𝐶‾ 𝐷‾ + 𝐴𝐵𝐶‾𝐷 + 𝐴𝐵𝐶𝐷‾ + 𝐴𝐵𝐶𝐷

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K-map simplification for SOP form : Logical Diagram:

Quad 1 = Σm(1100,1101,1111,1110) = 𝐴𝐵,

Quad 2 = Lm(0101,0111,1101,1111) = 𝐵𝐷
Quad 3 = Σm(1101,1111,1001,1011) = 𝐴𝐷,
Pair 1 = Σm(0011,0010) = 𝐴‾ 𝐵‾ 𝐶
𝒇 = 𝑨𝑩 + 𝑨𝑫 + 𝑩𝑫 + 𝑨 ‾𝑩
‾𝑪 𝑓 = (AB)(AD)(BD)(A‾ B‾ C) = AB + AD + BD + A ‾ B‾ C
Question 17: Simplify the following expressions and implement them with basic gate circuit:
(i) 𝐹‾ = 𝐴𝐵‾ + 𝐴𝐵𝐷‾ + 𝐴𝐵𝐷‾ + 𝐴‾ 𝐶‾ 𝐷‾ + 𝐴‾𝐵𝐶‾ (ii) 𝐺 = 𝐵𝐷 + 𝐵𝐶 𝐷‾ + 𝐴 𝐵‾ 𝐶‾ 𝐷‾
Solution:. (i) The K-map and its reduction, and the implementation of the minimal express using basic logic
gates F = A B + ABD + ABD + ACD + A BC

Logical Diagram:

𝐅 = 𝐀 + 𝐂𝐃 + 𝐁𝐂 = 𝐀 + 𝐂( 𝐁 + 𝐃)
(ii) 𝐺 = 𝐵𝐷 + 𝐵𝐶 𝐷‾ + 𝐴 𝐵‾ 𝐶‾ 𝐷‾
Logical Diagram:

 Combinational Circuits
Combinational circuits are the circuits in which the output at any point of time depends upon the
combination of the input signals present at that time only, and does not depend upon any past conditions. The
name combinational is derived from the combinations of logic gates used for such circuits.

Some of the basic and important combinational circuits are:

1. Half Adder – Performs the addition of two binary digits.
2. Full Adder – Performs the addition of three binary digits (including carry).
3. Half Subtractor – Performs the subtraction of two binary digits.
4. Full Subtractor – Performs the subtraction of three binary digits (including borrow).
5. Encoder – Converts multiple input lines into a smaller number of output lines.
6. Decoder – Converts a small number of input lines into multiple output lines.
7. Multiplexer (MUX) – Selects one of many input signals and forwards it to a single output.
8. Demultiplexer (DEMUX) – Takes a single input and routes it to one of several outputs.

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1. Half Adder : Half Adder circuit is a combinational circuit which is used for addition of two binary bits. It
has two inputs and two outputs (SUM and CARRY).
Truth table of Half Adder: Circuit Diagram of Half Adder

Input Output
x y Sum (S) Carry (C)
0 0 0 0
Expression for sum : 𝑺 = 𝒙‾𝒚 + 𝒙 𝒚‾ 0 1 1 0
=𝒙⊕𝒚 1 0 1 0
Expression for carry : 𝐂 = 𝐱. 𝐲 1 1 0 1

2. Full Adder: Full Adder circuit is a combinational circuit which is used for addition of three bits (full
addition i.e.. two input bits and a input carry). It has three inputs ( x, y and z) and two outputs (SUM and
CARRY).
Truth table of Full Adder: K-map simplification for SUM(S): K-map simplification for CARRY(C):
Inputs Outputs
x y 𝑧 Sum (S) Carry (C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
𝐒𝐔𝐌(𝐒) = 𝑥‾𝑦‾𝑧 + 𝑥‾𝑦𝑧‾ + 𝑥𝑦‾𝑧‾ + 𝑥𝑦𝑧 𝐂𝐀𝐑𝐑𝐘(𝐂) = 𝒙𝒚 + 𝒚𝒛 + 𝒙𝒛
0 1 1 0 1
1 0 0 1 0 = 𝑧(𝑥‾𝑦‾ + 𝑥𝑦) + 𝑧‾(𝑥𝑦 + 𝑥𝑦‾) = 𝑧(𝑥 ⊕ 𝑦) + 𝑧‾(𝑥 ⊕ 𝑦)
1 0 1 0 1 = 𝒛 ⊕ (𝒙 ⊕ 𝒚) = 𝒙 ⊕ 𝒚 ⊕ 𝒛
1 1 0 0 1
1 1 1 1 1 Circuit Diagram of Half Adder

3. Half Subtractor: Half subtractor circuit is a combinational circuit which is used for subtraction of two bits.
It has two inputs (x and y) and two outputs (Difference and Borrow).
Truth table of Half Subtractor:
Expression for borrow: B = 𝐱y.
Expression for difference 𝐷 = 𝑥‾ 𝑦 + 𝑥 𝑦‾ Input Output
=𝑥⊕𝑦 x y Difference (D) Borrow (B)
0 0 0 0
0 1 1 -1
Circuit diagram of Half Subtractor:
1 0 1 0
1 1 0 0

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4. Full Subtractor: A Full Subtractor is a combinational circuit used for the subtraction of three bits: minuend
(X), subtrahend (Y), and borrow-in (Bin). It has three inputs (X, Y, Bin) and two outputs (Difference and
Borrow-out).
Truth table of Full Subtractor: K-map simplification for Difference(D) K-map simplification for Borrow(B)
Inputs Outputs
𝐱 𝐲 z Difference (D) Borrow (B)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1 Difference (D) = 𝑥‾𝑦𝑧 + 𝑥‾𝑧‾ + 𝑥𝑦‾𝑧‾ + 𝑥𝑦𝑧 Borrow (B) = 𝑥‾𝑧 + 𝑦𝑧 + 𝑥‾𝑦
1 0 0 1 0 = 𝑧(𝑥‾𝑦‾ + 𝑥𝑦) + 𝑧‾(𝑥‾𝑦 + 𝑥𝑦‾)
1 0 1 0 0 = 𝑧(𝑥 ⊕ 𝑦) + 𝑧‾(𝑥 ⊕ 𝑦)
1 1 0 0 0 = 𝑧 ⊕ (𝑥 ⊕ 𝑦)
1 1 1 1 1 =𝑥⊕𝑦⊕𝑧
Logic Diagram:

5. Encoder: An Encoder is a combinational circuit that converts 2n input lines into nnn output lines. It is
commonly used in transmitter circuits to compress data, reducing multiple input bits into a smaller number of
output bits. The encoder performs the inverse operation of a decoder, converting 2n inputs into n outputs.
The output of an encoder can be of two types: General block diagram of encoder
1. Active High Output
 Implemented using OR gates.
 Requires n OR gates for realization.
2. Active Low Output
 Implemented using NOR gates.
 Requires n NOR gates for realization.
6. Decoder:
 A Decoder is a combinational logic circuit that converts an N-bit binary input into M output lines, where
only one output line is activated for each possible input combination.
 Since each of the N input bits can be either 0 or 1, there are 2N possible input combinations. For each of
these combinations, only one output will be active (HIGH), while all other outputs remain inactive
(LOW).
 Some decoders are designed to produce active LOW outputs, where the selected output is LOW (0), and
all others remain HIGH (1).
General Block Diagram of a Decoder:
 A decoder takes N input lines and produces M
output lines (M ≤ 2n).
 Some decoders do not utilize all 2N possible input
codes.
 Decoders are sometimes called minterm or
maxterm generators because they produce
unique output combinations for each input.

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Properties of Decoders:
1. For each input combination, exactly one output is true (HIGH or LOW depending on the design).
2. Each output equation contains all input variables in either their true or complemented form.
3. These properties hold for all sizes of decoders.
Because of these characteristics, decoders can be used to implement arbitrary Boolean functions. If a function
is represented as a sum of minterms, a decoder (acting as a minterm generator) can be used to realize the
function efficiently.
7. Multiplexer (MUX): A Multiplexer (MUX) is a combinational circuit that selects one of multiple input data
lines and forwards it to a single output line based on the values of selection inputs. It is also known as a data
selector.
 A MUX has 2ⁿ input lines, n selection lines, and one output.
 The selection lines determine which one of the input lines is
transmitted to the output.
 A multiplexer is widely used in data transmission, signal
routing, and arithmetic logic units (ALUs).
Basic 2-input Multiplexer: The logic circuitry and function table for
a 2input multiplexer with data inputs D0 and D1, and data select input
S. The logic level applied to the S input determines which AND gate
enabled, so that its data input passes through the OR gate to the output.
The output, Z = S‾ D 0 + SD1
When S = 0, AND gate 1 is enabled and AND gate 2 is disabled. So, Z = D0
When S = 1, AND gate 1 is disabled and AND gate 2 is enabled. So, Z = D1
Logic diagram: Functional Table:
S Output (Z)
0 D0
1 D1

8. Demultiplexer (DEMUX): Demultiplexing is the process of receiving a single input and distributing it
across multiple output channels. It is also known as "Data Distribution" because it takes one data source and
selectively transmits it to one of the multiple outputs.
 A Multiplexer (MUX) takes multiple inputs and transmits one to the output.
 A Demultiplexer (DEMUX) performs the reverse operation by taking one input and distributing it across
multiple outputs.
 A DEMUX can be considered a data distributor since it directs the same data
to different destinations.
Properties of Demultiplexer:
 1-to-N (or 2N) Device – Takes one input and sends it to one of many outputs.
 Select Lines Determine Output Destination – The selection inputs decide
which output line gets the input signal.
 Used for Data Routing – Often used in communication systems to distribute
data.
 Acts as a Multi-Position Switch – Similar to a switch that directs a signal to
different lines.
 Inverse of Multiplexer – A multiplexer combines signals, while a demultiplexer splits them.

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