DESIGN AND P E R F O W C E EVALUATION OF

SOFTWARE DEFINED RADIO PROTOTYPE FOR PHS AND lEEE802.11 WIRELESS LAN
I
Kazuhirn IIEHARA, Hirnyuki SHIBA, Takasbi SHONO, Ynshi SAIRATO, H i s h i YOSHIOKA,
Masashi NAKATSUGAWA, Shuji KUBOTA, and Masahirn UMEAIRA

NTT Network Innovation Laboratories, NTT Corporation

1-1 Hikari-no-oka, Yokosuka, 2394847 Japan, [email protected]

Abstract-A software defined radio (SDR) prototype best way with which to achieve seamless mobile
based on a multiprocessorarchitecture ( W A ) is developed. communications (Fig. 1).
Software for Japanese personal handy phone system (PHS)
of a 2G mobile system, and IEEE802.11 wireless LAN,
which has much wider bandwidth than the 2G systems, is
successfully implemented. Newly developed flexible-rate
pre-/post-processor (FR-PPP) achieves the flexibility and
wideband performance that the platform needs. This
paper shows the design of the SDR prototype and evaluates
its performance by experiments that include PHS processor
load and processing delay characteristics and wireless LAN .. .
processor load and throughput characteristics.

KeywnrdsSoftware defined radio, PHS, wireless LAN, Fig. 1 Service image of SDR
IEEE802.11, multiprocessor architecture, DSP, CPU,
We have reported an SDRprototype which can support
FPGA, over-the-air download.
only narrow bandwidth systems (up to few 100 kHz) such
as PDC and PHS [7],[8]. This paper describes an
I. INTRODUCTION advanced SDR prototype using newly developed
Recent progress in technologies and cost-reductions in flexible-rate pre-/postprocessors (FR-PPPs) that offer
digital signal processing devices are driving the research improved bandwidths of up to more than 20 MHz and
and development of software defined radios (SDRs). Their improved flexibility, in order to handle wireless LAN
architecture and program download schemes have been systems that use the direct sequence spread spectrum
discussed in the SDR forum and conferences [I]-[3]. The (DSSS) scheme. The prototype has demonstrated
FCC adopted rule changes to accommodate the successfully switching between the PHS and wireless LAN
authorization and deployment of the SDRs in September (IEEE802.11). The prototype also implements the
2001 [4]. The new rules allow manufacturen and over-the-air (OTA) download pmtocol. This function
operators to reconfigure devices afler they have been allows users to update and/or bug-fix the terminals even
deployed in the field. Their wide application areas when they are at home.
include military and cellular communications, home Section Il describes the design of the platform. The
networks, ITS [ 5 ] , and broadcasting. actual program design method is shown in Section m,and
In the mobile communication fields, many kinds of the validity of the design method is confiied by
second generation (2G) mobile systems such as GSM, experimental results in Section Iv. Section V concludes
DAMPS, PDC, and PHS are currently in use, and in Japan the paper.
a thud generation (3G) mobile system, W-CDMA, entered
commercial service in October 2001. In addition, next II. DESIGN OF PLATFORM
generation mobile systems that can offer higher data-rates
The prototype consists of three stages: radio frequency
from several tens of Mbit/s to 100 Mbit/s, are being
(RF), intermediate frequency (IF), and baseband (BB)
developed [6]. In addition to these public mobile services,
stages. The RF and IF stages consist of multiband analog
many private systems such as IEEE802.11x wireless LANs
circuits. A/D conversion is performed at the IF. The
and Bluetooth have become popular. The users needs to
digital IF and BB stages consist of just programmable
buy a wireless terminal dedicated for each system because
devices. Fig. 2 shows a block diagram of the platfom
these systems have their own specifications: ffequency,
The prototype has three independent RF/IF branches for
modulation and demodulation schemes, and
future adoption of simultaneous multimode operation
communication protocol. Also the coverage of these
and/or smart antennas. The platform uses the
systems is restricted to specific areas. SDR is seen as the

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multivrocessor architecture M . A ) ,. shown in Fig.- 3, A. MulfibondRFilF ondA/D ondD/A circuifs
consists of four DSPs, a CPU, and t h e
pre-/post-processors (F'PPs). A @-bit VME bus connects The RF signal received by the antenna is
the DSP, CPU, and external interface modules. down-converted by analog circuits to an IF signal and then
Table 1 shows major specifications of the platform analog-todigital converted. A multiband RF/E circuit
The DSP module is a general-purpose DSP board based on super-hetemdyne scheme was developed. The
consisting of four fued-point arithmetic chips, each with multiband opemtion at 1.5/1.9/2.45 GHz was realized with
a single amplifier by switching handpass filters, according
200 MHz clock and 1,600 MIPS maximum operation
power. The CPU is a 400 M H z PowerPC. The to the..PDC, PHS, and IEEE802.11 standards. A
multiband monopole antenna that resonates at these
real-time operating system (KTOS) is VxWorks.
Memories, a hard disk, and man-machine interface devices Wuencies is used.
A/D conversion is performed by under-sampling the
for user operation are connected to the CPU via local and
expansion buses. For PHS operation, the external 66*l1 MHz IF signal using an ADC with 12-bit resolution
interface module provides an ISDN service in the cell and 88 MSPS sampling rate. The AGC circuit is set
station (CS) platform, and voice and bearer services in the before the ADC. D/A conversion is performed using a
DAC with 14-bit resolution after up-sampling the 22-tll
personal station (PS) platform. This is the only difference
between the CS and PS platforms. For the wileless LAN M H z BB signal. Imaging at 66*11 MHz is used as the IF
. .
operation, the CPU module provides an Ethernet interface stpa'.
in both the access point (AP)and station (STA) platforms.
Fig. 4 shows the appearance of the prototype. B. ReconJgurable digifolIFporf
I Yt.M.m* The IF is too high to be processed by BB processors,
(EarS t ) so pre-/post-processors (PPPs) are used to realize the
lSDN
mnnins,,
high-speed real-time digital processing required; these
yore
Be-
include filtering, wavefonn-shaping, and specmun
de-spreading.
Param81er~ha~g~ab18
A
Fig. 2 Block diagram of prototype.

GP" Hob*

(a) canventiona1PPP

Fig. 3 ,Multiprocessorarchitecture @PA). (b) FR-PPP

Fig. 5 Configurations of conventional PPP and FR-PPP
Table 1 Ma'or s ecificationsof latform (receiving blocks).
2WMW)
(l,600~4~,400MlPS,
IMS320C6201~4

V x W o h 5.2 (Real-time OS) The newly pmposed flexible-rate pre-/post-pmcessor

ADC IF und-mpling(l2-bit. SSMSPS) (FR-PPP) consists of field programmable gate arrays
(FPGAs) and direct digital synthesizer (DDS). Each
branch uses two 1 MGate FPGAs for pre- and
post-processing. Fig. 5 shows the configurations of the
CPU
receiving blocks of a conventional PPP and the FR-PPP.
Emma1 I F Conventional PPPs, commercially available digital
up/down converters, are composed of parameter-preset
M u b a n d RFI F
hard-wired circuits including various kinds of filters to
support the wireless systems targeted. Therefore, their
Fig. 4 Appearance of prototype. ci&t scale is excessive and their bandwidth is restricted to

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 about 1-5 MHz. On the other hand, the circuit scale of the major parameters of both systems.
the FR-PPP is much smaller because the FPGA can flexibly
act as the filters needed for each system. In addition, Table 3 Major parameters of wireless systems
wbile conventional PPPs use complicated interpolation
circuits to support the various clock-rates of the targeted
wireless systems, the DDS in the FR-PPP directly generates
the clock-rates demanded in an arbitrary manner. This
also reduces the circuit scale and offers high-speed
operation. These breakthroughs realize a small circuit
scale (75% smaller), a wide-bandwidth (more than 20
MHz) and very flexible SDR that can support wireless
LANs as well as 2G systems such as PHS.
I .. , I

C. Reconfgurable Baseband (BB)

The software architecture of SDRs is still under
The prototype uses a microprocessor (CPU) and digital discussion in the SDR forum [IO] and SDR related projects.
signal processors (DSPs) to perform BB processing and Architecture selection strongly depends on the OS, API,
control. The CPU, a 400 MHz PowerPC, handles and protocol stack, acd impacts program overhead and
high-layer protocols including PHS call control and system performance. It also influences future
medium access control (MAC) for the wireless LAN. expandability. (Note: In this paper, the term A P I is used
Physical layer processes such as modulation and in the strict sense defined in tbe SDR forum.)
demodulation, voice coding and decoding etc., are handled Fig. 6 shows the program component architecture of
by the DSPs. Each DSP offers the computational power the prototype. A system control program, an over-the-air
of 1,600 MIPS. Two DSP chips are used, one for (OTA) download program, and communication control
transmitting, and tbe other for receiving. Table 2 programs run on the RTOS. The system control program
summaizes the fimction assignment to the processors. handles the user interface, and system management and
control. It executes the OTA download program and the
communication control programs.

ReSl.The os (vxwolhs)
Fig. 6 Program component architecture.

The OTA download program is designed to be very

general compact, and secure. The protocol works over
ID.DESIGN OF SOFTWARE TCP/IP so if the communication mode changes, the OTA
A . Safmare Architecture download protocol is not affected. The OTA download
protocol not only downloads the software, but also
The SDR prototype operates as the terminal of a specific authenticates and encrypts the data using Secure Socket
wireless system after loading the software of the system Layer (SSL). To ensure secure downloads, the 128-bit
into its processors. The programs written for the next-generation block-cipber “Camellia,” which was
prototype reproduce almost all of the key operating co-developed by NTT and Mitsubishi Electric Corporation
functions of PHS and the direct-sequence spread spectrum [ll], was implemented as the cipber algorithm of SSL.
(DSSS) scheme of infrastructure mode IEEE802.11 The communication control program are packaged
wireless LAN offered by the regular commercial terminals. binary files; each consists of CPU, DSP, and FR-PPP
PHS is a four-channel TDMA-TDD wireless system that programs which togelher constitute a wireless system
was standardized by Japanese RCR STD-28 [9]. The protocol. The CPU and DSP programs were written in
CODEC uses 32 kbit/s ADPCM and the modulatiodde- the C programming language and the FPGA configuration
modulation schemes are d4shiR QPSWincohemt data of the FR-PPP was written in the Verilog hardware
detection. The IEEE802.11 wireless LAN supports definition language (HDL).
multi-rate transmission by using DBPSK (IMhit/s) and
DQPSK (2MbiVs) modulation schemes. Table 3 shows

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B. PHS Program C. IEEE802.1I WirelessLAN Progrnm
In the PHS communication control program, the CPU In the wireless LAN communication control program,
propm handles call control tasks and a MAC layer controls and physical layer processes are
DSP-task-management task. The priority of these tasks is basically assigned to the CPU and DSP programs,
set by the RTOS considering the processing time of each respectively. With a few exceptions, the spectrum
task. PHS imposes strict processing limits on the DSP de-spreading process is handled by the FR-PPP because it
tasks to achieve real-time communication because it uses requires real-time correlation detection for very high-speed
the TDMA-TDD access scheme. Therefore, the signals; the chip-rate is 11 Mchip/s. The load of the
scheduling of DSP tasks should be pre-assigned and the spectrum spreading process is small, so it can normally be
DSP loads of the tasks should be appropriately shared to handled by the DSP. In addition, the 32-bit frame check
avoid overloads. Table 4 shows an example of DSP task sequence (FCS) process is assigned to the DSP because it
scheduling. The DSP-task-management task directs the consists of product-sum operations which are very suitable
execution of these DSP tasks via an API between the CPU for the DSPs. The API between the CPU and DSP
and DSP programs as shown in Fig. 7. programs is the same as that of PHS, but interruption
timing uses MAC layer packet data units (MF'DUs).
Since the MPA of the platform uses the W E bus
between the CPU and DSP, it causes troublesome
processing delay. For instance, the data aansfer time was
estimated to be about 40ps, and the intermption response
time to be about 3ps [12]. They make it diflicult for
CSMA-CA protocol to realize !&-order response times.
The IEEE802.11specifies the short interhme space (SIFS)
Frame camtruetian of lops [13]. Therefore, we parameterized the SIFS time
Voice decodrng and the distributed coordinate function intefime space
Mdulsti'Xl
7 (uplink slog (DIFS) time as follows in order to evaluate system response
P
performance;
SIFS' h&YIFS,
DIFS' W I F S = M x (SIFS+ ZxNot-Time) ,

_"II:,
where, Mis defined as an IFS factor.
Fig.8 shows the relationship between an IFS factor and
:if&:cor throughput. It was simulated under the condition that
packet error and congestion are negligible. The
..... s?.M.-.u:..::
. ... .. .. ......
.. .. . . throughput was defined as the maximum mnsmission rate
Rsspnre .."
of MPDU. When the IFS factor, M, is 10, throughput
becomes about 70 % of the original performance (M=l).

Fig. 7 API between CPU and DSP programs. 2Mbiffs mode

First, the CPU program writes an API command and

related parameters into a shared memory. Next tbe CPU
program interrupts the DSP prognun, which is
synchronized to TDMA slot timing. The intemption
moves the access authority of the shared memory from the
CPU to the DSP. The DSP program reads the shared
memory to obtain the API command and parameters.
After the DSP program executes the task the DSP program
writes the result into the shared memory and interrupts the
CPU prognrm. This interruption returns the access 0
0 500 1000 1500
authority to the CPU, and the CPU program recognizes the Frame length (byte)
completion of the API command, and the CPU program's
state transits. Real-time signal processing can be Fig. 8 Relationship hetween IFS factor and throughput.
achieved by perfomfng these controls in each TDMA slot.

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 Tv. PERFORMANCE EVALUATION
Fig. 8 shows the experimental setup used. The
program sizes of the non-compressed packaged PHS and
wireless LAN communication contml programs were about
2 B y t e s and 3 MBytes, respectively.

I .
.II
I I (I
I( I I
III (
00 500 1000 1500
Frame length (byte)
PHS Mode Fig. 10 Throughput characteristics for wireless LAN
ISON mode.

Next, the PHS communication control program was

loaded into the platform by OTA downloading. Basic
characteristics of the platform, such as spectrum and
constellation, were measured, which confirmed that the
Fig. 8 Experimental setup.
DSP and FR-PPP programs performed as designed. The
burst waveforms of tbe traffic channel (TCH), whose
First, by downloading the wireless LAN program and
interval was eight TDMA slots (5 msec), were observed to
establishing STA-Ap communication, we confrmed that
be as designed. Communication between the CS and PS
data conqunication between two PCs connected to
was established and clear voice communication was
'different SDR prototypes was realized. Fig. 9 shows achieved to also w n h that the communication sequence
measured average DSP loads of each data symbol in written in the CPU program was successfully realized.
wireless LAN mode. The ratio of average DSP loads for Fig. 11 shows the measured average DSP loads of the
each signal process on the DSPs for transmitting and PS prototype in each TDMA slot when 2-TDMA (control
receiving is shown The measured value was about 60%,
channel (CCH) and TCH), including the CODEC, which
which confirmed that DSP load never became excessive. imposes the largest load, was processed. The average
The measured minimum IFS factor M that could ensure
DSP load is defined as the processing time normalized by
CSMA-CA protocol on the platform was 10. This value the TDMA slot time. The CS prototype showed almost
can be further minimized by using on-board or onchip the same results. This confirms that all tasks were
processors, for instance. Fig. 10 shows tbe tbroughput performed as designed and that DSP loads never became
characteristics for both the 1 MbiWs and 2 Mbitl5 modes. excessive. This means that real-time communication w a s
When M is not less than 10, measured throughput a p e d successfully achieved. In addition, we note that 4-TDMA
very well with the simulation. This confirmed that the processing is possible by using the currently idle slots.
new programs were performing as intended.
0.20 , , , , , , ,
0.7,
1 n Tx IUollnk 7th plot1
17
RX inawnlink 3rd ;a)
0.15
P9
w2 0.10
e
t 0.05

' 1 2 3 4 5 6 7 8
TDMArMI
Fig. 11 Measured average DSP loads of personal station
Fig. 9 Measured average DSP loads of each symbol for in each TDMA slot for PHS mode.
wireless LAN mode.

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 Fig. 12 shows an example of measured processing REFERENCES
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ACKNOWLEDGEMENTS [I41 ITU-T Recommendation, G.114.
The authors would like to thank Dr.M. Kawacbi, Dr.T.
Masamura, Dr. H. Mizuno, and Mr. K. Araki for their
helpful discussions aid suggestions.

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