Digital IC Design Practice Questions
Company: Tessolve Semiconductor
Duration: 3 Hours
PART A: Fill in the Blanks with Answers
Section A: Logic Gates & Boolean Algebra
1. odd
2. A
3. all basic gates
4. NAND
5. A + B
6. A(A + B)
7. NAND
8. OR
9. OR
10. 16
Section B: Combinational Circuits
11. three
12. A AND B
13. two
14. 2ⁿ
15. highest
16. circuit simplification
17. equal, greater, less
18. 7-segment display
19. AND, OR
20. many
Section C: Verilog & HDL Basics
21. module
22. sequential
23. 5
24. my_reg
25. =
26. one
27. wire
28. don’t care
29. triggered
30. always
31. transition, memory
32. combinational
33. conditional (?:)
34. constant
35. unspecified
Section D: RTL Design & FSMs
36. Register Transfer Level
37. registers, operations
38. 3
39. inputs
40. one-hot
41. one-hot
42. current state
43. one
44. current
45. redundant
46. gates
47. feedback
48. functional
49. coding
50. 2
Section E: Timing Analysis & Constraints
51. propagation delay
52. buffer
53. edge
54. flip-flops
55. setup violation
56. Static Timing Analysis
57. combinational
58. synchronous
59. met
60. timing
61. period
62. constraint
63. synthesis
64. clock
65. clock
Section F: Synthesis & Optimization
66. synthesis
67. cell
68. Cadence Genus
69. logic
70. buffer
71. technology
72. logic
73. multicycle
74. delay
75. ALUs
76. dead
77. registers
78. signal
79. optimized
80. fanout
Section G: DFT (Design for Testability)
81. flip-flops
82. Built-In Self-Test
83. coverage
84. delay
85. known
86. output
87. control
88. test
89. 0
90. time
91. faults
92. scan
93. test
94. scan
95. LFSR
Section H: Layout, Physical Design & Backend
96. placement
97. metal
98. layout generation
99. routing
100. circuit
101. current
102. straps
103. signal
104. fabrication
105. skew
106. layout
107. Layout vs Schematic
108. layout rule
109. metal
110. ground
Section I: Mixed Concepts & Application Design
111. synchronous
112. loads
113. delay
114. noise
115. flip-flops
116. N
117. XOR
118. constant
119. inverter
120. highest
PART B
Q1. What is the reason for longer rise and fall time? How to improve it?
A. Reasons for longer rise and fall times:
- High load capacitance
- Weak drive strength of gate
- Long interconnects and routing delays
Improvements:
- Use buffers or inverters to boost signal
- Reduce parasitic capacitance by optimizing layout
- Use stronger drive gates
- Minimize fan-out
Q2. What are the requirements to convert the truth table to a digital waveform?
Requirements:
- Define time intervals for input transitions
- Map inputs to timing diagram
- Apply gate or flip-flop logic to determine outputs
- Include propagation delays in waveform
Q3. Analyze the binary data at the given intervals.
A. Let's analyze the binary data of signals A, B, and C at the marked time intervals T1 to T5
from the given waveform.
Step-by-Step Analysis:
Time A B C
T1 1 0 1
T2 0 1 0
Time A B C
T3 1 0 0
T4 0 1 1
T5 1 0 0
Final Answer to Fill:
A: 1 0 1 0 1
B: 0 1 0 1 0
C: 1 0 0 1 0
Q4. Redraw the AND gate waveform with timing information.
A.
Q5. What is the reason for longer rise and fall time? How to improve it?
A. Reason for Longer Rise and Fall Time:
High Load Capacitance:
When the output drives a large capacitive load (due to many connected gates or long
interconnects), the charging and discharging take longer.
Weak Drive Strength:
If the driving gate cannot source or sink enough current quickly, the transitions become slower.
High Fan-Out:
Driving too many inputs from a single output increases capacitive loading, slowing transitions.
Long Routing Paths:
Longer metal traces introduce parasitic capacitance and resistance, increasing the RC time
constant.
How to Improve Rise and Fall Times:
Use Buffers or Inverters:
Insert buffers between stages to drive large capacitive loads.
Increase Drive Strength of Cells:
Choose standard cells with higher drive capability (e.g., AND2X4 instead of AND2X1).
Minimize Fan-Out:
Reduce the number of gates driven directly by a single output.
Shorten Interconnect Lengths:
Optimize layout to reduce RC delay by minimizing wire length.
Technology Scaling or Optimization:
Use a faster or optimized process node if available.
Q6. A and B input pins, rise/fall times are 10ns. Assume A has 5ns additional delay than B.
Redraw the output waveform of the AND gate considering the time and delay mentioned.
(Period = 25ns)
A.
Q7. Draw a D flip-flop with all signals and draw the waveform for 4 cycles.
A.
Q8. Observe the waveform given below
a) What is (t1 – t2)?
This interval is the setup time (t_setup) — the minimum time before the rising edge of the clock
that the D input must be stable.
t1 − t2 = Setup Time
b) What is (t2 – t3)?
This is the time after the rising clock edge when the output Q begins to change. It is referred
to as the clock-to-Q delay start or contamination delay.
t2 − t3 = Clock-to-Q Delay Start (t_ccq)
c) What is (t2 – t4)?
This is the full clock-to-Q propagation delay — the time it takes for the output Q to become fully valid
after the clock edge.
t2 − t4 = Propagation Delay (t_pd or t_clk→Q)
Q9. Redraw the D-Flipflop waveform with clock freq = 10 MHz, Setup time = 10ns, hold time =
15ns and propagation time = 20ns .
A.
Q10. Draw clock waveform with clear timing information to transmit same data at Q output of
D-Flip Flop with specification 𝑡𝑠𝑒𝑡𝑢𝑝 = 15𝑛𝑠, 𝑡ℎ𝑜𝑙𝑑 = 10𝑛𝑠, 𝑡𝑝𝑑 = 15𝑛𝑠 .
A.
Q11. Given the specifications below, calculate
a. How many inputs can the output drive Low?
b. How many inputs can the output drive High?
c. What is the maximum number of inputs that the output can be connected to and still guarantee
correct operation?
A. Given TTL Output Specifications:
VOH = 2.4 V at -2.6 mA
VOL = 0.4 V at 24.0 mA
TTL Input Specifications:
IIH = 150 μA at 2.4 V
IIL = -0.8 mA at 0.4 V
Calculations:
a) Output driving LOW (sinking current):
Output can sink 24.0mA total
Each input draws 0.8mA when LOW
Number of inputs = 24.0mA / 0.8mA = 30
b) Output driving HIGH (sourcing current):
Output can source 2.6mA total
Each input draws 150μA when HIGH
Number of inputs = 2.6mA / 0.15mA ≈ 17.33 → 17 (must round down)
c) Maximum guaranteed inputs:
Limited by the worse case (HIGH drive)
Maximum = 17 inputs
Q12. Define the important specifications of Pattern Generator .
A. Key Specifications:
Channel count: Number of parallel output bits
Pattern depth: Maximum number of vectors stored
Clock rate: Maximum pattern generation speed
Timing resolution: Minimum time between pattern changes
Output voltage levels: Compatibility with target system
Memory segmentation: Ability to create loops/jumps
Trigger capabilities: Synchronization with external events
Data formats: Binary, hex, ASCII support
Edge placement: Precision of signal transitions
Q13. What are the important specifications of Logic Analyzer?
A. Key Specifications:
Channel count: Number of simultaneous input signals
Sample rate: Determines timing resolution
Memory depth: Number of samples stored per acquisition
Trigger capabilities: Complex conditional triggering
Input voltage ranges: Compatibility with target signals
Threshold adjustment: For different logic families
Timing resolution: Minimum distinguishable time interval
Protocol analysis: Built-in decoding for common protocols
Glitch detection: Ability to capture short pulses
Bandwidth: Analog frequency response
Q14. Draw the block diagram of Pattern Generator.
A.
Q15. Draw the block diagram of Logic Analyzer
.
