Enrolment No.

/Seat No_______________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE- SEMESTER–III (NEW) EXAMINATION – WINTER 2024
Subject Code: 3130704 Date: 10-12-2024
Subject Name: Digital Fundamentals
Time: 10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1* (a) (a) Perform the following mathematical operations using 2’s 03
complement method.
(i) (9)10 + (-5)10
(ii) (3)10 – (8)10
(b) State and prove De-Morgan’s theorems using truth-tables. 04
(c) Explain the characteristics of Digital ICs. 07
Q.2 (a) Design a Full Adder circuit using basic logic gates. 03
(b) Design a modulo-6 ripple counter using T-Flip-flops. 04
(c) Design a 4-bit Binary to Gray Code Converter using K-map. 07
OR
(c) Draw a two input TTL NAND gate and explain its operation. 07

Q.3 (a) Explain Race Around Condition in JK flip flop. 03

(b) Design a 1 - bit Magnitude Comparator. 04
(c) Explain Hamming codes for error correction with a suitable example. 07
OR
Q.3 (a) Find expression for the following and implement using logic gates. 03
F(A,B,C,D) = πM(0,2,3,6,7,8,9,12,13)
(b) Implement D flip flop using JK flip flop. 04
(c) Design a 4-bit twisted Ring Counter using JK flip flops. 07

Q.4 (a) Differentiate Synchronous Counters and Asynchronous Counters. 03

(b) Implement the following using 8:1 MUX. 04
F = f(A,B,C,D) = Σm(2,4,5,7,10,14)
(c) Design a synchronous BCD counter using J-K flip-flops. 07
OR
Q.4 (a) Implement full subtractor using 3:8 decoder and write a truth table. 03
(b) Explain the specifications of Digital to Analog Converters. 04
(c) Explain Successive Approximation type A/D converter. 07

Q.5 (a) Differentiate Static RAM and Dynamic RAM. 03

(b) Write a short note on FPGA. 04
(c) Explain the operation of Dual-slope A/D converter. 07
OR
Q.5 (a) Explain basic structure of a CCD (Charge Coupled Device). 03
(b) Write a short note on Programmable Array Logic. 04
(c) Explain various types of Read Only Memory. 07
*********************************

1
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER– III(NEW) EXAMINATION – WINTER 2022
Subject Code:3130704 Date:27-02-2023
Subject Name:Digital Fundamentals
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

Marks
Q.1 (a) Implement NOR, AND, & OR gates using NAND gates only 03
(b) Wrtite the boolean expression for the logic diagram given below and 04
simplify it as much as possible and draw the logica digarm that implements
the simplified expression

(c) Do as directed: 07
1. Convert (75.75) 10 = (___) 8 = (___)16
2. Convert (101.10)16 = (__)8
3. Add (17)10 and (-25)10 using 8-bit 2’s complement

Q.2 (a) Explain SR flip-flop using characteristic table & characteristic equation 03
(b) Explain 4-bit parallel binary adder with neat and clean diagram 04
(c) Obtain the set of prime implicants for Function F= 07
∑ m (1,2,3,5,6,7,8,9,12,13,15)
OR
(c) A combinational logic circuit is defined by the functions: 07
F1= Ʃ (0,1,2,4) and F2= Ʃ (0, 5, 6,7).
Implement the circuit with a PLA having three inputs, four product terms
and two outputs.
Q.3 (a) Differentiate synchronous counter and asynchronous counter 03
(b) Explain BCD adder using two 4-bit adder IC and a correction -detector 04
circuit
(c) Do the conversion of JK flip flop to T flip flop and D flip flop to JK 07
OR
Q.3 (a) Design 4 X 16 decoder using two 3 X 8 decoders 03
(b) List and explain in detail Binary codes with example 04
(c) Design mod-6 asynchronous counter using T flip flop 07

Q.4 (a) Reduce the expression Σ (2, 3, 6,7,8,10,11,14) using K-map 03

1
 (b) Do as directed: 04
1. Add 25+17 in BCD
2. Add 37 +28 in XS-3
(c) With a neat block diagram explain the function of encoder. Explain priority 07
encoder?
OR
Q.4 (a) Explain R-2R ladder type D/A converter 03
(b) Implement the following Boolean functions with a 3 x 1 multiplexer F (w, 04
x, y, z) = Σ (2, 3, 5, 6, 11, 14, 15)
(c) Design Combinational circuit for Binary to Xs-3 conversion 07

Q.5 (a) Compare TTL, ECL, & CMOS logic families. 03

(b) Draw truth table of 2-bit digital comparator 04
(c) List out various commonly used D/A converters. Draw & explain any one 07
D/A converter.
OR
Q.5 (a) A combinational logic circuit is defined by the functions: 03
F1= Ʃ (0,1,2,5,7) and F2= Ʃ (1, 2,4, 6). Implement the circuit with a
PROM
(b) Explain types of shift-register and their application 04
(c) List out various commonly used A/D converters. Draw & explain any one 07
A/D converter

2
 Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III (NEW) EXAMINATION – WINTER 2021
Subject Code:3130704 Date:23-02-2022
Subject Name:Digital Fundamentals
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS

Q.1 (a) Implement EX-NOR using NAND gate. 03

(b) Convert the decimal number 225.225 to octal and hexadecimal. 04
(c) Give classification of logic families and compare CMOS and TTL. 07
Q.2 (a) Convert F(A,B,C) = BC+A into standard minterm form. 03
(b) With logic diagram and truth table, explain the working of 3 line to 8 line 04
decoder.
(c) Explain Successive Approximation A/D converter in detail. 07
OR
(c) A combinational logic is defined by functions: 07
F1(A,B,C) = ∑m (3,5,6,7) F2(A,B,C) = ∑m (0,2,4,7)
Implement the circuit with PLA having 3 inputs, 4 product terms & 2 outputs.

Q.3 (a) Simplify the Boolean expression: F(x,y,z) = ∑m (0,1,3,4,5,7) 03

(b) Explain S-R clocked flip flop. 04
(c) Design full adder circuit using decoder and multiplexer. 07
OR
Q.3 (a) Generate AND & EX-OR gates using NOR gate. 03
(b) Implement D flip flop using JK flip flop. 04
(c) Design a counter to generate the repetitive sequence 0,4,2,1,6. 07

Q.4 (a) What is race around condition in JK flip flop. 03

(b) Construct a ring counter with five timing signals. 04
(c) Design BCD to Excess 3 code converter using minimum number of NAND 07
gates.
OR
Q.4 (a) Explain 2-bit comparator circuit. 03
(b) Write a short note on FPGA. 04
(c) What is Digital to Analog converter? Draw and Explain R-2R DAC. 07

Q.5 (a) Perform following operation using 2’s complement method. 03

(11010)2 – (1000)2
(b) Write a short note on Read Only Memory (ROM). 04
(c) Explain the working of 4 bit binary ripple counter. 07
OR
Q.5 (a) Obtain the truth table of the function: F = xy+yz+zx . 03
(b) Implement following functions using ROM. 04
F1 = ∑m (1,3,4,6) and F2 = ∑m (0,1,5,7).
(c) Explain in detail Dual Slope A/D converter. 07

**********

1
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III (NEW) EXAMINATION – WINTER 2023
Subject Code:3130704 Date:25-01-2024
Subject Name:Digital Fundamentals
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS

Q.1 (a) List out various logic families. Also list characteristics of digital IC. 03
(b) State and prove De-Morgan’s theorems using truth-tables. 04
(c) Implement AND, OR, EX-OR gates using NAND & NOR gates. 07

Q.2 (a) Reduce the expression F = x’y’z +yz+ xz 03

(b) Convert the decimal Number 330.5 to base 4 and base 8. 04
(c) Design a Combinational circuit that convert Binary to BCD code converter. 07
OR
(c) Design a Combinational circuit that convert BCD to Excess 3 code 07
converter.

Q.3 (a) Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 03
1, 3, 5,6, 7, 10, 13,14, 15)
(b) Explain 4 – bit parallel adder with diagram. 04
(c) Design 2 - Bit Magnitude Comparator. 07
OR
Q.3 (a) Design D FF using SR FF. Write truth table of D FF. 03
(b) Minimize following Boolean function using K-map: F(A,B,C,D) = Σ m(1, 04
5, 6, 12, 13, 14) + d(2, 4)
(c) Design 3-bit even parity generator circuit. 07

Q.4 (a) Compare static RAM and dynamic RAM. 03

(b) Explain JK flip flop with its characteristic table and excitation table. 04
(c) Write a brief note on race around condition and its solution. Draw & explain 07
the logic diagram of master-slave JK flip-flop.
OR
Q.4 (a) Explain the types of ROM. 03
(b) Explain Look-ahead Carry generator 04
(c) Design a Synchronous counter with the following binary sequence: 0, 1, 3, 07
4,5, 7 and repeat. Use T – flip-flops

Q.5 (a) Explain the working of a Counter. 03

(b) Explain R-2R ladder type D/A converter 04
(c) A combinational circuit is defined by the function F1 (A, B, C,) = Σ m 07
(0,1,3,4) F2 (A, B, C,) = Σ m (1.2.3,4,5) Implement the circuit with a PLA
having 3 inputs, 3 product term & 2 outputs.

1
 OR
Q.5 (a) Explain the working of SISO shift register. 03
(b) Explain the specification of D/A converter 04
(c) Describe operation of D/A converter with binary-weighted resisters 07

*************

2
Enrolment No./Seat No_______________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III EXAMINATION – SUMMER 2025
Subject Code:3130704 Date:06-06-2025
Subject Name:Digital Fundamentals
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) State and Apply DeMorgan’s theorem.: [(x+y)’+(x+y)’]’=x+y 03
(b) Do As Directed: 04
1. Convert (0.6875)10 to Binary.
2. Give the octal equivalent of hexadecimal numbers of DC.BA.
3. Convert (101101.1101)2 to Hexadecimal.
4. Give the Truth Table of XOR gate.

(c) Prove that NAND and NOR gates are universal gates. 07

Q.2 (a) Determine the value of base x if (211)x = (152)8 03

(b) Subtract (111001)2 from (101011)2 using 1’s complement 04
(c) Simplify and implementation the following SOP function using NOR 07
gates F(A,B,C,D)= ∑m(0,1,4,5,10,11,14,15)
OR
(c) Simplify the Boolean expression using K-map and implement using 07
NAND gates F(A,B,C,D) = ∑m(0,2,3,8,10,11,12,14)

Q.3 (a) Design the combinational circuit of 4 Bit Parallel Adder. 03

(b) Implement the following Boolean function using 8:1 multiplexer: 04
F(A, B, C, D) = A’BD’ + ACD + A’C’ D +B’CD
(c) Design a combinational circuit with four input lines that represent a 07
decimal digit in BCD and four output lines that generate the 9’s
complement of the input digit.
OR
Q.3 (a) Design Truth table for the Half adder and write the expression for the 03
sum and carry.
(b) Implement the following Boolean function using 8:1 multiplexer: 04
F(A,B,C,D) = Σ𝑚 (0,3,4,7,8,9,13,14)
(c) Design 5 to 32 line decoder using 3 to 8 line decoder and 2 to 4 line 07
decoder.

Q.4 (a) Explain about Ring counter. 03

(b) Describe how T flip-flop is converted into D flip-flop. 04
(c) What is the function of shift register? With the help of simple diagram 07
explain its working.
OR
Q.4 (a) Explain various applications of the register. 03
(b) Describe how JK flip-flop is converted into D flip-flop. 04
(c) Draw the state diagram of BCD ripple counter, develop its logic diagram 07
and explain its operation.
1
Q.5 (a) Write difference between PROM, PLA & PAL. 03
(b) Using 8x4 ROM, realize the expressions W(A,B,C) =∑m(0,1,3,5,7) 04
,X(A,B,C) =∑m(0,2,4,5) , Y(A,B,C) =∑m(1,2,4,7) ,
Z(A,B,C=∑m(0,3,5,6,7). Show the data at address 2 & 6.
(c) Implement the following function using PLA 07
F1= ∑m(0,2,5,8,9,11),F2=∑m(1,3,8,10,13,15),F3=∑m(0,1,5,7,9,12,14).
OR
Q.5 (a) Discuss : Field Programmable Gate Array (FPGA) 03
(b) Explain Successive Approximation type A/D converter. 04
(c) Give a brief on various types of memories. 07

*************

2
 Enrolment No./Seat No_______________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III (NEW) EXAMINATION – SUMMER 2024
Subject Code:3130704 Date:06-07-2024
Subject Name: Digital Fundamentals
Time:10:30 AM TO 01:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS

Q.1 (a) List out various logic families. Also list characteristics of digital IC. 03
(b) State and prove De-Morgan’s theorems using truth-tables. 04
(c) Implement AND, OR, EX-OR gates using NAND & NOR gates. 07

Q.2 (a) Reduce the expression F = x’y’z +yz+ xz 03

(b) Convert the decimal Number 330.5 to base 4 and base 8. 04
(c) Design a Combinational circuit that convert Binary to BCD code converter. 07
OR
(c) Design a Combinational circuit that convert BCD to Excess 3 code 07
converter.

Q.3 (a) Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 1, 3, 03
5,6, 7, 10, 13,14, 15)
(b) Explain 4 – bit parallel adder with diagram. 04
(c) Design 2 - Bit Magnitude Comparator. 07
OR
Q.3 (a) Design D FF using SR FF. Write truth table of D FF. 03
(b) Minimize following Boolean function using K-map: F(A,B,C,D) = Σ m(1, 5, 6, 04
12, 13, 14) + d(2, 4)
(c) Design 3-bit even parity generator circuit. 07

Q.4 (a) Compare static RAM and dynamic RAM. 03

(b) Explain JK flip flop with its characteristic table and excitation 04
table.
(c) Write a brief note on race around condition and its solution. Draw & explain the 07
logic diagram of master-slave JK flip-flop.
OR
Q.4 (a) Explain the types of ROM. 03
(b) Explain Look-ahead Carry generator 04
(c) Design a Synchronous counter with the following binary sequence: 0, 1, 3, 4,5, 07
7 and repeat. Use T – flip-flops

Q.5 (a) Explain the working of a Counter. 03

(b) Explain R-2R ladder type D/A converter 04
(c) A combinational circuit is defined by the function F1 (A, B, C,) = Σ m (0,1,3,4) 07
F2 (A, B, C,) = Σ m (1.2.3,4,5) Implement the circuit with a PLA having 3 inputs,
3 product term & 2 outputs.
OR
Q.5 (a) Explain the working of SISO shift register. 03
(b) Explain the specification of D/A converter 04
(c) Describe operation of D/A converter with binary-weighted resisters 07
*************

1
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER–III(NEW) EXAMINATION – SUMMER 2023
Subject Code:3130704 Date:01-08-2023
Subject Name:Digital Fundamentals
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.

MARKS
Q.1 (a) Define the logic family properties: 03
(i) fan in (ii) propagation delay (iii) power dissipation
(b) Convert the following number to the given base: 04
(i) (62)10 = (?)2 = (?)8
(ii) (AFB)16 = (?)2 = (?)8
(c) Why NAND and NOR gates are called universal gates? 07
Explain with appropriate example.

Q.2 (a) Explain the half subtractor with logic circuit. 03

(b) Minimized the boolean expression using K-map 04
f (A, B, C, D) = ∑m (0, 1, 5, 6, 7, 8, 9) + d(10, 11, 12, 13, 14,
15)
(c) Design BCD to excess-3 converter. 07
OR
(c) Design a circuit which compare two binary number whether 07
A>B, A=B or A<B.

Q.3 (a) Draw the circuit of a J-K flip-flop. 03

(b) Describe the operation of a shift register with suitable 04
diagram.
(c) Design the four bit Johnson counter and explain the 07
operation.
OR
Q.3 (a) Explain different methods of Triggering of flip-flop. 03
(b) What are qualitative differences between parallel loading 04
and serial loading in shift registers?
(c) Design a 3 bit synchronous counter using JK flip flop. 07

Q.4 (a) How can we describe the resolution of a D/A converter? 03

(b) A 10-bit D/A converter provides an analog output which 04
has a maximum value of 10.23 volts. Find the resolution of
this D/A converter.
(c) Explain the working of R-2R ladder type D/A converter. 07
OR
Q.4 (a) Explain the types of A/D convertors. 03
(b) A 10-bit D/A converter has a step-size of 10 mV. Determine 04
the full-scale output voltage and the percentage resolution.

1
 (c) Describe the successive approximation A/D conversion 07
principle with the neat diagram, explain this type of A/D
converter.

Q.5 (a) Draw and explain the structure of a RAM cell. 03

(b) Implement using PLA 04
f1 = ∑m(0, 3, 4, 7)
f2 = ∑m(3, 5, 6, 7)
(c) Discuss in brief semiconductor memory organization and 07
its operation.
OR
Q.5 (a) Compare the SRAMs and DRAMs. 03
(b) Implement the following Boolean expressions using a 04
PROM.
f1 (x2, x1, x0) =  m (0, 1, 2, 5, 7)
f2 (x2, x1, x0) =  m (1, 2, 4, 6)

(c) What is a programmable LOGIC Array (PLA)? Describe 07

with a logic diagram the principle of operation of a PLA.
What are its advantages?

*************

2
Seat No.: ________ Enrolment No.___________

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER– III (NEW) EXAMINATION – SUMMER 2022
Subject Code:3130704 Date:18-07-2022
Subject Name:Digital Fundamentals
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) List out various logic families. Also list characteristics of digital IC. 03
(b) What is signal? Explain different types of signal. 04
(c) Implement the following Boolean function using MUX 07
a) F(A,B,C) = ∑(1,3,6)
b) F(A,B,C) = π(2,3,5)

Q.2 (a) Perform the binary subtraction using 2’s complement 03

(0111)2 - (1101)2
(b) Convert the decimal Number 250.5 to base 4 and base 8. 04
(c) Design a Combinational circuit that convert 8- 4 -2 -1 code to BCD 07
OR
(c) Explain various logic gates. 07

Q.3 (a) Compare Half adder and Full adder. 03

(b) Explain NAND gate as a Universal Gate. 04
(c) Implement 2-bit Magnitude comparator. 07
OR
Q.3 (a) Simplify Boolean function using K-MAP 03
F(A, B, C, D)=ABC’D’ + ABC’D + ABCD’ + AB’CD’
(b) Explain 4 bit Binary Parallel Adder. 04
(c) Explain Minterm and Maxterm. 07

Q.4 (a) Give the difference between sequential circuit and combinational 03
circuit.
(b) Explain Look-ahead Carry generator. 04
(c) Explain JK Flip-Flop. 07
OR
Q.4 (a) Explain NAND SR Latch. 03
(b) Explain clock triggering mechanism. 04
(c) What is race around condition (racing)? How to solve it? 07

Q.5 (a) Classify different types of digital to analog converters. 03

(b) Compare static RAM and dynamic RAM. 04
(c) List out different types of ROM. Also explain ROM. 07
OR
Q.5 (a) Discuss the application of shift registers. 03
(b) Explain working of counter. 04
(c) Describe operation of D/A converter with binary-weighted resisters. 07

***********