NAND Flash Applications

Design Guide

System Solutions from

Toshiba America Electronic Components, Inc.

Atsushi Inoue, Staff MTS, Memory Business Unit

Doug Wong, Staff MTS, Memory Business Unit

Revision 2.0
March 2004

TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.

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Copyright © 2004 by Toshiba America Electronic Components, Inc.

All Rights Reserved.

This NAND Flash Applications Design Guide and the information and know-how it contains constitute the exclu-
sive property of Toshiba America Electronic Components, Inc. (“TAEC”), and may not be reproduced or disclosed
to others without the express prior written permission of TAEC. Any permitted reproductions, in whole or in part,
shall bear this notice.

The information in this NAND Flash Applications Design Guide has been checked, and is believed to be reliable;
however, the reader understands and agrees that TAEC MAKES NO WARRANTY WITH RESPECT TO THIS
DESIGN GUIDE, ITS CONTENTS OR THEIR ACCURACY, AND EXCLUDES ALL EXPRESS AND IMPLIED
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All information in this NAND Flash Applications Design Guide is subject to change without prior notice, at TAEC’s
sole discretion.

All trademarks, trade names, product, and/or brand names are the property of their respective holders.

* The information contained herein is subject to change without notice.

* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA
products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA
products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook,” etc.
* The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These
Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”).
Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices,
etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk.
* The products described in this document may include products subject to foreign exchange and foreign trade laws.
* The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export. Any export
or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

1. History of Flash at Toshiba

TABLE OF CONTENTS
When Dr. Masuoka, who is now a professor at before the submission of the IEDM paper. Why Mr.
Tohoku University, joined Toshiba in 1971, he had Ariizumi suggested the term “Flash” was because the
1. HISTORY OF FLASH AT TOSHIBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
been thinking that the substitution of magnetic memory device could erase a large number of memory cells
2. HOW FLASH WORKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 would be indispensable for the development of semi- simultaneously, which made him imagine the Flash of a
conductor memory. camera. But no one, at the moment, could have
2.1 NAND VS NOR FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
dreamed that Flash memory would be used in digital
3. THE NAND FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 He also understood that the market size for memory cameras as it is today. So what was first called simulta-
is more dependent on its bit cost than its user-friendli- neously erasable EEPROM became known as “Flash”
3.1 PAGE READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
ness. For instance, let’s compare the market size from 1984. The memory cell area for the first proposed
3.2 PAGE PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 between DRAMs and SRAMs. SRAM is faster, requires Flash EEPROM was 64 sq. microns while a conven-
no refresh, and is very user-friendly, but the market size tional byte-erasable EEPROM cell at that time occu-
3.3 BLOCK ERASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
for DRAMs is much larger than that of SRAMs. The pied 272 sq. microns using the same lithography
4. HARDWARE INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 only reason why the DRAM market is larger is because design rule of 2 microns.
the cost of DRAMs is much lower than that of SRAMs.
5. LARGE BLOCK VS. SMALL BLOCK NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
This is the RAM story, but the ROM story is similar. Like In December of 1984, the first paper for the Flash
6. FAILURE MODE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 SRAM, the byte-EEPROM (electrically erasable pro- EEPROM was presented at IEDM in San Francisco. A
grammable read only memory) is very user-friendly, subsequent paper on a 256k bit Flash EEPROM was
6.1 BAD BLOCK IDENTIFICATION (INITIAL BAD BLOCKS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
because it can erase and program a single byte. But presented at ISSCC in San Francisco in February of
6.2 BLOCKS THAT FAIL DURING USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 its cost is so high that it cannot be widely adopted. A 1985. After that, Dr. Masuoka was interviewed by
mechanical hard disk, which can also be considered Business Week and the Flash EEPROM was reported
6.3 FAILURE MODES MECHANISM AND SYMPTOMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
to be a type of non-volatile memory, does not offer in Business Week on Mar. 25, 1985. On the news, Dr.
Permanent Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 byte programming, but does offer sector (sometimes R.D. Pashley of Intel was interviewed to provide coun-
referred to as block) programming and is widely used terpoints against the future of Flash EEPROM, but
Soft Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
because of low cost. What is required for hard disk afterwards, Intel stopped developing UV-EPROM (ultra-
7. MANAGING NAND FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 emulation is not the flexibility of byte programming, violet erasable programmable read only memory) and
but a low cost per bit. focused on Flash memory development. And Dr.
7.1 BAD BLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Pashley later became the General Manager of the
7.2 ERROR CORRECTING CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Based on the concepts above, Dr. Masuoka Flash memory division of Intel.
applied for a patent on simultaneously erasable
7.3 WEAR LEVELING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EEPROMs in 1980. Although a conventional byte-EEP- After Toshiba presented the 256k bit Flash EEP-
7.4 SOFTWARE DRIVERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ROM has two transistors per cell, a new memory cell, ROM at the ’85 ISSCC, Seeq developed a 128k bit
which consists of only one transistor, was proposed to Flash EEPROM and announced it at the ’87 ISSCC.
7.5 HARDWARE CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
reduce cost. To realize a one-transistor cell, the byte Seeq’s memory cell was programmed by hot electron
8. TIPS FOR USING NAND FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 erase scheme was dismissed, and a simultaneous injection and erased by field emission from the floating
8.1 MROM / NOR REPLACEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 multi-byte erase scheme was adopted. The develop- gate to the drain. Therefore, Seeq’s cell could be real-
ment of an actual test device was started in 1983 with ized by a dual polysilicon structure while Toshiba’s
8.2 TO PARTITION OR NOT TO PARTITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Dr. Masuoka’s colleagues: Mr. Asano and Mr. Iwahashi Flash EEPROM cell used a triple polysilicon structure
8.3 CONSIDERATIONS FOR PREPROGRAMMING NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 for the design, Mr. Tozawa, Mr. Komuro, Mr. Tanaka for due to the formation of the erase gate. Intel presented
the device technology, and supported by Mr. Suzuki, a 256k bit Flash EEPROM at the ’88 ISSCC. Intel
8.4 CONSIDERING MEMORY CARDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 the memory senior manager. Fortunately, the device adopted the same cell structure as that of the UV-
9. INTRODUCTION TO COMPACTFLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 was verified to be functional. In June of 1984, the first EPROM. It is programmed by the hot electron injection
paper was submitted to IEDM. At that time, Dr. Masuoka like a UV-EPROM and erased by the field emission
recognized that it must be the first simultaneously eras- from the floating gate to the source. In principal, this
able EEPROM in the world and thought about naming it concept is quite similar to that of the first proposed
with his colleagues. Mr. Ariizumi, one of his colleagues, Flash EEPROM by Toshiba.
* The information contained herein is subject to change without notice. proposed naming it “Flash” sometime in June of 1984,
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA
products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA
products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook,” etc.
* The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These
Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”).
Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices,
etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk.
* The products described in this document may include products subject to foreign exchange and foreign trade laws.
* The products contained herein may also be controlled under the U.S. Export Administration Regulations and/or subject to the approval of the U.S. Department of Commerce or U.S. Department of State prior to export. Any export
or re-export, directly or indirectly in contravention of any of the applicable export laws and regulations, is hereby prohibited.

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

2.How Flash Works

Like a UV-EPROM cell, a Flash EEPROM cell has eliminated, an electrically re-programmable non-volatile a new Flash configuration that reduces memory cell The power consumption of NAND Flash or NOR
a dual gate structure in which a floating gate exists memory can be realized by utilizing only one transistor area so that a lower bit cost can be achieved. In 1987, Flash is about one tenth that of a magnetic hard disk
between a control gate and a silicon substrate of a per cell. A UV-EPROM also simultaneously erases all Toshiba proposed the NAND Flash, and its NAND drive. Also, the seek time for semiconductor memories
MOSFET. A floating gate is perfectly isolated by an its bits, and is programmed by a hot electron injection structured cell arranged as eight memory transistors in is much faster than that of a magnetic hard disk.
insulator, e.g., silicon dioxide, so that the injected elec- mechanism. In this sense, UV-EPROM is similar to series. The NAND Flash cell array, fabricated by using However, NAND Flash and NOR Flash must be erased
trons cannot leak out of the floating gate after power is Flash EEPROM in functionality except that the erase conventional self-aligned dual polysilicon gate technol- before reprogramming, while a magnetic hard disk
removed. This is the basic storage mechanism for the operation is carried out by UV irradiation. ogy, had only one memory transistor, one forth of a requires no erasure. Therefore, in the case of continu-
Flash EEPROM non-volatile memory. The charge select transistor and one sixteenth of the contact hole ous programming where the seek time is negligibly
retention mechanism for Flash EEPROM is the same area per bit. This technology realizes a small cell area small, a magnetic hard disk drive can be programmed
as conventional UV-EPROM and byte-erasable EEP- 2.1 NAND vs NOR Flash without scaling down the device dimensions. The cell more quickly.
ROM. Like a UV-EPROM, a Flash EEPROM was origi- area per bit was half that of a DRAM using the same
nally programmed by a hot electron injection mecha- Current semiconductor memories achieve random design rule of 1µm (which was used for the 1M bit For both for NOR Flash and NAND Flash, the
nism, and like a byte-erasable EEPROM, it was erased access by connecting the memory cells to the bit lines DRAM). As a result, Toshiba realized that it was possi- endurance (which means the number of cycles a block
by field emission from a floating gate. Although the in parallel, as in NOR-type Flash. In NOR-type Flash, if ble for higher capacity NAND Flash to be developed or chip can be erased and programmed) is limited.
erase mechanism for a Flash EEPROM cell is the any memory cell is turned on by the corresponding earlier than DRAM (for the same density) by one In order to replace the UV-EPROM with Flash, an
same as that for a byte-erasable EEPROM cell, their word line, the bit line goes low (see figure 1). Since the process generation. In comparison, conventional EEP- endurance of 1,000 cycles was sufficient. It is estimated
basic uses as LSI memories are typically different. In a logic function is similar to a NOR gate, this cell ROM was behind DRAM by one process generation at that at least 1,000,000 cycles are required to replace a
Flash EEPROM, the whole chip can be erased simulta- arrangement results in NOR Flash. that time. magnetic hard disk drive. NOR Flash is typically limited
neously, while a byte-erasable EEPROM is erased only However, speedy access is not always required in to around 100,000 cycles. Since the electron flow dur-
one byte at a time. When the byte erase function is order to replace magnetic memory. The NAND Flash is As explained above, the most important character- ing hot electron injection into the floating gate during
istic of memory is the bit cost. In the case of a semi- programming is different from the one due to tunneling
conductor memory, the bit cost is dependent on the from the floating gate to the source during erasing,
NAND NOR memory cell area per bit. And since the cell area of oxide degradation is enhanced. However, in NAND
NAND Flash is smaller than that of NOR Flash, NAND Flash, both the programming and erasing is achieved
Flash has always had the potential from the start to be by uniform Fowler-Nordheim tunneling between the
Cell Bit Line Bit Line less expensive than NOR Flash. However, it takes a floating gate and the substrate. This uniform program-
Contact
Word line rather long time for a NAND Flash to read out the first ming and uniform erasing technology guarantees a
data byte compared to NOR Flash because of the wide cell threshold window even after 1,000,000
Word line resistance of the NAND cell array. Nonetheless, this cycles. Therefore, NAND Flash has better characteris-
time is still much faster than the seek time for a hard tics with respect to program/erase endurance. In some
disk by several orders of magnitude. Therefore, NAND recent scaled NOR Flash memories, their erasing
Array
Unit Cell Unit Cell
Flash is ideally positioned as a replacement for mag- scheme has been changed from source side erasing
netic hard disks. to uniform channel erasing, which is the same as the
NAND Flash.
The advantages of NAND Flash are that the eras-
ing and programming times are short. The program- From a practical standpoint, the biggest difference
Layout ming current is very small into the floating gate a designer will notice when comparing NAND Flash
because NAND Flash uses Fowler-Nordheim tunneling and NOR Flash is the interface. NOR Flash has a fully
Source line Source line for both erasing and programming. Therefore, the memory-mapped random access interface like an
power consumption for programming does not signifi- EPROM, with dedicated address lines and data lines.
2F 2F cantly increase even as the number of memory cells Because of this, it is easy to “boot” a system using
being programmed is increased. As a result, many NOR Flash. On the other hand, NAND Flash has no
2F 5F
NAND Flash memory cells can be programmed simul- dedicated address lines. It is controlled using an indi-
taneously so that the programming time per byte rect I/O-like interface and is controlled by sending com-
Cross-section becomes very short. Conversely, the NOR Flash can mands and addresses through an 8-bit bus to an inter-
be programmed only by byte or word, and since it uses nal command and address register. For example, a typ-
the hot electron injection mechanism for programming, ical read sequence consists of the following: writing to
it also consumes more power, and the programming the command register the “read” command, writing to
time per byte is longer. The programming time for NOR the address register 4 bytes of address, waiting for the
Cell size 4F2 10F2 Flash is typically more than an order of magnitude device to transfer the requested data in the output data
greater than that of NAND Flash. register, and reading a page of data (typically 528
Figure 1. NAND Flash vs. NOR Flash

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

bytes) from the data register. The NAND Flash’s opera- internal. Because NAND Flash is optimized for solid- The basic interface is fairly simple. When asserted • Command phase: With CLE=1, ALE=0, the com-
tion is similar to other I/O devices like the magnetic disk state mass storage (low cost, high write speed, high low, the chip enable (CE#) pin enables the NAND Flash mand byte 00h is placed on the I/O pins and WE#
drive it was originally intended to replace. But because erase speed, high endurance), it is the memory of to accept bytes provided to the I/O pins of the chip is brought low, then high. This stores the “read
of its indirect interface, it is generally not possible to choice for memory cards such as the SmartMediaTM, when write enable (WE#) is asserted low or enable the mode 1” command into the command register.
“boot” from NAND Flash without using a dedicated SDTM card, CompactFlashTM, and MemoryStickTM. output of a data byte when read enable (RE#) is assert-
state machine or controller. The advantage of the indi- ed low. When CE# is high, the chip ignores RE# and • Address phase: With CLE=0, ALE=1, the first
rect interface is that the pinout does not change with WE# and the I/O is tri-stated. The Command Latch address byte is placed on the I/O pins and WE# is
different device densities since the address register is Enable (CLE) pin and the Address Latch Enable (ALE) toggled. This first address byte “N” (called the col-
pin act as multiplexer select pins by selecting which umn byte in Figure 5) is usually set to 0 in order to
20V 0V internal register is connected to the external I/O pins. start reading from the beginning of the page. It is
There are only three valid states as shown in the possible to set N to any value between 0 and 255.
table below: Because the page is actually 528 bytes long, a dif-
ferent read command is used if you want output
0V 0V 20V 20V data to start from byte 256-511 (read mode 2—
ALE CLE Register Selected command byte 01h is used instead of 00h). A third
0 0 Data register read command is used if you want output data to
N N N N 0 1 Command register come from bytes 512-527 (read mode 3—com-
(Tunneling) (Tunneling) 1 0 Address register mand byte 50h is used instead of 00h). It should
1 1 Not defined be noted that the full page is transferred from
P (Si-Sub) P (Si-Sub)
memory into the register. The value N, in conjunc-
0V 20V Table 1. NAND Register Selection. tion with the read command used, simply sets the
Programming Erasing output data pointer within the register. The
The key to understanding how the NAND Flash address bytes which follow after column byte N,
Figure 2. NAND Flash Cell Biasing.
operates is the realization that in the NAND Flash, the indicated by Row1 and Row2 in the figure, are
read and program operation takes place on a page used to set the page within a block (lowest 5 bits
3. The NAND Flash Interface basis (i.e., 528 bytes at a time for most current NAND in byte Row1), and the block within the device. In
devices) rather than on a byte or word basis like NOR the higher density NAND devices, the address
The pinout of the standard NAND Flash in the TSOP I package is shown in figure 3 below. Flash. A page is the size of the data register. The erase phase is 4 bytes long rather than 3.
operation takes place on a block basis (for most current
NAND devices, the block size is 32 pages). There are • Data Transfer phase: CLE and ALE are set to
NC 1 48 NC CLE: Command Latch Enable
NC 2 47 NC
only three basic operations in a NAND Flash: read a zero while the chip goes busy in preparation
NC 3 46 NC
ALE: Address Latch Enable page, program a page, and erase a block. Let’s exam- for data readout. During the busy period, the
NC 4 45 NC CE#: Chip Enable ine each of these operations in more detail. ready/busy pin (R/B) goes low for up to 25
NC 5 44 I/O 8 microseconds while data is being read from the
WE#: Write Enable
GND 6 43 I/O 7 memory array and transferred into the data
R/B 7 42 I/O 6 RE#: Read Enable 3.1 Page Read register. During this period, it is important that
RE# 8 41 I/O 5 chip enable is held low to keep the read operation
WP#: Write Protect
CE# 9 40 NC
In a page read operation, a page of 528 bytes is from being stopped mid-cycle (note: this restric-
NC 10 39 NC R/B: Ready/Busy
transferred from memory into the data register for out- tion is removed in a new family of NAND Flash
NC 11 38 NC
GND: Test Input (grounded) put. The sequence is as follows: devices known as CE don’t care).
Vcc 12 37 Vccq
Vss 13 36 Vss I/O: Input Output
NC 14 35 NC • Read Out phase: Once R/B returns high, data is
Vcc: Positive Supply (core) Register Data-Out
NC 15 34 NC available in the data register for read out. The first
CLE 16 33 NC Vccq: Positive Supply (I/O) tR data byte output is byte N. Each RE# pulse reads
ALE 17 32 I/O 4 Address out the next byte in the register. Once the last byte
Vss: Negative supply (ground) N
WE# 18 31 I/O 3 (D527) is read out, standard NAND Flash will auto-
WP# 19 30 I/O 2
matically go busy (another data transfer phase) in
NC 20 29 I/O 1 Page Address
Cell preparation for reading out the next page (with no
NC 21 28 NC
NC 22 27 NC
additional command or address input). In the data-
NC 23 26 NC sheet, this is called sequential read. If this is not
NC 24 25 NC desired, chip enable must be brought high (Note:
For the CE don’t care family of NAND Flash, the
Figure 4. Page Read Operation. automatic sequential read function does not exist).
Figure 3. NAND Flash Pinout.

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

low low
CE CE

ALE ALE

CLE CLE
WE WE

RE RE
high
Command Command Command
DN DN+1 D527
I/O1~8 00H Col Row1 Row2 I/O1~8 80H Col Row1 Row2 D0 D1 D527 10H

Wait(tPROG)
R/B R/B
Wait(tR) Address Address Address Data-In Data-In Data-In
Address Address Address Data-Out Data-Out Data-Out
N

Figure 5. Page Read Timing Diagram. Figure 7. Page Programming Timing Diagram.

Why is a page 528 bytes long? Since the original • Command phase: With CLE=1, ALE=0, the com- • Data Input phase: CLE and ALE are set to zero, Register Erase
intent of the NAND Flash was to replace magnetic hard mand byte 80h is placed on the I/O pins and WE# and data bytes are written into the data register.
disk drives, the intention was for the page to be big is brought low, then high. This stores the “serial If you try to write more bytes than the page size,
enough to store 1 sector (512 bytes) worth of data with data input” command into the command register. the last byte in the register will contain the last
16 bytes extra for overhead such as error correcting This command also resets the register to all “1”s byte written.
code. Because the use of ECC is common with NAND (all FFh). Page Address
Flash, read mode 1 is the most often used read com- • Address phase: With CLE=0, ALE=1, the first • Program phase: With CLE=1, ALE=0, the auto
mand as it enables one to read the entire 528 byte page. address byte is placed on the I/O pins and WE# is program command (10h) is written to the com- Cell
toggled. This first address byte “N” (called the col- mand register. The device then goes busy for
umn byte in the figure below) is usually set to 0 in tPROG (typically 250us). During this busy period,
3.2 Page Program order to start writing from the beginning of the page. even if chip enable goes high, the device will Figure 8. Block Erase Operation.
However, like the read command, it is also possible finish programming.
In a page program operation, a page of 528 bytes to set N to any value between 0 and 255. The first
is written into the data register and then transferred into byte that is written in the data phase will then • Timeout Check phase: Although not shown on the • Command phase: With CLE=1, ALE=0, the com-
the memory array. The sequence is as follows: overwrite the FFh at location N in the register. If diagram, it is typical to check the status after pro- mand byte 60h is placed on the I/O pins and WE#
you desire to overwrite the register values starting gramming. If the device was unable to program a is brought low, then high. This stores the “auto
at byte N (N=256-527), you need to precede the bit from 1 to 0 within the time allowed, the block erase” command into the command register.
80h command with either 01h or 50h (the read pass/fail bit returned by the status read command
mode 2 and read mode 3 commands). It should will indicate a failure. If this happens, the block • Address phase: With CLE=0, ALE=1, two address
Register Data-In
be noted that the full page is transferred from the should be considered bad because the device bytes are written into the address register. Notice
register into the memory each time the program has already attempted to program the bit multiple that only two address bytes are required. There is
command (10h) is received. However, since the times before the internal timeout occurred. no “column” byte as in the read and program
tPROG
serial data input command (80h) resets the regis- operations. In the first address byte (Row1), only
Page Address ter to all “1s,” bytes in the register that are not the upper 3 bits are used. The lower 5 bits of
overwritten with data will remain “1” and should not 3.3 Block Erase Row1 are reserved for the page within the block
Cell affect the memory contents. Like the read mode, (for device with 32 pages per block) and during a
the address bytes which follow after column byte In a block erase operation, a group of consecutive block erase operation, all pages within the block
N, indicated by Row1 and Row2 in the figure, are pages (typically 32) is erased in a single operation. will be erased; therefore, the value of the least
used to set the page within a block (lowest 5 bits While programming turns bits from “1” to “0”, block era- significant 5 bits are actually Don’t Care. The upper
Figure 6. Page Program Operation. in byte Row1), and the block within the device. In sure is necessary to turn bits from “0” back to “1”. In a 3 bits of Row1 and the 8 bits of Row2 determine
the higher density NAND devices, the address brand new device, all usable (good) blocks are in the the block that will be erased. Because this is only
phase is 4 bytes long rather than 3 (Figure 7). erased state. 11 bits (2048 blocks max.), higher density NAND
devices require 3 address bytes (Figure 9).

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

CE
low Command In/Address In

tCLS/tALS tCLH/tALH
CLE/ALE
ALE
tCS tCH

Symbol Spec
CLE CE
Setup tCLS 0ns
WE tWP tALS 0ns

WE tCS 0ns

tALS/tCLS tALH/tCLH tDS 20ns

RE Hold tCLH 10ns
high
Command Command ALE/CLE tALH 10ns
tCH 10ns
I/O1~8 60H Row1 Row2 D0H
tDS tDH tDH 10ns
Other tWP 25ns
Wait(tERASE) I/01 to I/08
R/B
Address Address

Set up time for ALE, CLE, -CE is based on the falling edge of -WE, hold time base on the rising
Figure 9. Block Erase Timing Diagram. edge of -WE.
Set up time for I/0 is based only on the rising edge of -WE.

• Erase phase: With CLE=1, ALE=0, the auto block remain continuously asserted low during the read Figure 10. NAND Flash Timing Requirement for Address/Command Inputs.
erase confirm command (D0h) is written to the cycle busy period. For chip enable don’t care
command register. The device then goes busy for NAND, this restriction is removed.
tERASE (typically 2ms). During this busy period, • Signal ALE is shown to be high continuously
even if chip enable goes high, the device will between individual write cycles. Actually, in The data read cycle is shown below. Not shown Don’t Care during the busy period preceding the data
finish erasing the block. between write cycles, ALE can go low as long on the diagram are CLE and ALE, which are both read cycle. For standard NAND, chip enable must be
as the setup and hold times are met. assumed to be low. This diagram is for the Chip Enable held low during the busy period preceding data read out.
• Timeout Check phase: Although not shown on the Don’t Care NAND; notice that the chip enable state is
diagram, it is typical to check the status after These timing diagrams are relatively easy to
erasing to make sure a timeout (erase failure) did achieve if you connect the NAND Flash to a state
not occur. If the device was unable to erase the machine. However, if you intend to connect the NAND
block successfully within the time allowed, the to a microprocessor bus directly, some glue logic will be
Data Read
pass/fail bit returned by the status read command necessary. There are several ways to connect the
tRC
will indicate a failure. If this happens, the block NAND Flash to the host:
Symbol Spec
should be considered bad because the device CE
tRC 50ns
has already attempted to erase the block (and 1) Using general purpose input/output (GPIO) pins tRP 35ns
verify it is erased) multiple times before the 2) Using a memory-mapped interface with glue logic tREH 15ns
tRP tREH tRP tCH
internal timeout occurred. 3) Using a Chip-Enable Don’t Care NAND tREA 35ns
tCEA 45ns
RE
tOH 10ns
The key requirement in all cases will be to meet the tOH tOH
tRR 20ns
4. Hardware Interfacing timing diagram restrictions. For example, the setup and tREA tRHZ tREA tRHZ
hold times for CLE, ALE, CE#, and data input with tCEA

When you examine the timing diagrams in the respect to WE# are shown below. Note that CLE, ALE, I/0 to I/08
datasheets for standard NAND Flash devices, you will and CE# are not required to be held in a particular
tRR
notice that there was the expectation that NAND Flash state outside the interval. The practical implication is
would be connected to a controller chip or specialized that CLE and ALE can be connected to the host
interface state machine because of two characteristics: address lines in order to select the internal register
RY/BY
connected: data register, command register, or
• The chip enable is shown asserted low continu- address register.
ously during the period of the operation. Actually,
chip enable can be deasserted in between individ- Figure 11. NAND Flash Timing Requirement for Data Reads.
ual write cycles and read cycles; however, it must

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Using GPIO Pins The GPIO pin controlling the chip enable is asserted low at the beginning of the NAND read, program, or
erase cycle and is not deasserted until the end of the entire cycle. Note that the read enable and write enable to
Using GPIO pins to control the NAND signals (such as ALE, CLE, /CE, /WE, and /RE) offers great flexibility in the NAND is qualified by an address decoded chip select. In this way, only read or writes intended for the NAND
meeting the NAND timing requirements. However, unless the speed requirements are relatively low, the perform- actually toggle the NAND’s read enable or write enable pins. When /CS is deasserted, the glue logic deasserts
ance is likely to be a fraction of the NAND’s potential performance. Also, GPIO pins are often scarce in a system, /RE and /WE, which tri-state the NAND’s outputs.
so this may not be an acceptable use of a scarce resource. However, although adding GPIO pins to the interface
may involve additional cost, it may be easier to control the NAND for some platforms.
Using a Chip Enable Don’t Care NAND
Vcc

Perhaps the simplest method to connect NAND Flash to a microprocessor bus is the use of a Chip Enable
Don’t Care (CEDC) NAND Flash instead of a standard NAND Flash. The main difference between standard
GPIO /RB NAND and CEDC NAND is that chip enable does not need to be continuously asserted low during the read busy
period. The removal of this restriction allows chip enable to be deasserted between individual read or write cycles
GPIO /CE and enables the direct connection of the NAND to a microprocessor with no glue logic. The NAND chip enable will
GPIO ALE
Standard or work as expected and qualify the read enable and write enable signals. The only function that was removed from
Chip Enable standard NAND to make this possible was the elimination of the automatic sequential read function,
GPIO CLE DC NAND
which was rarely used anyway.
GPIO /RE Vcc

GPIO /WE

D0-7 I/O 1-8 GIPO /RB

/CS /CE
Connected only to NAND
TC582562AXB
A1 ALE
Shared by other memory devices CEDC NAND
A0 CLE
Figure 12. Physical Connection When GPIO are Used.
/OE /RE

Memory-Mapped Interfacing using Glue Logic /WE /WE

In order to interface to a standard NAND Flash device, it is necessary to use a latched signal to drive the
D0-7 I/O 1-8
NAND’s chip enable. The simplest approach is to use a latched GPIO pin.
Vcc
Connected only to NAND
Shared by other memory devices

A1 ALE Figure 14. Connection Using Chip Enable Don’t Care NAND.
A0 CLE

GPIO /RB
Standard or Unlike NOR Flash, NAND Flash does not have any dedicated address pins to be connected to the microprocessor
Chip Enable address pins. Therefore, most people think that a direct interface between NAND and a microprocessor is difficult.
GPIO
/CE DC NAND
However, as shown in Figure 14, the interface does not require any glue logic. Toshiba has demonstrated this glue-
/CS less NAND connection between the Toshiba TX4927 MIPS processor and the Toshiba TC582562AXB NAND Flash.
/RE
/OE

/WE
/WE On the TX4927 demonstration board, the timing for the chip select (/CS) of the TX4927 was modified as
described in Figures 15 and 16. This was easily done by changing the register values that controlled the timing for
D0-7 I/O 1-8 /CS. Most high end processors with integrated chip select circuitry have programmable timing. With CLE connect-
ed to A0 and ALE connected to A1, the software driver for the NAND need only access 3 address locations.
Connected only to NAND
Access to the base address for /CS accesses the NAND data register by setting CLE=0 (A0=0) and ALE=0
(A1=0). Writes to base address+1 writes the NAND command register by setting CLE=1 (A0=1) and ALE=0
Shared by other memory devices
(A1=0). Writes to base address+2 writes the NAND address register by setting CLE=0 (A0=0) and ALE=1 (A1=1).
Figure 13. Physical Connection When Memory Mapped.

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Command In/ Address In (120ns/cycle) 5. Large Block vs. Small Block NAND

With the introduction of the CEDC NAND, interfac- in a block size that is 8 times larger. The first of these
GBUSCLK = 100MHz = 10ns
ing to NAND Flash has never been easier. new large block NAND Flash devices is the 1 Gbit-
The bus speed is set to 1/4 of the GBUSCLK SYSCLK = 40ns
TC58NVG0S3AFT05. Note that all large block devices
40ns 40ns 40ns In the current NAND architecture, each page con- will also have the CEDC feature. The increased page
S1 S2 S3 sists of 528 bytes, and each block consists of 32 and block size will enable faster program and erase
SYSCLK pages. Future NAND devices will use the large speeds in future high density NAND Flash.
page/large block structure in which a page in a single
CE*
Symbol Spec 4927 memory array will be 2112 bytes (4 times larger) and a Although the internal architecture will be different,
ADDR[19:0] Setup tCLS 0ns 40ns block will consist of 64 pages (2 times larger) resulting the external physical interface will be the same.
tALS 0ns 40ns
ACE* tCS 0ns 40ns
tDS 20ns 80ns
OE*/BUSSPRT*
Hold tCLH 10ns 40ns Density 0.16 micron 0.13 micron 0.13 micron
tALH 10ns 40ns
SWE* Small Page (528 B) Small Page (528 B) Large Page (2112 B)
tCH 10ns 40ns
BWE* f c f tDH 10ns 40ns Small Block (16kB) Small Block (16kB) Large Block (128kB)
c
Other tWP 25ns 40ns 64 Mb TC58V64BFT (standard) N/A N/A
BE* f f
128 Mb TC58128AFT (standard) TC58DVM72A1FT00 (standard) N/A
DATA[15:0]
TC581282AXB (CEDC) TC58DVM72A1XB11 (CEDC) N/A
ACK* 256 Mb TC58256AFT (standard) TC58DVM82A1FT00 (standard) N/A
TC58256AXB (CEDC) TC58DVM82A1XB11 (CEDC) N/A
* BWE, BE, ACK is not used
512 Mb TC58512FT (standard) TC58DVM92A1FT00 (standard) N/A
TH58DVM92A1XB11 (CEDC) N/A
Figure 15. Command In Address Timing Generated by TX4927. 1 Gb TH58100FT (standard) TC58DVG02A1FT00 (standard) TC58NVG0S3AFT05 (CEDC)
2 Gb N/A N/A TH58NVG1S3AFT05 (CEDC)
Data Read (120ns/cycle)
Note: CEDC = Chip Enable Don’t Care

Table 2. Toshiba NAND Flash Product Families.

40ns 40ns 40ns
S1 S2 S3
SYSCLK
Therefore, in most cases, only the Flash software needs to be updated in order to use these new devices.
CE*

ADDR[19:0] Symbol Spec 4927

tRC 50ns 120ns The effective read speed of the large block NAND devices is similar to the small block devices:
ACE* tRP 35ns 40ns
tREH 15ns 80ns
OE*/BUSSPRT* Read Time = 6 cycles x 50ns + 25 µs + 2112 cycles x 50ns = 131 µs
tREA 35ns approx 80ns
tCEA 45ns approx 80ns
Read Speed = 2112 bytes/131 µs = 16.1 Mbytes/sec
SWE*
tOH 10ns -(*1)

BWE* f The effective write speed of the large block NAND devices is more than 3 times faster than small block
NAND devices.
BE* f c f

DATA[15:0] Write Time = 5 cycles x 50ns + 2112 cycles x 50ns + 1 cycle x 50ns + 200µs = 306 µs
Write Speed = 2112 bytes/306µs = 6.9 Mbytes/sec
ACK*

The effective erase speed is nearly 8 times faster than small block NAND devices.

Data Latch Erase Time = 4 cycles x 50ns + 2ms = 2ms

* BWE, BE, ACK is not used Erase Speed = 128kB/2ms = 64 Mbytes/sec
(*1) Data latch point is within OE low, so not an issue

Figure 16. Data Read Timing Generated by TX4927.

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6. Failure Mode Overview

6.1 Bad Block Identification (Initial Bad Blocks) During outgoing testing and burn-in testing, blocks 6.2 Blocks that Fail During Use 6.3 Failure Modes Mechanism and Symptoms
that are considered bad by Toshiba are marked with a
The NAND Flash was designed to serve as a low 00h in byte 0x205 (byte 517) in each page of a bad As mentioned in the previous section, all Flash Although random bit errors may occur during use,
cost solid state mass storage medium. In order to block (this is the same as the SmartMedia format for memory has a finite lifetime and will eventually wear this does not necessarily mean that a block is bad.
achieve this goal, the standard specification for the marking bad blocks). Toshiba determines that blocks out. Since each block is an independent unit, each Generally, a block should be marked as bad only if
NAND allows for the existence of bad blocks in a cer- are bad by performing extensive pattern testing over block can be erased and reprogrammed without affect- there is a program or erase failure. The four main fail-
tain percentage. A bad block list (or bad block table) both temperature and voltage extremes. ing the lifetime of the other blocks. For NAND memory, ure modes that can be distinguished as “permanent
that can be updated needs to be maintained in the sys- each good block can be erased and reprogrammed failures” or “soft errors” are described below.
tem. The bad block table can either be stored in one of The cause of bad blocks could be a number of more than 100,000 to 1,000,000 times typically before
the good blocks on the chip, or on another chip in the reasons (decoder failure, word line failure, memory cell the end of life. This is described in Toshiba’s NAND Permanent Failures
system such as RAM. A bad block table is also required failure), so once the bad blocks have been located, datasheet.
because unlike magnetic media, Flash memory does Toshiba recommends that the bad blocks no longer be Write/Erase Cycle Endurance—This error may be man-
not possess infinite write/erase capability; there is a accessed. To locate the bad blocks on a brand new The primary wear out mechanism is believed to be ifested as a cell, page, or block failure which is detect-
finite number of write and erase cycles that all types of device, read out each block. Any block that is not all excess charge trapped in the oxide of a memory cell, ed by doing a status read after either an auto program
Flash memory can achieve. Because all Flash memory FFh (all 1s) in byte 517 (starting from byte 0) of the 1st and the net effect is that erase times increase until an or auto block erase operation (Figure 18).
will eventually wear-out and no longer be useable, a page of a block is a bad block. The figure below is a internal timer times out (Narrowing Effect). The pro-
bad block table needs to be maintained to track blocks flowchart that shows how bad blocks can be detected gramming time seen by the user actually decreases Soft Errors
that fail during use. by doing a read check on each block. slightly with an increasing number of total write/erase
cycles, so the device’s end of life is not characterized Over Programming—This is caused when the threshold
Allowing for the existence of bad blocks increases Once you erase a block, the non-FF bytes will also by program failures. Generally, only a severe device voltage of a “0” data cell becomes too high as a result
the effective chip yield and enables a lower cost. The be erased. If this occurs, re-identifying the bad blocks failure can cause a page program failure. of excess programming current. Normally, all threshold
existence of bad blocks does not affect the good blocks will be difficult without testing at different temperatures voltages are below a bias voltage (Vbias) so that the
because each block is independent and individually and voltages and running multiple test patterns, so if Therefore, blocks should be marked as bad and no application of Vbias to unselected pages will enable
isolated from the bit lines by block select transistors. the list of bad blocks is lost, recovering bad block loca- longer accessed if there is either a block erase failure them to turn on (Figure 19). If the threshold voltage of a
tions is extremely difficult. or a page program failure. This can be determined by cell is too high (Figure 20), the bias voltage that is sup-
doing a status read after either operation. The status posed to be high enough to turn on any cell during the
read command is used to determine the outcome of the read cycle is insufficient, so the cell never turns on
Start Read Check: To verify the column address 517 previous erase or program operation. Block erase oper- (Figure 21). Therefore the error occurs during a pro-
byte of 1st page in the block with FF (Hex)
ations are automatically verified, so the entire block is gram, but can only be detected by reads. The resultant
FFh if the status bit indicates the erase operation error symptom is that all cells on that bit line in the
passed. For programming, the status bit indicates the block read out as “0,” so in the worse case scenario, if
Block =1
program operation passed if all zeros (“0”) in the data this bit is supposed to be “1” for all other pages in the
register are correctly programmed into memory. One block, there will be a one bit failure for each page in the
(“1”) bits in the data register are not verified and are block. This condition is cleared by a block erase.
Read Check
ignored. Therefore, if “0s” are already programmed into
a page in memory, all program operations to that page, Program Disturb—In this failure mode, a bit is uninten-
Pass regardless of the data in the data register, would pass. tionally programmed from “1” to “0” during the program-
By not verifying “1s,” partial page programming is possible. ming of a page. The bit error may occur either on the
Block = Block +1 Bad Block *1 page being programmed or on another page in the
block. Bias voltage conditions in the block during page
programming can cause a small amount of current to
tunnel into memory cells. Multiple partial page pro-
gramming attempts in a block can aggravate this error
No
Last Block symptom. Since this error is caused by the soft pro-
gramming of memory cells, the condition is removed by
Yes block erasure.

End Program disturb effects are also worsened by ran-

domly programming pages in a block. Therefore, the
datasheets for NAND Flash now require programming
*1. No erase operation is allowed to bad blocks
pages in sequential order only (from lowest page
address to highest page address).
Figure 17. Bad Block Test Flow.
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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

Vpp (Program)
Vth
Programmed Cell Erased Cell
"0" Data "1" Data Over programmed bit
VBias —

n n n n
+ Data "0"

p-well p-well

Vpp (Erase)

- Data "1"
Write/Erase
Leak in oxide
Endurance Stress
R1

R2
bit, page,
n n n n
or block failure

Figure 20. Programmed Bit Exceeding VBias.

p-well

Figure 18. Write/Erase Endurance.

Bit Line
Bit Line [V] [V]
Bit Line Bit Line
Bit Line Pre-charge Over Programmed Cell Bit Line Pre-charge
Voltage Voltage
"0" "0"
Unselected page = Vbias: Tr = ON
Unselected page = Vbias: Tr = ON

Unselected page = Vbias: Tr = ON

{
Selected page = 0 Volt: Tr = ON if "1"data
OFF if "0"data "1"
Selected page = 0 Volt: Tr = ON
But because above cell does not
turn on, the current does not flow.

0 Unselected page = Vbias: Tr = ON

Unselected page = Vbias: Tr = ON Time 0 Time

The sense amp senses the bit line voltage The sense amp senses "0" data for cells that are affected
and determines "1" or "0" by over programmed cell.

Figure 19. Normal Read Operation. Figure 21. Read Operation with Over Programmed Cell.

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

Data Retention—A memory may change its state after a certain amount of storage time. This is due to charge
VBL = 0V VBL = 10V VG = 20V VG = 20V VG = 10V injection or charge leakage (Figure 24).
Tr1 Tr2 Tr3

VG= 10V
Tr1 Tr2
VG = 20V
(selected page)
Tr3 n n n n n n
VG = 10V

p-well p-well p-well

n n n n
VG = 10V

VBL = 10V
Intentional Weak programming stress Storage
p-well p-well
Program "1" "0"
"0" data "1" data

Tr2, Tr3: Weak program stress Possible unintentional program "1" "0"

Figure 22. Bias Condition During Program and Program Disturb Conditions.

n n n n
Read Disturb—In this failure mode, a read operation can disturb the memory contents causing a “1” to change to
a “0.” The bit error occurs on another page in the block, not the page being read. During a read operation, pages
p-well Storage p-well
are read by applying zero volts to the selected word line. All other pages in the block are biased to a positive volt-
age (Vbias) so that their memory cells will turn on regardless of whether they have been programmed or not. This "1" data "0" data
bias potential causes a tiny amount of charge to flow. After a large number of read cycles (between block erases),
the charge can build up and can cause a cell to be soft programmed from “1” to “0.” Block erasure removes
the charge. Figure 24. Data Retention.

7. Managing NAND Flash NAND Flash devices have a minimal amount of redun-
Bit Line VBias dant memory blocks because it was always expected
In order to use NAND Flash effectively, the NAND that an intelligent controller would ignore the bad
Flash must be managed by some kind of external con- blocks. Since NAND Flash would be used for solid
troller. This may be done either by software executing state mass storage, it was expected that blocks would
VBias on the host (e.g. a device driver), or by firmware exe- eventually wear out; therefore, it was expected that the
VBias cuting on a dedicated microcontroller (e.g. a USB or system be able to handle bad blocks that would form
n n ATA controller). This is necessary in order to make during use.
0V
(selected page) the NAND Flash appear to the system as an ideal
block device. The standard factory location for the bad block byte
p-well is byte 517 (the 518th byte) of a NAND page. If this
VBias byte is FFh, the block is good, otherwise, the block is
Very weak program stress 7.1 Bad Block Management bad (typically indicated by 00h). This format for marking
bad blocks is from the SmartMedia card (NAND Flash
Continuous read without Possible unintentional program "1" "0" In a brand new device, the standard NAND Flash in a removable card package) and was standardized by
erase in between specification allows for the existence of initial bad the SSFDC Forum (Solid State Floppy Disk Card – the
blocks. Standard NOR Flash devices have extra spare former name of SmartMedia). If additional bad blocks
memory blocks that are used to replace bad blocks, but form during use, the block is marked as bad. Generally,
Figure 23. Read Disturb.

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 NAND FLASH APPLICATIONS DESIGN GUIDE NAND FLASH APPLICATIONS DESIGN GUIDE

this is possible even if the block being marked was drive, the physical areas of the Flash that contain the
considered bad by the factory. To distinguish between FAT and directory would be worn out first, leading to Product Name Company/Sponsor Website
factory marked bad blocks and blocks that go bad during early failure of the file system stored on the Flash. In F1Pack Angel & Jet Tokyo Electron http://tmg-eng.teldevice.co.jp/f1pack.html
use, two flag values are defined in the SmartMedia for- order to spread out the writes across as much of the FlashFX Datalight http://www.datalight.com
mat: 00h (for initial factory marked bad blocks) and F0h Flash as possible, a wear leveling algorithm is imple- JFFS2 Red Hat http://sources.redhat.com/jffs2/
(for blocks that go bad during system use). mented by the controller (software or firmware in a
NAND File system Kyoto Software Research Contact Toshiba http://www.toshiba.com/taec/
hardware controller) which translates a logical address
An alternative approach to the “in block” method of to different physical addresses for each rewrite. smxFFS Micro Digital http://www.smxinfo.com
keeping track of bad blocks is to maintain a bad block Generally, this logical to physical lookup table is imple- TargetFFS-NAND Blunk Microsystems http://www.blunkmicro.com/ffs
table. However, where do you store a bad block table mented in RAM and is initialized at power up by read- TrueFFS M-Systems http://www.m-sys.com
since that block could be bad? For NAND TSOP ing each physical block in the NAND Flash to deter- YAFFS Toby Churchill http://www.aleph1.co.uk/armlinux/projects/yaffs/
devices only, the first block of the NAND Flash (block 0) mine its logical block value.
is guaranteed to be good. Thus, Block 0 could be used Table 3. Sampling of NAND Flash Software Drivers.
to hold a bad block table if desired. However, at power Ideally, wear leveling is intrinsic to the file system
up, many systems simply scan the first page of each itself. Several new file system device driver programs
block to determine whether they are good or bad and exist, which write new data sequentially rather than 8. Tips for Using NAND Flash There is one question that often comes up: “Is ECC
build a bad block table in RAM. overwriting a fixed location. These device drivers typi- really necessary?” After all, the likeliest cause of a bit
cally execute on the host processor and use a tech- 8.1 MROM / NOR Replacement error is during the programming process. For example,
nique known as journaling. Two examples of journaling if you program a block, then verify it has no errors, how
7.2 Error Correcting Code systems for Flash memory are JFFS2 (Journaling In many cases, the intended use of the NAND reliable is the data? In these ROM-like applications
Flash File System 2) and YAFFS (Yet Another Flash Flash is to act as a large read-only memory. There are where the write/erase cycles are very low, the actual
The use of an error correcting code is essential in File System), which automatically spread out wear by two problems to consider. First, some type of bootstrap failure rate for a block is about 3 ppm after 10 years
order to maintain the integrity of stored code. Soft writing sequentially to free Flash space. See the web- ROM is necessary (unless the processor has a built-in (i.e. 3 blocks out of every million blocks will have a bit
errors (especially during programming) occur at a rate sites in Table 3 for further information. NAND controller state machine) since NAND Flash is error after 10 years) in which a block failure is defined
of approximately 1E -10 or 10 -10 or about 1 bit per 10 bil- not a random access device. The bootstrap ROM will as a single bit error. This result was derived from test-
lion bits programmed. Single bit correcting (two bit error typically be MROM or NOR Flash, although some ing 29,708 pieces of 512Mb NAND (0.16um) by writing
detecting) Hamming code is sufficient for NAND Flash. 7.4 Software Drivers processors have the ability to boot from a serial EEP- a checkerboard pattern into blocks and storing at 125C.
Toshiba has developed C sample code for implementing ROM. The bootstrap ROM code’s job is to copy code Since there will be a non-zero data retention failure
Hamming code. It is available in a separate document Software drivers for managing NAND Flash are from the NAND Flash into system RAM. The second rate, you should limit the amount of code to 1 block to
entitled, The SmartMediaTM ECC Reference Manual. becoming available from a variety of sources. There problem, the existence of initial bad blocks that must be achieve a low ppm probability of failure.
are open source developments such as JFFS2 and skipped over, is handled by the bootstrap ROM code.
YAFFS, as well as a number of drivers available from Of course for systems without a significant amount of It is taken for granted that NAND Flash is not
7.3 Wear Leveling third parties. The table below lists the sources of NAND RAM space, shadowing code from the NAND into RAM bootable (at least for the moment) because of the lack
Flash driver software we are currently aware of or have is not a viable option. However, for most systems run- of separate address and data lines, but there actually is
If Flash memory had infinite write/erase endurance, discovered on the web. ning on a 32 bit microprocessor and running an indus- a variant of NAND Flash that is! Co-developed by
wear leveling would not be necessary. However, unlike trial strength real-time OS, significant amounts of RAM Toshiba and M-Systems, the monolithic DiskOnChip®
magnetic media, Flash memory eventually wears out (SDRAM) are likely to be available, and shadowing from has a true random access type of interface (13 address
and no longer programs or erases in the allotted 7.5 Hardware Controllers NAND Flash would be a very cost effective solution. lines, 16 data lines, chip enable, write enable, output
amount of time. Because the design of typical file sys- enable, etc.) in a TSOP or BGA package. A small boot-
tems assumed the characteristics of magnetic media, There are a number of sources for hardware con- Typically, the bootstrap ROM code would be written strap loader program (1kB or 2kB) can be executed
certain physical locations may be repeatedly rewritten. trollers for NAND Flash. To date, the main application in assembly language and should do minimal system directly from the DiskOnChip® without shadowing.
For example, in the DOS FAT file system, the FAT and for these controllers has been for use inside Flash initialization like setting up chip selects and initializing TrueFFS® software drivers have been written by M-
directory areas must be modified multiple times each memory cards such as CompactFlash, USB drives, the DRAM controller. Then the bootstrap ROM code Systems for the following operating systems: Windows
time a file is written or appended. When multiplied by or Flash memory card reader/writers. Manufacturers would: CE, Linux, VxWorks, Symbian, Windows NT, PSOS,
the thousands of files in a typical file system, the FAT include SST, Cypress, Standard Microsystems Corp., QNX, Nucleus, and DOS.
and directory areas of the disk will experience vastly and many others. 1. Read the first page of a NAND block and, exam-
more writes than any other area of the disk. ine the bad block mark location
When Flash memory is used to emulate a disk 2. Determine whether the block is good or not
3. If good, copy the data from the NAND Flash into
system DRAM and correct the data if necessary
4. If bad, skip over the block
5. If additional blocks need to be transferred,
repeat the process

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8.2 To Partition or Not to Partition block distribution will vary from chip to chip, the last 9. Introduction to CompactFlash The CompactFlash card is essentially a solid state
physical block programmed will differ. If the second par- ATA disk drive. To control an ATA disk drive, one writes
In the previous section, the NAND Flash is used tition (i.e. file system partition) is to be written starting The CompactFlashTM card is a small, removable, to the task file registers. The values put into these task
exclusively as a ROM in which a file system is unnec- at the same physical address in every chip during the storage and I/O card. Invented by SanDisk, the specifi- file registers control the drive (the ANSI T13 committee
essary. However, many applications may wish to use second program operation, several spare blocks (1- cations are now determined by the CompactFlash defines these registers and the commands used to
part of the NAND Flash as a ROM, and part as a file 2%) typically need to be added to the code partition to Association (CFA) (http://www.compactflash.org), an control all ATA/IDE drives—see http://www.t13.org).
system. In this case, there are basically two approach- allow for bad blocks to enable the second partition to organization that promotes the adoption of These task file registers can be mapped into either
es. In the first case, we can partition the NAND Flash start at a fixed block location. Of course, there is still a CompactFlash. The CompactFlash can be used in such memory or I/O address space.
into two separate distinct regions in which code is possibility that in a particular chip, the bad blocks are applications as portable and desktop computers, digital
stored in one partition and the file system is stored in concentrated in the code partition section. If this hap- cameras, handheld data collection scanners, PDAs, A typical CompactFlash card consists of a con-
the other. In the second case, we could use the entire pens, there would be an insufficient number of good Pocket PCs, handy terminals, personal communicators, troller and several NAND Flash memory chips. The
NAND Flash as a file system and store the code as a blocks in the physical block range allocated for code advanced two-way pagers, audio recorders, monitoring convenient aspect of using them is that the controller
special file within it. The first case will be simpler to storage to actually store the code. Also, the hassle of devices, set-top boxes, and networking equipment. typically implements ECC in hardware and the NAND
implement because the bootstrap loader program will dealing with two separate files (code and file system) to Flash management in firmware offering both high relia-
not have to understand the file system in order to be programmed can lead to errors. Therefore, it will be A CompactFlash card is essentially a small form bility and high performance. Two application notes de-
retrieve code from the NAND Flash. However, the sec- more convenient to avoid partitioning the Flash and factor card version of an ATA PC Card (AT Attachment) scribing a reference interface between the CompactFlash
ond case is more versatile. If code should grow in the implement case 2 in section 8.2 by storing the code as specification and includes a True IDE (Integrated Drive card and either the MPC8260 or PPC405 are available
future, there is no need to repartition the NAND Flash. a special file in the file system and program a single file Electronics) mode which is compatible with the from Toshiba America Electronic Components, Inc.
Development is easy because one can simply reload a into the Flash. ATA/ATAPI-4 specification. As such, there are three (http://www.applications.toshiba.com).
new ROM image as a file. However, a more sophisti- distinct interface modes that a CompactFlash card
cated bootstrap loader program requiring more space can use:
will be necessary. 8.4 Considering Memory Cards
• PC Card Memory Mode (uses WE#, OE# to
If portable storage is necessary, the easiest access memory locations)
8.3 Considerations for Preprogramming NAND solution is to use one of the removable memory cards • PC Card I/O Mode (uses IOWR#, IORD# to
available. The advantage of using a memory card is access I/O locations)
The preprogramming of NAND Flash (i.e. the pro- that most memory cards (except the SmartMedia and • True IDE Mode (uses IOWR#, IORD# to access
gramming of NAND Flash chips before they are sol- xD Picture Card, for example) have a built-in memory I/O locations)
dered on to the system board as opposed to in-system controller chip. Toshiba, as the inventor of SmartMedia,
programming) is different than the preprogramming co-inventor of the SD card, and a major manufacturer
NOR Flash primarily because of the existence of bad of CompactFlash cards, offers a variety of possible
blocks which prevents the use of fixed physical solutions. For further information on these cards see:
addressing. Device programmers that can program
NAND Flash are designed to program only good, whole • SmartMedia – http://www.ssfdc.or.jp
blocks and skip over bad blocks. All overhead bytes • SD Card – http://www.sdcard.org
(including ECC bytes) must be included in the data file • CompactFlash – http://www.compactflash.org
itself. In the data file, every 518th byte (byte 517) out of
every 528 bytes should be left as 0xFFh. As discussed
in section 6.1, this byte is reserved as the bad block
flag byte. A separate white paper describing the issues
in preprogramming NAND Flash is available from
Toshiba America Electronic Components, Inc.
(http://www.toshiba.com/taec ->products->memory->
Flash-NAND).

If the NAND Flash is divided into two partitions as

described in section 8.2, it will be necessary to program
the NAND Flash in two operations. In the first opera-
tion, the code portion is programmed. Since the bad

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NOTES NOTES

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 NAND FLASH APPLICATIONS DESIGN GUIDE

NOTES

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For more information about Toshiba's memory products, please go to:
www.memory.toshiba.com.

©2004 Toshiba America Electronic Components, Inc.

All product or brand names are the propenty of their respective holders.

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