NATIONAL INSTITUTE OF TECHNOLOGY PATNA Department of Electronics and Communication Engineering MID SEMESTER EXAMINATION, Jul-Dec 2024 3" Semester Regular Examination: Sept-Oct 2024 SUBJECT NAME: DIGITAL ELECTRONICS SUBIECT CODE ECM BRANCH: ECE Time: 02 Hours Max Marks: 30 Instructions: 1. All questions are compulsory 2. Assume any suitable data if necessary 3. The CO (Course Outcome) and Level (from Bloom's Taxonomy) related to questions are given in the left-hand side and Marks are mentioned on the right-hand side margin. Marks 16 Questions I"(a) Given AB+ AB=C, find AC+AC. |b) Simplify the following Boolean function using K-Map F,(A,B,C)=)'m(I,3,4,6) F,(A.B,C_D)=Y'm(0,1,2,3,5,7,8;12514). (¢)_Make a K-Map for the given logic function. Minimize it and realize using only NAND Gate. F(A,B,C,D) = ¥)m(1,3,7,10,11,14,15) +d (0,2,5) (d) What is parity bit generator? Design a 4-bit even party generator circuit. (©) How many NAND and NOR gates are required to implement the AND and X- QNo. | CO | Level cor, NOR gate. (Marks 2) Qa | Coz, | 12.3.4 | (Convert ihe following) co3 “a. binary number into its equivalent gray code: 111001 b. gray code int its binary number: 101110 (2) Convert the following ©. (807),.in BCD code 4d. (286), in XS-3 code (8) Solve the following Give the minimum two-level SOP realization of the function using only AND gates F=7m(0, 3, 4, 5, 7) b. Reduce the expression F=A| [p+C(aB+ac)] OR OF, | _U,R, | Attemprall questions (each 2 mark). ; a co2 a. Inthe given circuit, the propagation delay of each inverter is 50 ns, Evaluate the frequency of the generated square waveform at Y. y Qu b. Given (3410.0703)1o->(X)isand then number (X)is >(Y)oy where v=ft ifX > (ECE) 16 “(2 HX < (ECE) Find X and Y. ‘The K-map for a Boolean function is shown in the figure. Determine the minimize logic expression in POS form and calculate the number of _gssential prime implicants for SOP function. ce.8 efels ufofels|a a. Drav the bubbled AND gate using npn transistors TI and T2 and construct, its truth table indicating inputs A, B, and transistor T1 and T2 states with the output Y. In the circuit shown below, the diode has a negligible voltage across itunder +5 V, A,B, C, and D are digital signals with OV as logic 0 and Vee as logic 1. What will be the Boolean expression for Y ? am ¥ comes Me He py BR: a = oe £ The two signed numbers represented in 8-bit signed 2's complement form are P= 10010101 and Q= 00101001. IF Y =P +Q then determine Y in decimal and the 2's complement form. g. _ Implement 2 input XOR and XNOR gate using 2 input NAND gate. hh. Find the Max-term for Boolean expression AB+ACD. col, TW) Minimize the Togic function using Guine-MeCluskey minimization technique 921 ¢o2 | 1256 F (ABCD) = Yim (0,1,2,3,9,10) +4 (4,5,6) OR ‘Simplify the given function f(A, B, C,D) = Lm, 1,4,5,8, 9, 13, 15) by using Q2 col UA Quine McCluskey Method. col, : ‘ ries a3 | COb | 12.366 | Design a BCD to 7-egment splay decoder circuit using logic gates OR Cor TU] Two square waves, P of 5 kHz and Q of 10 kHz frequency, are applied as inputs to 3 the following logic gates. Draw the output waveform in each case. (a) Bubbled AND gate (b) Bubbled OR gate (c)X-OR (d) X-NOR. col, Q4 co2, 1,2,3,4 | (a) Design full adder logic circuit using two Half Adder cO3 OR @. Determine the gates GI and G2 in the figure shown to get the output ¥ = AB + CD a a Qs | cor) UR se [ L., =p" :