PIC Microcontrollers

UNIT - II
PIC 18: Family Overview, Architecture, Instruction Set, Addressing
modes. Timers, interrupts of PIC 18, Capture/Compare and PWM
modules of PIC 18.

By
M.Mahesh Babu

4/10/2024 1
 Overview
• Intel created the first microcontroller (8051) with
Harvard Architecture 8051 in 1980, and microcontrollers
have revolutionized the electronics and embedded
industries ever then.
• With the evolution of technology, we now have several
more efficient and low-power microcontrollers such as
AVR, PIC, and ARM.
• These microcontrollers are more capable and simple to
use, as they support the most recent communication
protocols such as USB, I2C, SPI, and CAN.
• In this, we’ll look at what a PIC microcontroller is, what
it can do, and why it’s so popular in Embedded systems.
4/10/2024 2
 Overview and Features
• The term PIC stands for Peripheral Interface
Controller .
• Microchip Technology, USA .
• Basically RISC microcontrollers
• 5 ports
• It has two types of internal memories .
– One is program memory and
– the other is data memory.
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 Overview of PIC Microcontroller:
• PICs use an instruction set that varies in length from
about 35 instructions for the low-end PICs to more
than 70 for the high-end devices.
• The accumulator, which is known as the work register
in PIC documentation, is part of many instructions
since the PIC contains no other internal registers
accessible to the programmer.
• The PICs are programmable in their native Assembly
Language, which is straightforward and not difficult to
learn. In addition, C language and BASIC compilers
have been developed for the PIC.
• Open-source Pascal, JAL, and Forth compilers are also
available for PIC programming.
4/10/2024 4
 PIC microcontrollers
• Peripheral Interface Controller (PIC) was
originally designed by General Instruments.
• In the late 1970s, GI introduced PIC® 1650 and
1655 – RISC with 30 instructions.
• PIC was sold to Microchip
• Features: low-cost, self-contained, 8-bit,
Harvard structure, pipelined, RISC, single
accumulator, with fixed reset and interrupt
vectors.
4/10/2024 5
 Microcontroller with
the Harvard Architecture
 PIC microcontrollers
• Manufactured by Microchip Technology
• High performance/low cost for embedded
applications
• Work strictly with 8-bit data
• Varying complexity, characterized by
– Interfaces supported
• SPI, I2C, Ethernet, etc.
– Number of instructions
• Anywhere from ~35 to ~80
– Amount of internal memory available
– Internal modules
• Capture, compare, timers, etc.

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 Features
• Speed:
– When operated at its maximum clock rate a PIC executes most of
its instructions in 0.2 s or five instructions per microsecond.
• Instruction set Simplicity :
– The instruction set is so simple that it consists of only just 35
instructions
• Integration of operational features:
– Power-on-reset (POR) and brown-out protection ensure that the
chip operates only when the supply voltage is within
specifications. A watch dog timer resets the PIC if the chip
malfunctions or deviates from its normal operation at any time.
• Programmable timer options:
– Three timers can characterize inputs, control outputs and provide
internal timing for the program execution.

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 Features
• Interrupt control:
– Up to 12 independent interrupt sources can control
when the CPU deal with each sources.
• Powerful output pin control:
– A single instruction can select and drive a single
output pin high or low in its 0.2 s instruction
execution time. The PIC can drive a load of up to
25A.
• I/O port expansion:
– With the help of built in serial peripheral interface the
number of I/O ports can be expanded. EPROM/DIP/
ROM options are provided.

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 The Different between microcomputer system and
microcontroller based system

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 Microcontroller
• A microcontroller is a computer implemented on a VLSI chip.
• It contains everything contained in a microprocessor along with one or
more of the following components:
– Memory
– Timer
– Pulse-width modulation (PWM) module
– Analog-to-digital converter
– Digital-to-analog converter
– Direct memory access (DMA) controller
– Parallel I/0 interface
– Serial I/0 interface
– Memory component interface circuitry
– Software debug circuitry
– Etc.

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 Embedded System
• Microcontrollers are sometimes called
embedded microcontrollers, which just means
that they are part of an embedded system --
that is, one part of a larger device or system.
• The majority of microcontrollers in use today
are embedded in other machinery, such as
automobiles, telephones, appliances, and
peripherals for computer systems. These are
called embedded system.
4/10/2024 12
 …cont’d
• Typical input and output devices include
switches, relay, solenoids, LEDs, small or
custom LCD displays, radio frequency devices,
and sensors for data such as temperature,
humidity, light level etc.
• Embedded systems usually have no keyboard,
screen, disks, printers, or other recognizable
I/O devices of a personal computer, and may
lack human interaction devices of any kind.
4/10/2024 13
 Microcontroller Types

4/10/2024 14
 Types of Microcontroller
15

• Freescale 68HC11 (8-bit)

• Intel 8051
• Silicon Laboratories Pipelined 8051 Microcontrollers
• ARM processors (from many vendors) using ARM7 or Cortex-M3
cores are generally microcontrollers
• STMicroelectronics STM8 (8-bit), ST10 (16-bit) and STM32 (32-
bit)
• Atmel AVR (8-bit), AVR32 (32-bit), and AT91SAM (32-bit)
• Freescale ColdFire (32-bit) and S08 (8-bit)
• Hitachi H8, Hitachi SuperH (32-bit)
• Hyperstone E1/E2 (32-bit, First full integration of RISC and DSP
on one processor core [1996])
• Infineon Microcontroller: 8, 16, 32 Bit microcontrollers for
automotive and industrial applications.
4/10/2024 15
 …cont’d
• MIPS (32-bit PIC32)
• NEC V850 (32-bit)
• Microchip PIC (8-bit PIC16, PIC18, 16-bit dsPIC33/PIC24)
• PowerPC ISE
• PSoC (Programmable System-on-Chip)
• Rabbit 2000 (8-bit)
• Texas Instruments Microcontroller MSP 430 (16-bit), C2000 (32-
bit), and Stellaris (32-bit)
• Toshiba TLCS-870 (8-bit/16-bit)
• Zilog eZ8 (16-bit), eZ80 (8-bit)
• etc

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 Microchip PIC
• PIC is a family of Harvard architecture
microcontroller made by Microchip Technology.
• The name PIC initially referred to "Peripheral
Interface Controller“.
• This was originally designed to help PDP computers
monitor their peripheral devices, and is thus
referred to as a peripheral interface unit.
• Compared to other microcontrollers, these
microcontrollers can run a program very quickly
and comfortably.
• The architecture of PIC Microcontrollers is based
on Harvard architecture.
4/10/2024 17
 Microchip PIC
• PIC microcontrollers were the first RISC
microcontroller.
• PICs are popular with both industrial developers
and hobbyists alike due to their low cost, wide
availability, large user base, extensive collection
of application notes, availability of low cost or
free development tools, and serial
programming (and re-programming with flash
memory) capability.

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4/10/2024 19
 Two Different Architectures
• Organization of program and data memory
• PIC MCU technically “modified Harvard
architecture”

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 Two Different Architectures

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• PIC Microcontroller
– Programmable Interface Controller
• 8-bit MCU (depending on RAM size, IO pins, stack size, enhanced
architecture)
– Base-line (including Dust, 6-pin, no interrupts)
– Mid-range
– High-end (PIC18F, uses C18 compiler)
• 16-bit MCU
– Enhanced with dsp features (support for VoIP)
– Smaller, faster, low-power; uses C30 Compiler
– PIC24, dsp30/33
• 32-bit MCU
– Instruction cache, low-power, faster RAM
– C32 compiler

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 PIC Microcontroller product family
• Microchip Company’s PIC microcontrollers are
grouped into four broad groups.
• Each family has a variety of components along
with built in special features.
• It offers a lot of memory sizes and pin packages
and different clock rating.
• They are:
– First family:PIC10 (10FXXX) called Low End
– Second family:PIC12 (PIC12FXXX) called Mid-Range
– Third family:PIC16 (16FXXX)
– Fourth family: PIC 17/18 (18FXXX)

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 PIC Microcontroller product family
• 8-bit microcontrollers • 32-bit microcontrollers
– PIC10 – PIC32
– PIC12
• 16-bit digital signal
– PIC14
controllers
– PIC16
– dsPIC30
– PIC17
– dsPIC33F
– PIC18
• 16-bit microcontrollers
– PIC24F
– PIC24H

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• PIC microcontrollers are manufactured by Microchip. They are
available in 8-bit, 16-bit, and 32-bit.
• 8-bit PIC microcontrollers have various families which are as
follows-
Features Baseline Mid-Range Enhanced Mid-Range Advanced PIC18
PIC10, PIC12,
Families PIC10, PIC12 PIC12Fxxx,PIC16Fxxx PIC 18
PIC16
Program
Max 3 KB Max 14 KB Max 28 KB Max 128 KB
Memory
Max 368
Data Memory Max 138 Bytes Max 1-5 KB Max 4 KB
Bytes
Performance 5 MIPS 5 MIPS 8 MIPS 16 MIPS
Addition to Addition to midrange  CAN
baseline
 8-bit ADC • Multiple Peripheral  USB
 I2C/SPI communication
 Internal  ETHERNET
Features  PWM • High Performance
Oscillator
 LIN
 UART • PWM with
 Comparator
independent Time-  PLL Clock
 10-bit
Space generator
ADC
4/10/2024 25
 Flash (4K)
EEPROM – can be accessed individually
36 I/O ports
F FLASH
C EPROM
• Most of the families are pin-compatible but assigned
functions are different for different families.
• For example, PIC16F877A has I2C (SDA and SCL) pins
multiplexed with PORTC whereas in PIC18F4550 they are
multiplexed with PORTB but both families are pin compatible.
• In family names, there are suffixes used in between which tell
– PIC18FXXX – ‘F’ implies Flash Program Memory
– PIC16CXXX – ‘C’ implies EPROM Program Memory
– PIC18LFXXX – ‘LF” implies Low Voltage operation
• It varies from family to family.
• Whenever a new part is designed to replace an older part, a
new version of the part is obtained by adding extra alphabet
at the end like 16F877 and 16F877A.

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 PIC Microcontroller product family
• The F in a name generally indicates the PIC micro uses flash
memory and can be erased electronically.
• The C generally means it can only be erased by exposing the
die to ultraviolet light (which is only possible if a windowed
package style is used). An exception to this rule is the PIC16C84
which uses EEPROM and is therefore electrically erasable.

1:

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4/10/2024 30
 PIC Microcontroller Architecture:

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 Simplified View of
a PIC Microcontroller

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• PIC micro controller supports the RISC architecture that
is reduced instruction set computer.
• If a computer or controller is said that it supports
reduced instruction set you should remember the
following points:
1. RISC has very few instructions (approx. ~ 35) which are
used in the program.
2. Length of the instruction is small and fixed and takes same
amount of time for processing.
3. As the instruction is small it will take less time to process
another words CPU will be fast.
4. Compiler need not be complex and debugging will be very
easy in the programmer point of view.

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• Memory: Memory module in the PIC consists of RAM, ROM
and STACK
• RAM: we know that RAM (Random Access Memory) which is
a volatile memory used for storing the data temporarily in its
registers.
• RAM memory is divided in to Banks, in each banks we have
number of registers.
• The RAM registers is divided into 2 types: They are
– General purpose registers (GPR) and
– Special purpose registers (SPR).

4/10/2024 34
 1. GPR: general purpose registers as the name implies for general
usage. For example if we want to multiply any two numbers
using PIC we generally take two registers for storing the
numbers and multiply the two numbers and store the result in
other registers. So general purpose registers will not have any
special function or any special permission, CPU can easily access
the data in the registers.
2. SPR: Special function registers are having the specific functions,
when we use this register they will act according to the
functions assigned to them. They cannot be used like normal
registers. For example you cannot use STATUS register for
storing the data, STATUS registers are used for showing the
status of the program or operation. User cannot change the
function of the Special function register; the function is given by
the vendor at the manufacturing time.

4/10/2024 35
• ROM: we know that ROM (Read Only memory) is a non volatile memory used for
storing the data permanently.
• In microcontroller ROM will store the complete instructions or program, according the
program microcontroller will act.
• ROM is also called program memory in this memory user will write the program for
microcontroller and save it permanently and get executed by the CPU. According to the
instruction executed by the CPU the PIC microcontroller will perform the task.
• In ROM there are different types which are used in different PIC microcontrollers.
• EEPROM: In the normal ROM we can write the program for only one time we cannot
reuse the Microcontroller for another time where as in the EEPROM (Electrically
Erasable Programmable Read Only Memory) we can program the ROM for number of
times.
• Flash Memory: flash memory is also PROM in which we can read write and erase the
program more than 10,000 times. Mostly PIC microcontroller uses this type of ROM.
• Stack: when an interrupt occur PIC has to first execute the interrupt and the existing
process address which is being executed is stored in the stack. After completing the
interrupt execution, PIC will call the process with the help of address which is stored in
stack and get executing the process.

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• Bus: Bus is mainly used for transferring and receiving
the data from one peripheral to another.
• There are two types of buses.
• Data Bus: It is used to transfer/receive only the data.
• Address Bus: is used to transmit the memory address from
peripherals to CPU.
• I/O pins are used for interfacing the external
peripherals, UART and USART is serial communication
protocol which is used for interfacing serial devices like
GPS, GSM, IR, Bluetooth etc.

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 PIC Microcontroller product family
• Every PIC has some major and common units like:
– Processor
– Memory (RAM, ROM, EPROM)
– Input/ Output ports
– Serial and Parallel ports
– Timer
– counter
– A-D converter or D-A converter
– Flash memory (program memory)
– SRAM memory (Data memory)
– various crystal oscillators

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ADVANTAGES OF PIC MICROCONTROLLER:
• PIC microcontrollers are reliable, and the percentage of PIC
microcontrollers that are defective is relatively low. Because to its
RISC design, the PIC microcontroller has an extremely quick
performance.
• It is a RISC (Reduced Instruction Set Computer) design
• Only thirty seven instructions to remember
• It is low cost, high clock speed
• Because of its efficient coding, the PIC can run with significantly
less programme memory than its larger competitors.
• When comparing to other microcontrollers, power consumption
is very less and programming is also very easy.
• Interfacing of an analog device is easy without any extra circuitry

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 DISADVANTAGES OF PIC MICROCONTROLLER

• Because of the RISC architecture, the software

is somewhat long (35 instructions)
• One single accumulator is present and
program memory is not accessible

4/10/2024 40
 PIC18F Microcontroller Series
• PIC16-series microcontrollers have been around for many
years. Although these are excellent general purpose
microcontrollers, they have certain limitations.
• For example, the program and data memory capacities
are limited, the stack is small, and the interrupt structure
is primitive, all interrupt sources sharing the same
interrupt vector.
• PIC16-series microcontrollers also do not provide direct
support for advanced peripheral interfaces such as USB,
CAN bus, etc., and interfacing with such devices is not
easy.
• The instruction set for these microcontrollers is also
limited.
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 PIC18F Microcontroller Series
• Microchip Inc. has developed the PIC18 series of
microcontrollers for use in high-pin count, high-density,
and complex applications.
• The PIC18F microcontrollers offer cost efficient
solutions for general purpose applications written in C
that use a real-time operating system (RTOS) and
require a complex communication protocol stack such
as TCP/IP, CAN, USB, or ZigBee.
• PIC18F devices provide flash program memory in sizes
from 8 to 128Kbytes and data memory from 256 to
4Kbytes, operating at a range of 2.0 to 5.0 volts, at
speeds from DC to 40MHz.
4/10/2024 42
 PIC18F Microcontroller Series
• Microchip technology introduced 8-bit, 16-bit and
32-bit portable microcontrollers called PIC18
microcontrollers with nano-watt technology to
perform a huge range of tasks.
• These are used in many electronics applications
and industries due to their high performance and
low power consumption.
• The family of PIC microcontrollers includes
– PIC18FXXXX (F- flash program memory),
– PIC18CXXXX (C- EEPROM program memory), and
– PIC18LFXXXX (L- low voltage operation).

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 PIC18F Microcontroller Family
• The PIC18 microcontroller family provides
PICmicro® devices in 18- to 80-pin packages,
that are both socket and software upwardly
compatible to the PIC16 family.
• PIC18 one of the higher performers of the
Microchip’s PIC families.
• There is now both a 32 bit PIC32 family and
DSPIC (16 bit) with high performance.

4/10/2024 44
 PIC18F Microcontroller Family
• The PIC18 family includes all the popular peripherals, such as
MSSP, ESCI, CCP, flexible 8- and 16-bit timers, PSP, 10-bit ADC,
WDT, POR and CAN 2.0B Active for the maximum flexible
solution.
• Most PIC18 devices will provide FLASH program memory in
sizes from 8 to 128 Kbytes and data RAM from 256 to 4
Kbytes; operating from 2.0 to 5.5 volts, at speeds from DC to
40 MHz.
• Optimized for high-level languages like ANSI C, the PIC18
family offers a highly flexible solution for complex embedded
applications.

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 PIC18F Microcontroller Family

4/10/2024 46
 Basic features of PIC18F-series
microcontrollers
• Basic features
– 77 instructions
– PIC16 source code compatible
– Program memory addressing up to 2Mbytes
– Data memory addressing up to 4Kbytes
– DC to 40MHz operation
– 8 8 hardware multiplier
– Interrupt priority levels
– 16-bit-wide instructions, 8-bit-wide data path
– Up to two 8-bit timers/counters
– Up to three 16-bit timers/counters
– Up to four external interrupts
– High current (25mA) sink/source capability
– Up to five capture/compare/PWM modules
– Master synchronous serial port module (SPI and I2C modes)
– Up to two USART modules

4/10/2024 47
 Basic features of PIC18F-series
microcontrollers
• Basic features (continued…)
– Parallel slave port (PSP)
– Fast 10-bit analog-to-digital converter
– Programmable low-voltage detection (LVD) module
– Power-on reset (POR), power-up timer (PWRT), and oscillator start-up timer (OST)
– Watchdog timer (WDT) with on-chip RC oscillator
– In-circuit programming
• In addition, some microcontrollers in the PIC18F family offer the following
special
• features:
– Direct CAN 2.0 bus interface
– Direct USB 2.0 bus interface
– Direct LCD control interface
– TCP/IP interface
– ZigBee interface
– Direct motor control interface
4/10/2024 48
 PIC18F Microcontroller Family
• Most devices in the PIC18F family are source
compatible with each other.
• Table 2.1 gives the characteristics of some of the
popular devices in this family.
• The architectures of most of the other microcontrollers
in the PIC18F family are similar.
• The following are similarities between PIC16F and
PIC18F:
– Similar packages and pinouts
– Similar special function register (SFR) names and functions
– Similar peripheral devices
4/10/2024 49
• So why use the 18 series over the 16 series. Here are some attributes
taken from a common set of chips from the 16 series range.

• Here is the same kind of information but taken from the datasheet of the
18 series.

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 Table 2.1: The 18FXX2 microcontroller family

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4/10/2024 52
 Architecture of PIC18Fxx Microcontroller

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4/10/2024 54
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4/10/2024 56
 Introduction to PIC18F4520
• It is an 8-bit enhanced flash PIC microcontroller that
comes with nanoWatt technology and is based on RISC
architecture.
• Many electronic applications house this controller and
cover wide areas ranging from home appliances,
industrial automation, security system and end-user
products.
• This microcontroller has made a renowned place in the
market and becomes a major concern for university
students for designing their projects, as this controller
comes with inbuilt peripheral with the ability to
perform multiple functions on a single chip.

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4/10/2024 58
4/10/2024 59
 Introduction to PIC18F4520

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• What is PDIP?
• PDIP is Plastic Dual In-Line Package. It is one
of the many IC packages categorized under
Dual In-Line Package (DIP).
• It is described as being “mature” because of
the high-resistance to moisture, a factor that
could have contributed to the package’s
wearing out faster if it weren’t there.

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• QFN: This is called the Quad Flat No Leads
package.
• This package looks like all it has is just a few
pieces of exposed metal on the
bottom. Well that pretty much what it really
is. The leads are to be surface mounted on
just like the CBGA . It is generally made out
of plastic or what is called air-cavity. The
plastic is a common package and is easier to
make, although the air-cavity allows the QFN
to run at much higher frequencies.

4/10/2024 62
• TQFP: Thin Quad Flat Pack.
• This package has gull-wing leads and a
thermal pad and greatly resembles the
LQFP. It is actually much thinner, but it
can only have 32 – 128 leads. Much less
than the LQFP.

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4/10/2024 64
 PIC Microcontroller - PIC18F
• PIC18F4520 is a PIC microcontroller, introduced
Microchip, and mainly used in automation and
embedded systems.
• It comes in three packages known as PDIP, QFN,
and TQFP where the first one is 40-pin (mostly
used) while other two come with a 44-pin
interface.
• This microcontroller version comes with CPU,
timers, 10-Bit ADC and other peripherals that are
mainly used to develop a connection with external
devices.
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 PIC microcontroller - PIC18F
• The PIC18F4520 contains 256 bytes of EEPROM data
memory, 1536 bytes of RAM, and program memory of
32K.
• It also incorporates 2 Comparators,10-bit Analog-to-
Digital (A/D) converter with 13 channels.
• The Enhanced Universal Asynchronous Receiver
Transmitter (EUSART) feature is useful for developing
the serial communication with other devices.
• The asynchronous serial port is added on the chip that
can be interfaced both ways i.e. 3-wire Serial Peripheral
Interface (SPI™) or the 2-wire Inter-Integrated Circuit
(I²C™) Bus.
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 Resolutio
ROM Clock
RAM A/D n of A/D Compar- 8/16 – bit Serial PWM
family [Kbyt Pins Freq. Others
[bytes] Inputs Converte ators Timers Comm. Outputs
es] [MHz]
r
Base-Line 8 - bit architecture, 12-bit Instruction Word Length
0.375
PIC10FXXX 16 - 24 6-8 4-8 0-2 8 0-1 1x8 - - -
- 0.75
0.75 -
PIC12FXXX 25 - 38 8 4-8 0-3 8 0-1 1x8 - - EEPROM
1.5
0.75 -
PIC16FXXX 25 - 134 14 - 44 20 0-3 8 0-2 1x8 - - EEPROM
3
Vdd =
PIC16HVXXX 1.5 25 18 - 20 20 - - - 1x8 - -
15V
Mid-Range 8 - bit architecture, 14-bit Instruction World Length
1.75 - 1-2x81
PIC12FXXX 64 - 128 8 20 0-4 10 1 - 0-1 EEPROM
3.5 x 16
1-2x81
PIC12HVXXX 1.75 64 8 20 0-4 10 1 - 0-1 -
x 16
1.75 - 1 - 2 x 8 1 USART I2C
PIC16FXXX 64 - 368 14 - 64 20 0 - 13 8 or 10 0-2 0-3 -
14 x 16 SPI
1.75 - 2 x 8 1 x USART I2C
PIC16HVXXX 64 - 128 14 - 20 20 0 - 12 10 2 - -
3.5 16 SPI
High-End 8 - bit architecture, 16-bit Instruction Word Length
USB2.0
4- 256 - 0 - 2 x 8 2 CAN2.0
PIC18FXXX 18 - 80 32 - 48 4 - 16 10 or 12 0-3 0-5 -
128 3936 - 3 x 16 USART I2C
SPI
USB2.0
8- 1024 - 0 - 2 x 8 2 USART
PIC18FXXJXX 28 - 100 40 - 48 10 - 16 10 2 2-5 -
128 3936 - 3 x 16 Ethernet
I2C SPI
PIC18FXXKX
4/10/2024 8 - 64 768 - 1 x 8 3 x USART I2C
28 - 44 64 10 - 13 10 2 2 -67
X 3936 16 SPI
 The PIC18 CPU Register
• The group of registers from 0xFD8 to 0xFFF are
dedicated to the general control of MCU
operation.
– The CPU registers are listed in Table 1.2.
– The WREG register is involved in the execution of
many instructions.
– The STATUS register holds the status flags for the
instruction execution and is shown in Figure 1.6.

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 File Register (or) Register set
• File Register – (data RAM) read/write memory used by CPU (varies from
32 bytes to .. depending on chip size (family)
• The register set controls the microcontroller which contains:
– General purpose registers (GPR).
– Special function registers (SFR).
• The GPR is a set of 8-bit-wide general purpose registers used to store
dynamic data.
• All models contains at least GPR locations 0x000 through 0x07F, plus the
SFR at 0xF80 through 0xFFF or 256 bytes of SRAM.
• The GPR is accessed through a 12-bit address with the most significant 4
bits containing a bank location.
• Data memory banks each contain 256 bytes of data memory.
• Data bank 0 contains registers 0x000 through 0x0FF, data bank 1 contains
register locations 0x100 through 0x1FF, and so forth.
4/10/2024 70
 File Registers of PIC12, PIC16, and PIC18

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 Access bank
• Access bank: is addressed without using a data bank register,
so it is easier to access and more efficient to access in a
program.
• These access bank addresses are accessed using a single 8-bit
address.
• To access locations in the data RAM outside of the access bank,
use a combination of an 8-bit address and the 4-bit bank select
register (BSR).
• A bit in an instruction, called the a-bit, selects the access bank
(when a = 0) or the bank indicated by the bank select register
(when a = 1).
4/10/2024 73
 Special Function Registers (SFR)
• The special function registers (SFR) are used to perform a variety of
special tasks in a microcontroller, for example, the bank select
register (BSR).
• SFR can :
– hold a product after a multiplication,
– indicate the status of the outcome of an instruction,
– accumulate results from arithmetic and logic operations, and
– address a location in a program.
• All of the special function registers are located at the top of the
data memory in the access bank. All special function registers have
a name and an address, where either can be used for accessing
them.
4/10/2024 75
4/10/2024 76
 Accumulator (WREG)
• The accumulator or, as it is often called, the working register (W register
or WREG) is an 8-bit register that is accessed by many instructions.

• This register is most likely called an Accumulator because it is where

results accumulate for many instructions.

• Most CPUs contain an accumulator as the main working register. In the

PIC18 family, the working register (WREG) is located in the SFR area at
address 0xFE8.

• Although this register is assigned an address, many instructions access it

without using its address by its name or implicitly as part of an instruction.

• This implicit form of addressing is why WREG is called the working register
or accumulator.
 Bank select register (BSR)
• The bank select register (which is 4 bits wide) plus an 8-bit
address combine to form the 12-bit data memory address
when the a-bit in the instruction is a logic one.

• This allows access to any register in any bank in the data

memory.
4/10/2024 79
 Product registers
• The product registers hold the result or product after the multiply
instruction executes.

• A special register is needed for multiplication because a product is

always twice the width of the multiplier.

• The MULLW instruction multiplies the W register by the literal

value.

• Because this is an 8-bit microcontroller and the multiplication is 8

bits, the product is 16 bits in width and stored in the PRODL and
PRODH registers.
 Status registers (SR)
• The status register (SR) indicates the outcome of an operation.

• Only five of the eights bits indicate status and are labeled N
(negative), OV (overflow), Z (zero), DC (digit carry), and C (carry).

• The status bits are tested by the conditional branch instructions

that are most often used to form the if-then-else construct in
programming as well as other programming constructs.

• The status register bits will normally change only for an arithmetic
or logic operation in the PlC.
 Status registers (SR)

4/10/2024 82
 Status bits
• N(negative) is a logic 1 if the result of an arithmetic or logic
operation is negative and a 0 if the result is positive.

• OV (overflow) is a logic 1 if the result of an arithmetic operation

overflows the signed contents of an 8-bit answer.

• Z (zero) is a logic 1 if the result of an arithmetic or logic operation is

a zero. If the result is not zero, then the zero bit is a zero.

• DC (digit carry) is a half-carry. It watches if a carry out from the

4th lower order of the byte is occurred. The values it can get are:
0: No carry-out from 4th lower order of the byte occurred.
1: A carry-out from the 4th lower order of the byte occurred.

• C (carry) holds a carry from the most significant bit of the result.
 Program counter (PC)
• The program counter, a 2l-bit register in the PlC 18 family, addresses
the next location in the program memory and allows instructions to
be accessed sequentially from the program memory.

• The program counter is a counter, but does not count programs. It

counts up through the memory to access the next instruction in a
program, which is probably why it is named the program counter.

• In some machines, this register is more appropriately called the

instruction address register (IAR).

• The flow of a program is modified if the contents of the program

counter are changed.
4/10/2024 85
Program Memory
• Program memory is 16-bits wide accessed through a
separate program data bus and address bus inside the
PIC18.
• Program memory stores the program and also static data in
the system.
– On-chip
– External
• On-chip program memory is either PROM or EEPROM.
– The PROM version is called OTP (one-time programmable)
(PIC18C)
– The EEPROM version is called Flash memory (PIC18F).
• Maximum size for program memory is 2M
– Program memory addresses are 21-bit address starting at
location 0x000000
• Example: PIC18F4520 has 32K program memory
4/10/2024 86
Data Memory (1)
• Used for transitory data when the program is being
executed
– Example: A=1, B=2, C=3 X=A+B+Cà A+B=W;W+C=W
• Data memory is either SRAM or EEPROM.
– Some chips only have SRAM
– Others may have SRAM and EEPROM
• EEPROM stores permanently
• Various PIC18 versions contain between 256 and
3968 bytes of data memory
– For example: SRAM data memory begins at 12-bit address
0x000 and ends at 12-bit address 0xFFF (4K)

4/10/2024 87
Data Memory (2)
• Data memory is often divided into two sections
– General Function Registers (GFR) or register file location
• 000-0xF7F locations
– Special Function Registers (SFR) – specific to PIC
• 0xF80-0xFFF (upper 128 bytes)
• Depending on the PIC chip, the sizes for GFR and SFR
are different

4/10/2024 88
Program Stack Memory
• The PIC18 contains a program stack that stores
up to 31 return addresses from functions.
– 31-deep
– The program stack is 21 bits in width as is the
program address (remember address memory is 2M)
• Stack memory uses SRAM
• Operation of a stack
– When a function is called, the return address (location
of the next step in a program) is pushed onto the
stack.
• For example: Stack number 1 will have value= 0x0x1F0000
– When the return occurs within the function, the return
address is retrieved from the stack and placed into
4/10/2024
the program counter. 89
 PIC18F452/4520/45K20
Memory - Example
• Program Memory: 32 K
(215)
– Address range: 000000 to
007FFFH
– 16-bit registers
• Data Memory: 4 K
– Address range: 000 to FFFH
– 8-bit registers
• Data EEPROM
– Not part of the data memory
space
– Addressed through special
function registers

4/10/2024 90
PIC18F – MCU and Memory

16
bit

8 bit

4/10/2024 91
 Microprocessor Unit (1 of 3)
Includes Arithmetic Logic Unit (ALU)
• Includes Arithmetic Logic
Unit (ALU), Registers, and
Control Unit
– Arithmetic Logic Unit (ALU)
• Performs logical and
arithmetic functions
– WREG – working register (acts
as an accumulator) – used to
perform arithmetic or logical
functions
– Status register that stores flags
– indicates the status of the
operation done by ALU
– Instruction decoder (ID)– when
the instruction is fetched it
goes into the ID to be
interpreted – tell the processor
4/10/2024 92
what to do
 Microprocessor Unit (1 of 3)
Includes Arithmetic Logic Unit (ALU)
All arithmetic and logical instructions are
carried out by the ALU.

4/10/2024 93
 Microprocessor Unit (1 of 3)
Includes Arithmetic Logic Unit (ALU)
• General ALU Architecture

4/10/2024 94
 Microprocessor Unit (2 of 3)
• Registers – hold memory
address
– Bank Select Register (BSR)
• 4-bit register used in direct
addressing the data
memory
– File Select Registers (FSRs)
• 16-bit registers used as
memory pointers in indirect
addressing data memory
– Program Counter (PC)
• 21-bit register that holds
the program memory
address while executing
programs
4/10/2024 95
 Microprocessor Unit (3 of 3)
• Control unit
– Provides timing and control signals to various
Read and Write operations

4/10/2024 96
 PIC18F452/4520 Memory

4/10/2024 97
 Data Memory Organization
• The data memory in PIC18 devices is
implemented as static RAM.
• Each register in the data memory has a 12-bit
address, allowing up to 4096 bytes of data
memory.
• The memory space is divided into as many as
16 banks that contain 256 bytes each;

4/10/2024 98
 Data memory (SRAM)
• The data memory is either SRAM or SRAM and EEPROM.
• The data memory provides a place to store transitory data as an
application executes and is lost (except for the EEPROM data)
when power is removed from the system.
• The data memory SRAM is accessed through a 12-bit address so
the largest data memory available is 3968 bytes at address
0x000 through 0xF7F.
• The data memory SRAM also contains addresses that are used to
program the special functions of the microcontroller. These
special function registers (SFR) are at data memory addresses
0xF80 through 0xFFF or the upper 128 bytes of the data memory
space.
• The other data memory locations are called general function
registers (GFR) located at addresses 0x000 through 0xF7F. The
GFRs are also sometimes called register file locations.
 Data memory (EEPROM)
• If a PlC microcontroller contains EEPROM, the EEPROM data
memory is accessed through the special function registers in a
separate address space devoted to the EEPROM.

• The size of the EEPROM is determined by the PlC part number and
ranges from 0 bytes to a maximum of 1024 bytes.

• According to Microchip, a location in the EEPROM can be written

up to one million times.

• The EEPROM locations should only store information that does not
change frequently.
 Stack memory
• The stack memory is a small memory of 31 locations, each
contains 21-bit.

• The stack memory holds only return addresses from functions.

• The stack is 21 bits wide because it is designed to store

program memory addresses.

• 31-deep stack is large enough to function in most applications.

• The only way to use a location on the stack is to call a

function.
Data Memory 000h
07Fh
Access RAM
PIC16F8F2520/4520
080h Register File (data
Organization 0FFh
100h
Bank 0 GPR
memory) Map

Bank 1
FFF=212=16x256=4096=4K GPR
1FFh
• Data Memory up to 4k 200h
Bank 2
bytes GPR Access Bank

– Data register map - with 2FFh

00h
Access RAM (GPR)
12-bit address bus 000-FFF 7Fh
80h
Access SFR
• Divided into 256-byte D00h FFh

Bank 13
banks GPR
256 Bytes
DFFh
• There are total of F banks E00h GPR=General Purpose Reg.
SFR=Special Function Reg.
• Half of bank 0 and half of Bank 14
GPR
bank 15 form a virtual EFFh

F00h
bank that is accessible no F7Fh
Bank 15 GPR

matter which bank is F80h

FFFh Access SFR
selected
 PIC18F452/4520 – Data Memory with
Access Banks
• Three ways to access data registers:
– Direct using Bank Select Registers (BSR)
• Bank address (4-bit) + Instruction (8-bit)
– Indirect using File Select Registers (FSR)
• FSR contains the address of the data
register
• MPU uses FSR to access data registers
– Access Bank
• using General Purpose Registers (GPR)
directly accessible via 8-bits of register
 Data Memory with Access Banks

GPR=General Purpose Reg.

SFR=Special Function Reg.

We will discuss the access to Data Memory also known as

every region later, while talking “Register File”
about PIC18 instructions

FFF=212=16x256=4096=4K
 Accessing Data Memory
The machine code for a PIC18 instruction has only 8 bits for a data
memory address which needs 12 bits. The Bank Select Register
(BSR) supplies the other 4 bits.

26
 Program Memory Organization
• The program counter (PC) is 21-bit long, which
enables the user program to access up to 2 MB
of program memory.
– The PIC18 has a 31-entry return address stack to
hold the return address for subroutine call.
– After power-on, the PIC18 starts to execute
instructions from address 0.
– The location at address 0x08 is reserved for high-
priority interrupt service routine.
– The location at address 0x18 is reserved for low-
priority interrupt service routine.
4/10/2024 106
 Program Memory Organization
• The PIC18F2420 and PIC18F4420 each have 16
Kbytes of Flash memory and can store up to
8,192 single-word instructions.

• The PIC18F2520 and PIC18F4520 each have 32

Kbytes of Flash memory and can store up to
16,384 single-word instructions.

4/10/2024 107
4/10/2024 108
 Program Memory
The RESET vector
address is at 0000h and A 21-bit program counter is
capable of addressing the 2-
the interrupt vector Mbyte program memory
addresses are at 0008h space.
and 0018h.

PIC18F452 each have 32

Kbytes of FLASH
memory.
This means that it can
store up to 16K of single
word instructions
 PROGRAM MEMORY MAP AND STACK
• The program memory map
for PIC18F2420/2520/
4420/4520 devices is
shown in Figure 5-1.

4/10/2024 110
 Program counter (PC):
• The Program Counter (PC) specifies the address of the
instruction to fetch for execution.
• Program counter is 21-bit register.
• It holds the address of instruction in memory.
• Its function is to keep the track of program execution.
• The program instruction bytes are fetched from
location in memory that are addressed by the
program counter.
• The data bytes in program memory are accessed by
the PC.
4/10/2024 111
 Program counter (PC):
• The PC addresses bytes in the program memory.
• To prevent the PC from becoming misaligned with
word instructions, the Least Significant bit of PCL is
fixed to a value of ‘0’.
• The PC increments by 2 to address sequential
instructions in the program memory.
• The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly.

4/10/2024 112
 stack pointer
• RETURN ADDRESS STACK:
– The return address stack allows any combination of up to 31 program calls and
interrupts to occur.
– The PC is pushed onto the stack when a CALL or RCALL instruction is executed
or an interrupt is Acknowledged.
– The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE
instruction.
– PCLATU and PCLATH are not affected by any of the RETURN or CALL
instructions.
– The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer,
STKPTR.
– The stack space is not part of either program or data space.
– The stack pointer is readable and writable and the address on the top of the
stack is readable and writable through the top-of stack Special File Registers.
– Data can also be pushed to, or popped from the stack, using these registers.
– The stack pointer is initialized to ‘00000’ after all Resets.

4/10/2024 113
• Top-of-Stack Access
• Only the top of the return address stack (TOS) is readable and writable.
• A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack
location pointed to by the STKPTR register (Figure 5-2).
• This allows users to implement a software stack if necessary.
• STKPTR REGISTER

4/10/2024 114
 PIC18 Instruction Cycle
• The microcontroller clock input, whether from an
internal or external source, is internally divided
by four to generate four non-overlapping
quadrature clocks (Q1, Q2, Q3 and Q4).
• Internally, the program counter is incremented on
every Q1; the instruction is fetched from the
program memory and latched into the instruction
register during Q4.
• The instruction is decoded and executed during
the following Q1 through Q4.
4/10/2024 115
4/10/2024 116
 Addressing Modes
• Information in the data memory space can be
addressed in several ways. For most instructions, the
Addressing mode is fixed.
• All MCUs use addressing modes to specify the operand to
be operated on.
• The PIC18 MCU provides register direct, immediate,
inherent, indirect, and bit-direct addressing modes for
specifying instruction operands.
• Other instructions may use up to three modes, depending on
which operands are used and whether or not the extended
instruction set is enabled.

4/10/2024 117
• The PIC18F provides six addressing
modes:
1. Literal or Immediate Addressing Mode
2. Inherent or Implied Addressing Mode
3. Direct or Absolute Addressing Mode
4. Indirect Addressing Mode
5. Relative Addressing Mode
6. Bit Addressing Mode

4/10/2024 118
 Literal or Immediate Addressing
Mode
• Immediate addressing mode:
• In the literal or immediate mode, the operand data is a literal or
constant data.
• Immediate data is part of the instruction. This means that the data
follows the opcode after assembling an instruction with immediate
addressing mode.
• The immediate addressing mode is used to load the data into PIC
registers and WREG register.
• However, it cannot use to load data into any of the file register.
• Example:
– 1. MOVLW 50H
– 2. ANDLW 40H
– 3. IORLW 60H

4/10/2024 119
 Direct or Absolute Addressing Mode
• Direct addressing mode:
• In direct addressing mode, the 8- bit data in RAM memory
location whose address is specified in the instruction.
• This address specifies either a data register address in one of
the banks of data SRAM or a location in the Access Bank as the
data source for the instruction.
• Direct addressing mode specifies all or part of the source
and/or destination address of the operation within the opcode
itself.
• This mode is used for accessing the RAM file register.
• Example:
– 1. MOVWF 0X10
– 2. MOVFF PORTB, POTRC
– 3. MOVFF 0X30, PORTC

4/10/2024 120
 Indirect Addressing Mode
• indirect addressing mode:
• In Indirect Addressing Mode, a register is used as a
pointer to an address in the data memory.
• indirect addressing mode is used for accessing data
stored in the RAM part of file register.
• In this addressing mode a register is used as pointer to
the memory location of the file register.
• Three file select registers are used. They are FSR0,
FSR1 and FSR2.
• Example:
– 1. LFSR1,0X55
– 2. MOVWF INDF2

4/10/2024 121
 Indirect Addressing Mode
• The PIC18F provides the indirect addressing mode with four sub-modes as
follows:
– 1. Indirect with post-increment mode
– 2. Indirect with post-decrement mode
– 3. Indirect with pre-increment mode
– 4. Indirect with 8-bit indexed mode
• The sub-modes can be used with various PIC18F instructions. The SFRs
are utilized by the sub-modes as follows:
• - Indirect with post-increment mode uses SFR’s called POSTINC0 through
POSTINC2 registers. POSTINC0 is associated with FSR0, POSTINC1 with
FSR1, and POSTINC2 with FSR2.
• - Indirect with post-decrement mode uses SFR’s called POSTDEC0 through
POSTDEC2. POSDEC0 is associated with FSR0, POSDEC1 with FSR1,
and POSDEC2 with FSR2.
• - Indirect with pre-increment mode uses SFR’s called PREINC0 through
PREINC2 registers. PREINC0 is associated with FSR0, PREINC1 with
FSR1, and PREINC2 with FSR2.
• - Indirect with 8-bit indexed mode uses SFR’s called PLUSW0 through
PLUSW2. PLUSW0 is associated with FSR0, PLUSW1 with FSR1, and
4/10/2024 122
PLUSW2 with FSR2.
 Relative Addressing Mode
• Relative Addressing Mode:
• All conditional and one unconditional branch (BRA) instructions in the
PIC18F use relative addressing mode.
• The conditional branch instructions in the PIC18F are based on four flags,
namely C, Z, OV, and N. Each conditional branch instruction specifies an 8-
bit offset.
• As an example, consider BNC 0x03.
• Note that BNC stands for “Branch if no carry”. If the C (carry flag) in the
Status register is 0, then the PC is loaded with the (PC +2 + 03H x 2).
• When the PIC18F executes the BNC instruction, the PC points to the next
instruction. This means that if BNC is located at address 0050H in program
memory, the PC will contain 0052H (PC + 2) when the PIC18F executes BNC.
Hence, if C = 0, then after execution of the BNC 0x03 instruction, the PC will
be loaded with address 0058H (0052H + 03H x 2). Hence, the program will
branch to address 0058H which is 6 steps forward relative to the current
contents of PC. This is called “Relative Addressing Mode”.
4/10/2024 123
4/10/2024 124
• Indexed ROM addressing mode:
– This addressing mode is used for accessing the
data from look up tables that reside in the PIC18
program ROM.

4/10/2024 125
 Standard Instruction Set
• The standard PIC18 instruction set adds many enhancements to the
previous PICmicro® instruction sets, while maintaining an easy
migration from these PICmicro instruction sets.
• Most instructions are a single program memory word (16 bits), but
there are four instructions that require two program memory
locations.
• Each single-word instruction is a 16-bit word divided into an
opcode, which specifies the instruction type and one or more
operands, which further specify the operation of the instruction.
• The instruction set is highly orthogonal and is grouped into four
basic categories:
– Byte-oriented operations
– Bit-oriented operations
– Literal operations
– Control operations
4/10/2024 126
 General Format for Instructions
• Byte-oriented file register operations

4/10/2024 127
• Bit-oriented file register operations

4/10/2024 128
• Control operations

4/10/2024 129
 PIC18F Instruction Set
• The PIC18 has 77 instructions.
• Four of these are 32-bit instructions, whereas the others are all 16
bits.
• A subset of the PIC18 instructions is:
– Data Movement Instructions
– Arithmetic instructions
– Logic instructions
– Rotate instructions
– Bit manipulation instructions
– Jump/Branch instructions
– Test, Compare, and Skip instructions
– Table Read/Write instructions
– Subroutine instructions
– System control instructions

4/10/2024 130
• Data Movement Instructions
– Memory data must be placed in appropriate registers before
useful operations can be performed.
– Data movement instructions are provided for this purpose. A
subset of the data movement instructions is listed in Table 1.3.

4/10/2024 131
• Arithmetic Instructions
• The PIC18F arithmetic instructions allow:
• ∙∙ 8-bit addition and subtraction
• ∙∙ 8-bit by 8-bit unsigned multiplication. The PIC18F does not provide any signed
multiplication and division (Signed and Unsigned) instructions.
• ∙∙ Negate instruction
• ∙∙ Decrement and Increment Instructions
• ∙∙ BCD Adjust (BCD Correction)
• All instructions in Table 6.6 are executed in one cycle.
• ∙∙ The size of each instruction is one word.
• ∙∙ a = 0 means that the data register is located in the access bank while a = 1
means that the contents of BSR specify the address of the bank.
• ∙∙ For destination: d = 0 means that the destination is WREG while d = 1 means
that the destination is file register. As mentioned before, W or F instead of 0 or 1
will be used in this book for better clarity.
• ∙∙ The PIC18F does not provide any multiplication (signed) and division (signed
and
• unsigned) instructions.

4/10/2024 132
4/10/2024 133
 Arithmetic Instructions
• ADDLW 8-bit ;Add 8-bit number to W & set flags
ADDLW 0x32 ;Add 32H to W

• ADDWF F,d,a ;Add W to F & set flags

;Save result in W if d = 0 (or W)
;Save result in F if d = 1 (or F)
ADDWF 0x20,0 ;Add W to REG20H and
;save result in W
ADDWF 0x20,W ;Alternate format

ADDWF 0x20,1 ;Add W to REG20H and

;save result in REG20H
ADDWF 0x20,F ;Alternate format

330_03 134
 Arithmetic Instructions
• ADDWFC F,d,a ;Add W to F with carry
;and save result in W or F
• SUBLW 8-bit ;Subtract W from literal
• SUBWF F,d,a ;Subtract W from F
• SUBWFB F,d,a ;Subtract W from F with borrow
• INCF F,d,a ;Increment F
• DECF F,d,a ;Decrement F
• NEGF F,a ;Take 2’s Complement of F

330_03 135
 Arithmetic Instructions
• MULLW 8-bit ;Multiply 8-bit Literal and W
;Save result in PRODH:PRODL
• MULWF F,a ;Multiply W and F
;Save result in PRODH:PRODL
• DAW ;Decimal adjust W for BCD
;Addition

330_03 136
 Points to Remember
• Arithmetic instructions
– Can perform operations on W and 8-bit literals
• Save the result in W
– Can perform operations an W and F
• Save the result in W or F
– In general, affect all flags

330_03 137
• ADD Instructions
– ADD is the generic name of a group of instructions that
perform the addition operation.
– The ADD instruction may have two or three operands.
– A three-operand ADD instruction includes the carry flag in
the STATUS register as one of the operand.
– The PIC 18 MCU has 3 ADD instructions:

4/10/2024 138
4/10/2024
139
• SUB Instructions
• SUB is the generic name of a group of instructions that perform the
subtraction operation.
• The SUB instruction may have two or three operands. A three-operand
SUB instruction includes the carry flag in the STATUS register as one of the
operands.
• The PIC18 MCU provides four SUB instructions:

4/10/2024 140
4/10/2024 141
 Multiplication Instructions
• Multiplication Instructions
– The PIC18F includes an 8 x 8 hardware multiplier as part of the
ALU.
– The multiplier performs an unsigned operation and provides a
16-bit result that is stored in the product register pair,
PRODH:PRODL.
– Because of hardware implementation, the multiplier executes
the multiplication operation in a single instruction cycle.
– The PIC18F includes two instructions for performing 8-bit x 8-bit
unsigned multiplication providing 16-bit result in the product
register PRODH:PRODL.
– None of the status flags are affected. Note that neither overflow
nor carry is possible in this operation.
4/10/2024 142
4/10/2024 143
• The PIC18F unsigned multiplication instructions are described in the
following:
• MULLW data8 ( MULLW 0x03)
– instruction performs an unsigned multiplication between the 8-bit
contents of WREG and 8-bit immediate data.
– The 16-bit result is placed in the PRODH:PRODL register pair.
– PRODH contains the high byte, and PRODL contains the low byte.
– The contents of WREG are unchanged.
– As an example, consider MULLW 0x03.
• Prior to instruction execution: [WREG] = 02H
• After Instruction execution: [PRODH] = 00H, [PRODL] = 06H, [WREG] = 02H
• = unchanged
• MULWF F, a (MULWF 0x50)
– instruction performs an unsigned multiplication between the 8-bit contents of
WREG and 8-bit contents of the specified data register.
– The 16-bit result is placed in the PRODH:PRODL register pair.
– PRODH contains the high byte, and PRODL contains the low byte.
– The contents of the WREG and the data register are unchanged.
– The data register is in the access bank if a = 0 or specified by BSR if a = 1.
4/10/2024 144
 Negate instruction
• The PIC18F Negate instruction is illustrated by means
of numerical examples in the following.
– NEGF F, a (NEGF 0x70) instruction negates the contents of
the specified data register using two’s complement.
– The result is stored in the data register.
– The data register is in access bank if a = 0 or specified by
BSR if a = 1.
– An example is NEGF 0x70.
• Prior to instruction execution: [0x70] = 02H.
• After instruction execution: [0x70] = FEH = – 2 (decimal).

4/10/2024 145
 Decrement and Increment Instructions
• The PIC18F decrement and increment instructions are
illustrated in the following by means of numerical
examples.
– DECF F, d, a (DECF 0x50, W or DECF 0x50, F)
• decrements the contents of the specified data register by 1.
• The result is stored in WREG if d = 0 or in the data register if d = 1.
• The data register is in the access bank if a = 0 or specified by BSR
if a = 1.
• All flags are affected.
– An example is DECF 0x50, F.
– Prior to instruction execution: [0x50] = 01H.
– After instruction execution: [0x50] = 00H.
– Note that DECF 0x50, W decrements [0x50] by 1 and the result
is stored in WREG.
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 Decrement and Increment Instructions
• INCF F, d, a (INCF 0x50, W or INCF 0x50, F)
– increments the contents of the specified data register
by 1.
– The result is stored in WREG if d = 0 or in the data
register if d = 1.
– The data register is in the access bank if a = 0 or
specified by BSR if a = 1.
• An example is INCF 0x50, F.
– Prior to instruction execution: [0x50] = FFH = – 110.
– After instruction execution: [0x50] = 00H.
– INCF 0x50, W performs the same operation as INCF
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 BCD adjust instruction
• BCD adjust (BCD correction) instruction
– The PIC18F contains a BCD adjust instruction
– which will be illustrated in the following by means of a
numerical example.
– DAW instruction -adjusts the eight-bit result in WREG
after adding two packed
– BCD numbers using ADDLW or ADDWF or ADDWFC to
provide the correct packed BCD result.

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 BCD adjust instruction
• Consider the following instruction sequence:
– MOVLW 0x29 ; Move 29H into WREG
– ADDLW 0x54 ; Add 29H with 54H and store the result in
WREG
– DAW ; Decimal adjust WREG to provide the correct
packed BCD result
• The details of the result obtained by the instruction sequence
above are provided in the following:

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 Logic Instructions
• The PIC18F logic instructions include:
– logic AND,
– NOT (one’s complement),
– OR,
– Exclusive-OR operations.
• Table 6.7 lists PIC18F Logic instructions.
• we explain the Logic instructions using the access
bank and specifying F or W in place of ‘d’.

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 Logic Instructions
• COMF F,d,a ;Complement (NOT) F
;and save result in W or F
• ANDLW 8-bit ;AND Literal with W
• ANDWF F,d,a ;AND W with F and
;save result in W or F
• IORLW 8-bit ;Inclusive OR Literal with W
• IORWF F,d,a ;Inclusive OR W with F
;and save result in W or F
IORWF 0x12,F ;OR W with REG12H and
;save result in REG12H
• XORLW 8-bit ;Exclusive OR Literal with W
• XORWF F,d,a ;Exclusive OR W w/ F
;and save result in W or F

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 Logic Instructions

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 Logic Instructions
• All instructions in the above are executed in one
cycle.
• The size of each instruction is one word.
• All instructions affect N and Z flags; other flags are
not affected.
• a = 0 means that the data register is located in the
access bank while a = 1 means that the contents of
BSR specify the address of the bank.
• For destination: d = 0 means that the destination is
WREG while d = 1 means that the destination is file
register F.
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 Logic Instructions
• ANDLW data8 (ANDLW 0x8F)
– instruction ANDs the contents of WREG with the 8-bit literal (immediate data,
data8).
– The result is placed in WREG.
• As an example, consider ANDLW 0x8F.

• N and Z flags are affected. Z = 0 (Result is nonzero) and N = 0 (Most

Significant Bit of the result is 0).
• The status flags are affected in the same way after execution of other logic
instructions such as OR, XOR, and NOT.

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 Logic Instructions
• ANDWF F, d, a (ANDWF 0x60, W or ANDWF 0x60, F)
– instruction ANDs the contents of WREG with register ‘F’.
– If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank.
• As an example, consider ANDWF 0x60, F.
– Prior to instruction execution: [0x60] = 0xFF, [WREG] =
0x01
– After instruction execution: [0x60] = 0x01, [WREG] = 0x01
(unchanged), Z =0, N = 0
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 Logic Instructions
• The AND instruction can be used to perform a masking operation.
– If the bit value in a particular bit position is desired in data byte, the data
can be logically ANDed with appropriate data to accomplish this.
– For example, the bit value at bit 2 of an 8-bit number 0100 1Y10 (where
unknown bit value of Y is to be determined) can be obtained as follows:

• ANDWF 0x60, W performs the same operation as ANDWF 0x60, F

except the result is stored in WREG.

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 Logic Instructions
• COMF F, d, a (COMF 0x50, W or COMF 0x50, F)
– instruction complements (one’s) the contents of register ‘F’.
– If ‘d’ is ‘0’, the result is stored in WREG.
– If ‘d’ is ‘1’, the result is stored back in register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank.
• For example, consider COMF 0x50, W.
– Prior to instruction execution: [0x50] = 0x01, [WREG] = 0x57
– After instruction execution: [WREG] = 0xFE, [0x50] = 0x01
(unchanged), Z = 0, N = 1; No other flags are affected.
– Note that COMF 0x50, F is the same as COMF 0x50, F except
that the result is stored in WREG.
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 Logic Instructions
• XORLW data8 (XORLW 0x02)
– instruction exclusive-ORes the contents of WREG with 8-bit literal
(immediate data, data8).
– The result is placed in WREG.
• As an example, consider XORLW 0x02.
– Prior to instruction execution: [WREG] = 0x42
– After instruction execution: [WREG] = 0x40, Z = 0, N = 0 ; no other flags
are affected.
• The Exclusive-OR instruction can be used to find the ones
complement of a binary number by XORing the number with
all 1’s as follows:

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 Logic Instructions
• XORWF F, d, a (XORWF 0x42, W or XORWF 0x42, F)
– instruction exclusive Ores the contents of WREG with
register ‘F’.
– If ‘d’ is ‘0’, the result is stored in WREG.
– If ‘d’ is ‘1’, the result is stored back in the register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select bank.
• As an example, consider XORWF 0x42, W.
– Prior to instruction execution: [WREG] = 0xFF, [0x42] = 0xFF
– After instruction execution: [WREG] = 0x00, Z = 1, N = 0 ;
No other flags are affected.
• Note that XORWF 0x42, F stores the result in 0x42.
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 Rotate Instructions
• The PIC18 MCU provides four rotate instructions.
• The PIC18F Rotate instructions are:
– RRCF,
– RRNCF,
– RLCF, and
– RLNCF.

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 Rotate Instructions
• They allow a program to rotate the file register
right or left.
• These are two types of rotations.
– One is a simple rotation of the bits of the file
register, and
– the other is a rotation through the carry.

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 Rotate Instructions

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 Rotate Instructions
• All instructions in the above are executed in one cycle.
• The size of each instruction is one word.
• a = 0 means that the data register is located in the access bank
while a = 1 means that the contents of BSR specify the address
of the bank.
• For destination: d = 0 means that the destination is WREG
while d = 1 means that the destination is file register, F.
• RLCF and RRCF affect N, Z, and C flags according to the result
while RLNCF and RRNCF affect N and Z flags based on the
result.

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 Rotate Left f through Carry
• RLCF F, d, a (RLCF 0x40, W or RLCF 0x40, F)
– instruction rotates the contents of register ‘F’ one bit to the left through
the Carry flag.
– If ‘d’ is ‘0’, the result is placed in WREG.
– If ‘d’ is ‘1’, the result is stored back in register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank.
• As an example, consider RLCF 0x40, W.
– Prior to instruction execution: [WREG] = 0xFF, [0x40] = 0xAF , C = 0
– After instruction execution: [WREG] = 0x5E, C = 1, Z = 0 (result in WREG
after rotating is nonzero), N = 0 (most significant bit of result, 0x5E is 0);
no other flags are affected.
• Note that RLCF 0x40, F stores the result in data register 0x40.
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 Rotate Left f (No Carry)
• RLNCF F, d, a (RLNCF 0x70, W or RLNCF 0x70, F)
– instruction rotates the contents of register ‘F’ one bit to the left.
– If ‘d’ is ‘0’, the result is placed in WREG.
– If ‘d’ is ‘1’, the result is stored back in register ‘F’.
– If ‘a’ is ‘0’, the access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank
• As an example, consider RLNCF 0x70, F.
– Prior to instruction execution: [WREG] = 0x89, [0x70] = 0x32
– After instruction execution: [0x70] = 0x64, [WREG] = 0x89 (unchanged),
Z=0
– (result in 0x70 after rotating is nonzero) , N = 0 (most significant bit of
result, 0x64 is 0) ; no other flags are affected.
• Note that RLNCF 0x70, W stores the result in WREG.
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 Rotate Right f through Carry
• RRCF F, d, a (RRCF 0x30, W or RRCF 0x30, F)
– instruction rotates the contents of register ‘F’ one bit to the right
through the Carry flag.
– If ‘d’ is ‘0’, the result is placed in WREG.
– If ‘d’ is ‘1’, the result is stored back in register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank .
• As an example, consider RRCF 0x30, F.
– Prior to instruction execution: [WREG] = 0x91, [0x30] = 0x27 , C = 0
– After instruction execution: [0x30] = 0x13, [WREG] = 0x91 (unchanged),
C = 1, Z = 0 (result, 0x13 is nonzero), N = 0 (most significant bit of result,
0x13 is 0) ; no other flags are affected.
• Note that RRCF 0x30, W stores the result in WREG.
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 Rotate Right f (No Carry)
• RRNCF F, d, a (RRNCF 0x60, W or RRNCF 0x60, F)
– instruction rotates the contents of register ‘F’ one bit to the right.
– If ‘d’ is ‘0’, the result is placed in WREG.
– If ‘d’ is ‘1’, the result is stored back in register ‘F’.
– If ‘a’ is ‘0’, the Access Bank is selected.
– If ‘a’ is ‘1’, the BSR is used to select the bank.
• As an example, consider RRNCF 0x60, F.
– Prior to instruction execution: [WREG] = 0xB3, [0x60] = 0x28
– After instruction execution: [0x60] = 0x14, [WREG] = 0xB3 (unchanged),
Z=0
– (result, 0x14 after rotating is nonzero), N = 0 (most significant bit of
result, 0x14 is 0) ; no other flags are affected.
• Note that RRNCF 0x60, W stores the result in WREG.
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• PIC18F4550 is an 8-bit microcontroller of PIC18 family.
• PIC18F family is based on 16-bit instruction set architecture.
• PIC18F4550 consists of 32 KB flash memory, 2 KB SRAM and 256
Bytes EEPROM.
• This is a 40 pin PIC Microcontroller consisting of 5 I/O ports (PORTA,
PORTB, PORTC, PORTD and PORTE). PORTB and PORTD have 8 pins
to receive/transmit 8-bit I/O data. The remaining ports have
different numbers of pins for I/O data communications.
• PIC18F4550 can work on different internal and external clock
sources. It can work on a varied range of frequency from 31 KHz to
48 MHz.
• PIC18F4550 has four in-built timers. There are various inbuilt
peripherals like ADC, comparators etc in this controller.
• PIC18F4550 is an advanced microcontroller which is equipped with
enhanced communication protocols like EUSART, SPI, I2C, USB etc.

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