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PLC1 Test 2015 01 Degree

The document is a written test for PLC Programming 1, with a total of 33 marks and a time allowance of 1.5 hours. It includes various questions on modular PLC systems, the PLC scan cycle, programming practices, and requires sketches and diagrams related to PLC operations. Additionally, it provides appendices with ladder symbols and logic block symbols for reference.

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saadasia1
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0% found this document useful (0 votes)
5 views9 pages

PLC1 Test 2015 01 Degree

The document is a written test for PLC Programming 1, with a total of 33 marks and a time allowance of 1.5 hours. It includes various questions on modular PLC systems, the PLC scan cycle, programming practices, and requires sketches and diagrams related to PLC operations. Additionally, it provides appendices with ladder symbols and logic block symbols for reference.

Uploaded by

saadasia1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

PLC Programming 1

SCEP518

Written Test
Time Allowed: 1 ½ hours

Weighting to final grade: 15%

Total Marks: 33

Notes:
 All working and answers should be in blue or black pen. Diagrams and
sketches only may be done in pencil.
 Calculators are the only electronic devices allowed
 Any work done in pencil or using white-out will not be eligible for re-marking.

Appendix: Ladder Symbols for Timer / Counter / Comparison

Student’s name _______________________


1. Name four typical modules used in a modular PLC system. (2 marks)

2. Briefly explain all steps of the PLC ‘scan cycle’. (3 marks)

3. Briefly describe one similarity between PLCs and relay logic. (2 marks)

Page 2 of 9
4. Briefly explain one important difference between switching PLC outputs by
transistors compared to triacs. (2 marks)

5. Sketch a diagram below showing the following details: (2 marks)


 a relay with a 24V AC coil,
 a normally-open push-button to switch the current to the coil, and
 a 110V DC load, switched by the relay contact. The load must be
energised when the relay coil is de-energised.

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6. Explain two aspects of good programming practice, as applied to PLC
programming. (2 marks)

7. Complete the diagram below to show: (3 marks)


 a 12 V DC sinking input terminal with one N/O wired push-button and
one N/C wired push-button.
 a sinking output terminal with one 24V DC relay coil

IN PLC OUT
0 0
1 1
2 2
3 3
4 4
5 5

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8. Refer to the program shown below and answer the questions that follow.

Figure 1 PLC ladder program

a) Complete the timing diagram below: (3 marks)


 You may ignore the effect of the scan cycle time.
 You may use the additional rows for working if you need to.

I0.0

I0.1

I0.2

Q0.0

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9. An emergency-stop button is to be used with a PLC.
 The PLC has one output, switching a relay coil.
 The PLC input and output circuits all operate on 24V DC. You may
show these as either sinking or sourcing.
 You may ignore other PLC inputs.

a. Sketch a wiring diagram showing the preferred safe use for an emergency-
stop button with a PLC. (2 marks)
Factors to refer to:
 NO or NC state of the e-stop contacts
 Where the e-stop is connected

PLC PLC
Input Output

b. Briefly explain the reasons for the connections you chose in your diagram
above. (2 marks)

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10. Refer to the Ladder logic program provided below and answer the
questions that follow.

40

Figure 2 Ladder logic program

a) Provide descriptive comments for the two rungs of the program as shown above. (2 marks)

b) Modify the program to meet the requirements below. Sketch a new ladder logic
program in the space on the following page. (4 marks)
 While timer TM0 is timing, an output light Q0.0 must flash on and off
repeatedly; on for 2 seconds and off for 1.2 seconds.
 If the output light flashes 12 times before the timer TM0 is finished, the
memory bit M0 must switch off and the counter must reset to zero.
 If the timer TM0 finishes before the counter reaches 12, the counter should be
reset to zero.

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Additional marks for:
c) Clarity and efficiency of ladder logic design (2 marks)
d) Include comments with your ladder logic solution. (2 marks)
Clearly state any assumptions that you make.

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Appendix: Ladder Logic Block Symbols
Counters: Timers

Comparison:

Page 9 of 9

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