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6.3.2.2.1 ADC Custom Channel Sequencer

The device incorporates an ADC custom channel sequencer. The ADC sequencer is used to specify which
channels are converted and in which order. In this way, channels that are of greater importance can be
converted more often than other lower-priority channels. The sequencer consists of 63 indexed slots that
provide a high level of flexibility in the channel-order configuration. In addition, the sequencer also provides
programmable start and stop index fields to configure the start and stop conversion points. Channel conversions
(and the order in which these conversions occur) are configured by writing to the respective ADC_CCS_IDS
register in the ADC CCS Configuration register page, while the start/stop index is configured by writing to
the ADC_CCS_CFG_0 register (located in the ADC CCS Configuration register page as well). In direct-mode
conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode
conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped.
The ADC input channel assignments for the sequencer are listed in Table 6-3.
Table 6-3. Custom Channel Sequence ADC Input
Assignments
CCS_ID[2:0] ADC INPUT
000 GND
001 SENSE0
010 SENSE1
011 ADC0
100 ADC1
101 TMP

6.3.2.3 Low-Latency Digital Filter

The device integrates a low-pass digital filter that performs both decimation and filtering on the ADC output
data, which helps with noise reduction. The digital filter is automatically adjusted for the different output data
rates and always settles within one conversion cycle. The user has the flexibility to choose different output
conversion time periods (tCT) from 52µs to 4.122ms. With this configuration the first amplitude notch appears
at the Nyquist frequency of the output signal which is determined by the selected conversion time period and
defined as fNOTCH= 1 / (2 × tCT). This means that the filter cut-off frequency scales proportionally with the data
output rate. Figure 6-5 shows the filter response when the 1.054ms conversion time period is selected
0

−10

−20
Gain (dB)

−30

−40

−50

−60
1 10 100 1k 10k 100k
Frequency (Hz) G001

Conversion time = 1.054ms,

single conversion only

Figure 6-5. ADC Frequency Response

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6.3.2.4 Flexible Conversion Times and Averaging

ADC conversion times for shunt voltage, bus voltage, and temperature can be set independently from 52μs to
4.122ms. The flexibility in conversion time allows for robust operation in a variety of noisy environments. The
device also allows for programmable averaging times from a single conversion all the way to an average of 1024
conversions. The amount of averaging selected applies uniformly to all active measurement inputs. Figure 6-6
and Figure 6-7 illustrate the effect of conversion time and averaging on a constant input signal.

Conversion Time: 52s

Conversion Time: 52s

12.5V/div
50V/div

Conversion Time: 1.054ms Conversion Time: 1.054ms

Conversion Time: 4.122ms

Conversion Time: 4.122ms

0 2000 4000 6000 8000 10000 0 2000 4000 6000 8000 10000
Number of Conversions Number of Conversions
Figure 6-6. Noise vs Conversion Time Figure 6-7. Noise vs Conversion Time
(Averaging = 1) (Averaging = 128)

6.3.2.5 Integrated Precision Oscillator

The internal timebase of the device is provided by an internal oscillator that is trimmed to less than 0.5%
tolerance at room temperature. The precision oscillator is the timing source for ADC conversions, as well as
the time-count used for calculation of energy and charge. The digital filter response varies with conversion time;
therefore, the precise clock maintains filter response and notch frequency consistency across temperature. On
power up, the internal oscillator and ADC take roughly 300µs to reach < 1% error stability.

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6.3.3 Output Switch Overview

The AMC7908 facilitates rapid turn-on and turn-off of the voltage at the device OUT outputs. The OUT0 and
OUT2 outputs (from groups A and B) can be switched on or off by the DRVEN inputs or alternatively through
software. The ON voltages are set by the DAC0 and DAC2 outputs of each respective DAC group, while the
OFF voltages are set by either VSS or a specified clamp voltage. The OUT0 and OUT2 pins are driven by DAC0
and DAC2 when the corresponding switch control pin or bit is asserted high (drive enabled). Otherwise, the OUT
pins are in a disabled state, and driven to either VSS or the corresponding clamp DAC.
Additionally, the DAC1 and DAC3 outputs from each group include a simplified switch network that facilitates fast
turn-off. The DAC1 and DAC3 pins can be switched on or off, either through one of the DRVEN pins or through
software. The DAC1 and DAC3 output pins are driven by the DAC1 and DAC3 buffers when on, and to VSS
when off. While fast turn-off is possible, turn-on time is limited by the DAC1 and DAC3 buffer bandwidth, and the
time taken by DAC1 and DAC3 to exit power-down state.
The switches are designed to be bidirectional, allowing for two-way current when powered on and blocking
voltage when powered off. The switch control is optimized for minimum delay between the DRVEN input and the
output pins voltage switching. The switches default to the off (drive disabled) state at start-up or after an alarm
event. Along with a VDD supply collapse, there are three additional reset events: a logic low on the RESET pin,
a software reset command, or an I2C general-call reset. All reset events generate a power-down, drive disable
sequence. At reset, the DAC and OUT outputs go to VSS.
Figure 6-8 shows the configuration of switching channels in the AMC7908, for both DAC output groups.
Group A Channels 1 - 4 Group B Channels 1 - 4

PDACA0 PDACB0
DACA0 DACB0

DACA0 DACB0
13-Bit 13-Bit
VSSA OUTA0 VSSB OUTB0
DRVEN[0:1] Pin or DRVEN_DACA0 Bit;CLAMP_SEL DRVEN[0:1] Pin or DRVEN_DACB0 Bit;CLAMP_SEL

DRVEN[0:1] Pin or DRVEN_DACA1 Bit or PDACA1 bit DRVEN[0:1] Pin or DRVEN_DACB1 Bit or PDACB1 bit

DACA1 DACB1
DACA1 DACB1
13-Bit 13-Bit

PDACA2 PDACB2
DACA2 DACB2

DACA2 DACB2
13-Bit 13-Bit
VSSA OUTA2 VSSB OUTB2
DRVEN[0:1] Pin or DRVEN_DACA2 Bit;CLAMP_SEL DRVEN[0:1] Pin or DRVEN_DACB2 Bit;CLAMP_SEL

DRVEN[0:1] Pin or DRVEN_DACA3 Bit or PDACA3 bit DRVEN[0:1] Pin or DRVEN_DACB3 Bit or PDACB3 bit

DACA3 DACB3
DACA3 DACB3
13-Bit 13-Bit

4 4 4 4

DRVEN, Powerdown and Clamp Control

DRVEN0 DRVEN1 CLAMP_SEL

Figure 6-8. Switch Block Diagram

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6.3.4 FLEXIO Pin

The AMC7908 features a FLEXIO pin that can be independently configured as a GPIO or a special function
pin. The function performed by the FLEXIO pin depends on the value written to the FLEXIO_FUNC field of the
GEN_CFG_1 register (located in the General Configuration page of the register map).
On the AMC7908, the following functions are performed by the FLEXIO pin. To enable FLEXIO special functions
on any DAC, the corresponding bits in the FLEXIO_EN register (located in the DAC Configuration register page)
must be set.
1. RESET: When FLEXIO_FUNC is set to 0x01, the FLEXIO pin acts as an active-low external reset. This
function is a default of the FLEXIO pin
2. ALARMOUT: When FLEXIO_FUNC is set to 0x02, the FLEXIO pin acts as an active-low alarm output.
The ALARMOUT pin is active-low and open-drain by default. The active level is configured by the
FLEXIO_OUT_POL bit, and the drive type is configured by the FLEXIO_OUT_ODE bit; see also Section
7.2.1.4. Use the ALARMOUT_SRC registers (addresses 0x48 and 0x49 in the General Configuration
register page) to configure the alarms that assert the pin; see also Section 7.2.
3. GPIO: When FLEXIO_FUNC is set to 0x04, the FLEXIO pin acts as a GPIO pin. The GPIO acts as an
output during write operations, and as an input during read operations. When a GPIO pin acts as an output,
the pin state is set by writing to the GPIO bit in the GPIO_DATA register (located in the global register
map). The active level is configured by the FLEXIO_OUT_POL bit, and the drive type is configured by the
FLEXIO_OUT_ODE bit; see also Section 7.2.1.4. When a GPIO pin acts as input, the digital value on the
pin is acquired by reading the GPIO_DATA register address. After a power-on reset or any forced reset, all
GPIO_DATA bits are reset to 1.
4. LDAC: When FLEXIO_FUNC is set to 0x08, the FLEXIO pin acts as an active-low trigger input for DAC
outputs DACA0 and DACA2. Specifically, when these DACs are configured to operate in synchronous mode,
the active data registers for these DACs only update after the pin is pulled to logic 0.
5. ALARMIN: When FLEXIO_FUNC is set to 0x10, the FLEXIO pin acts as an active-low alarm input pin. For
the ALARMIN pin to trigger DAC pin and OUT pin auto-power-down events, set the appropriate bits in the
DAC_APD_SRC and OUT_APD_SRC registers (located in the DAC Configuration register page).
6. DRVEN: When FLEXIO_FUNC is set to 0x20, the FLEXIO pin acts as switch-control input DRVEN2, in
addition to the existing DRVEN0 and DRVEN1 pins on the device. To enable DRVEN2 control on any
desired DAC, write to the respective bits in the FLEXIO_EN register (located in the DAC Configuration
register map),

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6.3.5 Internal Temperature Sensor

The device has an on-chip temperature sensor that measures the device die temperature. The normal operating
temperature range for the internal temperature sensor is limited by the operating temperature range of the
device (–40°C to +150°C).
The temperature sensor has a resolution of 16 bits (0.0078°C) and conversion is independent from the device
SAR ADC. Table 6-4 shows the temperature data results represented in binary format. The temperature data
format allows for representation of negative temperatures using signed 2's complement representation. Even
though the internal temperature sensor is operational for junction temperatures ranging from –40°C to +150°C,
the accuracy is specified only from –40°C to +125°C. Observe the parameter values listed in the Section 5.1 .
Table 6-4. Temperature Data Format (ADC_TMP [15:0])
INTERNAL TEMPERATURE REGISTER VALUE
TEMPERATURE
(°C) BINARY(1) HEX
–50 1110 0111 0000 0000 E700
–25 1111 0011 1000 0000 F380
–1 1111 1111 1000 0000 FF80
0 0000 0000 0000 0000 0000
1 0000 0000 1000 0000 0080
10 0000 0101 0000 0000 0500
25 0000 1100 1000 0000 0C80
50 0001 1001 0000 0000 1900
75 0010 0101 1000 0000 2580
100 0011 0010 0000 0000 3200
125 0011 1110 1000 0000 3E80
127 0011 1111 1000 0000 3F80
150 0100 1011 0000 0000 4B00

(1) Resolution is 0.0078125 °C/count.

To access the temperature data registers, read the ADC_TMP register, located in the global register page.
6.3.6 Programmable Out-of-Range Alarms
The AMC7908 is capable of continuously analyzing the supplies, reference, external ADC inputs, and internal
temperature for normal operation. Normal operation for the conversion results is established through the lower-
and upper-threshold registers. When any of the monitored inputs is out of the specified range, the corresponding
alarm bit in the alarm status registers is set. In addition, the global alarm bit (GALR in the GEN_STATUS
register) is also set.
All of the alarms can be set to activate the FLEXIO pin, when configured as ALARMOUT. Any alarm event can
activate the pin as long as the alarm is not masked in the ALARMOUT_SRC registers. When an alarm event is
masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not
activate the ALARMOUT pin.
The ALARM_LATCH_DIS bit (located in the GEN_CFG_0 register, part of the General Configuration register
page) sets the latching behavior for the internal device alarms, as well as the ALARMOUT pin. When the
ALARM_LATCH_DIS bit is cleared to 0, the alarms are latched. The alarms are referred to as being latched
because the GALR bit and ALARMOUT pin remain active until the GEN_STATUS register is read by software,
even if the alarm condition subsides before the read. This design makes sure that out-of-limit events cannot
be missed if the software is polling the device periodically. When the ALARM_LATCH_DIS bit is set to 1, the
alarm bits are not latched. In this case, the GALR bit and ALARMOUT pin are deactivated as soon as the
error condition subsides, regardless of whether the GEN_STATUS register is read or not. Regardless of the
ALARM_LATCH_DIS bit value, all bits in the alarm status registers are cleared only after a software read. Read

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the alarm status registers twice to confirm that the bits have cleared after the alarm condition subsides. These
bits are reasserted if the out-of limit condition still exists on the next monitoring cycle.
In addition, all of the alarms can be set to force one or more DACs to the power-down state. To enable this
functionality, the alarm event must be enabled as a power-down source by writing to the appropriate bits within
the DAC_APD_SRC and OUT_APD_SRC registers (all located within the DAC Configuration register page).
Additionally, the DAC outputs to be controlled by the alarm event must be specified. In this application, when a
DAC control alarm event is detected, all the DACs that are set to power down in response to the alarm do so.
When the alarm event is cleared, the DACs are reloaded with the contents of the DAC active registers, which
allows the DAC outputs to return to the previous operating point without any additional commands.
6.3.6.1 Temperature Sensor Alarm Function
The AMC7908 continuously monitors the internal die temperature. The device includes a thermal error alarm
bit (THERMERR_ALR) that is set when the die temperature exceeds 150°C. A thermal error alarm can be
configured to set the ALARMOUT pin, as well as configures all DAC outputs into the power-down state. If a
power-down event occurs due to a thermal alarm, the DAC outputs remain in power-down mode even after
the device temperature lowers below 150°C. To resume normal operation, the thermal error alarm must be
cleared while the DAC channels are in power-down mode. Apart from the thermal error alarm, the device also
features a temperature alarm with a configurable threshold (written to the TMP_UP_THRESH register in the
ADC Configuration register page). The TMP_ALR bit (in the ALARM_STATUS_0 global register) is set when
the ADC reads a temperature that exceeds the threshold, and can be configured to set the ALARMOUT pin or
trigger DAC power-down events.
6.3.6.2 Supply Out-of-Range Alarm Function
The AMC7908 is capable of monitoring all power supply voltages, including the internal reference. For VSS and
VCC power supply pins, after the voltage supply reaches the power-on threshold, the corresponding bits in the
Alarm Status registers are set if the magnitude of voltage at the respective supply pin is less than the supply
collapse threshold. Table 6-5 shows the voltage thresholds for power-supply alarm activation.
Table 6-5. Supply Alarm Thresholds
POWER SUPPLY ALARM THRESHOLD (POWER-ON) ALARM THRESHOLD (SUPPLY COLLAPSE)
VDD 2.9V 2.3V
VCCA/VCCB 2.2V 1.7V
VSSA/VSSB (low-range) –2.2V –1.7V
VSSA/VSSB (mid-range) –3.7V –3.2V
VSSA/VSSB (high-range) –6.7V –6.2V

The alarm depends on voltage magnitude (not polarity); therefore, the VSSA and VSSB alarms are set when the
respective pin voltages are less negative than the specified supply collapse thresholds. Additionally, the VSSA
and VSSB alarm thresholds are determined based on the range selected for the respective DAC group; see also
Section 7.2.1.5.
The device provides out-of-range detection for the high performance internal reference. If the internal reference
voltage is less than 1.5V (after initially reaching a power-on threshold of 2.0V), the reference alarm flag is set.
Verify that the reference alarm condition has not been issued prior to powering up the DAC output buffers.
By setting the appropriate bits in the DAC_APD_SRC and OUT_APD_SRC registers, both the power supply and
internal reference alarms can be configured to trigger the alarm pin, a DAC auto power-down event, or both.

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6.3.6.3 ADC Alarm Function

The device provides independent out-of-range detection for each of the ADC inputs. Figure 6-9 shows the
out-of-range detection block. When the measurement is out-of-range, the corresponding alarm bit in the alarm
status register is set to flag the out-of-range condition. The values in the ADC high limit and low limit registers
define the upper and lower bound thresholds for the ADC inputs.
ADCn
High Limit ±
(upp er b ound)
+

ADCn ADCn-ALR
Conversion Value Bit

±
ADCn
Low Limit +
(lower boun d)

Figure 6-9. ADC Inputs Out-of-Range Alarms

To prevent false alarms, an alarm event is only registered when the monitored signal is out of range for an N
number of consecutive conversions. If the monitored signal returns to the normal range before N consecutive
conversions, an alarm event is not issued. The false alarm factor, N, for the ADC input alarms can be configured
by writing to the FALR_ADC, FALR_SENSE and/or FALR_TMP fields in the ADC_GEN_CFG register (located in
the ADC Configuration register page).
If an ADC input signal is out of range and the alarm is enabled, the corresponding alarm bit is set to 1. However,
the alarm condition is cleared only when the conversion result returns a value lower than the high limit register
setting and higher than the low limit register setting by the number of codes specified in the ADC hysteresis
setting (see Figure 6-10). The hysteresis for ADC alarms can be set by writing to bits 7 through 0 in the
ADC_HYST_0 register. Hysteresis can also be set for the SENSE input alarms, by writing to bits 7 through 0 in
the ADC_HYST_1 register. In both these cases, the hysteresis is a programmable value between 0 LSB to 127
LSB.

High Th reshold

Hysteresis

Low Th reshold Hysteresis

Over High Alarm Belo w Low Alarm

Figure 6-10. ADC Alarm Hysteresis

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6.4 Device Functional Modes

The DACs in the AMC7908 are split into groups A and B, each with four DAC channels and two OUT channels.
The output range and clamp voltage for each DAC group is set independently, and thus, enables the device to
operate in one of the following modes:
• All-positive DAC range mode
• All-negative DAC range mode
• Mixed DAC range mode
6.4.1 All-Positive DAC Range Mode
In the AMC7908 all-positive DAC range mode, the two DAC groups are set to a positive-voltage output range
(0V to 10V).
Ensure that the minimum DAC output for each group is not less than the corresponding VSS voltage. In
all-positive DAC range mode, the minimum DAC output for both groups is 0V; consequently, connect the VSSA
and VSSB pins to GND.
Ensure that the maximum DAC output for each group is greater than the corresponding VCC voltage. In all-
positive DAC range mode, connect the VCCA and VCCB pins to a positive supply voltage; however these
pins are not required to be tied to the same potential. For best output and switching performance, ensure
that the voltage at the VCCA pin is always less than or equal to the voltage at the VCCB pin. Typically, the
positive voltage at each VCC pin is dictated by the desired positive-voltage output range, but this configuration
is not required. In the case where the VCC supply voltage for a group is less than the positive full-scale range
configuration, the maximum DAC voltage is limited to VCC[A,B]. Table 6-6 lists the typical configurations for this
mode.
Table 6-6. All-Positive DAC Range Mode Typical Configuration
PIN TEST CONDITIONS TYPICAL CONNECTION
VDD — 4.5V to 5.5V
VIO VIO ≤ VDD 1.65V to 5.5V
VCCA VDACA ≤ VCCA 3V ≤ VCCA ≤ 11V
VCCB VDACB ≤ VCCB 3V ≤ VCCB ≤ 11V
VSSA — GND
VSSB — GND
Thermal Pad — GND

After a reset event, the output range for each DAC group is automatically set by the autorange detector.
The VSS[A,B] pins set the clamp voltage for each DAC group. The clamp voltage depends only on the voltage
in the VSS[A,B] pins; therefore, changes to the DAC range registers do not affect the clamp setting. With both
VSSA and VSSB pins connected to GND, the clamp voltage for all DACs is 0V.

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6.4.2 All-Negative DAC Range Mode

In the AMC7908 all-negative DAC range mode, the two DAC groups are set to a negative-voltage output range
(–10V to 0V).
Ensure that the maximum DAC output for each group is not less than the corresponding VCC voltage. In
all-negative DAC range mode, the maximum DAC output for both groups is 0V; consequently, connect the VCCA
and VCCB pins to GND.
Ensure that the minimum DAC output for each group is not less than the corresponding VSS voltage. In all-
negative DAC range mode, connect the VSSA and VSSB pins to a negative supply voltage; however, these pins
are not required to be tied to the same potential. Specifically, ensure that the voltage at the VSSA pin is always
less than (more negative) or equal to the voltage at the VSSB pin. Typically, the negative voltage at each VSS
pin is dictated by the desired negative-voltage output range, but this configuration is not required. In the case
where the VSS supply voltage for a group is less than the negative full-scale range configuration, the minimum
DAC voltage is limited to VSS[A,B]. Table 6-7 lists the typical configurations for this mode.
Table 6-7. All-Negative DAC Range Mode Typical Configuration
PIN TEST CONDITIONS TYPICAL CONNECTION
VDD — 4.5V to 5.5V
VIO VIO ≤ VDD 1.65V to 5.5V
VCCA — GND
VCCB — GND
VSSA VDACA ≥ VSSA –11V ≤ VSSA ≤ –3V
VSSB VDACB ≥ VSSB –11V ≤ VSSB ≤ –3V
Thermal Pad — GND

After a reset event, the output range for each DAC group is automatically set by the autorange detector.
The VSS[A,B] pins set the clamp voltage for each DAC group. The clamp voltage depends only on the voltage
in the VSS[A,B] pins; therefore, changes to the DAC range registers do not affect the clamp setting. With both
VSSA and VSSB pins connected to negative supply voltages, the clamp voltage for DAC group A is equal to
VSSA, and the clamp voltage for DAC group B is equal to VSSB.

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6.4.3 Mixed DAC Range Mode

In the AMC7908 mixed DAC range mode, DAC group A is set to a negative-voltage output range (–10V to
0V) and DAC group B is set to a positive-voltage output range (0V to 10V). DAC group B cannot be set to a
negative-voltage output range if DAC group A is set to a positive-voltage output range.
The VCC pin of DAC group B must be connected to a positive supply voltage. Typically, the positive voltage at
the VCC pin is dictated by the desired positive-voltage output range, but this configuration is not required. In the
case where the VCC supply voltage for the positive-voltage output range group is less than the positive-voltage
full-scale-range configuration, the maximum DAC voltage is limited to VCC. The VSS pin of DAC group B must
be connected to GND.
The VSS pin of DAC group A must be connected to a negative supply voltage. Typically, the negative voltage at
the VSS pin is dictated by the desired negative-voltage output range, but this configuration is not required. In the
case where the VSS supply voltage for the negative output range group is less than the negative full-scale range
configuration, the minimum DAC voltage is limited to VSS. Connect the VCC pin of DAC group A to GND. Table
6-8 lists the typical configurations for this mode.
Table 6-8. Mixed DAC Range Mode Typical Configuration
PIN TEST CONDITIONS TYPICAL CONNECTION
VDD — 4.5V to 5.5V
VIO VIO ≤ VDD 1.65V to 5.5V
VCCA — GND
VCCB VSS ≤ VDACB ≤ VCC 3V ≤ VCC ≤ 11V
VSSA VSS ≤ VDACA ≤ VCC –11V ≤ VSS ≤ –3V
VSSB — GND
Thermal Pad — GND

The VSS[A,B] pins set the clamp voltage for each DAC group. The clamp voltage depends only on the voltage
in the VSS[A,B] pins; therefore, changes to the DAC range registers do not affect the clamp setting. The clamp
voltage for DAC group A is equal to VSSA, and the clamp voltage for DAC group B is equal to VSSB.

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6.5 Programming
The device communicates with the system controller through a serial interface, which supports either an I2C-
compatible two-wire bus or an SPI-compatible bus. The device includes a robust mechanism that detects
between an SPI-compatible or I2C-compatible controller, and automatically configures the interface accordingly.
The interface-detection mechanism operates at start-up, thus preventing protocol change during normal
operation.
Figure 6-11 shows that the device uses a paging system to organize registers by functionality.

Main Bus

Global Registers
Addresses: 0x00 to 0x1C

Page 0x00

General Configuration Registers

Addresses: 0x40 to 0x70

Page 0x01

ADC Configuration Registers

Addresses: 0x40 to 0x58

Page 0x02

ADC CCS Configuration Registers

Addresses: 0x40 to 0x7F

Page 0x03

DAC Configuration Registers

Addresses: 0x40 to 0x52

Page 0x04

DAC Buffer Data Registers

Addresses: 0x40 to 0x47

Page 0x06

DAC Active Data Registers

Addresses: 0x40 to 0x47

Figure 6-11. Register Page System

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In both SPI and I2C configurations, address 0x01 is used to select the different pages in the device. To read
and write to one of the device registers, the page for that register must first be selected by writing the 5-bit
representation of the page number (PAGE[4:0]) to address 0x01, as shown in Figure 6-12. The page register
holds the page value until a new page address is programmed to the device.
RegAddr[6:0] Data[15:8] Data[7:0]
SPI W
0x01 0x00 { 000, PAGE[4:0] }

RegAddr[6:0] Data[15:8] Data[7:0]

I2C S TargetAddr[6:0] W A B
0x01
A
0x00
A
{ 000, PAGE[4:0] }
A P

From Controller to Peripheral (SPI) or Target (I2C)

From Target to Controller

Figure 6-12. Page Access Format

Addresses 0x00 to 0x3F in each page are global registers, thus enabling access of these bits regardless of the
page configuration.
6.5.1 I2C Serial Interface
In I2C mode, the device operates only as a target device on the two-wire bus. Connections to either bus
are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike
suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The device
supports the transmission protocol for fast mode, and all data bytes are transmitted MSB first.
6.5.1.1 I2C Bus Overview
The device is I2C compatible. In I2C protocol, the device that initiates the transfer is called a controller, and
a device controlled by the controller is called a target. The bus must be controlled by a controller device that
generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions.
To address a specific device, a START condition is initiated. A START condition is indicated by pulling the data
line (SDA) from a high-to-low logic level while SCL is high. All targets on the bus receive the target address byte,
with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target
being addressed responds to the controller by generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a control signal.
After all data have been transferred, the controller generates a STOP condition. A STOP condition is indicated
by pulling SDA from low to high, while SCL is high.

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6.5.1.2 I2C Bus Definitions

The device is I2C-compatible and the bus definitions are listed in Table 6-9.
Table 6-9. I2C Symbol Set
CONDITION SYMBOL SOURCE DESCRIPTION
Begins all bus transactions. A change in the state of the SDA line, from
START S Controller high to low, while the SCL line is high, defines a START condition. Each
data transfer initiates with a START condition
Terminates all transactions and resets bus. A change in the state of the
SDA line from low to high while the SCL line is high defines a STOP
STOP P Controller
condition. Each data transfer terminates with a repeated START or STOP
condition.
IDLE I Controller Bus idle. Both SDA and SCL lines remain high.
Handshaking bit (low). Each receiving device, when addressed, is obliged
to generate an acknowledge bit. A device that acknowledges must pull
ACK (Acknowledge) A Controller/Target down the SDA line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of the acknowledge
clock pulse. Take setup and hold times into account.
Handshaking bit (high). On a controller receive, data transfer termination
NACK (Not Acknowledge) A Controller/Target can be signaled by the controller generating a not-acknowledge on the
last byte that has been transmitted by the target.
Active-high bit that follows immediately after the target address
sequence. Indicates that the controller is initiating the target-to-controller
READ R Controller data transfer. The number of data bytes transferred between a START
and a STOP condition is not limited and is determined by the controller
device. The receiver acknowledges data transfer.
Active-low bit that follows immediately after the target address sequence.
Indicates that the controller is initiating the controller-to-target data
WRITE W Controller transfer. The number of data bytes transferred between a START and a
STOP condition is not limited and is determined by the controller device.
The receiver acknowledges data transfer.
Generated by controller, same function as the START condition
REPEATED START Sr Controller
(highlights the fact that STOP condition is not strictly necessary.)
Active-high bit that indicates the controller is initiating a block access data
BLOCK ACCESS B Controller
transfer.

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6.5.1.3 I2C Target Address Selection

The I2C bus target address is selected by installing shunts from the A0 and A1 address pins to the VIO or GND
rails. The state of the address pins is tested after every occurrence of START condition on the I2C bus. The
device discerns between four possible options for each pin, shunt to VIO (logic 1), shunt to GND (logic 0), shunt
to SDA, and shunt to SCL for a total of four possible target addresses, as shown in Table 6-10.
Table 6-10. I2C Target Address Space
DEVICE PINS I2C TARGET ADDRESS
A1 A0 [A6:A0]
0 0 101 0000
0 1 101 0001
0 SDA 101 0010
0 SCL 101 0011
1 0 101 0100
1 1 101 0101
1 SDA 101 0110
1 SCL 101 0111
SDA 0 101 1000
SDA 1 101 1001
SDA SDA 101 1010
SDA SCL 101 1011
SCL 0 101 1100
SCL 1 101 1101
SCL SDA 101 1110
SCL SCL 101 1111

6.5.1.4 I2C Read and Write Operations

When writing to the device, the value for the address register is the first byte transferred after the target address
byte with the R/W bit low. Every write operation to the device requires a value for the address register, as shown
in Figure 6-13.

S TargetAddr[6:0] W A B RegAddr[6:0] A Data[15:8] A Data[7:0] A P

From Controller to Target

From Target to Controller

Figure 6-13. I2C Write Access Protocol

When reading from the device, the last value stored in the address register by a write operation is used to
determine which register is read by a read operation. To change which register is read for a read operation, a
new value must be written to the address register. This transaction is accomplished by issuing a target address
byte with the R/W bit low, followed by the address register byte; no additional data are required. The controller
can then generate a START condition and send the target address byte with the R/W bit high to initiate the read
command.
If repeated reads from the same register are desired, there is no need to continually send the address register
bytes because the device retains the address register value until the value is changed by the next write
operation. The register bytes are big endian and left justified.

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Terminate read operations by issuing a not-acknowledge command at the end of the last byte to be read. The
controller must leave the SDA line high during the acknowledge time of the last byte that is read from the target,
as shown in Figure 6-14.
S TargetAddr[6:0] W A B RegAddr[6:0] A Sr TargetAddr[6:0] R A Data[15:8] A Data[7:0] A P

From Controller to Target

From Target to Controller

Figure 6-14. I2C Read Access Protocol

Block access functionality is provided to minimize the transfer overhead of large data sets. Block access enables
multibyte transfers and is configured by setting the block access bit high. Until the transaction is terminated by
the STOP condition, the device reads and writes the subsequent memory locations, as shown in Figure 6-15 and
Figure 6-16. If the controller reaches address 0x7F in a page, the device continues reading and writing from this
address until the transaction is terminated.
Address of the first register of
the contiguous memory block

S TargetAddr[6:0] W A B RegAddr[6:0] A Data[15:8] A Data[7:0] A Data[15:8] A Data[7:0] A P

From Controller to Target Data to first register

From Target to Contoller

Figure 6-15. I2C Block Write Access

Address of the first register of
the contiguous memory block

S TargetAddr[6:0] W A B RegAddr[6:0] A Sr TargetAddr[6:0] R A

Data[15:8] A Data[7:0] A Data[15:8] A Data[7:0] A P

Data to first register

From Controller to Target

From Target to Controller

Figure 6-16. I2C Block Read Access

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6.5.1.5 I2C Timeout Function

The device resets the serial interface if either SCL or SDA are held low for 25ms (typical) between a START
and STOP condition. If the device is holding the bus low, the device releases the bus and waits for a START
condition. After the bus is released, all previously received frames on the bus are discarded by the device, and
any previous commands and acknowledgment requests are ignored. To avoid activating the timeout function, a
communication speed of at least 1kHz must be maintained for the SCL operating frequency. Figure 6-17 shows
the logic diagram for the timeout feature, while Figure 6-18 shows the timing diagram.

Bit 0 AMC7908 I2C Block

VIO Bit 1
25ms Counter (N-bit)
Bit N–2
Bit N–1
RPULLUP RPULLUP

SDA Frame Reset

SDA (Bidirectional)
2
I C Host Device
SCL
SCL In

Open Drain Buffers

Figure 6-17. I2C Timeout Logic Diagram

SCL (Host)

SCL (Gated)

SDA SDA from Host SDA Readback

0ms 25ms

Figure 6-18. I2C Timeout Timing Diagram

6.5.1.6 I2C General-Call Reset

The device supports reset using the two-wire general call address 00h (0000 0000b). The device acknowledges
the general-call address, and responds to the second byte. If the second byte is 06h (0000 0110b), the device
executes a software reset. This software reset initiates a reset event. The device takes no action in response to
other values in the second byte.

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6.5.2 Serial Peripheral Interface (SPI)

In SPI mode, the device is controlled through a flexible four-wire serial interface that is compatible with SPI-type
interfaces used on many microcontrollers and DSP controllers. The interface provides access to the device
registers.
6.5.2.1 SPI Bus Overview
A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a
continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is
24 bits long, thus the CS pin must stay low for at least 24 SCLK falling edges. The access cycle ends when the
CS pin is deasserted high. If the access cycle contains less than the minimum clock edges, the communication
is ignored. If the access cycle contains more than the minimum clock edges, only the last 24 bits are used by the
device. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.
In a serial interface access cycle, the first byte input to SDI is the instruction cycle that identifies the request as a
read or write command, and the 7-bit address to be accessed. The following bits in the cycle form the data cycle,
as shown in Table 6-11.
Table 6-11. SPI Serial Interface Access Cycle
BIT FIELD DESCRIPTION
Identifies the communication as a read or write command to the addressed register.
23 RW RW = 0 sets a write operation.
RW = 1 sets a read operation.
22:16 A[6:0] Register address. Specifies the register to be accessed during the read or write operation.
Data cycle bits.
15:0 DI[15:0] If a write command, the data cycle bits are the values to be written to the register with address A[6:0].
If a read command, the data cycle bits are don’t care values.

Read operations require that the SDO pin is first enabled by setting the SDO_EN bit. A read operation is initiated
by issuing a read command access cycle. After the read command, a second access cycle must be issued to get
the requested data, formatted as shown in Table 6-12. Data are clocked out on the SDO pin on SCLK rising or
falling edges, according to the FSDO bit setting.
Table 6-12. SDO Output Access Cycle
BIT FIELD DESCRIPTION
23 RW Echo RW bit from previous access cycle.
22:16 STATUS[6:0] Lower seven bits of the General Status (GEN_STATUS) register.
15:0 DO[15:0] Readback data requested on previous access cycle.

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7 Register Maps
7.1 Global Register Map
Table 7-1. Global Page: Global Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 NOP_RESET R/W 0000 SW_RESET / NOP[15:0]
01 PAGE R/W 0000 RESERVED PAGE[4:0]
GVCCVSS
GREF_ GTHERM_ GADC_ GSENSE_ ADC_ GALARM GTMP_
03 GEN_STATUS R 4000 RESERVED RESERVED _ RESERVED RESERVED GALR
ALR ALR ALR ALR READY IN_ALR ALR
ALR
ALARM_ ADC1_ ADC0_ SENSE1_ SENSE0_
04 R 0000 RESERVED TMP_ALR RESERVED RESERVED
STATUS_0 ALR ALR ALR ALR
ALARM_ ALARMIN_ REF_ THERM VSSB_ VSSA_ VCCB_ VCCA_
05 R 0000 RESERVED RESERVED RESERVED
STATUS_1 ALR ALR ERR_ALR ALR ALR ALR ALR
VCCB_ VSSB_ VSSB_ VSSA_ VSSA_ VSSA_
VCCB_ HIGH MID LOW VCCA_ HIGH MID LOW VDDL_
06 PWR_STATUS_0 R 0001 RESERVED
STS RANGE_ RANGE_ RANGE_ STS RANGE_ RANGE_ RANGE_ STS
STS STS STS STS STS STS
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
PDACB3_ PDACB2_S PDACB1_ PDACB0_S PDACA3_ PDACA2_S PDACA1_ PDACA0_
07 PWR_STATUS_1 R 0000 DACB3_ DACB2_ DACB1_ DACB0_ DACA3_ DACA2_ DACA1_ DACA0_
STS TS STS TS STS TS STS STS
STS STS STS STS STS STS STS STS
08 PWR_EN R/W 0200 RESERVED PDACB3 PDACB2 PDACB1 PDACB0 PDACA3 PDACA2 PDACA1 PDACA0
ALARM_
DAC_ ADC_
10 TRIGGER W 0000 RESERVED LATCH_
TRIG TRIG
CLR
11 GPIO_DATA R/W 0001 RESERVED GPIO
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
12 DRVEN_SW_EN R/W 00FF RESERVED SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
13 DRVEN R/W 0000 RESERVED
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
14 DAC_BCAST W 0000 RESERVED DAC[12:0]
ADC_ ALARM_
17 GLOBAL_CFG R/W 0000 RESERVED
BYP_EN BYP_EN
18 ADC_SENSE_0 R 0000 ADC[15:0]
19 ADC_SENSE_1 R 0000 ADC[15:0]
1A ADC_ADC_0 R 0000 ADC[15:0]
1B ADC_ADC_1 R 0000 ADC[15:0]
1C ADC_TMP R 0000 ADC[15:0]

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7.1.1 Global Registers: Global Page

7.1.1.1 NOP_RESET Register (address = 00h) [reset = 0000h]

Figure 7-1. NOP_RESET Register
15 14 13 12 11 10 9 8
SW_RESET[15:8]/NOP
R/W-0h

7 6 5 4 3 2 1 0
SW_RESET[7:0]/NOP
R/W-0h

Table 7-2. NOP_RESET Register Field Descriptions

Bit Field Type Reset Description
0 SW_RESET/NOP R/W 0h No operation (NOP) unless the data matches the following
specified value.
0x00AD: Software reset. Executes a full power-on-reset. Resets
the device and all registers to the default power-on-reset state.
Auto clears with execution

7.1.1.2 PAGE Register (address = 01h) [reset = 0000h]

Figure 7-2. PAGE Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED PAGE[4:0]
R-0h R/W-0h

Table 7-3. PAGE Register Field Descriptions

Bit Field Type Reset Description
4:0 PAGE R/W 0h Sets the page value. See the page map for more details.
Registers on the Global page are accessible from any page,
regardless of the page setting.
0x00: General Configuration Register Page
0x01: ADC Configuration Register Page
0x02: ADC CCS Configuration Register Page
0x03: DAC Configuration Register Page
0x04: DAC Buffer Register Page
0x06: DAC Active Register Page

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7.1.1.3 GEN_STATUS Register (address = 03h) [reset: 4000h]

Figure 7-3. GEN_STATUS Register
15 14 13 12 11 10 9 8
RESERVED GREF_ALR GTHERM_ALR GADC_ALR GSENSE_ALR
R-4h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
ADC_READY RESERVED GVCCVSS_ RESERVED GALARMIN_ RESERVED GTMP_ALR GALR
ALR ALR
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-4. GEN_STATUS Register Field Descriptions

Bit Field Type Reset Description
11 GREF_ALR R 0h Global reference status bit.
0: No alarm condition
1: Alarm condition present.
10 GTHERM_ALR R 0h Global thermal error/warning status bit.
0: No alarm condition
1: Alarm condition present.
9 GADC_ALR R 0h Global ADC status bit for all ADC inputs.
0: No alarm condition
1: Alarm condition present.
8 GSENSE_ALR R 0h Global sense voltage status bit for all SENSE voltage input pins.
0: No alarm condition
1: Alarm condition present.
7 ADC_READY R 0h ADC ready indicator.
0: ADC is ready for trigger to start.
1:ADC is not ready.
5 GVCCVSS_ALR R 0h Global VCC or VSS status bit.
0: No alarm condition
1: Alarm condition present.
3 GALARMIN_ALR R 0h Global ALARMIN status bit.
0: No alarm condition
1: Alarm condition present.
1 GTMP_ALR R 0h Global temperature sensor status bit.
0: No alarm condition
1: Alarm condition present.
0 GALR R 0h Global alarm bit. This bit is the OR function of all individual
alarm bits of the alarm status registers.

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7.1.1.4 ALARM_STATUS_0 Register (address = 04h) [reset: 0000h]

Figure 7-4. ALARM_STATUS_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_ALR
R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ALR ADC0_ALR RESERVED SENSE1_ALR SENSE_ALR
R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-5. ALARM_STATUS_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR R 0h Out-of-range alarm status for temperature sensor, defined by the
corresponding threshold registers.
0: Temperature reading is in the specified range
1: Temperature reading is out-of-range
5 ADC1_ALR R 0h Out-of-range alarm status for ADC1 defined by the
corresponding threshold registers.
0: ADC1 channel is in the specified range
1: ADC1 channel is out-of-range
4 ADC0_ALR R 0h Out-of-range alarm status for ADC0 defined by the
corresponding threshold registers.
0: ADC0 channel is in the specified range
1: ADC0 channel is out-of-range
1 SENSE1_ALR R 0h Out-of-range alarm status for SENSE1 defined by the
corresponding threshold registers.
0: SENSE1 channel reading is in the specified range
1: SENSE1 channel reading is out-of-range
0 SENSE0_ALR R 0h Out-of-range alarm status for SENSE0 defined by the
corresponding threshold registers.
0: SENSE0 channel reading is in the specified range
1: SENSE0 channel reading is out-of-range

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7.1.1.5 ALARM_STATUS_1 Register (address = 05h) [reset: 0000h]

Figure 7-5. ALARM_STATUS_1 Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ALR THERMERR_ RESERVED
ALR ALR
R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ALR VSSA_ALR RESERVED VCCB_ALR VCCA_ALR
R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-6. ALARM_STATUS_1 Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR R 0h ALARMIN alarm status.
0: ALARMIN has not triggered.
1: ALARMIN has triggered.
12 REF_ALR R 0h Reference alarm status.
0: Internal reference voltage is valid
1: Internal reference voltage is less than minimum reference
threshold voltage.
11 THERMERR_ALR R 0h Thermal error alarm status.
0: Die temperature is less than 150°C (typical)
1: Operating temperature greater than or equal to 150°C
5 VSSB_ALR R 0h VSSB alarm status.
0: VSSB has not been established or is more negative than the
minimum VSS threshold voltage
1: VSSB magnitude has reduced to less than the minimum VSS
threshold voltage magnitude
4 VSSA_ALR R 0h VSSA alarm status.
0: VSSA has not been established or is more negative than the
minimum VSS threshold voltage
1: VSSA magnitude has reduced to less than the minimum VSS
threshold voltage magnitude
1 VCCB_ALR R 0h VCCB alarm status.
0: VCCB has not been established or is greater than the
minimum VCC threshold voltage
1: VCCB has fallen below the minimum VCC threshold voltage
0 VCCA_ALR R 0h VCCA alarm status.
0: VCCA has not been established or is greater than the
minimum VCC threshold voltage
1: VCCA has fallen below the minimum VCC threshold voltage

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7.1.1.6 PWR_STATUS_0 Register (address = 06h) [reset = 0001h]

Figure 7-6. PWR_STATUS_0 Register
15 14 13 12 11 10 9 8
VCCB_STS VSSB_ VSSB_ VSSB_ VCCA_STS VSSA_ VSSA_ VSSA_
HIGHRANGE_ MIDRANGE_ LOWRANGE_ HIGHRANGE_ MIDRANGE_ LOWRANGE_
STS STS STS STS STS STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
RESERVED VDDL_STS
R-0h R-1h

Table 7-7. PWR_STATUS_0 Register Field Descriptions

Bit Field Type Reset Description
15 VCCB_STS R 0h Supply detection result for VCCB.
0: VCCB is less than the minimum VCC threshold voltage.
1: VCCB has exceeded the minimum VCC threshold voltage.
14 VSSB_HIGHRANGE_STS R 0h Supply detection result for VSSB.
0: VSSB is between 0V and the high range VSS threshold voltage.
1: VSSB has exceeded (is more negative than) the high range
VSS threshold voltage.
13 VSSB_MIDRANGE_STS R 0h Supply detection result for VSSB.
0: VSSB is between 0V and the mid range VSS threshold voltage.
1: VSSB has exceeded (is more negative than) the mid range
VSS threshold voltage.
12 VSSB_LOWRANGE_STS R 0h Supply detection result for VSSB.
0: VSSB is between 0V and the low range VSS threshold voltage.
1: VSSB has exceeded (is more negative than) the low range VSS
threshold voltage.
11 VCCA_STS R 0h Supply detection result for VCCA.
0: VCCA is less than the minimum VCC threshold voltage.
1: VCCA has exceeded the minimum VCC threshold voltage.
10 VSSA_HIGHRANGE_STS R 0h Supply detection result for VSSA.
0: VSSA is between 0V and the high range VSS threshold voltage.
1: VSSA has exceeded (is more negative than) the high range
VSS threshold voltage.
9 VSSA_MIDRANGE_STS R 0h Supply detection result for VSSA.
0: VSSA is between 0V and the mid range VSS threshold voltage.
1: VSSA has exceeded (is more negative than) the mid range
VSS threshold voltage.
8 VSSA_LOWRANGE_STS R 0h Supply detection result for VSSA.
0: VSSA is between 0V and the low range VSS threshold voltage.
1: VSSA has exceeded (is more negative than) the low range VSS
threshold voltage.
0 VDDL_STS R 1h Supply detection result for VDD.
0: VDD is less than the minimum threshold voltage.
1: VDD has exceeded the minimum threshold voltage.

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7.1.1.7 PWR_STATUS_1 Register (address = 07h) [reset = 0000h]

Figure 7-7. PWR_STATUS_1 Register
15 14 13 12 11 10 9 8
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
DACB3_ DACB2_ DACB1_ DACB0_ DACA3_ DACA2_ DACA1_ DACA0_
STS STS STS STS STS STS STS STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

7 6 5 4 3 2 1 0
PDACB3_ PDACB2_ PDACB1_ PDACB0_ PDACA3_ PDACA2_ PDACA1_ PDACA0_
STS STS STS STS STS STS STS STS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 7-8. PWR_STATUS_1 Register Field Descriptions

Bit Field Type Reset Description
15 DRVEN_DACB3_STS R 0h DACB3 drive enable status.
0: DRVEN = 0 (DACB3 disabled, outputs forced to VSS).
1: DRVEN = 1.
14 DRVEN_DACB2_STS R 0h DACB2 drive enable status.
0: DRVEN = 0 (DACB2 disabled, outputs forced to VSS).
1: DRVEN = 1.
13 DRVEN_DACB1_STS R 0h DACB1 drive enable status.
0: DRVEN = 0 (DACB1 disabled, outputs forced to VSS).
1: DRVEN = 1.
12 DRVEN_DACB0_STS R 0h DACB0 drive enable status.
0: DRVEN = 0 (DACB0 disabled, outputs forced to VSS).
1: DRVEN = 1.
11 DRVEN_DACA3_STS R 0h DACA3 drive enable status.
0: DRVEN = 0 (DACA3 disabled, outputs forced to VSS).
1: DRVEN = 1.
10 DRVEN_DACA2_STS R 0h DACA2 drive enable status.
0: DRVEN = 0 (DACA2 disabled, outputs forced to VSS).
1: DRVEN = 1.
9 DRVEN_DACA1_STS R 0h DACA1 drive enable status.
0: DRVEN = 0 (DACA1 disabled, outputs forced to VSS).
1: DRVEN = 1.
8 DRVEN_DACA0_STS R 0h DACA0 drive enable status.
0: DRVEN = 0 (DACA0 disabled, outputs forced to VSS).
1: DRVEN = 1.
7 PDACB3_STS R 0h DACB3 power status.
0: DACB3 disabled in low-power mode.
1: DACB3 is on.
6 PDACB2_STS R 0h DACB2 power status.
0: DACB2 disabled in low-power mode.
1: DACB2 is on.
5 PDACB1_STS R 0h DACB1 power status.
0: DACB1 disabled in low-power mode.
1: DACB1 is on.
4 PDACB0_STS R 0h DACB0 power status.
0: DACB0 disabled in low-power mode.
1: DACB0 is on.
3 PDACA3_STS R 0h DACA3 power status.
0: DACA3 disabled in low-power mode.
1: DACA3 is on.
2 PDACA2_STS R 0h DACA2 power status.
0: DACA2 disabled in low-power mode.
1: DACA2 is on.
1 PDACA1_STS R 0h DACA1 power status.
0: DACA1 disabled in low-power mode.
1: DACA1 is on.
0 PDACA0_STS R 0h DACA0 power status.
0: DACA0 disabled in low-power mode.
1: DACA0 is on.

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7.1.1.8 PWR_EN Register (address = 08h) [reset = 0200h]

Figure 7-8. PWR_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-2h

7 6 5 4 3 2 1 0
PDACB3 PDACB2 PDACB1 PDACB0 PDACA3 PDACA2 PDACA1 PDACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-9. PWR_EN Register Field Descriptions

Bit Field Type Reset Description
7 PDACB3 R/W 0h DACB3 enabled status.
0: DACB3 disabled.
1: DACB3 is enabled.
6 PDACB2 R/W 0h DACB2 enabled status.
0: DACB2 disabled.
1: DACB2 is enabled.
5 PDACB1 R/W 0h DACB1 enabled status.
0: DACB1 disabled.
1: DACB1 is enabled.
4 PDACB0 R/W 0h DACB0 enabled status.
0: DACB0 disabled.
1: DACB0 is enabled.
3 PDACA3 R/W 0h DACA3 enabled status.
0: DACA3 disabled.
1: DACA3 is enabled.
2 PDACA2 R/W 0h DACA2 enabled status.
0: DACA2 disabled.
1: DACA2 is enabled.
1 PDACA1 R/W 0h DACA1 enabled status.
0: DACA1 disabled.
1: DACA1 is enabled.
0 PDACA0 R/W 0h DACA0 enabled status.
0: DACA0 disabled.
1: DACA0 is enabled.

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7.1.1.9 TRIGGER Register (address = 10h) [reset = 0000h]

Figure 7-9. TRIGGER Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ALARM_ DAC_TRIG ADC_TRIG
LATCH_
CLR
R-0h W-0h W-0h W-0h

Table 7-10. TRIGGER Register Field Descriptions

Bit Field Type Reset Description
2 ALARM_LATCH_CLR W 0h Manually clear registers which are latching the alarm condition.
If an alarm condition is still present, the corresponding alarm
latches and alarm state are set again.
0: No action.
1: Clear the alarm bits.
1 DAC_TRIG W 0h Software LDAC trigger. This bit self-clears.
0: No action.
1: Initiate data transfer from DAC buffer registers to active
registers.
0 ADC_TRIG W 0h ADC conversion trigger. Set this bit to 1 to start the ADC
conversions. In direct-mode, this bit self-clears back to 0 after
all conversions are completed. In auto-mode, this bit remains
set and the ADC continuously converts until the user manually
clears the bit back to 0, stopping auto-mode. Before setting
ADC_TRIG to 1, confirm the ADC is ready by reading the
ADC_BUSY status bit twice in succession.
0: Stop ADC conversions. Read ADC_BUSY as 0 twice in
succession to confirm ADC is not converting data
1: Start ADC conversions

7.1.1.10 GPIO_DATA Register (address = 11h) [reset = 0001h]

Figure 7-10. GPIO_DATA Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED GPIO
R-0h R/W-1h

Table 7-11. GPIO_DATA Register Field Descriptions

Bit Field Type Reset Description
0 GPIO R/W 1h For write operations, the GPIO pin operates as an output, while
for read operations the GPIO pin operates as an input.0: Set
GPIO to logic low. 1: Set GPIO to logic high

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7.1.1.11 DRVEN_SW_EN Register (address = 12h) [reset = 00FFh]

Figure 7-11. DRVEN_SW_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_ SW_EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 7-12. DRVEN_SW_EN Register Field Descriptions

Bit Field Type Reset Description
7 DRVEN_SW_EN_DACB3 R/W 1h Enables software operation of DACB3 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
6 DRVEN_SW_EN_DACB2 R/W 1h Enables software operation of DACB2 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
5 DRVEN_SW_EN_DACB1 R/W 1h Enables software operation of DACB1 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
4 DRVEN_SW_EN_DACB0 R/W 1h Enables software operation of DACB0 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
3 DRVEN_SW_EN_DACA3 R/W 1h Enables software operation of DACA3 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
2 DRVEN_SW_EN_DACA2 R/W 1h Enables software operation of DACA2 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
1 DRVEN_SW_EN_DACA1 R/W 1h Enables software operation of DACA1 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.
0 DRVEN_SW_EN_DACA0 R/W 1h Enables software operation of DACA0 channel switch (DRVEN).
0: Software control disabled.
1: Software control enabled.

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7.1.1.12 DRVEN Register (address = 13h) [reset = 0000h]

Figure 7-12. DRVEN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_ DRVEN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-13. DRVEN Register Field Descriptions

Bit Field Type Reset Description
7 DRVEN_DACB3 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACB3.
0: DACB3 drive disabled, internally connected to VSSB.
1: DACB3 drive enabled.
6 DRVEN_DACB2 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACB2.
0: OUTB2 drive disabled, internally connected to VSSB or
DACB3, depending on CLAMP_SEL_OUTB2.
1: OUTB2 drive enabled, connected to DACB2.
5 DRVEN_DACB1 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACB1.
0: DACB1 drive disabled, internally connected to VSSB.
1: DACB1 drive enabled.
4 DRVEN_DACB0 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACB0.
0: OUTB0 drive disabled, internally connected to VSSB or
DACB1, depending on CLAMP_SEL_OUTB0.
1: OUTB0 drive enabled, connected to DACB0.
3 DRVEN_DACA3 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACA3.
0: DACA3 drive disabled, internally connected to VSSA.
1: DACA3 drive enabled.
2 DRVEN_DACA2 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACA2.
0: OUTA2 drive disabled, internally connected to VSSA or
DACA3, depending on CLAMP_SEL_OUTA2.
1: OUTA2 drive enabled, connected to DACA2.
1 DRVEN_DACA1 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACA1.
0: DACA1 drive disabled, internally connected to VSSA.
1: DACA1 drive enabled.
0 DRVEN_DACA0 R/W 0h Software drive enable value, when software control is enabled
on DRVEN_SW_EN_DACA0.
0: OUTA0 drive disabled, internally connected to VSSA or
DACA1, depending on CLAMP_SEL_OUTA0.
1: OUTA0 drive enabled, connected to DACA0.

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7.1.1.13 DAC_BCAST Register (address = 14h) [reset = 0000h]

Figure 7-13. DAC_BCAST Register
15 14 13 12 11 10 9 8
RESERVED DAC[12:8]
R-0h W-0h

7 6 5 4 3 2 1 0
DAC[7:0]
W-0h

Table 7-14. DAC_BCAST Register Field Descriptions

Bit Field Type Reset Description
12-0 DAC W 0h A write to this register sets all DAC buffer and active data
registers to the specified code, on channels configured in
broadcast mode.

7.1.1.14 GLOBAL_CFG Register (address = 17h) [reset = 0000h]

Figure 7-14. GLOBAL_CFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED ADC_BYP_EN ALARM_BYP_
EN
R-0h R/W-0h R/W-0h

Table 7-15. GLOBAL_CFG Register Field Descriptions

Bit Field Type Reset Description
1 ADC_BYP_EN R/W 0h ADC data bypass enable. Bypasses all ADC conversion results.
0: Bypass disabled.
1: All ADC data conversions are bypassed, with ADC registers
set to the code specified in the ADC_BYP register.
0 ALARM_BYP_EN R/W 0h Internal alarm bypass.
0: Bypass disabled.
1: All alarm condition states and alarm status bits are bypassed
to the values specified in the ALARM_STATUS_0_BYP and
ALARM_STATUS_BYP_1 registers.

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7.1.1.15 ADC_SENSE0 Register (address = 18h) [reset = 0000h]

Figure 7-15. ADC_SENSE0 Register
15 14 13 12 11 10 9 8
ADC[15:8]
R-0h

7 6 5 4 3 2 1 0
ADC[7:0]
R-0h

Table 7-16. ADC_SENSE0 Register Field Descriptions

Bit Field Type Reset Description
15:0 ADC R 0h Differential voltage measured across the shunt output. 2's
complement value.

7.1.1.16 ADC_SENSE1 Register (address = 19h) [reset = 0000h]

Figure 7-16. ADC_SENSE1 Register
15 14 13 12 11 10 9 8
ADC[15:8]
R-0h

7 6 5 4 3 2 1 0
ADC[7:0]
R-0h

Table 7-17. ADC_SENSE1 Register Field Descriptions

Bit Field Type Reset Description
15:0 ADC R 0h Differential voltage measured across the shunt output. 2's
complement value.

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7.1.1.17 ADC_ADC0 Register (address = 1Ah) [reset = 0000h]

Figure 7-17. ADC_ADC0 Register
15 14 13 12 11 10 9 8
ADC[15:8]
R-0h

7 6 5 4 3 2 1 0
ADC[7:0]
R-0h

Table 7-18. ADC_ADC0 Register Field Descriptions

Bit Field Type Reset Description
15:0 ADC R 0h ADCHV voltage output. Conversion factor: 3.125mV/LSB

7.1.1.18 ADC_ADC1 Register (address = 1Bh) [reset = 0000h]

Figure 7-18. ADC_ADC1 Register
15 14 13 12 11 10 9 8
ADC[15:8]
R-0h

7 6 5 4 3 2 1 0
ADC[7:0]
R-0h

Table 7-19. ADC_ADC1 Register Field Descriptions

Bit Field Type Reset Description
15:0 ADC R 0h ADCHV voltage output. Conversion factor: 3.125mV/LSB

7.1.1.19 ADC_TMP Register (address = 1Ch) [reset = 0000h]

Figure 7-19. ADC_TMP Register
15 14 13 12 11 10 9 8
ADC[15:8]
R-0h

7 6 5 4 3 2 1 0
ADC[7:0]
R-0h

Table 7-20. ADC_TMP Register Field Descriptions

Bit Field Type Reset Description
15:0 ADC R 0h Internal die temperature measurement. 2's complement value.
Conversion factor: 7.8125 m°C/LSB.

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7.2 General Configuration Register Map

Table 7-21. Page 0: General Configuration Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
40 CHIP_ID R 7980 CHIP_ID[15:0]
41 CHIP_VER R 0102 RESERVED VERSION_ID[3:0]
42 SDO_EN R/W 0000 RESERVED FSDO SDO_EN
FLEXIO_ FLEXIO_ ALARM_
44 GEN_CFG_0 R/W 0010 RESERVED OUT_ OUT_ LATCH_ RESERVED
POL ODE DIS
VSSB_ VSSA_ FLEXIO_
45 GEN_CFG_1 R/W 1101 RESERVED RESERVED RESERVED
RANGE[2:0] RANGE[2:0] FUNC[5:0]
ALARMOUT_ TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
48 R/W 0000 RESERVED RESERVED RESERVED
SRC_0 ALR_OUT ALR_OUT ALR_OUT ALR_OUT ALR_OUT
THERM
ALARMOUT_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
49 R/W 1833 RESERVED ERR_ RESERVED RESERVED
SRC_1 ALR_OUT ALR_OUT ALR_OUT ALR_OUT ALR_OUT
ALR_OUT
ALARM_
TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
4C STATUS_ R/W 0000 RESERVED RESERVED RESERVED
ALR_BYP ALR_BYP ALR_BYP ALR_BYP ALR_BYP
0_BYP
ALARM_ THERM
ALARMIN_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
4D STATUS_ R/W 0000 RESERVED ERR_ RESERVED RESERVED
ALR_BYP ALR_BYP ALR_BYP ALR_BYP ALR_BYP ALR_BYP
1_BYP ALR_BYP
VDD_
PORBASE
COLLAPSE RSTPIN_ VIO_
70 RESET_FLAGS W 000F RESERVED _
_ FLAG FLAG
FLAG
FLAG

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7.2.1 General Configuration Registers: Page 0

7.2.1.1 CHIP_ID Register (address = 40h) [reset = 7980h]

Figure 7-20. CHIP_ID Register
15 14 13 12 11 10 9 8
CHIP_ID[15:8]
R-79h

7 6 5 4 3 2 1 0
CHIP_ID[7:0]
R-80h

Table 7-22. CHIP_ID Register Field Descriptions

Bit Field Type Reset Description
15:0 CHIP_ID R 7980h Chip identification code

7.2.1.2 CHIP_VER Register (address = 41h) [reset = 0102h]

Figure 7-21. CHIP_VER Register
15 14 13 12 11 10 9 8
VERSION[15:8]
R-01h

7 6 5 4 3 2 1 0
VERSION[7:0]
R-02h

Table 7-23. CHIP_VER Register Field Descriptions

Bit Field Type Reset Description
15:0 VERSION[15:0] R 0102h Chip version ID, subject to change

7.2.1.3 SDO_EN Register (address = 42h) [reset = 0000h]

Figure 7-22. SDO_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED FSDO SDO_EN
R-0h R/W-0h R/W-0h

Table 7-24. SDO_EN Register Field Descriptions

Bit Field Type Reset Description
1 FSDO R/W 0h Enables faster SPI bus speeds by sending the SDO data out
one SCLK half-cycle earlier (FSDO mode).
0: FSDO disabled
1: FSDO enabled during read/write operations
0 SDO_EN R/W 0h SDO Enable. SDO is enabled for read and write operations
whenever the SPI CS pin is low. SDO is always disabled in I2C
mode regardless of this bit setting.
0: SDO disabled
1: SDO enabled during read/write operations

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7.2.1.4 GEN_CFG_0 Register (address = 44h) [reset = 0010h]

Figure 7-23. GEN_CFG_0 Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED FLEXIO_ FLEXIO_ ALARM_ RESERVED
OUT_POL OUT_ODE LATCH_DIS
R-0h R/W-0h R/W-1h R/W-0h R-0h

Table 7-25. GEN_CFG_0 Register Field Descriptions

Bit Field Type Reset Description
5 FLEXIO_OUT_POL R/W 0h FLEXIO output polarity, when using ALARMOUT or GPIO
functions.
0: ALARMOUT output is active low, and GPIO output is non-
inverted (0V if GPIO_DATA is set to 0x00h, and VIO if GPIO_DATA
is set to 0x01h).
1: ALARMOUT output is active high, and GPIO output is inverted
(VIO if GPIO_DATA is set to 0x00h, and 0V if GPIO_DATA is set to
0x01h.
4 FLEXIO_OUT_ODE R/W 1h FLEXIO open drain enable.
0: FLEXIO is push-pull output.
1: FLEXIO is open-drain output.
3 ALARM_LATCH_DIS R/W 0h Alarm latch disable.
0: Alarm state is latched.
1: Alarm state is not latched.

7.2.1.5 GEN_CFG_1 Register (address = 45h) [reset = 1101h]

Figure 7-24. GEN_CFG_1 Register
15 14 13 12 11 10 9 8
RESERVED VSSB_RANGE[2:0] RESERVED VSSA_RANGE[2:0]
R-0h R/W-1h R-0h R/W-1h

7 6 5 4 3 2 1 0
RESERVED FLEXIO_FUNC[5:0]
R-0h R/W-1h

Table 7-26. GEN_CFG_1 Register Field Descriptions

Bit Field Type Reset Description
14:12 VSSB_RANGE R/W 1h Configure VSS range for DAC group B; at any voltage outside
this range, VSSB_ALR can be set
001: Low-range VSS (–11V to –3V)
010: Mid-range VSS (–11V to –4.5V)
100: High-range VSS (–11V to –7.5V)
10:8 VSSA_RANGE R/W 1h Configure VSS range for DAC group A; at any voltage outside
this range, VSSA_ALR can be set
001: Low-range VSS (–11V to –3V)
010: Mid-range VSS (–11V to –4.5V)
100: High-range VSS (–11V to –7.5V)
5:0 FLEXIO_FUNC R/W 1h Sets function for FLEXIO pin
0x01: RESET
0x02: ALARMOUT
0x04: GPIO pin
0x08: LDAC
0x10: ALARMIN
0x20: DRVEN2

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7.2.1.6 ALARMOUT_SRC_0 Register (address = 48h) [reset = 0000h]

Figure 7-25. ALARMOUT_SRC_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_OUT
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_OUT ALR_OUT ALR_OUT ALR_OUT
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-27. ALARMOUT_SRC_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_OUT R/W 0h 0: Temperature alarm is not a source for ALARMOUT pin assertion.
1: Temperature alarm is a source for ALARMOUT pin assertion.
5 ADC1_ALR_OUT R/W 0h 0: ADC1 alarm is not a source for ALARMOUT pin assertion
1: ADC1 alarm is a source for ALARMOUT pin assertion
4 ADC0_ALR_OUT R/W 0h 0: ADC0 alarm is not a source for ALARMOUT pin assertion.
1: ADC0 alarm is a source for ALARMOUT pin assertion.
1 SENSE1_ALR_OUT R/W 0h 0: SENSE1 channel alarm is not a source for ALARMOUT pin
assertion.
1: SENSE1 channel alarm is a source for ALARMOUT pin assertion.
0 SENSE0_ALR_OUT R/W 0h 0: SENSE0 channel alarm is not a source for ALARMOUT pin
assertion.
1: SENSE0 channel alarm is a source for ALARMOUT pin assertion.

7.2.1.7 ALARMOUT_SRC_1 Register (address = 49h) [reset = 1833h]

Figure 7-26. ALARMOUT_SRC_1 Register
15 14 13 12 11 10 9 8
RESERVED REF_ THERMERR_ RESERVED
ALR_OUT ALR_OUT
R-0h R/W-1h R/W-1h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_OUT ALR_OUT ALR_OUT ALR_OUT
R-0h R/W-1h R/W-1h R-0h R/W-1h R/W-1h

Table 7-28. ALARMOUT_SRC_1 Register Field Descriptions

Bit Field Type Reset Description
12 REF_ALR_OUT R/W 1h 0: Reference alarm is not a source for ALARMOUT pin assertion.
1: Reference alarm is a source for ALARMOUT pin assertion.
11 THERMERR_ALR_OUT R/W 1h 0: Thermal alarm is not a source for ALARMOUT pin assertion.
1: Thermal alarm is a source for ALARMOUT pin assertion.
5 VSSB_ALR_OUT R/W 1h 0: VSSB alarm is not a source for ALARMOUT pin assertion.
1: VSSB alarm is a source for ALARMOUT pin assertion.
4 VSSA_ALR_OUT R/W 1h 0: VSSA alarm is not a source for ALARMOUT pin assertion.
1: VSSA alarm is a source for ALARMOUT pin assertion.
1 VCCB_ALR_OUT R/W 1h 0: VCCB alarm is not a source for ALARMOUT pin assertion.
1: VCCB alarm is a source for ALARMOUT pin assertion.
0 VCCA_ALR_OUT R/W 1h 0: VCCA alarm is not a source for ALARMOUT pin assertion.
1: VCCA alarm is a source for ALARMOUT pin assertion.

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7.2.1.8 ALARM_STATUS_0_BYP Register (address = 4Ch) [reset = 0000h]

Figure 7-27. ALARM_STATUS_0_BYP Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_BYP
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_BYP ALR_BYP ALR_BYP ALR_BYP
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-29. ALARM_STATUS_0_BYP Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_BYP R/W 0h Temperature alarm bypass command (when ALARM_BYP_EN = 1)
0: Temperature alarm status is forced to 0
1: Temperature alarm status is forced to 1
5 ADC1_ALR_BYP R/W 0h ADC1 alarm bypass command (when ALARM_BYP_EN = 1)
0: ADC1 alarm status is forced to 0
1: ADC1 alarm status is forced to 1
4 ADC0_ALR_BYP R/W 0h ADC0 alarm bypass command (when ALARM_BYP_EN = 1)
0: ADC0 alarm status is forced to 0
1: ADC0 alarm status is forced to 1
1 SENSE1_ALR_BYP R/W 0h SENSE1 alarm bypass command (when ALARM_BYP_EN = 1)
0: SENSE1 alarm status is forced to 0
1: SENSE1 alarm status is forced to 1
0 SENSE0_ALR_BYP R/W 0h SENSE0 alarm bypass command (when ALARM_BYP_EN = 1)
0: SENSE0 alarm status is forced to 0
1: SENSE0 alarm status is forced to 1

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7.2.1.9 ALARM_STATUS_1_BYP Register (address = 4Dh) [reset = 0000h]

Figure 7-28. ALARM_STATUS_1_BYP Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ THERMERR_ RESERVED
ALR_BYP ALR_BYP ALR_BYP
R-0h R/W-0h R/W-0h R/W-0h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_BYP ALR_BYP ALR_BYP ALR_BYP
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-30. ALARM_STATUS_1_BYP Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR_BYP R/W 0h ALARMIN bypass command (when ALARM_BYP_EN = 1)
0: ALARMIN alarm status is forced to 0
1: ALARMIN alarm status is forced to 1
12 REF_ALR_BYP R/W 0h Reference alarm bypass command (when ALARM_BYP_EN = 1)
0: Reference alarm status is forced to 0
1: Reference alarm status is forced to 1
11 THERMERR_ALR_BYP R/W 0h Thermal alarm bypass command (when ALARM_BYP_EN = 1)
0: Thermal alarm status is forced to 0
1: Thermal alarm status is forced to 1
5 VSSB_ALR_BYP R/W 0h VSSB alarm bypass command (when ALARM_BYP_EN = 1)
0: VSSB alarm status is forced to 0
1: VSSB alarm status is forced to 1
4 VSSA_ALR_BYP R/W 0h VSSA alarm bypass command (when ALARM_BYP_EN = 1)
0: VSSA alarm status is forced to 0
1: VSSA alarm status is forced to 1
1 VCCB_ALR_BYP R/W 0h VCCB alarm bypass command (when ALARM_BYP_EN = 1)
0: VCCB alarm status is forced to 0
1: VCCB alarm status is forced to 1
0 VCCA_ALR_BYP R/W 0h VCCA alarm bypass command (when ALARM_BYP_EN = 1)
0: VCCA alarm status is forced to 0
1: VCCA alarm status is forced to 1

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7.2.1.10 RESET_FLAGS Register (Offset = 70h) [Reset = 000Fh]

Figure 7-29. RESET_FLAGS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED VDD_ RSTPIN_FLAG VIO_FLAG PORBASE_
COLLAPSE_ FLAG
FLAG
R-0h W-1h W-1h W-1h W-1h

Table 7-31. RESET_FLAGS Register Field Descriptions

Bit Field Type Reset Description
3 VDD_COLLAPSE_FLAG W 1h VDD collapse flag.
Write to 0 to detect a VDD collapse event, at which time this flag is
automatically set to 1. VDD collapse occurs when VDD reaches to
within 1V of the VREF voltage.
2 RSTPIN_FLAG W 1h RESET pin reset flag.
Write to 0 to detect a RESET pin reset event, at which time this flag
is automatically set to 1.
1 VIO_FLAG W 1h VIO reset flag.
Write to 0 to detect a VIO reset event, at which time this flag is
automatically set to 1. VIO reset event occurs as a result of VIO
dropping below the POR threshold voltage.
0 PORBASE_FLAG W 1h POR base flag.
Write to 0 to detect a POR-base reset event, at which time this flag
is automatically set to 1. POR-base reset event occurs as a result of
VDD dropping below the POR threshold voltage.

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7.3 ADC Configuration Register Map

Table 7-32. Page 1: ADC Configuration Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC_GEN_ SHUNT_
40 R/W 3334 RESERVED FALR_ADC[2:0] RESERVED FALR_SENSE[2:0] RESERVED FALR_TMP[2:0] RESERVED CMODE RESERVED
CFG RANGE
CONV_
ADC_CONV_
41 R/W 0555 RESERVED CONV_RATE_TMP[2:0] RESERVED CONV_RATE_ADC[2:0] RESERVED RATE_
CFG_0
SENSE[2:0]
ADC_CONV_ AVG_
42 R/W 0000 RESERVED AVG_TMP[2:0] RESERVED AVG_ADC[2:0] RESERVED
CFG_1 SENSE[2:0]
44 ADC_BYP R/W 0000 ADC_BYP[15:0]
46 ADC_HYST_0 R/W 0808 HYST_TMP[7:0] HYST_ADC[7:0]
47 ADC_HYST_1 R/W 0008 RESERVED HYST_SENSE[7:0]
SENSE0_UP_
50 R/W 7FFF THRU[15:0]
THRESH
SENSE0_LO_
51 R/W 8000 THRL[15:0]
THRESH
SENSE1_UP_
52 R/W 7FFF THRU[15:0]
THRESH
SENSE1_LO_
53 R/W 8000 THRL[15:0]
THRESH
ADC0_UP_
54 R/W 7FFF RESERVED THRU[14:0]
THRESH
ADC0_LO_
55 R/W 0000 RESERVED THRL[14:0]
THRESH
ADC1_UP_
56 R/W 7FFF RESERVED THRU[14:0]
THRESH
ADC1_LO_
57 R/W 0000 RESERVED THRL[14:0]
THRESH
TMP_UP_
58 R/W 7FFF THRU[15:0]
THRESH

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7.3.1 ADC Configuration Registers: Page 1

7.3.1.1 ADC_GEN_CFG Register (address = 40h) [reset = 3334h]

Figure 7-30. ADC_GEN_CFG Register
15 14 13 12 11 10 9 8
RESERVED FALR_ADC[2:0] RESERVED FALR_SENSE[2:0]
R-0h R/W-3h R-0h R/W-3h

7 6 5 4 3 2 1 0
RESERVED FALR_TMP[2:0] RESERVED CMODE SHUNT_ RESERVED
RANGE
R-0h R/W-3h R-0h R/W-1h R/W-0h R-0h

Table 7-33. ADC_GEN_CFG Register Field Descriptions

Bit Field Type Reset Description
14-12 FALR_ADC R/W 3h False alarm protection for external input (ADC) channels. Value
represents the number of consecutive out-of-range conversions
required to trigger alarm.
000: 1
001: 4
010: 8
011: 16
100: 32
101: 64
110: 128
111: 256
10-8 FALR_SENSE R/W 3h False alarm protection for SENSE channels. Value represents
the number of consecutive out-of-range conversions required to
trigger alarm.
000: 1
001: 4
010: 8
011: 16
100: 32
101: 64
110: 128
111: 256
6-4 FALR_TMP R/W 3h False alarm protection for temperature measurements. Value
represents the number of consecutive out-of-range conversions
required to trigger alarm.
000: 1
001: 4
010: 8
011: 16
100: 32
101: 64
110: 128
111: 256
2 CMODE R/W 1h ADC conversion mode bit. This bit selects the ADC conversion
mode.
0: Direct-mode. The analog inputs specified in the device
sequencer are converted sequentially one time. When one set
of conversions is complete the ADC is idle and waits for a new
trigger.
1: Auto-mode. The analog inputs specified in the device
sequencer are converted sequentially and repeatedly. When one
set of conversions is complete the ADC sequencer returns to the
start index and repeats the sequence.
1 SHUNT_ R/W 0h Shunt voltage range selection bit for SENSE input channels
RANGE 0: ±163.84mV range
1: ±40.96mV range

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7.3.1.2 ADC_CONV_CFG_0 Register (address = 41h) [reset = 0555h]

Figure 7-31. ADC_CONV_CFG_0 Register
15 14 13 12 11 10 9 8
RESERVED CONV_RATE_TMP[2:0]
R-0h R/W-5h

7 6 5 4 3 2 1 0
RESERVED CONV_RATE_ADC[2:0] RESERVED CONV_RATE_SENSE[2:0]
R-0h R/W-5h R-0h R/W-5h

Table 7-34. ADC_CONV_CFG_0 Register Field Descriptions

Bit Field Type Reset Description
10-8 CONV_RATE_TMP R/W 5h Total acquisition + conversion time for temperature
measurements with no averaging.
000: 52μs
001: 86μs
010: 152μs
011: 282μs
100: 542μs
101: 1054μs
110: 2076μs
111: 4122μs
6-4 CONV_RATE_ADC R/W 5h Total acquisition + conversion time for ADC voltage
measurements with no averaging.
000: 52μs
001: 86μs
010: 152μs
011: 282μs
100: 542μs
101: 1054μs
110: 2076μs
111: 4122μs
2-0 CONV_RATE_SENSE R/W 5h Total acquisition + conversion time for SENSE shunt voltage
measurements with no averaging.
000: 52μs
001: 86μs
010: 152μs
011: 282μs
100: 542μs
101: 1054μs
110: 2076μs
111: 4122μs

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7.3.1.3 ADC_CONV_CFG_1 Register (address = 42h) [reset = 0000h]

Figure 7-32. ADC_CONV_CFG_1 Register
15 14 13 12 11 10 9 8
RESERVED AVG_TMP
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED AVG_ADC RESERVED AVG_SENSE
R-0h R/W-0h R-0h R/W-0h

Table 7-35. ADC_CONV_CFG_1 Register Field Descriptions

Bit Field Type Reset Description
10-8 AVG_TMP R/W 0h Averaging setting for temperature measurements. The device
reports and acts upon averaged result.
000: 1 sample
001: 4 samples
010: 16 samples
011: 64 samples
100: 128 samples
101: 256 samples
110: 512 samples
111: 1024 samples
6-4 AVG_ADC R/W 0h Averaging setting for ADC voltage measurements. The device
reports and acts upon averaged result.
000: 1 sample
001: 4 samples
010: 16 samples
011: 64 samples
100: 128 samples
101: 256 samples
110: 512 samples
111: 1024 samples
2-0 AVG_SENSE R/W 0h Averaging setting for SENSE shunt voltage measurements. The
device reports and acts upon averaged result.
000: 1 sample
001: 4 samples
010: 16 samples
011: 64 samples
100: 128 samples
101: 256 samples
110: 512 samples
111: 1024 samples

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7.3.1.4 ADC_BYP Register (address = 44h) [reset = 0000h]

Figure 7-33. ADC_BYP Register
15 14 13 12 11 10 9 8
ADC_BYP[15:8]
R/W-0h

7 6 5 4 3 2 1 0
ADC_BYP[7:0]
R/W-0h

Table 7-36. ADC_BYP Register Field Descriptions

Bit Field Type Reset Description
15-0 ADC_BYP R/W 0h ADC data bypass value. Only used when ADC_BYP_EN is set
to 1

7.3.1.5 ADC_HYST_0 Register (address = 46h) [reset = 0808h]

Figure 7-34. ADC_HYST_0 Register
15 14 13 12 11 10 9 8
HYST_TMP[7:0]
R/W-8h

7 6 5 4 3 2 1 0
HYST_ADC[7:0]
R/W-8h

Table 7-37. ADC_HYST_0 Register Field Descriptions

Bit Field Type Reset Description
15-8 HYST_TMP R/W 8h Hysteresis setting for temperature measurements. 1 LSB per
step.
7-0 HYST_ADC R/W 8h Hysteresis setting for ADC voltage measurements. 1 LSB per
step.

7.3.1.6 ADC_HYST_1 Register (address = 47h) [reset = 0008h]

Figure 7-35. ADC_HYST_1 Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
HYST_SENSE[7:0]
R/W-8h

Table 7-38. ADC_HYST_1 Register Field Descriptions

Bit Field Type Reset Description
7-0 HYST_SENSE R/W 8h Hysteresis setting for shunt voltage measurements. 1 LSB per
step.

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7.3.1.7 SENSE0_UP_THRESH Register (address = 50h) [reset = 7FFFh]

Figure 7-36. SENSE0_UP_THRESH Register
15 14 13 12 11 10 9 8
THRU[15:8]
R/W-7Fh

7 6 5 4 3 2 1 0
THRU[7:0]
R/W-FFh

Table 7-39. SENSE0_UP_THRESH Register Field Descriptions

Bit Field Type Reset Description
15-0 THRU R/W 7FFFh Upper threshold for shunt voltage measurements.
Corresponding alarm status bit is activated if (channel code >
UP thresh) or (channel code < LO thresh), and is cleared if
(channel code ≤ UP thresh – hysteresis) and (channel code ≥
LO thresh + hysteresis). Upper threshold minus hysteresis must
always be greater than lower threshold plus hysteresis.

7.3.1.8 SENSE0_LO_THRESH Register (address = 51h) [reset = 8000h]

Figure 7-37. SENSE0_LO_THRESH Register
15 14 13 12 11 10 9 8
THRL[15:8]
R/W-80h

7 6 5 4 3 2 1 0
THRL[7:0]
R/W-00h

Table 7-40. SENSE0_LO_THRESH Register Field Descriptions

Bit Field Type Reset Description
15-0 THRL R/W 8000h Lower threshold for shunt voltage measurements.
Corresponding alarm status bit is activated if (channel code >
UP thresh) or (channel code < LO thresh), and is cleared if
(channel code ≤ UP thresh – hysteresis) and (channel code ≥
LO thresh + hysteresis). Upper threshold minus hysteresis must
always be greater than lower threshold plus hysteresis.

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7.3.1.9 SENSE1_UP_THRESH Register (address = 52h) [reset = 7FFFh]

Figure 7-38. SENSE1_UP_THRESH Register
15 14 13 12 11 10 9 8
THRU[15:8]
R/W-7Fh

7 6 5 4 3 2 1 0
THRU[7:0]
R/W-FFh

Table 7-41. SENSE1_UP_THRESH Register Field Descriptions

Bit Field Type Reset Description
15-0 THRU R/W 7FFFh Upper threshold for shunt voltage measurements.
Corresponding alarm status bit is activated if (channel code >
UP thresh) or (channel code < LO thresh), and is cleared if
(channel code ≤ UP thresh – hysteresis) and (channel code ≥
LO thresh + hysteresis). Upper threshold minus hysteresis must
always be greater than lower threshold plus hysteresis.

7.3.1.10 SENSE1_LO_THRESH Register (address = 53h) [reset = 8000h]

Figure 7-39. SENSE1_LO_THRESH Register
15 14 13 12 11 10 9 8
THRL[15:8]
R/W-80h

7 6 5 4 3 2 1 0
THRL[7:0]
R/W-00h

Table 7-42. SENSE1_LO_THRESH Register Field Descriptions

Bit Field Type Reset Description
15-0 THRL R/W 8000h Lower threshold for shunt voltage measurements.
Corresponding alarm status bit is activated if (channel code >
UP thresh) or (channel code < LO thresh), and is cleared if
(channel code ≤ UP thresh – hysteresis) and (channel code ≥
LO thresh + hysteresis). Upper threshold minus hysteresis must
always be greater than lower threshold plus hysteresis.

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7.3.1.11 ADC0_UP_THRESH Register (address = 54h) [reset = 7FFFh]

Figure 7-40. ADC0_UP_THRESH Register
15 14 13 12 11 10 9 8
RESERVED THRU[14:8]
R-0h R/W-7Fh

7 6 5 4 3 2 1 0
THRU[7:0]
R/W-FFh

Table 7-43. ADC0_UP_THRESH Register Field Descriptions

Bit Field Type Reset Description
14-0 THRU R/W 7FFFh Upper threshold for ADC voltage measurements. Corresponding
alarm status bit is activated if (channel code > UP thresh) or
(channel code < LO thresh), and is cleared if (channel code
≤ UP thresh – hysteresis) and (channel code ≥ LO thresh +
hysteresis). Upper threshold minus hysteresis must always be
greater than lower threshold plus hysteresis.

7.3.1.12 ADC0_LO_THRESH Register (address = 55h) [reset = 0000h]

Figure 7-41. ADC0_LO_THRESH Register
15 14 13 12 11 10 9 8
RESERVED THRL[14:8]
R-0h R/W-0h

7 6 5 4 3 2 1 0
THRL[7:0]
R/W-00h

Table 7-44. ADC0_LO_THRESH Register Field Descriptions

Bit Field Type Reset Description
14-0 THRL R/W 0000h Lower threshold for ADC voltage measurements. Corresponding
alarm status bit is activated if (channel code > UP thresh) or
(channel code < LO thresh), and is cleared if (channel code
≤ UP thresh – hysteresis) and (channel code ≥ LO thresh +
hysteresis). Upper threshold minus hysteresis must always be
greater than lower threshold plus hysteresis.

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7.3.1.13 ADC1_UP_THRESH Register (address = 56h) [reset = 7FFFh]

Figure 7-42. ADC1_UP_THRESH Register
15 14 13 12 11 10 9 8
RESERVED THRU[14:8]
R-0h R/W-7Fh

7 6 5 4 3 2 1 0
THRU[7:0]
R/W-FFh

Table 7-45. ADC1_UP_THRESH Register Field Descriptions

Bit Field Type Reset Description
14-0 THRU R/W 7FFFh Upper threshold for ADC voltage measurements. Corresponding
alarm status bit is activated if (channel code > UP thresh) or
(channel code < LO thresh), and is cleared if (channel code
≤ UP thresh – hysteresis) and (channel code ≥ LO thresh +
hysteresis). Upper threshold minus hysteresis must always be
greater than lower threshold plus hysteresis.

7.3.1.14 ADC1_LO_THRESH Register (address = 57h) [reset = 0000h]

Figure 7-43. ADC1_LO_THRESH Register
15 14 13 12 11 10 9 8
RESERVED THRL[14:8]
R-0h R/W-0h

7 6 5 4 3 2 1 0
THRL[7:0]
R/W-00h

Table 7-46. ADC1_LO_THRESH Register Field Descriptions

Bit Field Type Reset Description
14-0 THRL R/W 0000h Lower threshold for ADC voltage measurements. Corresponding
alarm status bit is activated if (channel code > UP thresh) or
(channel code < LO thresh), and is cleared if (channel code
≤ UP thresh – hysteresis) and (channel code ≥ LO thresh +
hysteresis). Upper threshold minus hysteresis must always be
greater than lower threshold plus hysteresis.

7.3.1.15 TMP_UP_THRESH Register (address = 58h) [reset = 7FFFh]

Figure 7-44. TMP_UP_THRESH Register
15 14 13 12 11 10 9 8
THRU[15:8]
R/W-7Fh

7 6 5 4 3 2 1 0
THRU[7:0]
R/W-FFh

Table 7-47. TMP_UP_THRESH Register Field Descriptions

Bit Field Type Reset Description
15-0 THRU R/W 7FFFh Upper threshold for temperature measurements. Corresponding
alarm status bit is activated if (channel code > UP thresh) or
(channel code < LO thresh), and is cleared if (channel code
≤ UP thresh – hysteresis) and (channel code ≥ LO thresh +
hysteresis). Upper threshold minus hysteresis must always be
greater than lower threshold plus hysteresis.

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7.4 ADC Custom Channel Sequencer Configuration Register Map

Table 7-48. Page 2: ADC Custom Channel Sequencer Configuration Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
40 ADC_CCS_IDS_0 R/W 0201 RESERVED CCS_ID_1[2:0] RESERVED CCS_ID_0[2:0]
41 ADC_CCS_IDS_1 R/W 0403 RESERVED CCS_ID_3[2:0] RESERVED CCS_ID_2[2:0]
42 ADC_CCS_IDS_2 R/W 0005 RESERVED CCS_ID_5[2:0] RESERVED CCS_ID_4[2:0]
43 ADC_CCS_IDS_3 R/W 0000 RESERVED CCS_ID_7[2:0] RESERVED CCS_ID_6[2:0]
44 ADC_CCS_IDS_4 R/W 0000 RESERVED CCS_ID_9[2:0] RESERVED CCS_ID_8[2:0]
45 ADC_CCS_IDS_5 R/W 0000 RESERVED CCS_ID_11[2:0] RESERVED CCS_ID_10[2:0]
46 ADC_CCS_IDS_6 R/W 0000 RESERVED CCS_ID_13[2:0] RESERVED CCS_ID_12[2:0]
47 ADC_CCS_IDS_7 R/W 0000 RESERVED CCS_ID_15[2:0] RESERVED CCS_ID_14[2:0]
48 ADC_CCS_IDS_8 R/W 0000 RESERVED CCS_ID_17[2:0] RESERVED CCS_ID_16[2:0]
49 ADC_CCS_IDS_9 R/W 0000 RESERVED CCS_ID_19[2:0] RESERVED CCS_ID_18[2:0]
4A ADC_CCS_IDS_10 R/W 0000 RESERVED CCS_ID_21[2:0] RESERVED CCS_ID_20[2:0]
4B ADC_CCS_IDS_11 R/W 0000 RESERVED CCS_ID_23[2:0] RESERVED CCS_ID_22[2:0]
4C ADC_CCS_IDS_12 R/W 0000 RESERVED CCS_ID_25[2:0] RESERVED CCS_ID_24[2:0]
4D ADC_CCS_IDS_13 R/W 0000 RESERVED CCS_ID_27[2:0] RESERVED CCS_ID_26[2:0]
4E ADC_CCS_IDS_14 R/W 0000 RESERVED CCS_ID_29[2:0] RESERVED CCS_ID_28[2:0]
4F ADC_CCS_IDS_15 R/W 0000 RESERVED CCS_ID_31[2:0] RESERVED CCS_ID_30[2:0]
50 ADC_CCS_IDS_16 R/W 0000 RESERVED CCS_ID_33[2:0] RESERVED CCS_ID_32[2:0]
51 ADC_CCS_IDS_17 R/W 0000 RESERVED CCS_ID_35[2:0] RESERVED CCS_ID_34[2:0]
52 ADC_CCS_IDS_18 R/W 0000 RESERVED CCS_ID_37[2:0] RESERVED CCS_ID_36[2:0]
53 ADC_CCS_IDS_19 R/W 0000 RESERVED CCS_ID_39[2:0] RESERVED CCS_ID_38[2:0]
54 ADC_CCS_IDS_20 R/W 0000 RESERVED CCS_ID_41[2:0] RESERVED CCS_ID_40[2:0]
55 ADC_CCS_IDS_21 R/W 0000 RESERVED CCS_ID_43[2:0] RESERVED CCS_ID_42[2:0]
56 ADC_CCS_IDS_22 R/W 0000 RESERVED CCS_ID_45[2:0] RESERVED CCS_ID_44[2:0]
57 ADC_CCS_IDS_23 R/W 0000 RESERVED CCS_ID_47[2:0] RESERVED CCS_ID_46[2:0]
58 ADC_CCS_IDS_24 R/W 0000 RESERVED CCS_ID_49[2:0] RESERVED CCS_ID_48[2:0]
59 ADC_CCS_IDS_25 R/W 0000 RESERVED CCS_ID_51[2:0] RESERVED CCS_ID_50[2:0]
5A ADC_CCS_IDS_26 R/W 0000 RESERVED CCS_ID_53[2:0] RESERVED CCS_ID_52[2:0]
5B ADC_CCS_IDS_27 R/W 0000 RESERVED CCS_ID_55[2:0] RESERVED CCS_ID_54[2:0]
5C ADC_CCS_IDS_28 R/W 0000 RESERVED CCS_ID_57[2:0] RESERVED CCS_ID_56[2:0]
5D ADC_CCS_IDS_29 R/W 0000 RESERVED CCS_ID_59[2:0] RESERVED CCS_ID_58[2:0]
5E ADC_CCS_IDS_30 R/W 0000 RESERVED CCS_ID_61[2:0] RESERVED CCS_ID_60[2:0]
5F ADC_CCS_IDS_31 R/W 0000 RESERVED CCS_ID_63[2:0] RESERVED CCS_ID_62[2:0]
60 ADC_CCS_IDS_32 R/W 0000 RESERVED CCS_ID_65[2:0] RESERVED CCS_ID_64[2:0]
61 ADC_CCS_IDS_33 R/W 0000 RESERVED CCS_ID_67[2:0] RESERVED CCS_ID_66[2:0]
62 ADC_CCS_IDS_34 R/W 0000 RESERVED CCS_ID_69[2:0] RESERVED CCS_ID_68[2:0]
63 ADC_CCS_IDS_35 R/W 0000 RESERVED CCS_ID_71[2:0] RESERVED CCS_ID_70[2:0]

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Table 7-48. Page 2: ADC Custom Channel Sequencer Configuration Register Map (continued)
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64 ADC_CCS_IDS_36 R/W 0000 RESERVED CCS_ID_73[2:0] RESERVED CCS_ID_72[2:0]
65 ADC_CCS_IDS_37 R/W 0000 RESERVED CCS_ID_75[2:0] RESERVED CCS_ID_74[2:0]
66 ADC_CCS_IDS_38 R/W 0000 RESERVED CCS_ID_77[2:0] RESERVED CCS_ID_76[2:0]
67 ADC_CCS_IDS_39 R/W 0000 RESERVED CCS_ID_79[2:0] RESERVED CCS_ID_78[2:0]
68 ADC_CCS_IDS_40 R/W 0000 RESERVED CCS_ID_81[2:0] RESERVED CCS_ID_80[2:0]
69 ADC_CCS_IDS_41 R/W 0000 RESERVED CCS_ID_83[2:0] RESERVED CCS_ID_82[2:0]
6A ADC_CCS_IDS_42 R/W 0000 RESERVED CCS_ID_85[2:0] RESERVED CCS_ID_84[2:0]
6B ADC_CCS_IDS_43 R/W 0000 RESERVED CCS_ID_87[2:0] RESERVED CCS_ID_86[2:0]
6C ADC_CCS_IDS_44 R/W 0000 RESERVED CCS_ID_89[2:0] RESERVED CCS_ID_88[2:0]
6D ADC_CCS_IDS_45 R/W 0000 RESERVED CCS_ID_91[2:0] RESERVED CCS_ID_90[2:0]
6E ADC_CCS_IDS_46 R/W 0000 RESERVED CCS_ID_93[2:0] RESERVED CCS_ID_92[2:0]
6F ADC_CCS_IDS_47 R/W 0000 RESERVED CCS_ID_95[2:0] RESERVED CCS_ID_94[2:0]
70 ADC_CCS_IDS_48 R/W 0000 RESERVED CCS_ID_97[2:0] RESERVED CCS_ID_96[2:0]
71 ADC_CCS_IDS_49 R/W 0000 RESERVED CCS_ID_99[2:0] RESERVED CCS_ID_98[2:0]
72 ADC_CCS_IDS_50 R/W 0000 RESERVED CCS_ID_101[2:0] RESERVED CCS_ID_100[2:0]
73 ADC_CCS_IDS_51 R/W 0000 RESERVED CCS_ID_103[2:0] RESERVED CCS_ID_102[2:0]
74 ADC_CCS_IDS_52 R/W 0000 RESERVED CCS_ID_105[2:0] RESERVED CCS_ID_104[2:0]
75 ADC_CCS_IDS_53 R/W 0000 RESERVED CCS_ID_107[2:0] RESERVED CCS_ID_106[2:0]
76 ADC_CCS_IDS_54 R/W 0000 RESERVED CCS_ID_109[2:0] RESERVED CCS_ID_108[2:0]
77 ADC_CCS_IDS_55 R/W 0000 RESERVED CCS_ID_111[2:0] RESERVED CCS_ID_110[2:0]
78 ADC_CCS_IDS_56 R/W 0000 RESERVED CCS_ID_113[2:0] RESERVED CCS_ID_112[2:0]
79 ADC_CCS_IDS_57 R/W 0000 RESERVED CCS_ID_115[2:0] RESERVED CCS_ID_114[2:0]
7A ADC_CCS_IDS_58 R/W 0000 RESERVED CCS_ID_117[2:0] RESERVED CCS_ID_116[2:0]
7B ADC_CCS_IDS_59 R/W 0000 RESERVED CCS_ID_119[2:0] RESERVED CCS_ID_118[2:0]
7C ADC_CCS_IDS_60 R/W 0000 RESERVED CCS_ID_121[2:0] RESERVED CCS_ID_120[2:0]
7D ADC_CCS_IDS_61 R/W 0000 RESERVED CCS_ID_123[2:0] RESERVED CCS_ID_122[2:0]
7E ADC_CCS_IDS_62 R/W 0000 RESERVED CCS_ID_125[2:0] RESERVED CCS_ID_124[2:0]
7F ADC_CCS_CFG_0 R/W 0004 RESERVED CCS_START_INDEX[5:0] RESERVED CCS_STOP_INDEX[5:0]

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7.4.1 ADC CCS Registers: Page 3

7.4.1.1 ADC_CCS_IDS_n Registers (address = 40h to 7Eh) [reset = see ADC CCS Register Map]
For more information on reset values for this register, see Section 7.4.
Figure 7-45. ADC_CCS_IDS_n Register
15 14 13 12 11 10 9 8
RESERVED CCS_ID_a[3:0]
R-0h R/W

7 6 5 4 3 2 1 0
RESERVED CCS_ID_b[3:0]
R-0h R/W

Table 7-49. ADC_CCS_IDS_n Register Field Descriptions

Bit Field Type Reset Description
10-8 CCS_ID_a(1) R/W see ADC custom channel sequence index setting
Section 7.4 000: GND
001: SENSE0
2-0 CCS_ID_b(1) R/W see
010: SENSE1
Section 7.4
011: ADC0
100: ADC1
101: TMP

(1) CCS_ID_a refers to odd-indexed CCS ID registers, and CCS_ID_b refers to even-indexed CCS ID registers.

7.4.1.2 ADC_CCS_CFG_0 Register (address = 7Fh) [reset = 0004h]

Figure 7-46. ADC_CCS_CFG_0 Register
15 14 13 12 11 10 9 8
RESERVED CCS_START_INDEX[6:0]
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED CCS_STOP_INDEX[6:0]
R-0h R/W-4h

Table 7-50. ADC_CCS_CFG_0 Register Field Descriptions

Bit Field Type Reset Description
15 RESERVED R 0h
14:8 CCS_START_INDEX[6:0] R/W 0h Starting index pointer
7 RESERVED R 0h
6:0 CCS_STOP_INDEX[6:0] R/W 4h Stopping index pointer. Must not be less than the
CCS_START_INDEX.

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7.5 DAC Configuration Register Map

Table 7-51. Page 3: DAC Configuration Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC_
40 R/W 0000 DACB3_CURRENT[1:0] DACB2_CURRENT[1:0] DACB1_CURRENT[1:0] DACB0_CURRENT[1:0] DACA3_CURRENT[1:0] DACA2_CURRENT[1:0] DACA1_CURRENT[1:0] DACA0_CURRENT[1:0]
CURRENT
DAC_SYNC_ BCEN_ BCEN_ BCEN_ BCEN_ BCEN_ BCEN_ BCEN_ BCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_
41 R/W 0000
CFG DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0 DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
CLAMP_ CLAMP_ CLAMP_ CLAMP_
DAC_ DACB_ DACA_
42 R/W 0000 RESERVED RESERVED RESERVED SEL_OUT SEL_OUT SEL_OUT SEL_OUT
CFG BIPOLAR BIPOLAR
B2 B0 A2 A0
APD_ APD_ APD_ APD_ APD_EN_ APD_EN_ APD_EN_ APD_EN_ APD_EN_ APD_EN_ APD_EN_ APD_EN_
43 DAC_APD_EN R/W AAFF
EN_OUTB2[1:0] EN_OUTB0[1:0] EN_OUTA2[1:0] EN_OUTA0[1:0] DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
DACA_APD_ TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
44 R/W 0000 RESERVED RESERVED RESERVED
SRC_0 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
THERM
DACA_APD_ ALARMIN_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
45 R/W 1833 RESERVED ERR_ RESERVED RESERVED
SRC_1 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
ALR_APD
OUTA_APD_ TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
46 R/W 0000 RESERVED RESERVED RESERVED
SRC_0 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
THERM
OUTA_APD_ ALARMIN_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
47 R/W 1833 RESERVED ERR_ RESERVED RESERVED
SRC_1 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
ALR_APD
DACB_APD_ TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
48 R/W 0000 RESERVED RESERVED RESERVED
SRC_0 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
THERM
DACB_APD_ ALARMIN_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
49 R/W 1833 RESERVED ERR_ RESERVED RESERVED
SRC_1 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
ALR_APD
OUTB_APD_ TMP_ ADC1_ ADC0_ SENSE1_ SENSE0_
4A R/W 0000 RESERVED RESERVED RESERVED
SRC_0 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
THERM
OUTB_APD_ ALARMIN_ REF_ VSSB_ VSSA_ VCCB_ VCCA_
4B R/W 1833 RESERVED ERR_ RESERVED RESERVED
SRC_1 ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD ALR_APD
ALR_APD
DAC_CODE_
4C R/W 3F3F RESERVED DACA1_LIMIT[5:0] RESERVED DACA0_LIMIT[5:0]
LIMIT_0
DAC_CODE_
4D R/W 3F3F RESERVED DACA3_LIMIT[5:0] RESERVED DACA2_LIMIT[5:0]
LIMIT_1
DAC_CODE_
4E R/W 3F3F RESERVED DACB1_LIMIT[5:0] RESERVED DACB0_LIMIT[5:0]
LIMIT_2
DAC_CODE_
4F R/W 3F3F RESERVED DACB3_LIMIT[5:0] RESERVED DACB2_LIMIT[5:0]
LIMIT_3
DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_
50 DRVEN0_EN R/W 0000 RESERVED EN_ EN_ EN_ EN_ EN_ EN_ EN_ EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_
51 DRVEN1_EN R/W 0000 RESERVED EN_ EN_ EN_ EN_ EN_ EN_ EN_ EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_
52 FLEXIO_EN R/W 0000 RESERVED EN_ EN_ EN_ EN_ EN_ EN_ EN_ EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0

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7.5.1 DAC Configuration Registers: Page 3

7.5.1.1 DAC_CURRENT Register (address = 40h) [reset = 0000h]

Figure 7-47. DAC_CURRENT Register
15 14 13 12 11 10 9 8
DACB3_ DACB2_ DACB1_ DACB0_
CURRENT[1:0] CURRENT[1:0] CURRENT[1:0] CURRENT[1:0]
R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
DACA3_ DACA2_ DACA1_ DACA0_
CURRENT[1:0] CURRENT[1:0] CURRENT[1:0] CURRENT[1:0]
R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-52. DAC_CURRENT Register Field Descriptions

Bit Field Type Reset Description
15-14 DACB3_CURRENT R/W 0h DAC output current mode selection.
00: Start-up, 15mA
13-12 DACB2_CURRENT R/W 0h
01: Low current mode, 30mA
11-10 DACB1_CURRENT R/W 0h 10: Normal current mode, 90mA
9-8 DACB0_CURRENT R/W 0h 11: High current mode, 120mA

7-6 DACA3_CURRENT R/W 0h

5-4 DACA2_CURRENT R/W 0h
3-2 DACA1_CURRENT R/W 0h
1-0 DACA0_CURRENT R/W 0h

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7.5.1.2 DAC_SYNC_CFG Register (address = 41h) [reset = 0000h]

Figure 7-48. DAC_SYNC_CFG Register
15 14 13 12 11 10 9 8
BCEN_DACB3 BCEN_DACB2 BCEN_DACB1 BCEN_DACB0 BCEN_DACA3 BCEN_DACA2 BCEN_DACA1 BCEN_DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

7 6 5 4 3 2 1 0
SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_ SYNCEN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-53. DAC_SYNC_CFG Register Field Descriptions

Bit Field Type Reset Description
15 BCEN_DACB3 R/W 0h DAC broadcast enable.
0: Ignores broadcast writes on this DAC
14 BCEN_DACB2 R/W 0h
1: Allow broadcast writes on this DAC
13 BCEN_DACB1 R/W 0h
12 BCEN_DACB0 R/W 0h
11 BCEN_DACA3 R/W 0h
10 BCEN_DACA2 R/W 0h
9 BCEN_DACA1 R/W 0h
8 BCEN_DACA0 R/W 0h
7 SYNCEN_DACB3 R/W 0h DAC synchronous configuration.
0: Set DAC into asynchronous mode.
6 SYNCEN_DACB2 R/W 0h
1: Set DAC into synchronous mode.
5 SYNCEN_DACB1 R/W 0h
4 SYNCEN_DACB0 R/W 0h
3 SYNCEN_DACA3 R/W 0h
2 SYNCEN_DACA2 R/W 0h
1 SYNCEN_DACA1 R/W 0h
0 SYNCEN_DACA0 R/W 0h

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7.5.1.3 DAC_CFG Register (address = 42h) [reset = 0000h]

Figure 7-49. DAC_CFG Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
RESERVED CLAMP_SEL_ CLAMP_SEL_ CLAMP_SEL_ CLAMP_SEL_
OUTB2 OUTB0 OUTA2 OUTA0
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-54. DAC_CFG Register Field Descriptions

Bit Field Type Reset Description
3 CLAMP_SEL_OUTB2 R/W 0h Clamp voltage selection for OUTB2.
0: Clamp voltage is VSSB
1: Clamp voltage is DACB3
2 CLAMP_SEL_OUTB0 R/W 0h Clamp voltage selection for OUTB0.
0: Clamp voltage is VSSB
1: Clamp voltage is DACB1
1 CLAMP_SEL_OUTA2 R/W 0h Clamp voltage selection for OUTA2.
0: Clamp voltage is VSSA
1: Clamp voltage is DACA3
0 CLAMP_SEL_OUTA0 R/W 0h Clamp voltage selection for OUTA0.
0: Clamp voltage is VSSA
1: Clamp voltage is DACA1

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7.5.1.4 DAC_APD_EN Register (address = 43h) [reset = AAFFh]

Figure 7-50. DAC_APD_EN Register
15 14 13 12 11 10 9 8
APD_EN_OUTB2[1:0] APD_EN_OUTB0[1:0] APD_EN_OUTA2[1:0] APD_EN_OUTA0[1:0]
R/W-2h R/W-2h R/W-2h R/W-2h

7 6 5 4 3 2 1 0
APD_ APD_ APD_ APD_ APD_ APD_ APD_ APD_
EN_ EN_ EN_ EN_ EN_ EN_ EN_ EN_
DACB3 DACB2 DACB1 DACB0 DACA3 DACA2 DACA1 DACA0
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 7-55. DAC_APD_EN Register Field Descriptions

Bit Field Type Reset Description
15-14 APD_EN_OUTB2 R/W 2h OUTB pin auto-power-down enable
00: Ignore auto-power-down events on the OUTB pin.
13-12 APD_EN_OUTB0 R/W 2h
10: Disable OUTB pin drive channel, and connect to VSSB
during an auto-power-down event.
11: Disable OUTB pin drive channel, and connect to VSSB or
DAC output (depending on clamp setting) during an auto-power-
down event.
11-10 APD_EN_OUTA2 R/W 2h OUTA pin auto-power-down enable
00: Ignore auto-power-down events on the OUTA pin.
9-8 APD_EN_OUTA0 R/W 2h
10: Disable OUTA pin drive channel, and connect to VSSA
during an auto-power-down event.
11: Disable OUTA pin drive channel, and connect to VSSA or
DAC output (depending on clamp setting) during an auto-power-
down event.
7 APD_EN_DACB3 R/W 1h DAC pin auto-power-down enable
0: Ignore auto-power-down events on the DAC.
6 APD_EN_DACB2 R/W 1h
1: Force this DAC to power-down during an auto-power-down
5 APD_EN_DACB1 R/W 1h event.
4 APD_EN_DACB0 R/W 1h
3 APD_EN_DACA3 R/W 1h
2 APD_EN_DACA2 R/W 1h
1 APD_EN_DACA1 R/W 1h
0 APD_EN_DACA0 R/W 1h

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7.5.1.5 DACA_APD_SRC_0 Register (address = 44h) [reset = 0000h]

Figure 7-51. DACA_APD_SRC_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_APD
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-56. DACA_APD_SRC_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_APD R/W 0h This bit determines if group A DACs are forced into a power-
down state by this alarm. The respective DACA channels must
be enabled in the DAC_APD_EN register.
0: Temperature alarm does not trigger DACA auto-power-down
event
1: Temperature alarm triggers DACA auto-power-down event
5 ADC1_ALR_APD R/W 0h This bit determines if group A DACs are forced into a power-
down state by this alarm. The respective DACA channels must
be enabled in the DAC_APD_EN register.
0: ADC1 alarm does not trigger DACA auto-power-down event
1: ADC1 alarm triggers DACA auto-power-down event
4 ADC0_ALR_APD R/W 0h This bit determines if group A DACs are forced into a power-
down state by this alarm. The respective DACA channels must
be enabled in the DAC_APD_EN register.
0: ADC0 alarm does not trigger DACA auto-power-down event
1: ADC0 alarm triggers DACA auto-power-down event
1 SENSE1_ALR_APD R/W 0h This bit determines if group A DACs are forced into a power-
down state by this alarm. The respective DACA channels must
be enabled in the DAC_APD_EN register.
0: SENSE1 alarm does not trigger DACA auto-power-down
event
1: SENSE1 alarm triggers DACA auto-power-down event
0 SENSE0_ALR_APD R/W 0h This bit determines if group A DACs are forced into a power-
down state by this alarm. The respective DACA channels must
be enabled in the DAC_APD_EN register.
0: SENSE0 alarm does not trigger DACA auto-power-down
event
1: SENSE0 alarm triggers DACA auto-power-down event

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7.5.1.6 DACA_APD_SRC_1 Register (address = 45h) [reset = 1833h]

Figure 7-52. DACA_APD_SRC_1 Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ THERMERR_ RESERVED
ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-1h R/W-1h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-1h R/W-1h R-0h R/W-1h R/W-1h

Table 7-57. DACA_APD_SRC_1 Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR_APD R/W 0h 0: ALARMIN pin assertion is not a source for DACA auto-power-
down events
1: ALARMIN pin assertion is a source for DACA auto-power-
down events
12 REF_ALR_APD R/W 1h 0: Reference alarm is not a source for DACA auto-power-down
events
1: Reference alarm is a source for DACA auto-power-down
events
11 THERMERR_ALR_APD R/W 1h 0: Thermal error alarm is not a source for DACA auto-power-
down events
1: Thermal error alarm is a source for DACA auto-power-down
events
5 VSSB_ALR_APD R/W 1h 0: VSSB alarm is not a source for DACA auto-power-down events
1: VSSB alarm is a source for DACA auto-power-down events
4 VSSA_ALR_APD R/W 1h 0: VSSA alarm is not a source for DACA auto-power-down events
1: VSSA alarm is a source for DACA auto-power-down events
1 VCCB_ALR_APD R/W 1h 0: VCCB alarm is not a source for DACA auto-power-down
events
1: VCCB alarm is a source for DACA auto-power-down events
0 VCCA_ALR_APD R/W 1h 0: VCCA alarm is not a source for DACA auto-power-down
events
1: VCCA alarm is a source for DACA auto-power-down events

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7.5.1.7 OUTA_APD_SRC_0 Register (address = 46h) [reset = 0000h]

Figure 7-53. OUTA_APD_SRC_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_APD
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-58. OUTA_APD_SRC_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_APD R/W 0h This bit determines if group A OUT pins are forced into a power-
down state by this alarm. The respective OUTA pins must be
enabled in the DAC_APD_EN register.
0: Temperature alarm does not trigger OUTA pin auto-power-
down event
1: Temperature alarm triggers OUTA pin auto-power-down event
5 ADC1_ALR_APD R/W 0h This bit determines if group A OUT pins are forced into a power-
down state by this alarm. The respective OUTA pins must be
enabled in the DAC_APD_EN register.
0: ADC1 alarm does not trigger OUTA pin auto-power-down
event
1: ADC1 alarm triggers OUTA pin auto-power-down event
4 ADC0_ALR_APD R/W 0h This bit determines if group A OUT pins are forced into a power-
down state by this alarm. The respective OUTA pins must be
enabled in the DAC_APD_EN register.
0: ADC0 alarm does not trigger OUTA pin auto-power-down
event
1: ADC0 alarm triggers OUTA pin auto-power-down event
1 SENSE1_ALR_APD R/W 0h This bit determines if group A OUT pins are forced into a power-
down state by this alarm. The respective OUTA pins must be
enabled in the DAC_APD_EN register.
0: SENSE1 alarm does not trigger OUTA pin auto-power-down
event
1: SENSE1 alarm triggers OUTA pin auto-power-down event
0 SENSE0_ALR_APD R/W 0h This bit determines if group A OUT pins are forced into a power-
down state by this alarm. The respective OUTA pins must be
enabled in the DAC_APD_EN register.
0: SENSE0 alarm does not trigger OUTA pin auto-power-down
event
1: SENSE0 alarm triggers OUTA pin auto-power-down event

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7.5.1.8 OUTA_APD_SRC_1 Register (address = 47h) [reset = 1833h]

Figure 7-54. OUTA_APD_SRC_1 Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ THERMERR_ RESERVED
ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-1h R/W-1h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-1h R/W-1h R-0h R/W-1h R/W-1h

Table 7-59. OUTA_APD_SRC_1 Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR_APD R/W 0h 0: ALARMIN pin assertion is not a source for OUTA pin auto-
power-down events
1: ALARMIN pin assertion is a source for OUTA pin auto-power-
down events
12 REF_ALR_APD R/W 1h 0: Reference alarm is not a source for OUTA pin auto-power-
down events
1: Reference alarm is a source for OUTA pin auto-power-down
events
11 THERMERR_ALR_APD R/W 1h 0: Thermal error alarm is not a source for OUTA pin auto-power-
down events
1: Thermal error alarm is a source for OUTA pin auto-power-
down events
5 VSSB_ALR_APD R/W 1h 0: VSSB alarm is not a source for OUTA pin auto-power-down
events
1: VSSB alarm is a source for OUTA pin auto-power-down events
4 VSSA_ALR_APD R/W 1h 0: VSSA alarm is not a source for OUTA pin auto-power-down
events
1: VSSA alarm is a source for OUTA pin auto-power-down events
1 VCCB_ALR_APD R/W 1h 0: VCCB alarm is not a source for OUTA pin auto-power-down
events
1: VCCB alarm is a source for OUTA pin auto-power-down events
0 VCCA_ALR_APD R/W 1h 0: VCCA alarm is not a source for OUTA pin auto-power-down
events
1: VCCA alarm is a source for OUTA pin auto-power-down events

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7.5.1.9 DACB_APD_SRC_0 Register (address = 48h) [reset = 0000h]

Figure 7-55. DACB_APD_SRC_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_APD
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-60. DACB_APD_SRC_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_APD R/W 0h This bit determines if group B DAC pins are forced into a power-
down state by this alarm. The respective DACB pins must be
enabled in the DAC_APD_EN register.
0: Temperature alarm does not trigger DACB auto-power-down
event
1: Temperature alarm triggers DACB auto-power-down event
5 ADC1_ALR_APD R/W 0h This bit determines if group B DAC pins are forced into a power-
down state by this alarm. The respective DACB pins must be
enabled in the DAC_APD_EN register.
0: ADC1 alarm does not trigger DACB auto-power-down event
1: ADC1 alarm triggers DACB auto-power-down event
4 ADC0_ALR_APD R/W 0h This bit determines if group B DAC pins are forced into a power-
down state by this alarm. The respective DACB pins must be
enabled in the DAC_APD_EN register.
0: ADC0 alarm does not trigger DACB auto-power-down event
1: ADC0 alarm triggers DACB auto-power-down event
1 SENSE1_ALR_APD R/W 0h This bit determines if group B DAC pins are forced into a power-
down state by this alarm. The respective DACB pins must be
enabled in the DAC_APD_EN register.
0: SENSE1 alarm does not trigger DACB auto-power-down
event
1: SENSE1 alarm triggers DACB auto-power-down event
0 SENSE0_ALR_APD R/W 0h This bit determines if group B DAC pins are forced into a power-
down state by this alarm. The respective DACB pins must be
enabled in the DAC_APD_EN register.
0: SENSE0 alarm does not trigger DACB auto-power-down
event
1: SENSE0 alarm triggers DACB auto-power-down event

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7.5.1.10 DACB_APD_SRC_1 Register (address = 49h) [reset = 1833h]

Figure 7-56. DACB_APD_SRC_1 Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ THERMERR_ RESERVED
ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-1h R/W-1h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-1h R/W-1h R-0h R/W-1h R/W-1h

Table 7-61. DACB_APD_SRC_1 Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR_APD R/W 0h 0: ALARMIN pin assertion is not a source for DACB auto-power-
down events
1: ALARMIN pin assertion is a source for DACB auto-power-
down events
12 REF_ALR_APD R/W 1h 0: Reference alarm is not a source for DACB auto-power-down
events
1: Reference alarm is a source for DACB auto-power-down
events
11 THERMERR_ALR_APD R/W 1h 0: Thermal error alarm is not a source for DACB auto-power-
down events
1: Thermal error alarm is a source for DACB auto-power-down
events
5 VSSB_ALR_APD R/W 1h 0: VSSB alarm is not a source for DACB auto-power-down events
1: VSSB alarm is a source for DACB auto-power-down events
4 VSSA_ALR_APD R/W 1h 0: VSSA alarm is not a source for DACB auto-power-down events
1: VSSA alarm is a source for DACB auto-power-down events
1 VCCB_ALR_APD R/W 1h 0: VCCB alarm is not a source for DACB auto-power-down
events
1: VCCB alarm is a source for DACB auto-power-down events
0 VCCA_ALR_APD R/W 1h 0: VCCA alarm is not a source for DACB auto-power-down
events
1: VCCA alarm is a source for DACB auto-power-down events

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7.5.1.11 OUTB_APD_SRC_0 Register (address = 4Ah) [reset = 0000h]

Figure 7-57. OUTB_APD_SRC_0 Register
15 14 13 12 11 10 9 8
RESERVED TMP_
ALR_APD
R-0h R/W-0h

7 6 5 4 3 2 1 0
RESERVED ADC1_ ADC0_ RESERVED SENSE1_ SENSE0_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h

Table 7-62. OUTB_APD_SRC_0 Register Field Descriptions

Bit Field Type Reset Description
8 TMP_ALR_APD R/W 0h This bit determines if group B OUT pins are forced into a power-
down state by this alarm. The respective OUTB pins must be
enabled in the DAC_APD_EN register.
0: Temperature alarm does not trigger OUTB pin auto-power-
down event
1: Temperature alarm triggers OUTB pin auto-power-down event
5 ADC1_ALR_APD R/W 0h This bit determines if group B OUT pins are forced into a power-
down state by this alarm. The respective OUTB pins must be
enabled in the DAC_APD_EN register.
0: ADC1 alarm does not trigger OUTB pin auto-power-down
event
1: ADC1 alarm triggers OUTB pin auto-power-down event
4 ADC0_ALR_APD R/W 0h This bit determines if group B OUT pins are forced into a power-
down state by this alarm. The respective OUTB pins must be
enabled in the DAC_APD_EN register.
0: ADC0 alarm does not trigger OUTB pin auto-power-down
event
1: ADC0 alarm triggers OUTB pin auto-power-down event
1 SENSE1_ALR_APD R/W 0h This bit determines if group B OUT pins are forced into a power-
down state by this alarm. The respective OUTB pins must be
enabled in the DAC_APD_EN register.
0: SENSE1 alarm does not trigger OUTB pin auto-power-down
event
1: SENSE1 alarm triggers OUTB pin auto-power-down event
0 SENSE0_ALR_APD R/W 0h This bit determines if group B OUT pins are forced into a power-
down state by this alarm. The respective OUTB pins must be
enabled in the DAC_APD_EN register.
0: SENSE0 alarm does not trigger OUTB pin auto-power-down
event
1: SENSE0 alarm triggers OUTB pin auto-power-down event

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7.5.1.12 OUTB_APD_SRC_1 Register (address = 4Bh) [reset = 1833h]

Figure 7-58. OUTB_APD_SRC_1 Register
15 14 13 12 11 10 9 8
RESERVED ALARMIN_ REF_ THERMERR_ RESERVED
ALR_APD ALR_APD ALR_APD
R-0h R/W-0h R/W-1h R/W-1h R-0h

7 6 5 4 3 2 1 0
RESERVED VSSB_ VSSA_ RESERVED VCCB_ VCCA_
ALR_APD ALR_APD ALR_APD ALR_APD
R-0h R/W-1h R/W-1h R-0h R/W-1h R/W-1h

Table 7-63. OUTB_APD_SRC_1 Register Field Descriptions

Bit Field Type Reset Description
13 ALARMIN_ALR_APD R/W 0h 0: ALARMIN pin assertion is not a source for OUTB pin auto-
power-down events
1: ALARMIN pin assertion is a source for OUTB pin auto-power-
down events
12 REF_ALR_APD R/W 1h 0: Reference alarm is not a source for OUTB pin auto-power-
down events
1: Reference alarm is a source for OUTB pin auto-power-down
events
11 THERMERR_ALR_APD R/W 1h 0: Thermal error alarm is not a source for OUTB pin auto-power-
down events
1: Thermal error alarm is a source for OUTB pin auto-power-
down events
5 VSSB_ALR_APD R/W 1h 0: VSSB alarm is not a source for OUTB pin auto-power-down
events
1: VSSB alarm is a source for OUTB pin auto-power-down events
4 VSSA_ALR_APD R/W 1h 0: VSSA alarm is not a source for OUTB pin auto-power-down
events
1: VSSA alarm is a source for OUTB pin auto-power-down events
1 VCCB_ALR_APD R/W 1h 0: VCCB alarm is not a source for OUTB pin auto-power-down
events
1: VCCB alarm is a source for OUTB pin auto-power-down
events
0 VCCA_ALR_APD R/W 1h 0: VCCA alarm is not a source for OUTB pin auto-power-down
events
1: VCCA alarm is a source for OUTB pin auto-power-down
events

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7.5.1.13 DAC_CODE_LIMIT_0 Register (address = 4Ch) [reset = 3F3Fh]

Figure 7-59. DAC_CODE_LIMIT_0 Register
15 14 13 12 11 10 9 8
RESERVED DACA1_LIMITS[5:0]
R-0h R/W-3Fh

7 6 5 4 3 2 1 0
RESERVED DACA0_LIMITS[5:0]
R-0h R/W-3Fh

Table 7-64. DAC_CODE_LIMIT_0 Register Field Descriptions

Bit Field Type Reset Description
13-8 DACA1_LIMITS R/W 3Fh DAC active register latch code limit; off by default.
Program these bits with the following values to
5-0 DACA0_LIMITS R/W 3Fh
achieve the limit specified for the upper six MSBs of
the DAC codes.
00h: 007Fh 16h: 0B7Fh 2Bh: 15FFh
01h: 00FFh 17h: 0BFFh 2Ch: 167Fh
02h: 017Fh 18h: 0C7Fh 2Dh: 16FFh
03h: 01FFh 19h: 0CFFh 2Eh: 177Fh
04h: 027Fh 1Ah: 0D7Fh 2Fh: 17FFh
05h: 02FFh 1Bh: 0DFFh 30h: 187Fh
06h: 037Fh 1Ch: 0E7Fh 31h: 18FFh
07h: 03FFh 1Dh: 0EFFh 32h: 197Fh
08h: 047Fh 1Eh: 0F7Fh 33h: 19FFh
09h: 04FFh 1Fh: 0FFFh 34h: 1A7Fh
0Ah: 057Fh 20h: 107Fh 35h: 1AFFh
0Bh: 05FFh 21h: 10FFh 36h: 1B7Fh
0Ch: 067Fh 22h: 117Fh 37h: 1BFFh
0Dh: 06FFh 23h: 11FFh 38h: 1C7Fh
0Eh: 077Fh 24h: 127Fh 39h: 1CFFh
0Fh: 07FFh 25h: 12FFh 3Ah: 1D7Fh
10h: 087Fh 26h: 137Fh 3Bh: 1DFFh
11h: 08FFh 27h: 13FFh 3Ch: 1E7Fh
12h: 097Fh 28h: 147Fh 3Dh: 1EFFh
13h: 09FFh 29h: 14FFh 3Eh: 1F7Fh
14h: 0A7Fh 2Ah: 157Fh 3Fh: 1FFFh
15h: 0AFFh

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7.5.1.14 DAC_CODE_LIMIT_1 Register (address = 4Dh) [reset = 3F3Fh]

Figure 7-60. DAC_CODE_LIMIT_1 Register
15 14 13 12 11 10 9 8
RESERVED DACA3_LIMITS[5:0]
R-0h R/W-3Fh

7 6 5 4 3 2 1 0
RESERVED DACA2_LIMITS[5:0]
R-0h R/W-3Fh

Table 7-65. DAC_CODE_LIMIT_1 Register Field Descriptions

Bit Field Type Reset Description
13-8 DACA3_LIMITS R/W 3Fh DAC active register latch code limit; off by default.
Program these bits with the following values to
5-0 DACA2_LIMITS R/W 3Fh
achieve the limit specified for the upper six MSBs of
the DAC codes.
00h: 007Fh 16h: 0B7Fh 2Bh: 15FFh
01h: 00FFh 17h: 0BFFh 2Ch: 167Fh
02h: 017Fh 18h: 0C7Fh 2Dh: 16FFh
03h: 01FFh 19h: 0CFFh 2Eh: 177Fh
04h: 027Fh 1Ah: 0D7Fh 2Fh: 17FFh
05h: 02FFh 1Bh: 0DFFh 30h: 187Fh
06h: 037Fh 1Ch: 0E7Fh 31h: 18FFh
07h: 03FFh 1Dh: 0EFFh 32h: 197Fh
08h: 047Fh 1Eh: 0F7Fh 33h: 19FFh
09h: 04FFh 1Fh: 0FFFh 34h: 1A7Fh
0Ah: 057Fh 20h: 107Fh 35h: 1AFFh
0Bh: 05FFh 21h: 10FFh 36h: 1B7Fh
0Ch: 067Fh 22h: 117Fh 37h: 1BFFh
0Dh: 06FFh 23h: 11FFh 38h: 1C7Fh
0Eh: 077Fh 24h: 127Fh 39h: 1CFFh
0Fh: 07FFh 25h: 12FFh 3Ah: 1D7Fh
10h: 087Fh 26h: 137Fh 3Bh: 1DFFh
11h: 08FFh 27h: 13FFh 3Ch: 1E7Fh
12h: 097Fh 28h: 147Fh 3Dh: 1EFFh
13h: 09FFh 29h: 14FFh 3Eh: 1F7Fh
14h: 0A7Fh 2Ah: 157Fh 3Fh: 1FFFh
15h: 0AFFh

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7.5.1.15 DAC_CODE_LIMIT_2 Register (address = 4Eh) [reset = 3F3Fh]

Figure 7-61. DAC_CODE_LIMIT_2 Register
15 14 13 12 11 10 9 8
RESERVED DACB1_LIMITS[5:0]
R-0h R/W-3Fh

7 6 5 4 3 2 1 0
RESERVED DACB0_LIMITS[5:0]
R-0h R/W-3Fh

Table 7-66. DAC_CODE_LIMIT_2 Register Field Descriptions

Bit Field Type Reset Description
13-8 DACB1_LIMITS R/W 3Fh DAC active register latch code limit; off by default.
Program these bits with the following values to
5-0 DACB0_LIMITS R/W 3Fh
achieve the limit specified for the upper six MSBs of
the DAC codes.
00h: 007Fh 16h: 0B7Fh 2Bh: 15FFh
01h: 00FFh 17h: 0BFFh 2Ch: 167Fh
02h: 017Fh 18h: 0C7Fh 2Dh: 16FFh
03h: 01FFh 19h: 0CFFh 2Eh: 177Fh
04h: 027Fh 1Ah: 0D7Fh 2Fh: 17FFh
05h: 02FFh 1Bh: 0DFFh 30h: 187Fh
06h: 037Fh 1Ch: 0E7Fh 31h: 18FFh
07h: 03FFh 1Dh: 0EFFh 32h: 197Fh
08h: 047Fh 1Eh: 0F7Fh 33h: 19FFh
09h: 04FFh 1Fh: 0FFFh 34h: 1A7Fh
0Ah: 057Fh 20h: 107Fh 35h: 1AFFh
0Bh: 05FFh 21h: 10FFh 36h: 1B7Fh
0Ch: 067Fh 22h: 117Fh 37h: 1BFFh
0Dh: 06FFh 23h: 11FFh 38h: 1C7Fh
0Eh: 077Fh 24h: 127Fh 39h: 1CFFh
0Fh: 07FFh 25h: 12FFh 3Ah: 1D7Fh
10h: 087Fh 26h: 137Fh 3Bh: 1DFFh
11h: 08FFh 27h: 13FFh 3Ch: 1E7Fh
12h: 097Fh 28h: 147Fh 3Dh: 1EFFh
13h: 09FFh 29h: 14FFh 3Eh: 1F7Fh
14h: 0A7Fh 2Ah: 157Fh 3Fh: 1FFFh
15h: 0AFFh

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7.5.1.16 DAC_CODE_LIMIT_3 Register (address = 4Fh) [reset = 3F3Fh]

Figure 7-62. DAC_CODE_LIMIT_3 Register
15 14 13 12 11 10 9 8
RESERVED DACB3_LIMITS[5:0]
R-0h R/W-3Fh

7 6 5 4 3 2 1 0
RESERVED DACB2_LIMITS[5:0]
R-0h R/W-3Fh

Table 7-67. DAC_CODE_LIMIT_3 Register Field Descriptions

Bit Field Type Reset Description
13-8 DACB3_LIMITS R/W 3Fh DAC active register latch code limit; off by default.
Program these bits with the following values to
5-0 DACB2_LIMITS R/W 3Fh
achieve the limit specified for the upper six MSBs of
the DAC codes.
00h: 007Fh 16h: 0B7Fh 2Bh: 15FFh
01h: 00FFh 17h: 0BFFh 2Ch: 167Fh
02h: 017Fh 18h: 0C7Fh 2Dh: 16FFh
03h: 01FFh 19h: 0CFFh 2Eh: 177Fh
04h: 027Fh 1Ah: 0D7Fh 2Fh: 17FFh
05h: 02FFh 1Bh: 0DFFh 30h: 187Fh
06h: 037Fh 1Ch: 0E7Fh 31h: 18FFh
07h: 03FFh 1Dh: 0EFFh 32h: 197Fh
08h: 047Fh 1Eh: 0F7Fh 33h: 19FFh
09h: 04FFh 1Fh: 0FFFh 34h: 1A7Fh
0Ah: 057Fh 20h: 107Fh 35h: 1AFFh
0Bh: 05FFh 21h: 10FFh 36h: 1B7Fh
0Ch: 067Fh 22h: 117Fh 37h: 1BFFh
0Dh: 06FFh 23h: 11FFh 38h: 1C7Fh
0Eh: 077Fh 24h: 127Fh 39h: 1CFFh
0Fh: 07FFh 25h: 12FFh 3Ah: 1D7Fh
10h: 087Fh 26h: 137Fh 3Bh: 1DFFh
11h: 08FFh 27h: 13FFh 3Ch: 1E7Fh
12h: 097Fh 28h: 147Fh 3Dh: 1EFFh
13h: 09FFh 29h: 14FFh 3Eh: 1F7Fh
14h: 0A7Fh 2Ah: 157Fh 3Fh: 1FFFh
15h: 0AFFh

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7.5.1.17 DRVEN0_EN Register (address = 50h) [reset = 0000h]

Figure 7-63. DRVEN0_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_ DRVEN0_
EN_DACB3 EN_DACB2 EN_DACB1 EN_DACB0 EN_DACA3 EN_DACA2 EN_DACA1 EN_DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-68. DRVEN0_EN Register Field Descriptions

Bit Field Type Reset Description
7 DRVEN0_EN_DACB3 R/W 0h 0: Ignore DRVEN0 on DACB3
1: DRVEN0 enabled for DACB3
6 DRVEN0_EN_DACB2 R/W 0h 0: Ignore DRVEN0 on DACB2
1: DRVEN0 enabled for DACB2
5 DRVEN0_EN_DACB1 R/W 0h 0: Ignore DRVEN0 on DACB1
1: DRVEN0 enabled for DACB1
4 DRVEN0_EN_DACB0 R/W 0h 0: Ignore DRVEN0 on DACB0
1: DRVEN0 enabled for DACB0
3 DRVEN0_EN_DACA3 R/W 0h 0: Ignore DRVEN0 on DACA3
1: DRVEN0 enabled for DACA3
2 DRVEN0_EN_DACA2 R/W 0h 0: Ignore DRVEN0 on DACA2
1: DRVEN0 enabled for DACA2
1 DRVEN0_EN_DACA1 R/W 0h 0: Ignore DRVEN0 on DACA1
1: DRVEN0 enabled for DACA1
0 DRVEN0_EN_DACA0 R/W 0h 0: Ignore DRVEN0 on DACA0
1: DRVEN0 enabled for DACA0

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7.5.1.18 DRVEN1_EN Register (address = 51h) [reset = 0000h]

Figure 7-64. DRVEN1_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_ DRVEN1_
EN_DACB3 EN_DACB2 EN_DACB1 EN_DACB0 EN_DACA3 EN_DACA2 EN_DACA1 EN_DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-69. DRVEN0_EN Register Field Descriptions

Bit Field Type Reset Description
7 DRVEN1_EN_DACB3 R/W 0h 0: Ignore DRVEN1 on DACB3
1: DRVEN1 enabled for DACB3
6 DRVEN1_EN_DACB2 R/W 0h 0: Ignore DRVEN1 on DACB2
1: DRVEN1 enabled for DACB2
5 DRVEN1_EN_DACB1 R/W 0h 0: Ignore DRVEN1 on DACB1
1: DRVEN1 enabled for DACB1
4 DRVEN1_EN_DACB0 R/W 0h 0: Ignore DRVEN1 on DACB0
1: DRVEN1 enabled for DACB0
3 DRVEN1_EN_DACA3 R/W 0h 0: Ignore DRVEN1 on DACA3
1: DRVEN1 enabled for DACA3
2 DRVEN1_EN_DACA2 R/W 0h 0: Ignore DRVEN1 on DACA2
1: DRVEN1 enabled for DACA2
1 DRVEN1_EN_DACA1 R/W 0h 0: Ignore DRVEN1 on DACA1
1: DRVEN1 enabled for DACA1
0 DRVEN1_EN_DACA0 R/W 0h 0: Ignore DRVEN1 on DACA0
1: DRVEN1 enabled for DACA0

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7.5.1.19 FLEXIO_EN Register (address = 52h) [reset = 0000h]

Figure 7-65. FLEXIO_EN Register
15 14 13 12 11 10 9 8
RESERVED
R-0h

7 6 5 4 3 2 1 0
FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_ FLEXIO_
EN_DACB3 EN_DACB2 EN_DACB1 EN_DACB0 EN_DACA3 EN_DACA2 EN_DACA1 EN_DACA0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 7-70. FLEXIO_EN Register Field Descriptions

Bit Field Type Reset Description
7 FLEXIO_EN_DACB3 R/W 0h 0: Ignore FLEXIO on DACB3
1: FLEXIO enabled for DACB3
6 FLEXIO_EN_DACB2 R/W 0h 0: Ignore FLEXIO on DACB2
1: FLEXIO enabled for DACB2
5 FLEXIO_EN_DACB1 R/W 0h 0: Ignore FLEXIO on DACB1
1: FLEXIO enabled for DACB1
4 FLEXIO_EN_DACB0 R/W 0h 0: Ignore FLEXIO on DACB0
1: FLEXIO enabled for DACB0
3 FLEXIO_EN_DACA3 R/W 0h 0: Ignore FLEXIO on DACA3
1: FLEXIO enabled for DACA3
2 FLEXIO_EN_DACA2 R/W 0h 0: Ignore FLEXIO on DACA2
1: FLEXIO enabled for DACA2
1 FLEXIO_EN_DACA1 R/W 0h 0: Ignore FLEXIO on DACA1
1: FLEXIO enabled for DACA1
0 FLEXIO_EN_DACA0 R/W 0h 0: Ignore FLEXIO on DACA0
1: FLEXIO enabled for DACA0

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7.6 DAC Buffer Register Map

Table 7-71. Page 4: DAC Buffer Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
40 DACA0 R/W 0000 RESERVED DAC[12:0]
41 DACA1 R/W 0000 RESERVED DAC[12:0]
42 DACA2 R/W 0000 RESERVED DAC[12:0]
43 DACA3 R/W 0000 RESERVED DAC[12:0]
44 DACB0 R/W 0000 RESERVED DAC[12:0]
45 DACB1 R/W 0000 RESERVED DAC[12:0]
46 DACB2 R/W 0000 RESERVED DAC[12:0]
47 DACB3 R/W 0000 RESERVED DAC[12:0]

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7.6.1 DAC Buffer Data Registers: Page 4

7.6.1.1 DACA/Bn Buffer Registers (address = 40h to 47h) [reset = 0000h]

Figure 7-66. DACA/Bn Buffer Register
15 14 13 12 11 10 9 8
RESERVED DAC[12:8]
R-0h R/W-0h

7 6 5 4 3 2 1 0
DAC[7:0]
R/W-0h

Table 7-72. DACA/Bn Buffer Register Field Descriptions

Bit Field Type Reset Description
12-0 DAC R/W 0h Stores 13-bit data to be loaded to DACn active register, in MSB-
aligned, unipolar binary format.

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7.7 DAC Active Register Map

Table 7-73. Page 6: DAC Active Register Map
ADDR RESET BIT DESCRIPTION
REGISTER TYPE
(HEX) (HEX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
40 DACA0 R 0000 RESERVED DAC[12:0]
41 DACA1 R 0000 RESERVED DAC[12:0]
42 DACA2 R 0000 RESERVED DAC[12:0]
43 DACA3 R 0000 RESERVED DAC[12:0]
44 DACB0 R 0000 RESERVED DAC[12:0]
45 DACB1 R 0000 RESERVED DAC[12:0]
46 DACB2 R 0000 RESERVED DAC[12:0]
47 DACB3 R 0000 RESERVED DAC[12:0]

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7.7.1 DAC Active Data Registers: Page 4

7.7.1.1 DACA/Bn Active Register (address = 40h to 47h) [reset = 0000h]

Figure 7-67. DACA/Bn Active Registers
15 14 13 12 11 10 9 8
RESERVED DAC[12:8]
R-0h R-0h

7 6 5 4 3 2 1 0
DAC[7:0]
R-0h

Table 7-74. DACA/Bn Active Register Field Descriptions

Bit Field Type Reset Description
12-0 DAC R 0h Stores 13-bit data to be loaded to DACn channel in MSB-
aligned, unipolar binary format.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The primary application of the AMC7908 device is to provide power amplifier (PA) gate-bias control. The
integrated switches allow the gate bias to be switched between a temperature-adjusted on voltage and a static,
lower-potential off voltage.
In addition, the AMC7908 has features to detect alarm conditions, and in response, lower the gate voltages and
turn off the PA during these events.
8.1.1 Output Switching Timing
The externally applied output capacitors allow for noise filtering, and enable fast switching on the output
channels of the device. Large capacitors can be connected to the output of the static channels: DACA0, DACA1,
DACA2, DACA3 in group A, and DACB0, DACB1, DACB2, DACB3 in group B. Capacitors of lower values
can be connected to the dynamic channels: OUTA0, OUTA2, OUTB0, and OUTB2. This capacitor arrangement
means that the larger capacitors can quickly charge the smaller capacitors instead of relying on the DAC output
buffers.
Figure 8-1 shows a simplified model of a switch arrangement for the OUTA0 channel. The on-resistances of the
switches are represented by RSW1 and RSW2. These resistors primarily serve to limit the settling time of VOUTA1
after a switching event, as the settling time is essentially a resistor-capacitor (RC) function.

2 DACA0
DACA0 VDACA0
CDACA0
RSW2 SW2

DRVEN[0:1] pin/
DRVEN_DACA0 bit
OUTA0
VOUTA0
COUTA0
RSW1 SW2

DACA1
DACA1 VDACA1
2
CDACA1

Figure 8-1. Switching Transients

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For example, consider the case where DRVEN0 changes from a low state to a high state. The steady state of
VDACA0 is equal to VDACA1 before the switch event. After the DRVEN pin goes high, SW2 closes, connecting
COUTA1 and CDACA0 to each other. As these capacitors are now in parallel, the voltages across each equalize
to a new voltage. This voltage, described as VCDAC||COUT in the following equation, is calculated by finding the
charge stored in each capacitor. The total charge on the two capacitors in parallel is equal to the sum of the
charge of each capacitor.

QCDAC COUT = QCDAC + QCOUT (2)

VCDAC COUT CDACA1 + COUTA0 = VDACA1 × CDACA1 + VOUTA0 × COUTA0 (3)

V × CDACA1 + VOUTA0 × COUTA0

VCDAC COUT = DACA1 (4)
C +C
DACA1 OUTA0

The time required for the two outputs to equalize, described as the Capacitive Settling Period, is calculated using
the equation below. As DACA0 is lower potential than DACA1, VOUTA0 can be expressed as a charging function.

−t
VOUTA0 t = VCDAC COUT − VOUTA0 t0 1 − e RSW1 × COUTA0 + VOUTA0 t0 (5)

During the capacitive settling period, VDACA1 is expressed as a discharging RC function.

−t
VDACA1 t = VDACA1 t0 − VDACA1 t0 − VCDAC COUT 1 − e RSW1 × COUTA0 (6)

Connecting the capacitors together allows the output to change to VCDAC||COUT quickly, but after that period,
the DAC output buffer continues to charge COUTA1 to the VDACA0 value. The settling time for that final transition
depends on the RC function formed by the series resistance on the DAC output, the switch resistance, and the
capacitive load on the DAC. In addition, the output current of the DAC is limited.
Figure 8-2 shows the switch response for the OUTA0 pin when switching from a static DAC channel to VSS, and
Figure 8-3 shows the switch response of the OUTA0 signal when switching between static DAC outputs.

4 4
DRVEN0 DRVEN0
DACA0 (1µF) DACA0 (1µF)
2 OUTA0 (1nF) 2 OUTA0 (1nF)
VSS DACA1 (1µF)

0 0
Voltage (V)

Voltage (V)

-2 -2

-4 -4

-6 -6

-8 -8
-1 0 1 2 3 4 5 6 7 8 9 -1 0 1 2 3 4 5 6 7 8 9
Time (µs) Time (µs)

Figure 8-2. DAC-to-VSS Switch Response Figure 8-3. DAC-to-DAC Switch Response

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8.2 Typical Application

Figure 8-4 shows an example schematic for PA biasing applications using a single AMC7908 to bias the GaN
and LDMOS power amplifiers simultaneously. In this application, DAC group A is configured in a negative output
range, and DAC group B is configured in positive output range. VSS acts as the clamp voltage source for OUTA0,
DACA1 is used to drive a GaN power amplifier, and DACA2 is used as the off voltage for OUTA2
3.3V 5V
0.1 F 0.1 F

PAVDD1
VIO VDD VCCB VCCA
ADCHV0
470pF
100k

SENSE0+
 
2k

2k


R1
SENSE0

DACA0 GaN PA
10 F
OUTA0
10nF
GaN PA

DACA1
10nF
SDA/SCLK GaN PA
DACA2
SCL/CS 10 F

OUTA2
10nF
RST/FLEXIO 10
F
MCU DACA3
AMC7908
PAVDD2
DRVEN0

DRVEN1 SENSE1+
R2
100k

SENSE1
100k

  10F
DACB3 LDMOS PA

OUTB2
10nF

DACB2 LDMOS PA
10 F

DACB1 10nF

A1

A0 OUTB0
10nF

DACB0
LDMOS PA
GND VSSB VSSA 10 F

11V
0.1F

Figure 8-4. Power Amplifier Biasing

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8.2.1 Design Requirements

The example schematic uses the majority of the design parameters listed in Table 8-1.
Table 8-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
VCCA 11V or grounded
VCCB 11V or grounded
VSSA Grounded or –11V
VSSB Grounded or –11V
VDD 5V
VIO 1.8V
Group A selectable ranges:
0V to 10V, or –10V to 0V
DAC outputs
Group B selectable ranges:
0V to 10V, or –10V to 0V

8.2.2 Detailed Design Procedure

Using the parameters in Table 8-1, the following steps facilitate the design process:
• Connect VCC and VSS pins to external supply voltages as specified in Table 8-1. DAC group A must be
configured in a negative output range, and DAC group B must be configured in positive output range.
• Connect VIO pin to 1.8V supply voltage.
• Connect VDD pin to 5V supply voltage.
8.2.2.1 ADC Input Conditioning
The ADC inputs feature an input range that can be configured as either 0V to 2.5V or 0V to 5V.
To reduce ADC sample glitch, place a 470pF capacitor on the ADC input. Figure 8-5 shows that by adding small
series resistors (in series with the ADC inputs), a low-pass filter for noise filtering is implemented.
PAVDD

100
SENSE0+

RSHUNT 470pF MUX 12-Bit ADC

100 SENSE0

DAC or OUT pin

10nF

Figure 8-5. ADC Input Conditioning

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8.2.2.2 Quiescent Current and Total Power Consumption

Calculating the total power consumption of the device requires all of the supply inputs and DAC loads to be
known. Equation 7calculates the total power; each component is the power contributed by a supply or DAC
loads.

PTOTAL = PIO + PDD + PCC + PSS + PDAC − LOAD (7)

where
• PIO is the power consumed by the device from the VIO supply:
PIO = VIO × IIO − quiescent (8)
• PDD is the power consumed by the device from the VDD supply:
PDD = VDD × IDD − quiescent (9)
• PCC is the power consumed by the device from the VCC supply:
PCC = VCC × ICC − quiescent (10)
• PSS is the power consumed by the device from the VSS supply:
PSS = VSS × ISS − quiescent (11)
• PDAC-LOAD is the power consumed by the device as a result of the DAC loads from the sourcing or sinking
supply. The power of each DAC channel can be calculated separately, then summed to find the total power
of the DAC loads. The power depends not only on the voltage of the DAC output, but also on the difference
between the current sourcing or sinking supply and the DAC output voltage. The following equation shows
how to calculate PDAC-LOAD:

PDAC − LOAD = ∑nchannel n = 0 VSUPPLY − LOAD × ILOAD (12)

Figure 8-6 shows the load configuration in both the positive output range and negative output range.
Positive Output Negative Output
Configuration VCC Configuration

VCC
ILOAD

Output VDAC Output

DACn DACn
Buffer Buffer VDAC
ILOAD

VSS

VSS

Figure 8-6. DAC Output Load

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When the device is in the positive output range, the device is likely sourcing current. While in the negative range,
the device is likely sinking current. The difference between the supply voltage and the DAC output voltage is
VSUPPLY-LOAD, as shown in the following equations.
When the device is in the positive output range, VSUPPLY-LOAD can be calculated as:

VSUPPLY − LOAD = VCC − VDAC (13)

When the device is in the negative output range, VSUPPLY-LOAD can be calculated as:

VSUPPLY − LOAD = VSS − VDAC (14)

8.2.2.2.1 Maximum VCC and VSS Supply Current Transients

In many applications, the DAC outputs of the device have a capacitive load. When the DAC outputs transition
from one output voltage to another, the short-circuit limit protection can be triggered. If the DAC output buffer
reaches the short-circuit current limit of the amplifier, significant current is drawn from the output amplifier supply.
Equation 15 shows how to calculate the estimated maximum current that can be demanded of the supply during
the transition.

IVCC − MAX = IVCC − quiescent + ∑nchannel n = 0 ISHORT − CIRCUIT − LIMIT (15)

8.2.2.2.2 DAC Output Stability

Figure 8-7 shows the required configuration when capacitive loads are present on the DAC output. No series
resistor is required on the DAC output, as the DAC is able to prevent oscillation issues on the output amplifier.
VCC

AMC7908

Output
DACn To PA
Buffer

CLOAD

VSS

Figure 8-7. DAC Output Load

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8.2.3 Application Curves

8.2.3.1 DAC Load Stability
Figure 8-8 shows the DAC output response when the DAC is unloaded and loaded with a capacitor.

-2

-2.5

-3

DAC Output (V)

-3.5

-4

-4.5

-5
Unloaded
1µF
-5.5
-5 0 5 10 15 20 25 30 35 40 45 50 55
Time (µs)

DAC step size: –5V to –2.5V

Figure 8-8. DAC Settling Time vs Load Capacitance

8.2.3.2 Start-Up Behavior

The AMC7908 is designed to minimize DAC output glitch during power supply transients at power-on and
power-down. Figure 8-9 to Figure 8-12 detail this behavior.

6 240
VCC
5 VDD 200
VIO
4 DACA0 160
Output Voltage (mV)

OUTA0
Supply Voltage (V)

3 DACA1 120

2 80

1 40

0 0

-1 -40

-2 -80
-200 -100 0 100 200 300 400 500 600
Time (µs)

Figure 8-9. DAC Output During Figure 8-10. DAC Output During
VCC Power-On Transient VSS Power-On Transient
6 2
VCC
5 DACA0 0
OUTA0
DACA1
4 -2
Voltage (V)

Voltage (V)

3 -4

2 -6

1 -8
VSS
DACA0
0 -10 OUTA0
DACA1
-1 -12
-200 0 200 400 600 -200 0 200 400 600
Time (µs) Time (µs)

Figure 8-11. DAC Output During Figure 8-12. DAC Output During
VCC Power-Down Transient VSS Power-Down Transient

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8.3 Initialization Setup

After power-up, the device can be configured over the serial interface. The following steps can be used in a
typical configuration.
1. After the supplies have ramped to the final output voltage, issue a hardware or software reset to make sure
the device is in a known state. Allow approximately 5ms to 10ms for the device registers to initialize after the
reset event
2. Write to the ADC configuration page (ADC_CONFIG) to set the ADC conversion rate, conversion mode, and
ADC range.
3. Configure the ADC inputs and custom channel sequencer (CCS), by writing to the ADC data registers and
the ADC_CCS_CONFIG registers, respectively.
4. Set the DAC current limits by writing to the DAC_CURRENT register.
5. Initialize the DACs by configuring the DAC_APD_SRC registers, the OUT_APD_SRC registers, the
ALARMOUT_SRC registers, the DAC DRVEN_EN registers, and the DAC_CODE_LIMIT registers.
6. Set the ADC and temperature sensor alarm limits by writing to the ADC_ALR_APD and TMP_ALR_APD
registers respectively.
7. Write the initial DAC output values by writing to the DACn data registers.
8. Enable the DACs by writing to the device configuration or power enable (PWR_EN) registers.
9. Initiate a single (or multiple) ADC conversion by writing to the ADC trigger (ADC_TRIG) bit.
10. Update the DAC output values by writing to the DAC_TRIG bit.
8.4 Power Supply Recommendations
There is no required supply sequence, but be aware that the device stays in the reset state until all supplies
reach the power-good threshold. Also, a hardware or software reset to the device is recommended after the
supplies reach the power-good threshold, so that the device can initialize in a known state. Following this reset
(or any reset event) wait at least 5ms so that the device registers can properly initialize.
In applications where a negative voltage is applied to VSS first, some small negative voltages can be present
at other supply pins, such as the VIO and VDD pins. The negative voltages at the supply pins can exceed the
values listed in Section 5.1 , but because these voltages are created from intrinsic circuitry, the voltage levels are
safe for operation.
8.5 Layout
8.5.1 Layout Guidelines
• Bypass all power supply pins to ground with a low-ESR ceramic bypass capacitor. Bypass capacitors on the
VCCx and VSSx inputs are recommended to be 3 to 4 times the total capacitance on the respective group
DAC outputs to make sure the inrush current does not cause localized supply collapse when the outputs
transition to different voltage output. The typical recommended bypass capacitor has a value of 1µF and is
ceramic with X7R or NP0 dielectric.
• Place capacitors on the DAC[0:3], OUT0, and OUT2 pins as close to the device as possible. This placement
reduces the impact of parasitic inductance and resistance from the switching path. Parasitic inductance and
resistance delays the output settling time.
• Connect the thermal pad on the device to a large copper area, preferably a ground plane.
• When using the local temperature sensor for the output bias voltage temperature compensation, place the
device geographically close to the PA, preferably sharing a solid ground plane for thermal conduction.

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8.5.2 Layout Example

Figure 8-13. AMC7908 Layout Example

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:
• Texas Instruments, AMC7908EVM User's Guide
9.2 Trademarks
All trademarks are the property of their respective owners.
9.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.4 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
August 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical drawings. This information is the most current data available for the
designated devices. This data is subject to change without notice and revision of this document.
For the device packaging and orderable information, see the Mechanical, Packaging, and Orderable Information
section of the short data sheet available in the AMC7908 product folder.

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PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.1 B
A
4.9

PIN 1 INDEX AREA

5.1
4.9

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17

2X SYMM
33
3.5

0.3
32X
0.2
24 0.1 C A B
1
0.05 C

32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/A 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.25)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17

(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4223442/A 11/2016

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHB0032E VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.25)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4223442/A 11/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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