Digital Systems Design
(BECE102L)
Dr. Tanmaya Kumar Das
Assistant Professor Sr. Grade 1
School of Electronics Engineering,
Vellore Institute of Technology, Vellore
Course Objectives
• Provide an understanding of Boolean algebra and logic functions.
• Develop the knowledge of combinational and sequential logic
circuit design.
• Design and model the data path circuits for digital systems.
• Establish a strong understanding of programmable logic.
• Enable the student to design and model the logic circuits using
Verilog HDL.
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Course Outcome
At the end of the course the student will be able to
• Optimize the logic functions using and Boolean principles and K-map
• Model the Combinational and Sequential logic circuits using Verilog HDL
• Design the various combinational logic circuits and data path circuits
• Analyze and apply the design aspects of sequential logic circuits
• Analyze and apply the design aspects of Finite state machines
• Examine the basic architectures of programmable logic devices
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Syllabus
Module:1 Digital Logic [8 hours]
Boolean Algebra: Basic definitions, Axiomatic definition of Boolean Algebra, Basic
Theorems and Properties of Boolean Algebra, Boolean Functions, Canonical and
Standard Forms, Simplification of Boolean functions. Gate-Level Minimization: The
Map Method (K map up to 4 variable), Product of Sums and Sum of Products
Simplification, NAND and NOR Implementation. Logic Families: Digital Logic Gates,
TTL and CMOS logic families.
Module:2 Verilog HDL [5 hours]
Lexical Conventions, Ports and Modules, Operators, Dataflow Modelling, Gate Level
Modelling, Behavioural Modeling, Test Bench
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Syllabus (contd…)
Module:3 Design of Combinational Logic Circuits [8 hours]
Design Procedure, Half Adder, Full Adder, Half Subtractor, Full Subtractor, Decoders,
Encoders, Multiplexers, De-multiplexers, Parity generator and checker, Applications of
Decoder, Multiplexer and De-multiplexer. Modeling of Combinational logic circuits
using Verilog HDL.
Module:4 Design of data path circuits [6 hours]
N-bit Parallel Adder/Subtractor, Carry Look Ahead Adder, Unsigned Array Multiplier,
Booth Multiplier, 4-Bit Magnitude comparator. Modeling of data path circuits using
Verilog HDL.
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Syllabus (contd…)
Module:5 Design of Sequential Logic Circuits [8 hours]
Latches, Flip-Flops - SR, D, JK & T, Buffer Registers, Shift Registers - SISO, SIPO,
PISO, PIPO, Design of synchronous sequential circuits: state table and state diagrams,
Design of counters: Modulo-n, Johnson, Ring, Up/Down, Asynchronous counter.
Modeling of sequential logic circuits using Verilog HDL
Module:6 Design of FSM [4 hours]
Finite state Machine(FSM):Mealy FSM and Moore FSM , Design Example : Sequence
detection, Modeling of FSM using Verilog HDL
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Syllabus (contd…)
Module:7 Programmable Logic Devices [4 hours]
Types of Programmable Logic Devices: PLA, PAL, CPLD, FPGA Generic Architecture
Module:8 Contemporary issues [2 hours]
Guest lecture from Industries and R & D Organizations
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Text Book(s) and Reference Book(s)
Text Books
1. M. Morris Mano and Michael D. Ciletti, Digital Design: With an Introduction to the
Verilog HDL and System Verilog, 2018, 6th Edition, Pearson Pvt. Ltd.
Reference Books
1. Ming-Bo Lin, Digital Systems Design and Practice: Using Verilog HDL and FPGAs,
2015, 2nd Edition, Create Space Independent Publishing Platform.
2. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2009, 2nd
edition, Prentice Hall of India Pvt. Ltd.
3. Stephen Brown and ZvonkoVranesic, Fundamentals of Digital Logic with Verilog
Design, 2013, 3rd Edition, McGraw-Hill Higher Education.
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Mode of Evaluation
The rubrics for theory as follows:
✓ CAT I – 50 marks
✓ CAT II – 50 marks
✓ Assessment 1 – 10 marks ( Before CAT-I)
✓ Assessment 2– 10 marks (Between CAT-I and CAT-II)
✓ Assessment 3 – 10 marks (After CAT-II)
✓ FAT – 100 marks
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