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IPC-6013B CN 2009 January

Qualification

and Performance Specification for Flexible Printed Boards

Supersedes IPC-6013A with Amendment 2

April 2006

This standard was developed by IPC

Association Connecting Electronics Industries

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The principle of
In May 1995, the IPC Technical Action Executive Committee (TAEC) adopted the "Principles of Standardization" as the guiding principles for IPC's efforts in standardization.

standardization

The standard Standards should not:

should: Express the relationship between Design for Manufacturability (DFM) inhibit innovation;

and Design for Environment (DFE); Minimize increase time to market; exclude

time to market; Use simple (simplified) new customers; increase

language; Contain only technical specifications; Focus on cycle time; tell you how to do

the performance of the end product; something; include any data that cannot

Provide a feedback system on applications and withstand scrutiny

problems to facilitate future improvements

Specifically, IPC standards and publications serve the public interest by eliminating misunderstandings between manufacturers and customers, promoting product interchangeability and improvement, and assisting buyers

in selecting and obtaining appropriate products to meet their specific needs with the least delay. The existence of these standards and publications shall not preclude any consideration from

excluding IPC members or non-members from manufacturing or selling products that do not conform to the requirements of these standards and publications, nor shall they preclude voluntary

adoption by the public, whether domestically or internationally, by non-members.

IPC standards and publications are recommended, regardless of whether their adoption may involve patents on the document, material, or process. IPC assumes no obligation to

any patent owner nor to any group that adopts these recommended standards and publications. Users bear the sole responsibility for defending themselves against any allegations of

patent infringement.

IPC's Official It is the position of the IPC Technical Action Executive Committee that the use and implementation of IPC publications is entirely voluntary and forms part of the user-supplier relationship.

Statement on When an IPC publication is updated and a revised edition becomes available, the TAEC's opinion is that, unless required by contract, the relationship of using the new revised edition as part

Specification of the current edition is not automatically established. The TAEC recommends the use of the latest edition. Effective October 6, 1998

Revisions and Changes

Why should I pay By purchasing this standard, you are contributing to the development of new standards and the upgrading of industry standards. Standards foster mutual understanding

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product?

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Thank you for your continued support.

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photocopying, scanning, or other reproduction of this material without the prior written consent of the copyright owner is strictly prohibited and constitutes infringement

under U.S. copyright law.

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IPC-6013B CN
?

Qualification and performance specifications of flexible printed circuit boards

If a conflict occurs between

the English and translated

versions of this document, the
English version will take

precedence.

Developed by the IPC Flexible Circuits Committee

(D-10) and the Flexible Circuits Performance Specifications Subcommittee

In the event of any conflict between the English
(D-12). Translated by the IPC TGAsia D-12C Technical Group.
version and a translated version of this

document, the English version shall prevail.

replace:
Users of this standard are encouraged to participate in the development of future revisions.
IPC-6013A Amendment 2 – April 2006
IPC-6013A Amendment 1 – January 2005
Contact Details:
IPC-6013A – November 2003
Revision 1 – December 2005
IPC IPC China
IPC-6013A Amendment 1 includes:
3000 Lakeside Drive, Suite 309S Shanghai
IPC-6013 – November 1998,
Bannockburn, Illinois Office Tel: (8621) 54973435/36
Issue 1 – April 2000
60015-1249 Shenzhen
IPC-RF-245 – April 1987
Tel 847 615.7100 Office Tel: (86755) 86141218/19 Beijing
IPC-FC-250 – January 1974
Fax 847 615.7105 Office Tel:
(8610) 67885326 Suzhou Office
Tel: (86512)
67164877
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January 2009 IPC-6013B

Acknowledgements

Any standard encompassing complex technology requires extensive documentation. The entire IPC Flexible Circuits Committee (D-10) and the Flexible Circuits Performance Specifications Subcommittee (D-12) worked

tirelessly to develop this standard. We thank them for their selfless dedication. While it's impossible to list all the individuals and organizations that participated in and supported the development of this

standard, only the key members of the Flexible Circuits Performance Specifications Subcommittee are listed below. However, we must also mention the members of the IPC TGAsia D-12C Technical

Group, who diligently translated and reviewed the Chinese version of this standard, striving for accuracy and elegance. We would like to express our sincere gratitude to all of these organizations and individuals involved.

Flexible Circuit Committee Flexible Circuit Performance Specifications Subcommittee IPC Board Technical Liaison

President President

Thomas F. Gardeski Koop PeterBigelow IMI

EI du Pont de Minco Products, Inc. Inc.
and Co.
Vice Chairman Sammy Yi
Vice Mahendra Gandhi Flextronics International
Chairman Grumman
Koop Minco Products, Inc. Space Technology

Flexible Circuit Performance Specifications Subcommittee

TakahisaAkatsuka, Alan Exley, Raytheon Company Gary Matt McQueen, Crane

Mektron Ltd.
Ferrari, FTG Circuits Mark Roger Miedico, Raytheon
Lance Auer, Raytheon Missile Company
Finstad, Minco Products Inc.
Systems
Paula Molina-Canales,
Michael Green, Lockheed Martin
Greg Bartlett, TeledynePrinted Underwriters Laboratories Inc.
SpaceSystemsCompany
Circuit Technology
Steve Musante, Raytheon Missile
Russell Griffith, Flexible Circuits
John Bauer, Rockwell Collins Systems
Inc.
Michael Beauchesne,Amphenol Bob Bob Laboratories
William Hazen, Raytheon
Printed Circuits, Inc.
Company Steven Lockheed Martin
Roger Bell, SpaceSystems/Loral Maritime Systems & Sensors
Philip Henault, Raytheon
Elaine Brown, Lockheed Martin Company William Ortloff, Raytheon
Systems Integration Company
Toru Koizumi, JPCA-Japan
Mark Buechner, BAE Systems Electronics Packaging and Anthony Plemel, Minco Products
Circuits Association Inc.
Dennis Cantwell, Printed Circuits
Inc. Karin LaBerge, Microtek Greg Roettger, Minco Products
Laboratories Inc.
Christine Coapman, Delphi
Electronics and Safety Michael Luke, Raytheon Company Rollan Savage,High Performance Copper
Foil Inc.
David Corbett, DefenseSupply Clifford Maddox, Boeing
Center Columbus Company JosephScmidt, Raytheon Missile
Systems
David Daigle, Rockwell Duane Mahnke, Mahnke
Automation/Allen-Bradley William Consulting Robert Sheldon, Pioneer Circuits
Inc.
Dieffenbacher, BAE Systems Kenneth Manning, Raytheon
Platform Solutions C. Don Dupriest, Company Russell Shepherd, Microtek
Laboratories
Lockheed Martin Missiles and Fire Control Christin Martin, Lockheed Martin
Systems Integration Lowell Sherman, DefenseSupply
Center Columbus
Ted Edwards, Dynaco Corp. Randy Mcutt,
Grumman Corp.

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IPC-601 3B January 2009

Caroline Simonian-Owens, Mark Verbrugge, Minco Products John Williams, Raytheon

Underwriters Laboratories Inc. Inc. Company
Herb Stark, Flexible Circuits Inc. Steve Vetter, Crane Katsuya Yamada, Sumitomo
Electric Printed Circuits Inc
Dwaynee Unglesbee, Lockheed Clark Webster,ALL Flex LLC
Martin Maritime Systems& Ricky Yeung, Meadville Holdings
Sensors Dewey Whittaker, Honeywell Inc. Limited
Air Transport Systems
Crystal Vanderpan, Underwriters
Laboratories Inc.

D-12CN Technical Team

Members: Huang Benyu, Anjieli Electronics (Panyu) Industrial Co.,

Ltd., Li Shiming, Shenzhen Fastprint Circuit Technology Co., Ltd., Gong
Yonglin, Shanghai Meville Technology Co., Ltd.,
Chen Peiliang, China Printed Circuit Industry
Association, Ma Mingcheng, China Printed Circuit
Industry Association, Zheng Yuchuan, Anjieli Electronics (Panyu)
Industrial Co., Ltd., Xu Qingsong, Anjieli Electronics (Panyu)
Industrial Co., Ltd., Cai Qiaoer, Guangdong Shengyi
Technology Co., Ltd., Gong Lijun, Shenzhen Fastprint Circuit Technology
Co., Ltd., He Bo, Zhuhai Yuansheng Electronic Technology Co.,
Ltd., Li Zhidong, Shenzhen Fastprint Circuit Technology Co., Ltd., Li
Yating, Honeywell Aerospace Division, Yuan
Chang'e, Hong Kong Printed Circuit
Association, Chen Yanmai, Krotech (Changzhou)
Laboratory, Peng Jinqiang, Shenzhen
Nanshan Circuit Co., Ltd., Wu Bo, Shenzhen EasyLink
Technology Development Co., Ltd., Ma Daowen, Shenzhen Mindray
Bio-Medical Electronics Co., Ltd., Sun Gaixian, Guangzhou
Amphenol Integrity Flexible Circuit Co., Ltd., Chen Limin,
U-Link International Security Certification Co., Ltd., Liu Jiaxing, Trina
Systems Consulting Services (Shanghai) Co., Ltd., Chen Zhidong, Zhejiang Huali International Development Co., Ltd.

IPC expresses its sincere gratitude to CPCA for its support and contributions in the development of this standard.

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? Record

1 Scope...................................... 1 3.2.10 Marking ink................................................. 8

1.1 Scope .................................. 1 3.2.11 Plug Hole Insulation Material .................. 3.2.12 8

1.2 Purpose .................................. 1 External Heatsink .................. 3.2.13 Via 8

1.3 Performance Levels, Printed Board Types, and Installation 1 Protection .................. 3.2.14 Embedded Passive 8

Applications 1.3.1 Performance Levels 1.3.2 Printed 1 Material .................. Visual Inspection .................. 3.3.1 8

Board Types 1.3.3 Installation Application Categories 1 3.3 Appearance .................................. 8

1.3.4 Procurement Options 1.3.5 Materials, Plating 1 3.3.2 Structural Defects .................. 3.3.3 Plating 8

Processes, and Final Finishes 1.4 Terms and 1 and Coating Voids in Holes ........ 3.3.4 Lifted 9

Definitions 1 Lands .................. 3.3.5 Marking .................................. 3.3.6 12

2 Solderability .................................. 12

1.4.1 To be determined by negotiation between the supplier ....... 2 13

and the buyer (AABUS) 1.4.2 Covering layer 1.4.3 3 13

Covering film 3 3.3.7 Plating Adhesion .................................. 3.3.8 13

1.4.4 Covering Coating .................................. 1.4.5 3 Adhesion of Gold Plating to Solder Coating on Printed Board Edge Contacts

3 Joints of cladding....................... 13
Covering Material ...................................... 1.5

3 3.3.9 Workmanship quality ................................. 13

Explanation of “Should” ..................
3.4 Dimensional requirements ................................. 14
1.6 Unit Display....................................... 1.7 Version 3

3 3.4.1 Aperture, hole pattern accuracy, and pattern element accuracy 14

Updates............................
3.4.2 Hole ring and hole break (external ............... 14

2 Bootloader.................................. 3 layer) 3.4.3 Bow and twist (only for rigidity or reinforcement)
twenty one IPC ........................................ 3 board part) ........................... 17

2.2 Joint Industry Standards .................. 2.3 Other 4 3.5 Conductor Accuracy .................................. 3.5.1 17

Publications .................. 2.3. 1 American Society for 4 Conductor Width and Thickness ....... 3.5.2 Conductor 17

Testing and Materials .................. 4 Spacing ..................... 17

2.3.2 National Electronics Manufacturers Association 2.3.3 4 3.5.3 Conductor defects ................................. 3.5.4 17

American Society for Quality 4 Conductor surface ................................. 3.6 18

2.3.4 AMS........................ 4 Structural integrity ................................ 19

2.3.5 American Society of Mechanical Engineers .................. 4 3.6.1 Thermal Stress Testing .................................................. 20

2.3.6 Federal Standards ...................................... 4 3.6.2 Requirements for Microsectioned Coupons or Production Boards .. 20

3.7 Solder mask requirements................................... 28

3 Requirements .................................................. 5
3.7.1 Solder Mask Coverage .................................. 28
3.1 General .................................................. 3.2 5
3.7.2 Solder Mask Curing and Adhesion .................. 3.7.3 29
Materials used in this specification .................. 3.2.1 Laminates 5
Solder Mask Thickness .................. 29
and adhesives .................................. 5
3.8 Electrical Requirements .................................. 29
3.2.2 External bonding materials........................ 5
3.8.1 Dielectric Withstand Voltage .................. 3.8.2 29
3.2.3 Other dielectric materials... 5
Electrical Continuity and Insulation Resistance .................. 29
3.2.4 Metal foil................................ 5
3.8.3 Short Circuits between Circuits/PTHs and Metal Substrate .................. 30
3.2.5 Metal layer/core ................................................. 5
3.8.4 Moisture and Insulation Resistance (MIR) ............. 30
3.2.6 Metal plating and coating layers.................. 5 30
3.9 Cleanliness ................................................
3.2.7 Organic Solderability Preservative (OSP) ............ 8 30
3.9.1 Cleanliness before applying solder mask
3.2.8 Polymer coating (solder mask) 3.2.9 Hot .............. 8
3.9.2 Application of Solder Mask, Solder, or Other Surface Coatings
melt and flux ...................... 8 Cleanliness after................................... 30

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IPC-6013B January 2009

3.9.3 Cleanliness of the inner layer after oxidation treatment before lamination 30 Appendix A ................................................. 41

3.10 Special requirements 3.10.1 Degassing 3.10.2 30

Organic contamination 3.10.3 Fungus resistance 31 picture

3.10.4 Vibration 3.10.5 Mechanical shock 3.10.6 31

Figure 3-1 Transition zone................................ 9

Impedance test 3.10.7 Coefficient of thermal expansion 31

Figure 3-2 Unacceptable Cover Coating Coverage ................................ 11

(CTE) 31
Figure 3-3 Solder Wicking and Plating Penetration ................. 12
31
Figure 3-4 Ring Width Measurement (Outer Layer) ................................ 15
31
Figure 3-5 90° and 180° destruction ...................... 15
31
Figure 3-6 Reduction of conductor width ...................... 16
3.10.8 Thermal Shock .................................. 3.10.9 31
Figure 3-7 The larger and smaller clearance holes of the flexible printed circuit board allow tangency... 16
Surface Insulation Resistance (As Received) 3.10.10 ............. 31
Figure 3-8 Cover film adhesive squeeze out and cover coating oozing out...... 16
Metal Core (Horizontal Microsection) ............. 32
Figure 3-9 Material within the adhesive range extruded from the edge of the cover layer
3.10.11 Ionic Contamination (Resistivity Measurement by Solvent ..... 32
Missing or missing ...................................... 17
Extraction) 3.10.12 Simulated Rework 3.10.13 Bend Test 32
Figure 3-10 Excess copper between conductors and conductor nodules. 17
32
Figure 3-11 Rectangular surface mount lands................... 18
3.10.14 Flexural Resistance .................................. 3.10.15 32
Figure 3-1 2 Circular surface mount lands................... 19
Bond Strength (Unsupported Land) 3.10.16 Bond Strength ........... 33
Figure 3-1 3 Separation of outer copper foil ................. Figure twenty two

(Stiffener) ................................ 33
3-1 4 Definition of crack ................................ twenty two

3.11 Repair.................................................. 3.11.1 33

Figure 3-1 5 Typical microsection evaluation sample ................ twenty three

Circuit Repair........................... 3.12 33

Figure 3-16 Allowable etch depth....................... twenty three

Rework............................................. 33
Figure 3-1 7 Drill smear allowance ................................. Figure twenty three

4 Quality Assurance Regulations............................ 33 3-1 8 Negative etchback ................................................ twenty four

4.1 General Principles.................................................. 33 Figure 3-1 9 Coating folds/inclusions ...................... twenty four

4.1.1 Identification................................................ 33 Figure 3-20 Ring width measurement (inner layer) ................................ 25

4.1.2 Test Coupon Samples .................................. 4.2 33 Figure 3-21 Rotating microscopy section position detection hole damage........... 25

Acceptance Tests and Frequency .................................. 36 Figure 3-22 Microsection Position Rotation Comparison... Figure 25

4.2.1 C=0 Zero Acceptance Number Sampling Plan................ 36 3-23 Surface Copper Cover Measurement (Applicable to all fill

4.2.2 Arbitration Test...................................... 40 filled plated-through holes) ......................... 26

40 Figure 3-24 Copper cladding in Type 4 printed circuit board (acceptable) ........ 26
4.3 Quality consistency test......................

4.3.1 Selection of test coupons................................... 40 Figure 3-25 Copper cladding removed due to excessive grinding/scraping

(Unacceptable) ......................... Figure 26

5 Notes.................................... 40 3-26 Metal Core to Plated-Through Hole Spacing ................ 28

5.1 Order Information Procurement documents should clearly state the following. Figure 3-27 Measurement of minimum dielectric spacing................... 28

5.2 Superseded Specifications................................. 40 Figure 3-28 Bending test....................... 32

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surface

Table 1-1 Default requirements................................... 2

Table 3-1 Inner or outer metal layer ...................... 5

Table 3-2 Requirements for final coating, coating layer and copper plating........ 6

Table 3-3 Cover coating adhesion ....................... 12

Table 3-4 Solder Wicking/Plating Penetration Limits................ 12

Table 3-5 Reinforcement board cavity area

Percentage limit of................................... 12

Table 3-6 Visual inspection of voids in plating and coating layers........... 12

Table 3-7 PCB edge contact gap................... 13

Table 3-8 Minimum ring width............................ 15

Table 3-9 Covering layer adhesive extrusion and

Allowable value of cover coating seepage................. 16

Table 3-10 Minimum solderable ring width of pad area ................................ 16

Table 3-11 Conductor spacing requirements................... 17

Table 3-1 2 Plated-through hole integrity after thermal stress ................................ twenty one

Table 3-1 3 Inner copper foil thickness after processing................... 27

Table 3-1 4 Outer conductor thickness after electroplating................... 27

Table 3-15 Solder mask adhesion......................... Table 29

3-16 Dielectric withstand voltage test voltage............ 30

Table 3-1 7 Insulation resistance ...................... 30

Table 4-1 Identification Tests............................ 34

Table 4-2 Sampling plan for batch printed circuit boards of various levels C=0. 36

Table 4-3 Acceptance inspection and frequency....................... 37

Table 4-4 Quality consistency test....................... 40

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Qualification and performance specifications of flexible printed circuit boards

1 Scope Type 5 Flexible or rigid-flexible printed boards with two or more conductive layers but no plated-

through holes.

1.1 Scope This specification covers the qualification and performance requirements for flexible

printed boards. Flexible printed boards may be single-sided, double-sided, multilayer, or rigid-flex 1.3.3 Installation Category A: Able to

multilayer. All of these printed board constructions may have or may not have stiffeners, plated-
withstand deflection during installation.

through holes, and blind/buried vias.

Application B: Able to withstand continuous flexure, continuous flexure cycle

The number of cycles shall be as specified in the procurement documents.

Flexible or rigid-flex printed boards may contain build-up high-density interconnect (HDI) layers Application C: Withstands high temperature environments (over 105°C [221°F]). Application

in accordance with IPC-6016. These printed boards may include embedded active or passive D: UL listed.

circuits with discrete capacitor layers, embedded capacitive or resistive components.

1.3.4 Procurement Selection For procurement needs, the performance level of the purchased

goods and their installation and use categories should be specified in the procurement
The rigid portion of the printed circuit board may include an active or passive metal core or an
documents.
external metal heat sink frame.

The procurement documents should provide the supplier with sufficient information so that the
For version update revisions, see Section 1.7.
supplier can manufacture the flexible printed circuit board according to the requirements and

ensure that the user gets the expected product. The information included in the procurement
1.2 The purpose of this specification is to provide qualification and performance requirements
documents should comply with the requirements of IPC-D-325.
for flexible printed boards designed in accordance with IPC-2221 and IPC-2223.

NOTE: Identifiers are not required if the requirements are specified in words on the drawing.

1.3 Performance Level, Printed Board Type, and Installation

1.3.4.1 Selection (Default) The procurement documents shall specify the optional requirements
1.3.1 Performance Grades This specification recognizes that the performance requirements
within this specification. However, if no selection is made in the procurement documents, the
for flexible printed boards vary depending on the end use. According to IPC-6011, flexible
default requirements in Table 1-1 shall apply.
printed boards are classified into performance grades 1, 2, and 3.

1.3.5 Materials, Plating Process and Final Coating

1.3.2 Printed Board Types Performance requirements are established for different types of 1.3.5.1 Laminate Materials shall be identified by numbers and/or letters, grades, and types as

flexible printed boards. Flexible printed boards can be divided into the following types: specified in the specifications listed in the procurement documents.

Type 1 single-sided flexible printed circuit board with one conductive layer, with or without a
1.3.5.2 Electroplating Processes The electroplated copper process used to provide the primary
stiffener.

conductor within the hole shall be designated by a single digit as follows:

Type 2 double-sided flexible printed circuit board with two conductive layers and plated-through
1. Only acid copper plating is used
holes, with or without stiffener.

2. Pyrophosphate copper plating only

Type 3 multilayer flexible printed boards with three or more conductive layers and plated-through

holes, with or without stiffeners. 3. Acidic and/or pyrophosphate copper plating

Type 4 rigid-flex multilayer printed circuit boards have three or more conductive layers and plated- 4. Additive method/chemical copper plating

through holes. 5. Electroplated nickel base with copper plating process

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IPC-6013B January 2009

Table 1-1 Default requirements

item? Default selection

Performance level Level 2

Installation and use Use A

category Manufacturer confirmed

Material Final Coating X [Electrolytic Tin-Lead (Hot Melt) or Solder Coating]

coating Minimum starting All inner and outer layers are 1/2oz

copper foil Manufacturer confirmed

Copper foil type Electroplated component hole (±) 100 ÿm [3,937 ÿin]

diameter tolerance Electroplated via hole (+) 80 ÿm [3,150 ÿin] (-) No requirement (can be completely or partially blocked)

diameter tolerance Non-metallized hole (±) 80 ÿm [3,150 ÿin]

diameter tolerance Meets Level 2 requirements of Section 3.5.1

Conductor width tolerance Meets Level 2 requirements of Section 3.5.2

Conductor spacing Determined by the manufacturer; the finished product spacing is within 80% of the thickness selected in the design

tolerance Dielectric layer Minimum 100 ÿm [3,937 ÿin]

spacing Significant color contrast, non-conductive

Conductor If not specified, no solder mask is applied

lateral spacing Marking If no class is specified, IPC-SM-840 Class T

ink Solder mask Category 2 in J-STD-003

specification Add solder mask 40V

Solderability test Insulation (short circuit) See IPC-6011

Test Qualification Inspection Shape tolerance when not specified 0.5 mm [0.0197 in] for all external edges

NOTE: Pyrophosphate copper plating is no longer used. Nickel isolation layer/chemical gold (Table 3-2)

OSP Organic Solderability Preservative (in storage and assembly

1.3.5.3 Final coating The final coating may be, but is not limited to, the , Process to prevent oxidation and protect solderability) (Table 3-2)
following identifiers depending on the assembly process and final application:
EIG Chemical Nickel/Immersion Gold (Table 3-2)
One or a combination of the following. The procurement documents shall specify
DIG Direct Immersion Gold (Table 3-2)
Unless otherwise specified, the coating thickness shall be

Meet the requirements of Table 3-2.

IS immersion silver (Table 3-2)

IT immersion tin (Table 3-2)

S Solder coating (Table 3-2)

C Bare copper (Table 3-2)

T Electroplated Tin-Lead (Hot Melt) (Table 3-2)

X Y Other
S-type or T-type (Table 3-2)

TLU Electroplated Tin-Lead (Non-Fusing) (Table 3-2)

1.4 Terms and Definitions All terms in this specification are defined as follows:

G Gold plating of printed circuit board edge connectors (Table 3-2) Shall be consistent with IPC-T-50 and comply with Sections 1.4.1 through 1.4.5

GS soldering area gold plating (Table 3-2) Require.

GWB-1 Gold plating on wire bonding area (ultrasonic bonding)

1.4.1 Negotiation between the supply and demand parties (AABUS)
(Table 3-2)
Additional or supplementary requirements determined by the supplier and the purchaser in the document,

GWB-2 Gold plating on wire bonding area (hot press bonding)

Such as contract requirements, changes to procurement documents and drawings
(Table 3-2)
These requirements can be used to indicate that there are no

Nickel plating of printed circuit board edge connectors (Table 3-2) Independent test methods, test conditions, frequency, type or acceptance

Nickel layer as copper-tin diffusion barrier (Table 3-2) standard.

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2.1 IPC 1
1.4.2 Coverings Films and adhesives made from separate layers of compounds with

different properties.
IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits

1.4.3 Covering film is made of the following materials:

IPC-DD-135 Qualification Test of Organic Deposited Internal Dielectric Materials

for Multi-Chip Modules

i) Single-component homogeneous

material; ii) Independent layers of phase-like IPC-CF-152 Specification for Composite Metal Materials for Printed Wiring Boards

compounds; iii) Mixtures.

IPC-D-325 Documentation Requirements for Printed Board and Assembly Support

Drawings
1.4.4 Covercoat A liquid material applied to a circuit that subsequently becomes

a permanent dielectric coating.

IPC-A-600 Acceptability of Printed Boards

NOTE: Covercoat may degrade performance in tight bend radius applications. 2

IPC-TM-650 Test Method Manual

2.1.1 Microsectioning 2.1.1.2

Microsectioning using semi-automatic or fully automatic microsectioning equipment

1.4.5 Coverstock A thin dielectric material used to encapsulate a circuit, most
(optional)
commonly used for flexible circuits.

2.3.15 Purity of Copper Foil or Coating 2.3.38

1.5 Explanation of “shall” “Shall” is a verb used in the imperative sense and indicates Detection of Surface Organic Contaminants 2.3.39 Identification

from , mandatory requirements anywhere in this document. Deviations

of Surface Organic Contaminants (Infrared Analysis) 2.4.1 Adhesion, Tape Test

“shall” requirements may be considered if there is sufficient data to justify an 2.4.2.1

exception.
Flex Fatigue and Ductility, Metal Foil 2.4.3 Flex

Fatigue, Flexible Printed Wiring Materials 2.4.3.1 Flex Fatigue and

“Should” and “may” are used to express non-mandatory requirements.

Ductility, Flexible Printed Wiring 2.4.15 Surface Coating, Metal Foil

"Will" is used to express a statement of purpose. To help readers
2.4.18.1 Tensile Strength and Elongation Tests for Internal Coatings 2.4.20
For clear identification, “should” is indicated in bold font.
Terminal Bond Strength, Flexible Printed Wiring

1.6 Units All dimensions and tolerances in this specification are expressed in metric

units, with the corresponding imperial units indicated in parentheses. Users of this

specification are advised to use metric units. All dimensions greater than or equal to 2.4.22 Bow and Twist 2.4.28.1 Solder

0.25 mm [0.00984 in] are expressed in millimeters and inches. All dimensions less Mask Adhesion, Tape Test Method 2.4.36 Rework Simulation,

than 0.25 mm [0.00984 in] are expressed in micrometers and microinches. Plated-Through Holes with Leaded Components 2.4.41.2 Coefficient of Thermal

Expansion, Strain Gage Method 2.5.7 Dielectric Withstand

Voltage, PWB 2.5.5.7 Characteristic Impedance

1.7 Version Updates This specification uses gray shading to indicate the sections
and Delay of Printed Board Conductors, Time Domain Reflectometry (TDR)
that have been revised in this version. For revisions to figures or tables, only the

figure or ,table title is gray-shaded.

2.6.1 Fungus Resistance, Printed Wiring Materials 2.6.3

2 Referenced Moisture Resistance and Insulation Resistance, Printed Boards

Documents The following specifications form an integral part of this specification within 2.6.4 Outgassing, Printed Boards 2.6.7.2

the scope of this specification. In the event of a conflict between IPC-6013 and the Thermal Shock, Continuity, and Microsectioning, Printed Boards 2.6.8 Thermal

applicable documents listed, IPC-6013 shall prevail, with the exception of IPC-6011. Stress, Plated-Through Holes

1. www.ipc.org 2.
Current and revised editions of the IPC Test Methods Manual, IPC-TM-650, are available by order and download from the IPC website (www.ipc.org/html/testmethods.htm) .

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IPC-QL-653 Certification of Printed Board, Component, and Material Inspection and Testing IPC-9691 IPC-TM-650 Test Method 2.6.25, Anodic Conductive Filament (CAF) Resistance Test

Equipment (Electrochemical Migration Test) User Guide

IPC-SM-840 Identification and Performance Specifications for Permanent Solder Masks

3
IPC-2221 General Standard for Printed Board Design 2.2 Joint Industry Standards

IPC-2223 Flexible Printed Board Design Standard J-STD-003 Printed Board Solderability Test

IPC-2251 Design Guidelines for High-Speed Electronic Circuit Packaging J-STD-006 Requirements for electronic grade solder alloys and solid solders with and without

flux in the field of electronic soldering

IPC-4101 Specification for Base Materials for Rigid and Multilayer Printed Boards

IPC-4103 Specification for Base Materials for High-Speed/High-Frequency Applications 2.3 Other publications

IPC-4202 Flexible Substrate Media for Flexible Printed Circuits

4
2.3.1 American Society for Testing and Materials

IPC-4203 Dielectric Films and Flexible Adhesive Films for Adhesive Coatings of Flexible Printed
ASTM B 488 Standard Specification for Gold Electroplated Coatings for Engineering Use
Circuit Coversheets

ASTM B 579 Standard Specification for Tin-Lead Alloys

IPC-4204 Flexible Metal-Foil-Clad Dielectric Materials for Flexible Printed Circuits

5
2.3.2 National Electrical Manufacturers Association

IPC-4552 Specification for Electroless Nickel/Immersion Gold Plating on Printed Circuit Boards
LI-1 Industrial Laminated Thermoset Product Standard

IPC-4553 Specification for Immersion Silver Plating on Printed Circuit Boards

6
2.3.3 American Society for Quality
IPC-4562 Metal Foil for Printed Circuit Boards

H0862 Zero Acceptance Number Sampling Plan

IPC-4563 Guidelines for Resin-Coated Copper Foil for Printed Boards

7
IPC-4761 Printed Circuit Board Via Hole Structural Protection Design Guide 2.3.4 AMS

IPC-4781 Specification for the Identification and Performance of Permanent, Semi-permanent, SAE-AMS-QQ-A-250 General Specification for Aluminum and Aluminum Alloys, Aluminum and

and Temporary Marking and/or Marking Inks Aluminum Alloy Plates and Sheets

IPC-4811 Specification for Embedded Passive Resistor Materials for Rigid and Multilayer Printed SAE-AMS-2424 electroplating, low stress nickel deposit

Boards

8
2.3.5 American Society of Mechanical Engineers
IPC-4821 Specification for Embedded Passive Capacitor Materials for Rigid and Multilayer Printed

Boards ASME B46.1 surface texture (surface roughness, waviness, and laminar depth)

IPC-6011 General Performance Specification for Printed Boards

IPC-7711/21 Rework, Modification, and Repair of Electronic Assemblies 2.3.6 Federal Standard 9

IPC-9252 Electrical Test Requirements for Unpopulated Printed Boards QQ-S-635 steel

3. www.ipc.org
4. www.astm.org
5. www.nema.org
6. www.asq.org
7. www.sae.org
8. www.asme.org
9. www.sae.org

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3 Requirements 3.2.3 Other media materials Photosensitive imaging media should be in accordance with

The requirements of IPC-DD-135 should be selected and

3.1 General The flexible printed circuit boards provided in accordance with this specification shall
Other dielectric materials may be specified in the procurement documents.
Meets or exceeds the specificity specified in IPC-6011 and procurement documentation
Regulation.
The description and use of the test coupons are in

This is specified in IPC-2221. Although specific quality 3.2.4 Metal Foil Copper foil shall comply with the requirements of IPC-4562.
Quality control coupons are used to determine if they meet all performance requirements.
If it is critical to the function of the flexible printed circuit board, the metal foil

requirements, but these performance requirements apply to all flexible printed circuit board attachments.
Type, grade, foil thickness, bond enhancement treatment, and metal

Samples of continuous boards or flexible printed boards, and flexible printed boards to be delivered
The foil outline should be specified in the master layout drawing.
These requirements are based on the assumption that the flexible printed circuit board is designed
When in compliance with IPC-4563.

The design complies with the corresponding IPC design standards.

3.2.4.1 Resistive metal foil shall be specified in the procurement documentation.

3.2 The materials used in this specification are used to manufacture flexible printed circuit boards.
Constant resistance metal foil.
All materials for making panels should comply with relevant specifications and procurement

It is the user's responsibility to specify compliance with this regulation in the purchase documentation. 3.2.5 Metal layer/core metal layer and/or metal core substrate should

Materials that meet specifications and end-use requirements. When specified in the general layout drawing, as shown in Table 3-1.

Table 3-1 Internal or external attribute layer

NOTE: Where possible, suppliers should review the materials used for a given
Material specification combine?
If necessary,
SAE-AMS-QQ-A-250 compliant
If necessary, the procurement documents must be modified accordingly.
QQ-S-635 Comply with regulations

ASTM-B-152 or IPC-4562 compliant

3.2.1 Laminates and adhesive materials Metal-clad laminates, unclad
Aluminum Steel Copper Copper IPC-CF-152 Comply with regulations

Metal laminates, and bonding materials (bonding sheets) should be in accordance with
- Invar - Copper Copper - IPC-CF-152 Comply with regulations

IPC-4101, IPC-4103, IPC-4202, IPC-4203, IPC-

Molybdenum - Copper Other Comply with regulations Comply with regulations

4204 or LI 1-1989.

The materials of the parts should be selected in accordance with the requirements of IPC-4811 or IPC-4821.
3.2.6 Metallic Plating and Coatings Sections 3.2.6.1 to 3.2.6.8

The procurement documentation should specify the applicable dielectric, conductive, The thickness of the plating layer/coating layer of the section shall comply with the specifications in Table 3-2.

Specification sheet number, metal foil type and given, but the solder coating layer(s) and electroplated tin-lead (hot melt)

The thickness (weight) of the metal foil shall be as specified in the procurement documents. (T) thickness values are excluded. Coating S and T require appearance

When there are specific requirements, it is necessary to include them in the material procurement documents. Covered and meets the solderability test of J-STD-003. Plating and

Specify these requirements in detail. The metallized coating coverage requirement does not apply to the vertical edges of the conductors.

The copper is allowed to be exposed in the non-soldering area of the conductor surface, but it must be

3.2.1.1 The choice of flexible material is determined by the supplier.

Meet the requirements of Section 3.5.4.7. The selective plating/coating layer shall
Metal-coated dielectric materials and adhesive-coated dielectric films
When limited to the area specified in the procurement documents.
Available in accordance with IPC-4562, IPC-4202 and IPC-4203

In addition, when the NOTE: Suppliers shall specify solderability test procedures in accordance with J-STD-003.

When the materials of individual components are replaced, materials that comply with The test ; However, in the absence of regulations, the supplier

IPC-4204 can also be selected for replacement. category should be tested in accordance with Category 2 (steam aging is not required).

3.2.2 External bonding materials are used to bond flexible printed circuit boards. 3.2.6.1 Chemical Deposition and Conductive Coatings

Junction bonding materials for external heat sinks or stiffeners should be purchased The coating should be suitable for subsequent electroplating process, which can be chemical

The provisions for selecting documents in IPC-4202, , from IPC- or as per Plating, vacuum deposition of metal, can also be metallic or non-gold

IPC-4203, and IPC-4204. Electroless nickel/immersion gold plating should comply with

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IPC-6013B January 2009

IPC-4552 requirements. The measurement location and range should be determined by the supplier and the buyer. c) When tested in accordance with IPC-TM-650 Test Method 2.4.2.1

Determined by negotiation between the two parties. When the ductility is less than 80%,

Note: When the immersion gold thickness exceeds 0.125ÿm [4.925ÿin], 3.2.6.3 Additive electroless copper deposition as a base metal

May increase the risk of corrosion of the nickel barrier coating. Due to the design The electroless copper coating shall meet the requirements of this specification.

Effects of Pattern and Chemistry Variations on Solderability Coupons

3.2.6.4 Tin-lead plating The tin-lead plating shall conform to ASTM
The acceptance of the product may not represent the acceptance of the entire product.
B-579 has requirements for components (tin content is 50% to 70%).
To determine the uniformity of sediment thickness, it is strongly recommended to collect
Unless non-hot melt solution is selected, hot melt is required and the,thickness is full
The thickness of the deposited layer at different locations on the entire plate surface.
Meet the requirements of Table 3-2.

3.2.6.5 Solder coating Solder used in solder coating

3.2.6.2 Electroplated copper When specified, the electroplated copper coating shall be
It should be Sn60A, Sn60C,
The following requirements shall be met. The frequency of testing shall be determined by the ,
Pb40A, Pb36A, Pb36B, Pb36C, Sn63A, Sn
manufacturer to ensure process control.

63C or Pb37A.
a) When tested in accordance with IPC-TM-650 Test Method 2.3.15

When copper is used, the purity of the copper should not be less than 99.50%. 3.2.6.6 Nickel plating shall comply with SAE-AMS-2424

The thickness shall comply with the requirements of Table 3-2.

b) When tested in accordance with IPC-TM-650 Test Method 2.4.18.1

When the test sample thickness is 50ÿmÿ100ÿm[1,970 3.2.6.7 Electroplating? Gold plating shall comply with ASTM-B-488

ÿ inÿ3,940 ÿ in], its tensile strength should not be less than The purity, hardness and thickness of gold should meet the requirements of the purchase

36,000PSI[248MPa], And the elongation should not be less than The thickness of the gold plating in the wire bonding area should be

18%. When it meets the requirements of Table 3-2.

Table 3-2 Requirements for final coating, coating layer and copper plating

Code coating Level 1 Level 2 Level 3

Final coating

5
S Solder coating on bare copper Covered and weldable Covered and weldable 5 Covered and weldable 5

5
T Electroplated Tin-Lead (Hot-Fused) (Minimum) Covered and weldable Covered and weldable 5 Covered and weldable 5

XS or T type Comply with the requirements indicated in the code

TLU Electroplated Tin-Lead (Non-Fused) (Minimum) 8.0 ÿm[315 ÿin] 8.0 ÿm[315 ÿin] 8.0 ÿm[315 ÿin]
Gold for printed board edge connectors and non
G 0.8 ÿm[31.5 ÿin] 0.8 ÿm[31.5 ÿin] 1.25 ÿm[49.21 ÿin]
Welding area (minimum)

GS Gold for soldering areas (max) Gold 0.45 ÿm[17.72 ÿin] 0.45 ÿm[17.72 ÿin] 0.45 ÿm[17.72 ÿin]
electroplating for wire bonding areas
0.05 ÿm[1.97 ÿin] 0.05 ÿm[1.97 ÿin] 0.05 ÿm[1.97 ÿin]
Layer (ultrasonic bonding) (minimum)

GWB-1 Gold layer for wire bonding areas

Electroplated nickel base layer (ultrasonic bonding) 3 ÿ m [118 ÿ n] 3 ÿ m [118 ÿ in] 3 ÿ m [118 ÿ in]
(minimum)

Electroplated gold for wire bonding areas

0.3 ÿm[11.8 ÿin] 0.3 ÿm[11.8 ÿin] 0.8 ÿm[31.5 ÿin]
Layer (Thermosonic Bonding) (Minimum)

GWB-2 Gold layer for wire bonding areas

Electroplated nickel layer underneath (thermosonic bonding) 3 ÿ m [118 ÿ in] 3 ÿ m [118 ÿ in] 3 ÿ m [118 ÿ in]

(minimum)

Nickel is used in printed circuit board edge connectors

2.0 ÿm[78.7 ÿin] 2.5 ÿm[98.4 ÿin] 2.5 ÿm[98.4 ÿin]
(minimum)

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Code coating Level 1 Level 2 Level 3

1
Nickel layer as copper-tin diffusion barrier
1.3 ÿm[51.2 ÿin] 1.3 ÿm[51.2 ÿin] 1.3 ÿm[51.2 ÿin]
(minimum)
5
OSP Organic Solderability Preservative Electroless Solderable Solderable 5 Solderable 5

Nickel Layer (Minimum) 3ÿm [118ÿin] 3ÿm [118ÿin] 3ÿm [118ÿin]

EIG
8 8 8
Immersion Gold Layer (Minimum) 0.05 ÿm [1.97 ÿin] 0.05 ÿm [1.97 ÿin] Solderable 8 Solderable 6 0.05 ÿ m [1.97 ÿ in] solderable
8
DIG Direct Immersion Gold (solderable surface) Solderable Solderable 5 8
6
IS Immersion Silver Solderable Solderable Weldable 6

5
IT Immersion Tin Solderable To be Solderable 5

C Bare copper determined by negotiation between the supplier and the buyer

Copper plating on the surface and inside the holes

Level 1 Level 2 Level 3

Bronze 2 - Average through-hole

Type 12ÿm[472ÿin] 12ÿm[472ÿin] 12 ÿ m [472 ÿ in]

2, Type 3, Type 4 (ÿ6 layers) 25ÿm[984ÿin] 25ÿm[984ÿin] 25 ÿ m [984 ÿ in]

Type 3, Type 4 (ÿ6 layers) 35ÿm[1378ÿin] To be determined by 35ÿm[1378ÿin] 5ÿm[197ÿin] 35 ÿ m [1378 ÿ in]
7
Minimum coverage negotiation between the supplier and the buyer 12ÿm [472ÿin]

Level 1 Level 2 Level 3

Copper (maximum thickness 3)

Type 2 10 ÿ m [394 ÿ in] 10 ÿ m [394 ÿ in] 10 ÿ m [394 ÿ in]

3, 4 type (ÿ 6 layers) 3, 4 type (ÿ 6 20 ÿ m [787 ÿ in] 20 ÿ m [787 ÿ in] 20 ÿ m [787 ÿ in]

layers) Minimum copper coating 7 30ÿm[1181ÿin] To be determined by 30ÿm[1181ÿin] 5ÿm[197ÿin] blind hole 30 ÿ m [1181 ÿ in]

(via structure 4) negotiation between the supplier and the buyer 12ÿm [472ÿin]
4
average 2

20ÿm[787ÿin] 18ÿm[709ÿin] 20ÿm[787ÿin] 25 ÿ m [984 ÿ in]

Minimum thickness To be determined by 18ÿm[709ÿin] 20ÿm [787ÿin]
7
and minimum coverage negotiation between the supplier and the buyer 5ÿm [197ÿin] buried hole core 12ÿm [472ÿin]

Copper (via structure 4) average 2 material

13ÿm[512ÿin] 11ÿm[433ÿin] 15ÿm[592ÿin] 15 ÿ m [592 ÿ in]

Minimum To be determined by 13ÿm[512ÿin] 13ÿm [512ÿin]

thickness Minimum coating 7 negotiation between the supplier and the buyer 5ÿm [197ÿin] buried vias (for 12ÿm [472ÿin]

>2 layers)

Copper 2 - Average 20ÿm[787ÿin] 20ÿm [787ÿin] 25ÿm[984ÿin]

minimum thickness 18ÿm[709ÿin] To be determined 18ÿm [709ÿin] 5ÿm 20ÿm[787ÿin]

Minimum cladding 7 by negotiation between the supplier and the buyer [197ÿin] 12ÿm [472ÿin]
Note 1. Nickel plating is used under tin-lead or solder coatings to act as a barrier to prevent the formation of copper-tin compounds during high temperature operation.

NOTE 2. The copper plating (Section 1.3.5.2) thickness shall be continuous and extend from the hole wall or wrap around to the outside surface. See IPC-A-600 for hole wall copper plating thickness requirements.

NOTE 3 For Class 3 printed boards containing drilled holes <0.35 mm [0.0138 in] in diameter and having aspect ratios >3.5:1, the minimum copper plating thickness shall be 25 ÿm [984 ÿin].

Note 4. Low aspect ratio blind holes refer to blind holes with controlled drilling depth (such as laser drilling, mechanical drilling, plasma etching or photosensitive drilling). The performance characteristics of all plated holes should meet this specification.

requirements in .

Note 5. Hot air leveling (HASL, HAL) processes are considered difficult to control. Pad size and geometry add additional challenges to this process. These factors make the actual minimum thickness

Outside the scope of this specification , See also Section 3.3.6.

Note 6. When measuring immersion silver thickness, a specific land size is required for measuring thin and/or thick silver layers. Detailed measurement requirements are provided in IPC-4553.

NOTE 7. The copper wrap plating of filled plated-through holes shall comply with the requirements of 3.6.2.12.1.

Note 8. See Section 3.6.2.1.

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3.2.6.8 Immersion Silver Immersion silver shall be in accordance with IPC-4553. The 3.2.12 The thickness and materials of the heat dissipation layer and insulation materials constituting

pad dimensions used for thickness measurement are specified in IPC-4553 and are the outer heat dissipation layer shall be as specified in the procurement documents.

applicable to thin silver and/or thick silver deposits.

3.2.13 Via Protection The materials used to protect vias shall comply with those
NOTE: There are two different but acceptable processes for immersion silver: a thin
specified in the procurement documentation. The IPC-4761 design guide provides
silver deposition and a thick silver deposition.
information on material selection and considerations for via protection.

3.2.6.9 Other Metals and Coatings Other deposits such as palladium, rhodium, tin,

solder alloys, etc. may be used if specified in the procurement documentation.

3.2.14 Embedded Passive Materials: Embedded passive materials are materials and

methods used to add capacitance, resistance, and/or inductance to a printed board and

3.2.7 Organic Solderability Preservative (OSP) OSP is an anti-oxidation and solderability can be used to produce conventional core materials for flexible printed boards. These

protective layer applied to copper surfaces to maintain surface solderability during materials include laminates, resistive metal foils, plated resistors, conductive pastes,

storage and assembly processes. Storage of the coating, pre-assembly prebake, and and protective materials. Embedded passive materials must comply with the

subsequent soldering processes all affect solderability. Requirements for the shelf life
requirements of IPC-4811 or IPC-4821, or as specified in the procurement

and number of soldering cycles, if necessary, should be specified in the procurement documentation.

documentation.

3.3 Visual Inspection Finished flexible printed boards shall be inspected according to
3.2.8 Polymeric Coating (Solder Mask) When a permanent solder mask coating is
the following procedures. Flexible printed boards shall be of consistent quality and shall
specified, it shall be a polymeric coating in accordance with IPC-SM-840.
conform to the requirements of Sections 3.3.1 through 3.3.9.

Visual inspection of relevant properties should be conducted at 3 diopters (approximately

3.2.9 Fusing Fluids and Fluxes The fusing fluid and flux composition used for solder
1.75x magnification). If a suspected defect cannot be confirmed at 3 diopters, it should
coating should be capable of cleaning and fusing tin-lead plating and bare copper
be further verified at increasingly higher magnifications (up to 40x) to confirm its
surfaces to form a smoothly adherent coating. The fusing fluid should act as a heat
authenticity. Dimensional requirements, such as conductor spacing or width
transfer and distribution medium to prevent damage to the exposed base material of
measurement, may require other magnifications and an instrument with a crosshair or
the flexible printed board. The type and composition of the fusing fluid should be
scale that can accurately measure the specified dimensions. Other magnifications may
selected by the flexible printed board manufacturer.
be required by contract or specification.

NOTE: Due to the interaction of different materials in assembly soldering, the

compatibility of the fusing fluid with the end user's cleanliness requirements should be

3.3.1 Appearance
confirmed.

3.2.10 Marking Ink: Marking inks shall be permanent, non-nutrient (fungal-inhibiting), 3.3.1.1 Nicks, microcracks, or halos along the edges of flexible printed boards,

polymer inks and shall be specified in the procurement documentation. Marking inks notches, and non-plated-through holes on rigid sections are acceptable if the penetration

shall be applied to flexible printed boards or labels attached to flexible printed boards. depth does not exceed 50% of the distance from the edge to the nearest conductor or

Marking inks and labels must withstand subsequent processing with flux, cleaning 2.5 mm [0.0984 in], whichever is less. Ground planes shall be exempt from this ,

solvents, soldering, cleaning, and coating processes. If conductive marking inks are spacing requirement except where there is a voltage gradient between the edges of the

used, they shall be treated as conductive elements on the flexible printed board and board and the adjacent ground plane.

shall meet the requirements of IPC-4781.

The edges should be cut cleanly , There should be no metal burrs. Non-metallic

without burrs , materials are acceptable as long as they are not loose and/or do not

affect installation and function. When cutting or milling a pre-assembled board with a

3.2.11 Hole-filling insulation materials The insulation materials used to fill holes in flexible separable strip, the requirements for depaneling after flexible printed board assembly

printed circuit boards shall comply with the specifications in the procurement documents. must be met.

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3.3.1.2 Flexible Section Edges: The flexible section edges of flexible boards or rigid- 3.3.2.1 Measles. Measles are acceptable for Class 1, Class 2, and Class 3

flexible printed boards shall be free of burrs, nicks, or delamination exceeding the product. Measles in laminate substrates exceeding 50% of the spacing between

allowable limits specified in the procurement documentation. Type 1 and Type 2 flexible non-common conductors are considered a process indicator for Class 3 product

printed boards and Type 3 and Type 4 flexible printed boards shall not exhibit tears in and indicate variation in materials, equipment operation, workmanship, or process

the flexible section. The extent of nicks and tears due to discontinuous interfaces quality, but are not defects. While process indicators should be monitored as

created to facilitate circuit removal shall be determined by agreement between the part of the process control system, no action is required for individual process

purchaser and supplier. The minimum edge-to-conductor spacing shall be specified in indicators, and affected product should continue to be used as is.

the procurement documentation.

Note: White spots are an internal phenomenon in the laminate that may not
3.3.1.3 Rigid to Flexible Transition Zone: The transition zone is centered on the
expand under thermal stress and there is no clear conclusion that they are the
edges of the rigid and flexible sections. Inspection is limited to a 3.0 mm [0.118
cause of the growth of conductive anodic filaments (CAF). Delamination is an
in] radius around the center of the transition zone (i.e., the edge of the rigid
internal phenomenon that may expand under thermal stress and may also be
section) (see Figure 3-1). Visual defects due to manufacturing techniques (e.g.,
the cause of CAF growth.
adhesive squeeze-out, localized deformation of the dielectric or conductor,
Test Method , Both the IPC-9691 User Guide and IPC-TM-650 CAF
protrusion of dielectric material, microcracks, or halos) shall not be grounds for
2.6.25 provide additional information on determining the CAF growth performance
rejection. Defects outside the permitted range shall be determined by agreement
of laminates. Users who wish to include measling conditions in their requirements
between the purchaser and supplier, or as specified in the procurement
may consider using the IPC-6012 Class 3/A requirements for Class 3 products,
documentation.
which do not allow measling.

3.3.2 Structural Defects Defects include all internal and external features of the 3.3.2.2 Microcracks If microcracks do not reduce the conductor spacing below

printed board that are visible from the surface. the minimum value and are not due to simulated assembly processes

IPC-6013b-3-01-cn

Figure 3-1 Transition zone

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For Class 2 and 3 products, the span of microcracks shall not exceed 50% of 3.3.2.7 Surface voids Surface voids are acceptable if they do not exceed 0.8

the distance between adjacent conductors. mm [0.0315 in] in their longest dimension, do not bridge conductors, and do

not exceed 5% of the total area per side of the flexible printed board.

3.3.2.3 Delamination/Blistering Delamination and blistering are acceptable for

all classes if they do not exceed 1% of the area of each printed board side and 3.3.2.8 Color Variation in Bond Enhancement Treatment Areas Mottled or

do not reduce the spacing between conductive patterns below the minimum color variations in bond enhancement treatment areas are acceptable. Random

conductor spacing. Delamination and blistering shall not extend after thermal areas lacking treatment shall not exceed 10% of the total conductor surface

testing simulating the assembly process. For Class 2 and Class 3 products, area in the affected layer.

the span of blistering or delamination

, shall not exceed 25% of the spacing

between adjacent conductive patterns. For more information, see IPC- 3.3.2.9 Pink Ring: There is no evidence that the pink ring affects the

A-600. functionality of the printed board. Its presence may be considered a process

indicator or design variation, but is not grounds for rejection. For pink rings,

3.3.2.4 Foreign Inclusions Translucent particles shall be acceptable. Other the focus should be on the quality of the laminate bond.

inclusions in the printed board shall be acceptable provided they do not reduce

the distance between adjacent conductors below the minimum spacing 3.3.2.10 Covering and Cover Film Separation The cover film shall be uniform

specified in 3.5.2. and free of cover film separation, such as wrinkles, folds, and straw-like gaps.

Unlaminated defects shall be acceptable provided they meet the requirements

3.3.2.4.1 Foreign Inclusions Between Flexible Printed Boards and of Section 3.3.2.4 and the following provisions.
Stiffeners Opaque foreign inclusions, such as non-conductive foreign inclusions,
a) At random locations away from the conductor, each separation shall not
between flexible printed boards and stiffeners shall be acceptable if the bulge
shall not be within 0.80 x 0.80 mm [0.0315 x 0.0315 exceed and
or height does not exceed 100 ÿm [3,940 ÿin]. The inclusion shall not exceed
in] of a board edge or cover film opening. The total number of
5% of the stiffener bond area. It shall not contact component holes or printed
separations shall not exceed three within any 25 x 25 mm [0.984 x
board outline edges. Elongated non-conductive material shall not protrude
0.984 in] area of the cover film surface.
more than 1.0 mm [0.040 in] beyond the outline edge. Opaque foreign

inclusions shall not reduce the spacing between adjacent conductors below
b) The total length of separation should not exceed the spacing between adjacent conductors.
the minimum spacing specified in 3.5.2.
25%.

c) There shall be no cover film failures along the outer edges of the cover film,

3.3.2.5 Exposed Weave For Class 3 product, printed boards shall be free of than , and no cover film openings shall reduce the seal to less

exposed weave. Exposed weave or exposed/broken

, fibers are acceptable for the minimum edge-to-conductor spacing.

Class 1 and Class 2 product, provided the defect does not reduce the spacing

between conductors (excluding the exposed weave area) below the minimum 3.3.2.11 Cover coating requirements

requirement. See IPC-A-600 for more information.

3.3.2.11.1 Cover Coatings To prevent skipping, voiding, and misregistration

due to manufacturing variations, cover coatings are subject to the following

3.3.2.6 Scratches, Indentations, and Tooling Marks Scratches, indentations,

and tooling marks are acceptable if they do not expose the conductor or cause limitations:

fiber breakage in excess of the values permitted in 3.3.2.4 and 3.3.2.5 and do a) In areas where covercoat is required, metallic conductors shall not be

not reduce dielectric spacing below the specified minimum requirements. exposed or bridged by blisters. If covercoat repairs are required to

Indentations or tooling marks that result in delamination, changes in the cover these areas, they shall be made
, of a material that is compatible

physical dimensions of the conductor, or a reduction in conductor width or with the original covercoat and has the same resistance to soldering and

spacing shall be rejected. cleaning as the original covercoat.

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b) In areas containing parallel conductors, variations in the covercoat should 1) For surface mount lands, misalignment on the surface mount land

not expose adjacent conductors unless the area between the conductors shall not cause the covercoat to encroach on the land more than

is intentionally left open for test points or for some surface mount devices. 50 ÿm [1,970 ÿin] when the pitch is ÿ 1.25 mm [0.04921 in]; and

shall not cause the covercoat to encroach on the land more than

25 ÿm [984 ÿin] when the pitch is ÿ 1.25 mm [0.04921 in].

c) The covercoat does not need to be flush with the land surface. Misregistration
Encroachment may occur on adjacent sides of the surface mount
of the covercoat defined pattern shall not expose adjacent independent
land, but not on opposite sides.
lands or conductors (see Figure 3-2).

2) On BGA pads, if the pads are covered with coating

If clearance is specified, the covercoat is not allowed to encroach

on the pad except at the conductor connection. ,

3) When a BGA pad and via are connected and require coverlay dam

isolation, the coverlay dam shall be continuous without missing,

peeling or coverlay cracking resulting in an exposed metal path

between the BGA pad and the via.

f) Blistering should comply with the following:

1) Level 1: No bridging conductors ;

IPC-6013b-3-02-cn 2) Class 2 and Class 3: No more than two per side, with a maximum

Figure 3-2 Unacceptable Cover Coating Coverage length not exceeding 0.25 mm [0.00984 in], and not reducing the

electrical spacing between conductors by more than 25%.

d) If it does not violate the outer ring width requirements of the product level,
g) Pitting and voiding are permitted in non-conductive areas provided they are
Covercoat is permitted on the lands of plated-through holes where solder
adhered to the edges and do not lift or blister in excess of that permitted
connections are to be made. Covercoat should not intrude onto the walls
in 3.3.2.11.1(f).
of this type of plated-through hole. Other surfaces such as flexible printed
h) Coverage between closely spaced surface mount pads should
board edge connector contacts and surface mount lands shall be free of
Comply with the provisions of the procurement documents.
covercoat unless otherwise specified. Covercoat is generally permitted in
i) When the design requires coverage of the edge of a flexible printed board,
plated-through holes and vias where component leads are not to be
chipping or lifting of the covercoat along the edge of the flexible printed
soldered, unless the procurement documentation requires that these
board after processing shall not extend more than 1.25 mm [0.04291
holes be completely filled with solder. Covercoat may mask or plug vias
in] or 50% of the distance to the nearest conductor, whichever is less.
as required by the procurement documentation. Test points intended for

assembly testing must be free of covercoat unless covered as specified.

3.3.2.11.2 Covercoat Cure and Adhesion The cured covercoat shall not exhibit

e) When there is no plated-through hole in the pad, such as a surface mount tack or blistering in excess of that permitted in Section 3.3.2.11.1 (f). The

pad or ball grid array (BGA) pad, misalignment shall not cause the maximum percentage of peeling of the cured covercoat from Coupon G as

covercoat to encroach onto the pad, or the covercoat to be illegible specified in IPC-2221 shall conform to Table 3-3 when tested in accordance

beyond the following conditions: with IPC-TM-650, Test Method 2.4.28.1.

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IPC-6013B January 2009

Table 3-3 Covering coating adhesion?

What is the maximum percentage of peeling allowed?

surface? Level 1 Level 2 Level 3

Bare 10 5 0

copper, gold 25 10 5

or 10 5 0

nickel substrate hot melt metal (tin-lead plating, hot melt

50 25 10
Tin-lead and bright acid tin)

3.3.2.11.3 Covercoat thickness Unless otherwise specified in the procurement documentation

The thickness of the overcoat is not usually measured.

To measure thickness, you can use instrumental measurement or IPC-2221

Microsectioning of parallel conductors on coupon E as specified in

Conduct assessment.

3.3.2.12 Solder Wicking/Plating Penetration Solder Wicking or Other

Plating penetration should not extend into bends or flexible transition areas.

Solder wicking or other plating

Layer penetration should not exceed the limits specified in Table 3-4.

Table 3-4 Solder Wicking/Plating Penetration Limits

Level 1 Level 2 Level 3

0.5mm 0.3mm 0.1mm

[0.0197in], maximum [0.0118in], maximum [0.00394in], maximum

Figure 3-3 shows the penetration limits, defined as m1 and m2.

IPC-6013b-3-03-cn

3.3.2.13 The total void area of the reinforcement plate bond should not Figure 3-3 Solder wicking and plating penetration

Exceed the percentage of stiffener surface area given in Table 3-5.

Table 3-5 Reinforcement plate void ratio
The longest dimension of each cavity shall not exceed 2.5 mm [0.0984
Percentage limit of board surface area

Cavities along board edges, notches, and isolation holes whose penetration ,
Level 1 Level 2 Level 3

depth does not exceed 50% of the distance between the edge and the nearest conductor
33% 20% 10%

or 2.5 mm [0.0984 in], whichever is smaller, is acceptable.

To accept. 3.3.4 The connection plate is lifted. Perform a visual inspection according to Section 3.3.

When delivering the flexible printed circuit board (without thermal stress test)
3.3.3 Plating and coating inside holes Plating and coating inside holes
There should be no raised lands on the connector.
The coating voids shall not exceed the allowable range in Table 3-6.

Table 3-6 Visual inspection of voids in plating and coating layers

Material Level 1 Level 2 Level 3

Copper plating In no more than 10% of the wells, each In no more than 5% of the wells, each No holes allowed

Three cavities are allowed in the hole One void is allowed in the hole

Final coating In no more than 15% of the wells, each In no more than 5% of the wells, each In no more than 5% of the wells, each

5 cavities are allowed in the hole Three cavities are allowed in the hole One void is allowed in the hole

Note 1. For Class 2 products, copper plating voids shall not exceed 5% of the hole length. For Class 1 products, copper plating voids shall not exceed 10% of the hole length. Annular voids shall not exceed 1/4 of the circumference (90°).

NOTE 2: For Class 2 and Class 3 products,

, the coating voids shall not exceed 5% of the hole length. For Class 1 products, the final coating voids shall not exceed 10% of the hole length. For Class 1, Class 2, or Class 3 products, if ,

The annular cavity should not exceed 1/4 of the circumference (90°).

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3.3.5 Marking. If required, each individual flexible printed board, qualification The time to wet the metal hole wall and the top of the pad will also increase.

flexible printed board, and each set of circuits used for quality conformance testing

(as opposed to individual coupons) shall be marked. Marking is required to ensure

NOTE: Accelerated aging (steam aging) is applicable only to tin/lead, tin/lead
traceability between the flexible printed board and the test circuits and the
solder, or tin finishes and not to other final finishes.
manufacturing history, and to identify the supplier (e.g., trademark). If size and

space limitations prevent marking on individual flexible printed boards, marking

3.3.7 Plating Adhesion • Plating adhesion of flexible printed boards shall be tested
may be applied to the packaging or label.
in accordance with IPC-TM-650 Test Method 2.4.1 by applying a strip of pressure-

sensitive tape to the plating surface and then manually pulling it perpendicular to

Markings shall be made using the same ink or paint used to produce the conductor the circuit pattern.

3.2.10), , pattern or using a permanent anti-mold ink or paint (see Process

There should be no evidence of any detachment of the protective plating or
a laser marking device, or a vibrating pen on the metal area used for marking or a
conductor pattern
, foil. This is manifested by particles of the plating or pattern foil
permanent attached label.
adhering to the tape. If a plating protrusion (plating shavings) breaks off and adheres

to the tape, it only indicates the presence of a plating protrusion or plating

Conductive markings, either etched copper or conductive ink (see 3.2.10), shall be shavings, not a failure of the plating adhesion.

considered electrical components of the circuit and shall not compromise electrical
3.3.8 Exposed copper/plating overlap between the solder coating and gold plating
spacing requirements. All markings shall be compatible with the materials and
at the junction of the plating and solder coating on printed board edge contacts

components, legible for all tests, and in no way affect the performance of the flexible shall comply with the requirements of Table 3-7. Exposed copper/plating or gold

printed board.
overlap may appear discolored or gray-black and is acceptable (see Section 3.5.4.4).

Markings shall not cover lands that require soldering (see IPC-A-600 for legibility

, above markings.
requirements). Bar code markings are permitted in addition to the Table 3-7 PCB edge contact clearance

Minimum exposed copper gap The most plating overlap

When date codes are used, their format shall be determined by the supplier to

establish traceability to the date the production operation was completed.

Level 1 2.5 mm [0.0984 in] 2.5 mm [0.0984 in]

Level 2 1.25 mm [0.04921 in] 1.25 mm [0.04921 in]

Level 3 0.8 mm [0.0315 in] 0.8 mm [0.0315 in]

3.3.6 Solderability: Only flexible printed boards that will be soldered during post-
3.3.9 Process Quality Flexible printed boards shall be processed to a uniform
assembly operations require solderability testing. Printed boards not intended for
quality and free of visible dust, foreign matter, grease, fingerprints, transfer of tin-
soldering, such as those using press-fit components, do not require solderability
lead or solder to the dielectric surface, flux residue, and other contaminants that
testing. Such requirements should be specified on the master layout drawing.
could affect life, assembly, and usability. When metallic or non-metallic semi-
Flexible printed boards intended for surface mount applications do not require
conductive coatings are used, visible darkening of non-plated-through holes is not
solderability testing of plated-through holes.
considered foreign matter and does not affect the life or function of the printed

When required by procurement documentation, accelerated aging of coating

board. Flexible printed boards shall be free of defects beyond those permitted by

durability shall comply with the requirements of J-STD-003. The durability type shall
this specification. There shall be no separation of the plating from the conductor

be specified on the general layout drawing. However, if not specified, Category 2

pattern or the conductor from the substrate beyond the permitted limits. The flexible

shall be used, meaning accelerated aging of coating durability is not required. If printed board surface shall be free of loose plating chips.

required, test specimens shall be preconditioned and evaluated for surface and

hole solderability in accordance with J-STD-003.

For Class 1 and 2 products, fragments of coverlay or covercoat adhering to exposed

adhesive shall be acceptable if they do not fall off when rubbed with an isopropyl-

When solderability testing is required, the thickness of the flexible printed circuit coated device; for Class 3 products, there shall be no visible material adhering to

board and the copper thickness should be considered. If both increase, then the sufficient the adhesive.

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3.4 Dimensional Requirements Unless otherwise agreed upon between the purchaser However, in the event that any element is not specified in the procurement documents,

and supplier, verification of printed board dimensional requirements shall comply with the applicable IPC-2220 design series specifications shall apply.

the provisions of this section. Flexible printed boards shall conform to the dimensional

requirements specified in the procurement documentation. All dimensional

Nodules or rough plating in plated-through holes shall not reduce the hole diameter

characteristics, including, but not limited to, the shape, thickness, cutouts, notches,
below the minimum limit specified in the procurement documentation.

holes, notches, and printed board edge contacts that contact critical connector areas,
3.4.2 Annular Rings and Hole Breakouts (External) The minimum external annular
shall conform to the specifications of the procurement documentation. However, if the
ring width shall comply with the requirements of Table 3-8. The external annular ring
procurement documentation does
, not specify dimensional tolerances, the element
width is measured from the inside surface (inside the hole) of the plated-through or
tolerances of the appropriate IPC-2220 design series specifications shall apply.
unsupported hole to the edge of the annular ring on the printed board surface, as
Dimensional positioning of printed boards with datum or bidirectional tolerances
at the, conductor/land
shown in Figure
junction,
3-4. Ifand
a hole
the breakout
plated-through
occurs,
hole
it should
shouldnot
comply
occurwith the
,
specified in the procurement documentation shall be verified using the AQL levels specified in Table 4-3.
requirements of Sections 3.6.2.1 and 3.6.2.2. Printed boards with hole breakouts

Automatic detection techniques are allowed. should meet the electrical requirements of Section 3.8.2 (see Figures 3-5 and 3-6). For

,
Class 1 and Class 2 products, the use of fillet or "teardrop land" to add additional
The supplier may reduce the accuracy of the inspection elements if they can provide a
land area at the conductor junction is acceptable unless prohibited by the customer and
documented method and demonstrate their production capability to meet the specified
shall comply with the general requirements for lands with holes in IPC-2221. For Class
requirements. The supplier may provide proof of accuracy based on a sampling plan
3 products, the use of fillet or "teardrop land" shall be determined by agreement
that includes a method for collecting and recording process data.
between the supplier and the purchaser.

When the supplier does not have a process certification system for dimensional

accuracy, the AQL levels in Table 4-3 should be used to inspect each batch of products.
3.4.2.1 Solderable Anvil (External) Adhesive squeeze-out, solder mask misregistration,

and/or coverlay pads are permitted; however, the minimum solderable annular ring

3.4.1 Aperture, Hole Pattern Accuracy, and Pattern Element Accuracy The tolerances for shall meet the requirements in Table 3-9. When inspected in accordance with Section

aperture, hole pattern accuracy, and element positioning accuracy shall comply with the 3.3, the annular ring for external layers is measured from the inside surface (inside the

requirements of the procurement documents. hole) of the plated-through hole or unsupported hole to the edge of the annular ring

on the surface of the flexible printed board. If annular ring failure occurs, it shall not
The final hole diameter tolerance shall be verified on a sampling basis for all hole
occur at the conductor/land junction, and the plated-through hole shall meet the
diameters applicable to the design. The number of measurements for each hole diameter
requirements of Sections 3.6.2.1 and 3.6.2.2.
shall be determined by the manufacturer to adequately sample a sufficient number of

holes in the total number. 3.4.2.1.1 Permissible Tangency of Solderable Angle Rings Some flexible printed

boards are designed with solderable annular rings on only one side of the hole. For
Holes of specified size, including both non-plated-through and plated-through, holes,
example, some Type 1 and Type 5 flexible printed boards are manufactured with double-
should be inspected for hole pattern accuracy to meet the printed board dimensional
sided clearance (bare back). They rely on a coverlay or backing material to secure the
requirements of Section 3.4. Unless otherwise specified on the master drawing, holes
lands to the flexible printed board. As shown in Figure 3-7, such boards are designed
of unspecified size, such as plated-through holes and vias, do not need to be inspected
with a smaller clearance opening (smaller clearance) on the component side of the
for hole pattern accuracy because their locations are provided by the database and
unsupported hole and a larger clearance opening (larger clearance) on the solder side
controlled by the annular ring requirements for surface or internal lands. If required on
of the unsupported hole. Other similar flexible printed board designs may restrict the
the master drawing, hole pattern accuracy can be demonstrated by a qualification report
clearance hole diameter to minimize solder capacity or maximize dielectric spacing
or by sampling according to the AQL requirements of Section 3.4.
between holes. Unless otherwise specified in the procurement documentation,

The accuracy of graphic elements shall comply with the provisions of the procurement documents. solderable annular rings with smaller clearance openings must maintain at least 360°

The accuracy of graphic elements can be proved by the appraisal report or in accordance with Section 3.4. tangency.

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Table 3-8 Maximum Ring Width 1

characteristic Level 1 Level 2 Level 3

When the outer layer plated-through holes are evaluated by visual inspection, the hole When assessed by visual inspection, the hole on the The minimum ring width should be 50 ÿm [1,970

damage on the connection land is not greater than 180°. connecting pad is allowed to be broken by no more than ÿ in].

90° and there is a 50 ÿm [1,970 ÿin] hole ring over at least

The reduction at the land/conductor junction shall be In isolated areas, due to defects such as pits, dents,
2
270° of the circumference.
less than the width reduction allowed in 3.5.3.1. notches, pinholes or oblique holes, the minimum outer

The reduction in width at the land/conductor junction ring width may be reduced by an additional 20% of

shall be less than the width reduction allowed in Section the minimum ring width.

3.5.3.1. The land/conductor junction shall not be less

than 50 ÿm [1,970 ÿin] or less than the minimum

conductor width, whichever is less. Hole breakouts

Internal layer plated-through holes are permitted to have hole breakouts as long as within 90° are permitted as long as the reduction in width The minimum ring width of the inner layer should be 25 ÿm [984

the reduction at the land/conductor junction is below the at the land/conductor junction is less than the width ÿ in].

width reduction limit allowed in Section 3.5.3.1. reduction allowed in Section 3.5.3.1. Hole breakouts on

lands shall not

When the outer layer unsupported hole is assessed by visual inspection, the connection plate exceed 90° when evaluated by visual inspection. The minimum ring width should be 150 ÿm [5,906

2 2
The hole on the ring should not be broken more than 90°.
ÿ in].

The width reduction at the land/conductor junction shall The reduction at the land/conductor junction shall be In isolated areas, due to defects such as pits, dents,

be less than the width reduction allowed in 3.5.3.1. less than the width reduction allowed in 3.5.3.1. notches, pinholes or oblique holes, the minimum outer

ring width may be reduced by an additional 20% of

the minimum ring width.

Note 1. Land breakout and conductor width reduction on lands are shown in Figures 3-5 and

3-6. Note 2. Minimum lateral conductor spacing should be maintained. Examples of land breakout and conductor width reduction on lands are shown in Figures 3-5 and

3-6. Note 3. See Section 3.6.2.10 for annular ring width requirements for functional and nonfunctional lands.

IPC-6013b-3-04-cn IPC-6013b-3-05-cn

Figure 3-4 Ring width measurement (outer layer) Figure 3-5 90° and 180° destruction

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IPC-6013B January 2009

3.4.2.2 Coverlay Adhesive Extrusion and Covercoat Bleeding As shown in Figure

3-8, coverlay adhesive extrusion (j) or covercoat bleed-out on the metal foil

surface shall meet the requirements of Table 3-9. As shown in Figure 3-8,

the minimum solderable ring width (k) in the pad area shall meet the requirements

of Table 3-10.

IPC-6013b-3-06-cn

Figure 3-6 Reduction of conductor width

Table 3-9 Allowable values for cover layer

adhesive extrusion and cover coating seepage

For metal foils 70 ÿm [2,756 For metal foils above 70 ÿm

grade ÿin] and below [2,7 56 ÿin]

ÿ0.5mm[0.0197in] or determined by

Grade 1 and 2 ÿ 0.3 mm [0.0118 in] negotiation

between the supplier and

the buyer ÿ0.4mm[0.0157in] or

Level 3 ÿ0.2mm[0.0079in] determined by

negotiation between the supplier and the buyer

IPC-6013b-3-08-cn

Figure 3-8 Cover film adhesive squeeze out and cover coating oozing out

Table 3-10 Maximum solder ring width of pad area

grade Weldable ring width

Class 1: Solderable annular ring for at least 240° of

circumference; 50 ÿm [1,970 ÿin] solderable annular ring for at

Level 2
least 270° of

circumference; 50 ÿm [1,970 ÿin] solderable annular ring for

Level 3
360° of circumference

NOTE: Missing or missing material is permitted within the adhesive extrusion area

at the edge of the cover layer as shown in Figure 3-9. These areas are not

required to be surface coated but ,shall comply with the requirements of Section

3.5.4.7.

IPC-6013b-3-07-cn 3.4.2.3 Stiffener Clearance Holes The overlap of the stiffener and the flexible

printed wiring shall not reduce the outer annular ring below the value specified in
Figure 3-7: Tangent clearance holes allowed for larger and smaller clearance holes in flexible printed circuit boards

3.4.2.

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80% of the pattern width. When not specified on the master drawing, the

minimum conductor thickness shall comply with the requirements of Sections

3.6.2.13 and 3.6.2.14.

3.5.2 Conductor Spacing Conductor spacing shall be within the tolerances specified on the

master layout drawing. The minimum spacing between conductors and the edge of the

flexible printed board shall comply with the specifications on the master layout drawing. The

allowable reduction in the minimum conductor spacing in isolated areas is shown in Table 3-11.

Table 3-11 Conductor Spacing Requirements

For Class 1 Level

and Class 2 , the minimum conductor 3: Due to rough conductor edges

IPC-6013b-3-09-cn

spacing can be reduced by 50% and burrs, the minimum

Figure 3-9 Missing or missing material within the adhesive extrusion at the edge of the coverlay
due to rough conductor edges, burrs, etc. conductor spacing can be reduced by 20%.
1.

Coverlay 2.

Conductor with clearance land 3. If no minimum spacing is specified, the

, nominal conductor spacing shown in the
Edge of the clearance hole after coverlay
engineering documentation shall be reduced due to processing, which shall be
addition 4. Coverlay adhesive

extrusion 5. Peeling or missing adhesive extrusion 20% for Class 3 product

, and 30% for Class 1 and Class 2 product (the ,

minimum finished product spacing requirements stated previously still apply)

3.4.3 Bow and Twist (Rigid or Stiffener Portions Only) Unless otherwise specified
(see Figure 3-10).
in the procurement documentation, the maximum bow and twist of the rigid or

stiffener portion of a flexible printed board designed in accordance with

IPC-2221 and IPC-2223 shall be 0.75% for boards intended for surface mount

components and 1.5% for other printed boards. Bow and twist requirements

for products panelized for assembly shall be determined by agreement between

the purchaser and supplier.

Bow, twist, or a combination thereof should be physically measured and the

percentage calculated in accordance with IPC-TM-650 Test Method 2.4.22,

which consists of four steps for measuring bow and twist of cut-to-size in-process

or finished flexible or rigid-flex printed boards, including single-sided, double-

sided, and multilayer boards.

3.5 Conductor Accuracy: All conductive areas on flexible printed boards, including ,

conductors, lands, and conductive layers, must meet the visual inspection and dimensional
IPC-6013b-3-10-cn

requirements specified in Sections 3.5.1 through 3.5.4.8. Conductor patterns must Figure 3-10 Excess copper between conductors and conductor nodules

conform to the procurement documentation. Dimensional characteristics must be verified

in accordance with IPC-A-600. Automated Optical Inspection (AOI) inspection methods 3.5.3 Conductor Defects The conductive pattern shall be free of cracks, splits,

are permitted. Internal layer conductors must be inspected prior to lamination and during
or tears. The conductor geometry is defined as its width × thickness × length.

the internal layer manufacturing process.

Any combination of defects specified in Sections 3.5.3.1 and 3.5.3.2 that reduces

the conductor's equivalent cross-sectional area (width × thickness) by no ,

3.5.1 Conductor Width and Thickness When the general layout drawing does not specify, the more than 20% of the minimum value (minimum width × minimum thickness) for

minimum conductor width shall be the conductor width provided in the procurement documents. Class 2 and Class 3 products; or no more than 20% for Class 1 products.

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The sum of the lengths of defective areas on a conductor shall not The surface mount pad's "good area" is defined as 80% of the pad's

exceed 10% of the conductor length or 25 mm [0.984 in] for Class 1 center width multiplied by 80% of its length, as shown in Figure 3-11.

and 13 mm [0.512 in] for Class 2 and Class 3, whichever is less. , For Class 2 and 3 products, defects within the pad should not exceed

10% of the pad's length or width. For Class 1 products, defects within

the pad,should not exceed 20% of the pad's length or width, and

defects within the pad should be located outside the surface mount
3.5.3.1 Reduction in Conductor Width. Reductions in the minimum pad's "good area." For Class 1, 2, and 3 products, one visible ,
conductor width (specified or derived) due to misalignment or isolated
electrical test probe mark is permitted within the "good area."
defects that expose base material (e.g., conductor edge roughness,

nicks, pinholes, or scratches) shall not exceed 20% of the minimum

conductor width for Class 2 and 3 product and 30% of the minimum ,

conductor width for Class 1 product.

Note: Because the allowable reduction in conductor width is based on the

customer's original drawing design, manufacturers must understand their own

etching capabilities and add production compensation to the customer's original

drawing design during pre-processing (CAM) design.

3.5.3.2 Reduction in Conductor Thickness The allowable reduction in

minimum conductor thickness due to isolated defects (such as rough

edges, nicks, pinholes, or scratches) shall not exceed 20% of the

minimum conductor thickness for Class 2 and Class 3 products; and

Class
, 1shall
products.
not exceed 10% of the minimum conductor thickness for IPC-6013b-3-11-cn

30%. Figure 3-11 Rectangular surface mount connection pad

3.5.4 Conductor table?

3.5.4.2.2 Circular Surface Mount Pads (BGA Pads) For Class 1, 2, or 3

product, defects such as nicks, dents,

, and pinholes along the pad ,
3.5.4.1 Gaps and Pinholes in Ground or Power Planes For Class 2 and Class 3
edge shall not exceed 10% of the pad diameter radiating radially from
products, gaps and pinholes in ground or power planes shall be permitted if their
the center of the pad. Furthermore, these defects shall not exceed 20%
longest dimension is not greater than 1.0 mm [0.0394 in] and the maximum
of the pad circumference for Class 2 or 3 product, or 30% of the pad
2 2
dimension is within 625[96.88in
cm per side. ] is acceptable; for Class 1 products,
circumference for Class 1 printed boards, as shown in Figure 3-12. The
the longest dimension shall not exceed 1.5 mm [0.0591 in] and no more
defect-free area, centered at the midpoint of the pad diameter, shall be
2
than 6 locations shall be within an area of 625 cm2 [96.88 in] per ]
80% of the pad diameter. For Class 1, 2, and 3 product, one visible
side .
electrical test probe mark is permitted within the intact area.

3.5.4.2 Solderability Table Mounting lands shall not have defects

along the edge or within the land area exceeding the requirements of

3.5.4.2.1 and 3.5.4.2.2. 3.5.4.3 Metal Wire Bond Pads (WBP) Metal wire bond pads shall have

a final conductive coating of electroplated gold or electroless nickel/

3.5.4.2.1 Rectangular surface mount lands. Defects along the outer immersion gold (EIG) for ultrasonic bonding (GWB-1) and hot bonding

edge of the land, such as nicks, dents, pinholes, etc., shall not exceed (GWB-2) as specified in Section 1.3.5.3, or as specified in the

20% of the land length or width for Class 2 and 3 products; and 30% procurement documentation. The final coating thickness shall conform

for Class 1. Defects shall not encroach upon the land width. to the applicable coating requirements in Table 3-2.

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3.5.4.5 Dewetting For tin, tin-lead reflowed, or solder coated surfaces,

dewetting on conductors, solder connection areas, and ground or power

planes is permitted as follows:

a) Permitted for all grades on conductors and layers not intended for solder

connections.

b) Individual weld connection areas: Level 1 - 15%; Level 2 - 5%; Level 3 -

5%.

3.5.4.6 Nonwetting Nonwetting shall not occur on any conductive surface

where a solder connection is required, for tin, tin-lead reflowed, or solder

coated surfaces.

IPC-6013b-3-12-cn
3.5.4.7 Final Coating Coverage (Termination Area) The final coating shall

Figure 3-12 Round surface mount connection pad meet the solderability requirements of J-STD-003. For Class 1, 2, and 3

products, 5% exposed copper

, is permitted outside the termination area or
The intact area of the bond pad shall be the area within 80% of the length
areas requiring solder fillet. Coverage does not apply to vertical edges of
and 80% of the width of the pad centered on the wire bond pad as shown in
conductors.
Figure 3-11.
, The maximum surface roughness of the intact area of the wire

bond pad shall be measured according to the test method agreed upon by
3.5.4.8 Conductor Edge Plating Width When printed boards are solder coated
the supplier and the purchaser and shall be 0.8 ÿm [32 ÿin].
or tin-lead plated and heat-fused and , According to IPC-TM-650

RMS (Root Mean Square). If using IPC-TM-650 Test Method 2.4.15, it is tested in accordance with Test Method 2.4.1 (see IPC-2221), there shall be
recommended that the roughness sampling width defined in that method
, be
no plating width increase at the conductor edges.
adjusted to approximately 80% of the maximum length of the wire bond pad

to obtain the RMS value within the intact area. The intact area should be 3.6 Structural Integrity Flexible printed boards shall meet the structural

free of indentations, nodules, scratches, visible electrical test probe marks, integrity requirements for thermal stress (after solder float) evaluation

or other defects that violate the 0.8 ÿm [32 ÿin] RMS roughness requirement. coupons specified in Section 3.6.2. Although coupons A and B or A/B are

For more information on surface roughness, see specified for this test, production printed boards may be used in place of

ASME B46.1. coupons A and B or A/B. The production printed boards should preferably

contain surface mount pads

, and vias, or a mix of surface mount and through-
3.5.4.4 Printed Board Edge Connector Lands. Except as provided below, flexible
hole technology. The holes selected should be equivalent to those specified
printed board edge lands plated with gold or other precious metals shall be free
for the quality conformance test coupons. Microsections from the production
of the following phenomena in the plugging and unplugging areas or contact areas:
printed boards should be taken from opposite corners of the production

a) Cuts or scratches that expose the underlying nickel or board, including the X and Y axes.

copper. b) Exposed solder or tin-lead

Flexible finished boards and all other coupons containing plated-through
plating. c) Nodules or metal bumps that protrude from the surface.
holes in quality conformance test circuits shall meet the requirements of this

The longest dimension of pits, dents or indentations shall not exceed 150 ÿm section. Structural integrity shall be evaluated by microsectioning of test

acceptable provided No more than three defects per land [5,910 ÿin] are , specimens of Type 2 through Type 4 flexible printed boards. Features that do

that no more than 3 defects occur on more than 30% of the lands. These not apply to Type 2 flexible printed boards (such as requirements for inner

defect limits do not apply to the 150 ÿm [5,910 ÿin] wide edge area layer separation, inner layer inclusions, and inner layer copper cracks) are

surrounding the land including the contact area. not evaluated. Dimensions that can only be measured by using microsectioning

techniques are also specified in this section. Blind and buried vias shall be

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IPC-6013B January 2009

For proper design of blind and buried via test coupons for plated-through hole The integrity of the copper foil and plating of plated-through holes shall be

qualification, refer to IPC- inspected at 100X ± 5% magnification. Referee inspection shall be completed at

2221. 200X ± 5% magnification. Each side of the hole shall be inspected separately.

Inspection of laminate thickness, copper foil thickness, plating thickness, layup

All properties and requirements shall be evaluated on coupons that have been
orientation, lamination, and plating voids shall be completed at the magnification
thermally stressed and shall meet all requirements. However, at the ;
specified above. For foils less than 3/8 oz, a higher magnification may be
supplier's option, some of the properties or conditions listed below may be
required to determine compliance with the minimum thickness requirements.
evaluated on coupons that have not been thermally stressed.
Plating thicknesses less than 1.0 ÿm [39.4 ÿ]in shall not be measured using
? Copper plating voids
metallographic techniques.
? Coating folds/inclusions

? Burrs and nodules

NOTE: Other techniques used to supplement the evaluation of microscopic sections should be determined by

? Fiberglass protrusion
agreement between the supplier and the purchaser.

? Wicking
3.6.2 Requirements for Microsectioned Coupons or Production Boards When
? Final coating voids
inspected by microsectioning, coupons or printed boards shall conform to the

? Etching requirements of Table 3-12 and 3.6.2.1 through 3.6.2.18.

? Negative etchback
3.6.2.1 Plating Integrity The plating integrity of plated-through holes shall meet
? Plating/coating thickness
the requirements of Table 3-12. For Class 2 and Class 3 products, there shall

? Inner and surface copper layer or metal foil thickness be no plating separation (except as noted in Table 3-12), plating cracks, and no

? Lamination (rigid part) separation

, or contamination at the internal interconnection between the plated-

through hole wall and internal layers.

? Angle ring

When copper cores or heat sinks are used for electrical functional circuits, the
3.6.1 Thermal Stress Specimens should be preconditioned by baking at 120 to
above requirements must be met. However, when different materials are used
150°C [248 to 302°F] for at least 6 hours to remove moisture. Thicker or more
to make the cores or heat sinks, spots or pitting may occur between the metal
complex specimens may require longer baking times. After preconditioning, cool
and the hole wall plating. When microsections are evaluated, the area of these
the specimens to room temperature on a ceramic plate in ,a desiccator. Unless
contamination or inclusions should not exceed 50% of the area of each
otherwise specified in the purchase documentation, thermal stress testing shall
interconnection and should not appear at the interface between the copper foil
be conducted in accordance with IPC-TM-650, Test Method 2.6.8, Test
layer on the metal core and the copper plating on the hole wall.
Condition A (289°C [552°F]) for [F] specimens, except that polyester flexible

products shall be tested in accordance with Test Condition C. 3.6.2.2 Plating Voids Any copper plating thickness less than the minimum

(235°C [455°F]). thickness specified in Table 3-2 shall be considered voids. Class 1 product shall

comply with the plating void requirements established in Table 3-11. For
After thermal stress testing, the test coupon or flexible printed board should be
Class 2 and Class 3 product, there
, shall be no more than one void per coupon
microsectioned. Microsectioning should be performed on the test coupon or
or finished board and the following requirements must be met:
flexible printed board in accordance with IPC-TM-650 Test Method 2.1.1 or
a) There shall be no more than one plating void per test coupon or production
2.1.1.2. Evaluation of all applicable plated-through holes and vias, including blind
printed board, regardless of length or size.
and buried vias and similar structures found on the finished printed board, should

be inspected on vertical sections in accordance

, with Table 4-3. The sections b) There should be no plating voids whose length exceeds 5% of the total thickness of the

flexible printed board.

should be ground and polished to an accuracy that allows the observation area

of each plated-through hole to be within 10% of the drilled hole diameter. c) The interface between the inner conductive layer and the plated hole wall should not

There are plating voids.

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January 2009 IPC-6013B

Table 3-12 Plated-through hole integrity after thermal stress

property Level 1 Level 2 Level 3

Three cavities are allowed for each hole.

Multiple cavities are not allowed on the same plane. One void is permitted per specimen provided One void is permitted per specimen provided

Copper plating voids The length of the cavity should not be greater than 5% of the other microsectioning requirements of the other microsectioning requirements of

the thickness of the flexible printed circuit board. Not allowed Section 3.6.2.2 are met. Section 3.6.2.2 are met.

There are annular cavities greater than 90°.

The minimum copper thickness requirements in Table 3-2 must be met. For positive etchback, the measurement should be made along the topography of the dielectric

Coating folds/inclusions material. When negative etchback causes folding of the copper plating, the copper thickness measured from the inner layer should meet the minimum requirements. ;

And it should not exceed the limit of negative etchback allowed, see Figure 3-18. , The sample must be microetched.

Burrs 1 and nodules Allowed if minimum aperture requirements are met. Must meet minimum copper thickness requirements in Table 3-2.

Glass fiber protrusion 1 Allowed if minimum aperture requirements are met. Must meet minimum copper thickness requirements in Table 3-2.

wicking (maximum electroplated copper Maximum allowable sectioning requirements, Maximum allowable sectioning requirements, Maximum allowable sectioning requirements, Maximum allowable

penetration including etch back allowable value sectioning requirements,

80ÿ m [315 ÿ in]) Wicking 205 ÿm [8,070 ÿin] Maximum 180 ÿm [7,090 ÿin] Maximum 160 ÿm [6,300 ÿin] Maximum

(maximum electroplated copper allowable if other microsectioning requirements allowable if other microsectioning requirements allowable if other microsectioning requirements

penetration including desmear allowable value of Section 3.6.2.9 are met in Section 3.6.2.9 are met in Section 3.6.2.9 are met

50ÿm [197ÿin]) Inner layer 175 ÿm [6,890 ÿin] Only one 150 ÿm [5,910 ÿin] 130 ÿm [5,120 ÿin]

inclusions (inclusions at the interface

between the inner layer land and the 20% have impurities, and the impurities can only Not allowed

plated-through hole) appear on one side of the hole wall

as long as the crack does not penetrate the metal, foil

Inner copper foil cracks 2 It is allowed to have only one side of the hole wall Not allowed

"C" crack

2
Cracks in outer copper foil
No "D" cracks are allowed , Type "D" and "B" cracks are not permitted ,
(Types “A”, “B”, and “D” cracks)
Type "A" and "B" cracks Type “A” cracks allow
Hole wall/

corner cracks2 (Types “E” and “F”

Not allowed
cracks) Inner layer separations

(separation at the interface between 20% of each effective land is allowed to have

the inner layer land and the plated- inner layer separation, and it can only appear on Not allowed

one side of the land hole wall

through hole) Separation along the

This separation is permitted provided it does not extend beyond the vertical edge of the outer copper foil (see Figure 3-13).
vertical edge of the outer layer land

Corner length is allowed, the maximum length is

Plating separation Not allowed
130 ÿm [5,120 ÿin] Acceptable if

Hole wall dielectric/hole wall plating dimensional and coating requirements are met

separation thermal stress or pad lift after

If the finished flexible printed board meets the visual inspection requirements of Section 3.3, it is allowed
simulated rework

Note 1. Measured from the protruding end to the inside

of the hole. Note 2. Definition of copper foil crack: See Figure 3-14.

"A" type crack = crack in outer copper foil

Type “B” cracks = cracks that do not completely penetrate the plating (minimum plating thickness still remains) Type “C”

cracks = cracks in the inner copper foil

"D" crack = crack in the outer copper foil and plating that penetrates completely through the copper foil and plating

"E" cracks = cracks that appear only in the hole plating

"F" crack = crack that only appears in the corner plating

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IPC-6013B January 2009

Resample according to Table 4-2 to determine whether the defect

occurs randomly. If there are no plating voids in the resampled test

coupons or finished printed boards, the printed boards represented by

the test coupons or finished printed boards are considered acceptable;

however, if one plating void is found in the resampled microsection, the

product should be considered non-compliant.

3.6.2.3 Flexible Section Laminate Integrity For Class 1, Class 2, and

Class 3 flexible printed boards, adhesive voids shall not exceed 50

ÿm [197 ÿin] in Area B (see Figure 3-15). Boundary voids/cracks that

bridge Areas A and B shall not exceed 50 ÿm [197 ÿin]. The cumulative

length of multiple voids on the same layer between adjacent plated-

through holes shall not exceed the above limits.

3.6.2.4 Rigid Section Laminate Integrity: Substrate voids/cracks within

Area A (Figure 3-15) are acceptable. Substrate voids/cracks that

bridge Areas A and B or are entirely within Area B shall not ,

IPC-6013b-3-13-cn
exceed 80 ÿm [3,150 ÿin] for Class
, 2 and Class 3 product and 150 ÿm
Figure 3-13 Separation of outer copper foil
[5,906 ÿin] for Class 1 product., The cumulative length of multiple voids/

cracks between two adjacent plated-through holes on the same layer

shall not exceed the above limits. Cracks between two non-common

conductors, whether horizontally or vertically, shall not reduce the

minimum dielectric spacing.

3.6.2.5 Delamination or Blistering For Class 2 and Class 3 product, there shall be

no delamination or blisters. For Class 1 product, if delamination is present, evaluate

of Section , the entire printed board or blisters according to the requirements

3.3.2.3.

3.6.2.6 Etchback (Type 3 and Type 4 only) When specified on the

master drawing, flexible printed boards shall be etched back to remove

, resin and/or glass fibers from the sides of drilled holes before

plating. Etchback shall be between 5 ÿm [197 ÿin] and 80 ÿm [3,150 ÿin],

IPC-6013b-3-14-cn

with an optimum etchback depth of 13 ÿm [512 ÿin], as shown in Figure

Figure 3-14 Definition of cracks

3-16. Etchback shadowing is permitted on one side of each land.

d) Annular plating voids greater than 90° are not permitted. The When etchback is not specified and the printed board manufacturer

conductor final plating or coating material between the substrate and the elects to use etchback, the manufacturer shall demonstrate qualification

copper plating (e.g. after copper plating on the hole wall) is considered a void. of the etchback by qualification of test coupons or production boards.

During the inspection of the board, any plated-through hole with such a NOTE: Due to the variety of materials used in rigid-flex printed circuit board

condition shall be counted as a void. If a void is found during microsectioning construction, varying degrees of etchback can be expected for different

to meet the above conditions, it shall be removed from the same inspection batch. materials in the finished printed circuit board.

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NOTE 1. The heated zone is defined as the area extending 80 ÿm [3,150 ÿin] into the laminate from the outermost land edge on an inner or outer layer. NOTE 2.

Laminate and adhesive anomalies or defects (e.g., substrate voids, adhesive voids, substrate cracks, delamination/blistering, etc.) within Zone B after thermal stress or simulated rework should be evaluated in

accordance with Sections 3.6.2.3 and 3.6.2.4.

Note 3. After thermal stress or simulated rework, except for voids on the dividing , Laminate or adhesive anomalies occurring within Area A of the specimen shall not be evaluated.

line, Note 4. After thermal stress or simulated rework, laminate anomalies or defects in non-evaluation areas of the sample will not be evaluated.
IPC-6013b-3-15-cn

Figure 3-15 Typical microsection evaluation sample

Lateral removal of resin greater than 25 ÿm [984 ÿin] shall not occur. Random

tears or small areas of gouges exceeding 25 ÿm [984 ÿin] in depth shall not be

evaluated for smear removal. Smear removal is not required for Type 1 or Type 2

printed boards (see Figure 3-17).

IPC-6013b-3-16-cn

Figure 3-16 Allowable depth of etch back

The adhesive-free structure exhibits minimal etchback at the flexible dielectric to

metal interface.

NOTE: Etchback greater than 50 ÿm [1,970 ÿin] may cause plating folds or voids,

which may result in copper thickness not meeting requirements.

3.6.2.7 Desmearing (Type 3 and Type 4 Plates Only) Desmearing is the removal IPC-6013b-3-17-cn

of resin debris generated during hole formation. Desmearing shall adequately meet Figure 3-1 7 Decontamination allowance

the acceptability requirements for plating separation in Table 3-12.

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IPC-6013B January 2009

3.6.2.8 Negative Etchback When measured as shown in Figure 3-18, negative etchback
,

shall not exceed the dimensions specified in Figure 3-18. If etchback is specified in the

procurement documentation, negative etchback shall not be present. When negative

etchback results in copper plating folds or inclusions, the copper thickness measured

Figure , from the inner surface shall meet the minimum requirements, as shown in

3-19.

NOTE: In Figure 3-18, the dimension “X” describes the most common negative etchback

amount for inner layer copper foil (70%-80% of total thickness).

IPC-6013b-3-19-cn

Figure 3-19 Coating Folds/Inclusions 1. The

lowest copper thickness measurement point. If the fold at this location is not closed, it is unacceptable.

of.
2. Closed folds (inclusions) are acceptable if the minimum thickness requirement is met
of.
3. Measure the copper plating between the plating intersection lines in the sandwich area (must meet the minimum

local area thickness requirements).

Measure the inner annular ring width, as shown in Figure 3-20, to verify compliance of

the inner annular ring with Table 3-8. The inner annular ring width is measured from the

inside of the drilled hole to the edge of the inner land, as shown in Figure 3-20.

Evaluate negative etchback in accordance with Section 3.6.2.8 and Figure 3-18. Via

IPC-6013b-3-18-cn
external lands in sequentially laminated structures may be evaluated prior to the next

Figure 3-18 Negative etchback

lamination (see Section 3.4.2). The evaluation of sequentially produced via compliance

during the process should be documented. When microsectioned, lands not connected
3.6.2.9 Wicking (Electroplated Copper) When etchback is specified on the master
to the sequentially laminated via structure should be considered for inner annular
drawing, the maximum electroplated copper penetration measured from the edge of the
ring evaluation. Perform microsection analysis in accordance with Section 3.6.2. Unless
drill hole shall not exceed the values specified in Table 3-12, which is the sum of the
prohibited by the customer, the use of fillet or "teardrop" lands to create an additional
allowable values for electroplated copper wicking and etchback, as shown in Figure
land area at the conductor connection is acceptable for Class 1 and Class 2 products
3-16, or reduce the minimum conductor spacing below the minimum requirements in
and should comply with the general requirements for lands with holes as detailed in
Section 3.5.2. See Section 3.6.2.10.1 for minimum conductor spacing.
IPC-2221. For Level 3 products, the use of fillet or "teardrop" trays shall be determined

When etchback is not specified on the master drawing (drill smear removal only), the
by negotiation between the supplier and the purchaser. ,

maximum copper plated penetration measured from the edge of the drill hole shall not

exceed the values specified in Table 3-12, which are the sum of the allowable values for

electroplated copper wicking and drill smear removal (see Figure 3-17), or shall not NOTE: Due to conductor routing spacing limitations, printed board designs may have

non-functional lands of varying sizes.

reduce the minimum conductor spacing below the minimum requirements of Section

3.5.2.
Functional connection disks shall meet the minimum hole ring requirements. Non-functional

3.6.2.10 Hole Rings and Hole Breakouts (Inner Layer) If there is no alternative technology agreed connection disks with a diameter smaller than that of functional connection disks are not required to

upon by the purchaser and supplier, the hole rings and hole breakouts shall be cut by microsurgery. meet the minimum hole ring requirements.

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IPC-6013b-3-20-cn

Figure 3-2 0 Ring width measurement (inner layer)

Note: Consideration should be given to how the microsection is positioned or rotated.

Random misalignment may occur in the vertical direction, so vertical cutting does not IPC-6013b-3-22-cn

guarantee that pore breakage will be observed in the microsection image. Figures Figure 3-22 Microdissection position rotation

3-21 and 3-22 show different microsections obtained at different rotation angles.
Optional coupon F
Breakage may or may not be visible within a single microsection.
Custom-designed electrical test coupons

? X-ray photography technology

Horizontal microsection

? Analyze graphic skew through CAD/CAM data of each layer.

NOTE: Microsectioning or statistical sampling should be used to verify the correlation

of the approved technique with the calibration standards established for the specific

technique used.

3.6.2.10.1 Hole Breakout (Inner Layer) Condition If an offset breakout point is detected

on a vertical microsection, the following should be noted:

a) the minimum conductor width may be reduced where the conductor meets the land,

and

b) Insufficient electrical spacing.

IPC-6013b-3-21-cn NOTE: Electrical spacing may be further reduced due to plated copper penetration

Figure 3-21 Rotating micro-sectioning position detection hole damage due to a combination of etchback and wicking.

The extent and direction of the misalignment should be determined. Actual production
For Class 2 printed boards, if an inner layer annular ring failure is detected in a vertical

printed boards or test coupons should then be inspected to determine compliance.

section, but the extent of the failure cannot be determined, the inner layer registration
This testing may be accomplished using the techniques listed in Section 3.6.2.10.
can be assessed using non-destructive techniques other than microsectioning, such

as special patterns, probes, and/or software configured to provide information on the

inner layer remaining annular ring and pattern deflection. These techniques include,
3.6.2.11 Land Warping Land warping is permitted in microsections after thermal

but are not limited to, the following:

stressing.

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IPC-6013B January 2009

3.6.2.12 Plating/Coating Thickness The plating/coating thickness shall meet

the requirements in Table 3-2 or as specified in the procurement documentation,

as determined by microscopic examination or by appropriate electronic measuring

equipment. Measurements of plated-through holes shall record the average wall

thickness on each side of the hole. Isolated thick or thin areas shall not be used

to calculate the average. Isolated areas of reduced copper foil thickness due to

glass fiber protrusions shall meet the minimum thickness requirements in Table

3-2, measured from the end of the protrusion to the hole wall.
IPC-6013b-3-24-cn

Figure 3-24: Copper cladding in a Type 4 printed board (acceptable)

If isolated areas of copper thickness less than the minimum thickness specified

in Table 3-2 are detected, they should be considered voids and resampled

from the same lot in accordance with Table 4-2 to determine if the defect is

random. If additional test coupons or production printed boards do not contain

isolated areas of reduced copper thickness, the lot is considered acceptable.

However, if reduced copper thickness is observed in microsections,

, the lot is

considered nonconforming. ,

3.6.2.12.1 Copper wrap plating shall be continuous from the filled plated- NOTE: Dimension lines and arrows indicate where the copper wrap has been removed.

through hole to the outside surface of any plated structure, with the minimum IPC-6013b-3-25-cn

copper wrap plating as specified in Table 3-2. It shall extend at least 25 ÿm Figure 3-25 Copper cladding removed due to excessive grinding/scraping (unacceptable)

, [984 ÿin] beyond the required annular ring width (see Figures 3-23 and

3-24). Insufficient wrap plating due to reduction of the surface copper wrap 3.6.2.13 Minimum Internal Copper Foil Thickness: If the internal conductor

plating by machining (grinding, etching, scraping, etc.) is not permitted (see thickness is specified by copper foil weight, the minimum internal copper foil

Figure 3-25). thickness after processing shall meet the requirements of Table 3-13 for all

grades. This requirement is based on the minimum copper foil thickness in

IPC-4562 followed by two consecutive brushings. Each brushing is expected to

remove a certain amount of copper, and the table lists the amount of copper

allowed to be reduced during processing. When the procurement documentation

specifies a minimum copper foil thickness for internal conductors, the conductor

shall meet or exceed the minimum thickness requirement.

3.6.2.14 Minimum Conductor Thickness After Processing: The minimum conductor

thickness (copper foil plus copper plating) after processing shall conform to the

requirements of Table 3-14. When procurement documentation specifies a minimum

copper thickness for outer conductors, the specimen shall meet or exceed the minimum

thickness requirement. The minimum conductor thickness after processing given in Table
Note: If cover plating of plugged holes is required, the point above the plugged hole is not considered as the ,
measurement point when measuring the copper thickness of the cover. 3-14 is determined by the following formula.
IPC-6013b-3-23-cn

Figure 3-23 Table: Copper Wrap Measurement (Applicable to All Filled Plated-Through

Holes)

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Table 3-13 Inner copper foil thickness after adding?

Copper absolute value (IPC-4562)

1
The nominal value in the The maximum value allowed to be reduced during addition The maximum thickness of copper foil after heating

weight (ÿm) [ÿin] (ÿm) [ÿin] (ÿm) [ÿin]

1/8 oz [0.0051] 4.60[181] 1.50[59] 3.1[122]

1/4oz[0.0085] 7.70[303] 1.50[59] 6.2[244]

3/8oz[0.012] 10.80[425] 1.50[59] 9.3[366]

1/2 oz [0.0171] 15.40[606] 4.00[157] 11.4[449]

1oz[0.0343] 30.90[1,217] 6.00[236] 24.9[980]

2oz[0.0686] 61.70[2,429] 6.00[236] 55.7[2,193]

3oz[0.1029] 92.60[3,646] 6.00[236] 86.6[3,409]

4oz[0.1372] 123.50[4,862] 6.00[236] 117.5[4,626]

4 oz[0.1372] than the standard in IPC-4562 The copper foil thickness is reduced compared to IPC-4562

6.00[236]
above Weighing value reduced by 10%
10% of the value obtained is reduced by 6 ÿm [236 ÿin]
Note 1. For copper foil weighing less than 1/2oz, the thickness reduction value does not allow for rework. For copper foil weighing 1/2oz and above , The machining thickness reduction value allows one rework.

Table 3-14 Thickness of outer conductor after electroplating

Copper absolute value For level 1 and level 2 products For Level 3 products, Add the final surface conductor
(? IPC-4562 Products, plus the best coating Plus the most? coating Allowed in Canada
Thickness (ÿm) [ÿin]
The nominal value is reduced (0.0 20ÿm) (0.0 25 ÿm) The maximum value of reduction
3 3 2
weight 1,4 10%) (ÿm) [ÿin] [0.0007 9ÿin] 0.000 98 ÿin] (ÿm) [ÿin] Level 1 and Level 2 Level 3

1/8oz 4.60[181] 24.60[967] 29.60[1,165] 1.50[59] 23.1[909] 28.1[1,106]

1/4oz 7.70[303] 27.70[1,091] 32.70[1,287] 1.50[59] 26.2[1,031] 31.2[1,128]

3/8oz 10.80[425] 30.80[1,213] 35.80[1,409] 1.50[59] 29.3[1,154] 34.3[1,350]

1/2 oz 15.40[606] 35.40[1,394] 40.40[1,591] 2.00[79] 33.4[1,315] 38.4[1,512]

1oz 30.90[1,217] 50.90[2,004] 55.90[2,201] 3.00[118] 47.9[1,886] 52.9[2,083]

2oz 61.70[2,429] 81.70[3,217] 86.70[3,413] 3.00[118] 78.7[3,098] 83.7[3,295]

3oz 92.60[3,646] 112.60[4,433] 117.60[4,630] 4.00[157] 108.6[4,276] 113.6[4,472]

4oz 123.50[4,862] 143.50[5,650] Note 1. The base copper foil weight 148.50[5,846] 4.00[157] 139.5[5,492] 144.5[5,689]
is based on the design requirements in the procurement documents.

Note 2. For copper foil weighing less than 1/2 oz, the thickness reduction value does not allow for rework. Note 3. ; For copper foil weighing 1/2 oz and above, one rework is allowed for the machining reduction thickness.
Reference: Minimum copper plating thickness

Level 1 = 20 ÿm [787 ÿin] Level 2 = 20 ÿm [787 ÿin] Level 3 = 25 ÿm [984 ÿin]

NOTE 4 For copper foil weighing more than 4 oz,
, use the formula in Section 3.6.2.14.

Minimum surface conductor thickness = a + b - c Before metallographic sectioning, the specimen should be

Thermal stress test. In the area of insulating filling material, due to the core
in:
Suction, radial cracks, lateral gaps or voids should not cause adjacent

a = Absolute minimum copper foil thickness (greater than the standard in IPC-4562) The electrical spacing between conductor surfaces is reduced to less than 100 ÿm [3,937

(the weighing value is reduced by 10%)

From the edge of the plated hole to the core of the hole filling material

Suction and/or radial cracks should not exceed 75 ÿm [2,953 ÿin]

b = Minimum copper plating thickness (for Class 1 and Class 2 products ,
(See Figure 3-26).
20 ÿm [787 ÿin]; for Class 3 products, 25 ÿm

[984 ÿ in])
3.6.2.16 The minimum dielectric spacing should be

c = Maximum allowable reduction in processing Figure 3-27 provides the minimum dielectric spacing measurement.

Example of measurement method.

3.6.2.15 Is there any excess space between the plated hole and the metal core?

All metal core printed boards with gaps should be required to undergo horizontal metallographic examination. Note: The minimum rigid dielectric layer spacing may be specified as 30ÿm

slice , To observe the metal core/insulation material filled between the holes [1,181 ÿ in]; however, consideration should be given to using low-roughness copper

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IPC-6013B January 2009

For Class 2 and Class 3 products, buried vias must be at least 60% ,

filled with laminate resin or similar via-hole filling material. For Class 1

products, buried vias may not be filled with any filling material.

3.6.2.18 Nailheads There is no evidence that nailheads affect functionality.

The presence of nailheads may be considered a process indicator or design

variation but is not grounds for rejection.

3.7 Solder Mask Requirements When solder mask is required on printed

boards, the solder mask shall meet the qualification/conformance requirements

of IPC-SM-840. For Class 1 and Class 2 products, if no solder mask

performance level is specified,

, IPC-SM-840 Level T shall be used. For Class

3 products, Level H shall be used. , IPC-SM-840 should be used

The following conformance requirements shall also be met:

IPC-6013b-3-26-cn
3.7.1 Solder Mask Coverage Due to manufacturing variations such as
Figure 3-26: Distance from metal core to plated-through hole
skipping, voiding, and misalignment, solder mask coverage is subject to the

following limitations:

a. Metal conductors shall not be exposed in areas where solder mask

coverage is required. If solder mask repair is required to cover these

areas, it shall be made of a material that is compatible with the original

solder mask and has the same resistance to soldering and cleaning.

b. In areas containing parallel conductors, variations in solder mask should

not expose adjacent conductors unless the area between the conductors

IPC-6013b-3-27-cn is intentionally left as a test point or for some surface mount devices.

Figure 3-2 Measurement of the minimum dielectric spacing

c. Conductors under components should not be exposed, or other measures

The foil and applied voltage should be kept constant to prevent interlayer breakdown.
should be taken to electrically insulate the conductors. If components are
If the minimum dielectric spacing and number of reinforcement layers are not specified,
should be clearly , exposed, the area covered by the components
,
the minimum dielectric spacing shall be 90 ÿm [3,543 ÿin], and the number of
marked in the procurement documents.
reinforcement layers shall be selected by the supplier to ensure the minimum dielectric

d. The solder mask does not need to be flush with the pad surface. Misalignment
spacing. When the nominal rigid dielectric spacing specified in the drawing is less than
of the solder mask pattern with defined requirements should not expose
90 ÿm [3,543 ÿin], the minimum dielectric spacing shall be 25 ÿm [984 ÿin], and the
isolated lands or conductors.
number of reinforcement layers shall be selected by the supplier. Products with

transmission line impedance designs shall have special requirements and measurement e. If it does not violate the outer ring requirements of the product level,

methods specified in the procurement documentation. Solder mask is permitted on the lands of plated-through holes where

;
solder connections are to be made. Solder mask should not intrude into

3.6.2.17 Blind and buried vias Filling requirements for blind vias shall be the wall of the plated-through hole. Other surfaces such as printed

specified in the procurement documents. Unless otherwise specified, the board edge connector contacts and surface mount lands should be free

filling material in the blind via shall be flat and have a surface flatness within ± of solder mask unless otherwise specified.

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January 2009 IPC-6013B

Solder mask is permitted in holes and vias unless the purchase

, document If solder mask touch-up is required to cover these areas,

The components require these holes to be completely filled with solder. Solder resist can When using a solder resist that is compatible with the original solder resist and has the same solder resistance

To mask or plug the vias, this may also be required When tested according to IPC-TM-650

Do. Test points prepared for assembly testing must be free of Test Method 2.4.28.1 When testing, the cured solder mask

Solder mask unless

, specified to cover it. The maximum percentage of lift from Coupon G shall be in accordance with Table 3-

15.
f. When there is no plated hole on the connection pad, such
, as the pad is surface

Mounting pads or ball grid array pads should not be,misaligned. Table 3-15 Solder mask adhesion?

The solder mask invades the pad, or the solder mask boundary What is the maximum percentage of shedding allowed?

Table area Level 1 Level 2 Level 3

Unclear beyond the following conditions:
Bare 10 5 0
1) For sections greater than or equal to 1.25 mm [0.04921 in]
copper, 25 10 5
distance, misalignment on the surface mount pads should not cause 10 5 0
gold or

The solder mask encroaches on the pad more than 50ÿm [1,970ÿin]; nickel substrate molten metal (lead-tin plating, hot melt
50 25 10
For pitches less than 1.25 mm [0.04921 in], do not Tin-lead and bright acid tin)

The solder mask should not encroach on the pad more than 25ÿm[984
3.7.3 Solder Mask Thickness Unless otherwise specified in the procurement ,
ÿ in]. Encroachment can occur on surface mount pads
documentation, solder mask thickness does not need to be measured.
On adjacent sides, but not on opposite sides
The degree can be measured by instrument or by measuring the
superior.

Parallel conductors were microsectioned for evaluation.

2) On the ball grid array pad, if the pad is covered by the solder mask

If the limit is set, the offset allows the solder mask on the pad to have a 90° 3.8 Electricity? It is required to be tested according to the requirements of Table 4-3 and 4-4.

If clearance is specified, except for conductor connections

, During testing, flexible printed boards shall meet the following electrical requirements.

Except for the joints, the solder mask is not allowed to invade the pads.
3.8.1 The dielectric withstand voltage test coupons shall be as follows:

g. Pits and voids are permitted on the solder mask in non-conductor areas as long ,
After testing, the conductor should meet the requirements of Table 3-16.

as they are attached to the edges. , and does not exceed the requirements of Section 3.7.2
There should be no sparking or breakdown between the conductor and the pad.

Lifting or blistering is permitted.

Conduct dielectric withstand voltage test according to IPC-TM-650 test method 2.5.7

h. Solder mask between closely spaced surface mount lands The dielectric withstand voltage shall be applied to each conductor pattern.

Coverage shall be in accordance with the provisions of the procurement documents. All common parts and adjacent common parts of each conductor pattern

The voltage should be applied between the conductor patterns of each layer and between each
i. When the design requires the solder mask to cover the edge of the printed board , add

The solder mask is broken or lifted along the edge of the printed circuit board after processing Between graphics of adjacent layers for electrical insulation.

The extension shall not exceed 1.25 mm [0.04921 in], or

3.8.2 Electrical continuity and insulation resistance of flexible printed boards should
More than 50% of the distance to the nearest conductor, whichever is greater
When tested in accordance with IPC-9252.
Small value.

3.8.2.1 Connectivity flexible printed boards and qualification test boards should

The test is carried out according to the following procedure. The resistance value of the circuit
3.7.2 Solder Mask Curing and Adhesion? Cured Solder Mask

The coating should not show tack, delamination, bubbles or blistering. Should not be larger than the value specified in the procurement documents.

Should exceed the following ranges: Conductors or short, thick conductors can increase or decrease the resistance limit

The acceptance criteria for these special conductors must be specified at the time of purchase.
a. For Class 1 products, there are no bridging conductors.
in the file.
, on each side, with a maximum length of
b. For Level 2 and Level 3 products, there are two

The thickness does not exceed 0.25 mm [0.00984 in] and the conductor is not Each conductor or group of interconnected conductors should be passed through a current, and the electrodes

The electrical spacing between the components is reduced by more than 25%. Added to the connection plate at each end of the conductor or conductor group.

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IPC-6013B January 2009

Table 3-16 Dielectric Withstand Test Voltage

Level 1 Level 2 Level 3

Voltage for pitches greater than or equal to 80 ÿm [3,150 No requirements 500 Vdc +15, -0 500 Vdc +15, -0

ÿin] Voltage-time for pitches less than 80 ÿm No requirements 250 Vdc +15, -0 250 Vdc +15, -0
[3,150 ÿin] No requirements 30 s +3, -0 30 s +3, -0

The current of the body should not exceed the minimum value specified in IPC-2221 for the thinnest Table 3-17 Insulation resistance

For the requirements of 4.1.1 and 4.1.2 Level 1 Level 2 Level 3

The test current

, should not exceed 1A. Maintain electrical function in receiving state 500 Mÿ 500 Mÿ

Maintain electrical function after exposure to damp heat 100 Mÿ 500 Mÿ

The printed circuit board designed for the circuit should comply with the requirements of the layout drawing.

resistance requirements.
The outer conductor shall be coated with a coating that complies with IPC-CC-830.

3.8.2.2 The insulation resistance printed board or identification test board shall be Final measurement should be made 2 hours after removal from the test chamber.

Conduct the test according to the following procedures. The insulation resistance between conductors should be During the exposure in the test chamber, the

When in accordance with the values specified in the procurement documents. Each layer is applied with 100±10V DC polarization voltage.

The voltage applied between the networks must be high enough to enable the measurement to White spots on the coating, away from the edge of the test coupon or finished printed board

Sufficient current resolution. At the same time, this voltage must be low enough The edge should not exceed 3 mm [0.12 in].

Prevent spark discharge between adjacent networks, otherwise it may cause

3.8.4.1 The withstand voltage after MIR should be
Product defects. For manual testing, the voltage should be at least
After resistance test , Perform the voltage withstand test according to Section 3.8.1.
200V, and the voltage should be applied for at least 5 seconds.

The minimum test voltage applied

, when automatically testing equipment should be
3.9 Cleanliness requirements for permanent solder mask coatings
The maximum rated voltage of the printed circuit board. If the maximum rated voltage is not specified
Type 1 and Type 5 flexible printed boards shall be tested in accordance with 3.10.11.
The default value of 40V DC voltage is used.
Test and evaluate.

3.8.3 Short circuits between circuit/plated-through holes and metal substrates

The board shall be tested as per Section 3.8.1, but with a 500V (DC) 3.9.1 Cleanliness before solder mask application When printed boards are to be

Polarization voltage should be applied between conductors and/or between lands and When applying a permanent solder mask, print the

Between metal substrates, the application method should be such that each conductor/ Ions and other contaminants on the board should be within the permitted limits.

The pads are tested (e.g. with a metal brush or aluminum foil). When uncoated printed boards are tested in accordance with Section 3.9, contamination

There should be a gap between the circuit/plated hole and the metal substrate. Levels should not exceed 1.56 ÿg/cm2 sodium chloride equivalent.

Withstand 500V (DC). There should be no sparks or dielectric

3.9.2 After application of solder mask, solder or other surface coatings

Quality breakdown.

When the cleanliness level is specified, the printed board shall be cleaned in accordance with Section 3.9.

3.8.4 Moisture and Insulation Resistance (MIR) test coupons shall

tested and meet the requirements of the procurement documents.
Follow the procedure outlined below to perform the test.

Shall exhibit subsurface imperfections exceeding those permitted in Section 3.3.2.

3.9.3 The cleanliness of the inner layer after oxidation treatment before lamination should be as specified.

The resistance (at 500V DC) should meet the requirements given in Table 3-17.
Timing, inner layer should be tested in accordance with Section 3.9 and in accordance with the procurement document

For all product levels, no components

requirements.
The minimum requirement for flush printed circuit boards with components should be 50M?.

The insulation resistance requirements for the received state are specified in the special requirements section.
3.10 Special requirements, when specified in the procurement documents, shall be

(See Section 3.10.9).

Adopt some or all of the special

The damp heat and insulation resistance tests of printed boards should be conducted Requirements. Special markings in the procurement documents will indicate which

in accordance with IPC-TM-650 Test Method 2.6.3. Yes.

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January 2009 IPC-6013B

3.10.1 When specified, flexible printed boards shall be tested according to the The maximum output measured at the geometric center is 100 Gs. All four

following procedures. Total weight loss (TML) due to outgassing shall not exceed sides of the test coupon or production printed board should be fixed to prevent it

1.0%, and collectible volatile condensable matter (CVCM) shall be less than from moving.

0.1%. When tested in accordance with IPC-TM-650, Test Method 2.6.4, weight

loss shall be determined on test coupons made from representative base 3.10.5 Mechanical Shock The printed board under test shall pass the circuit test in

,
Section 3.8.2 after being subjected to the following mechanical shock test.
material or on production printed boards. As an alternative, outgassing data

from NASA or the original equipment manufacturer (OEM) shall be acceptable.

Mechanical shock testing should be performed in accordance with IPC-TM-650,

Test Method 2.6.5. The printed board should be subjected to three 100 Gs

pulses of 6.5 ms duration, applied to each of the three major sides. The test

coupon or production printed board should be secured on all four sides to

3.10.2 Organic Contamination Uncoated printed boards shall be tested according
prevent movement.
to the procedure outlined below. Any visually visible organic residue shall

constitute a failure. 3.10.6 Impedance Test Impedance requirements shall be specified in the procurement

documentation. Impedance testing may be performed on test coupons or on designated

Printed boards should be tested according to IPC-TM-650 Test Methods
circuits on the product. Time domain reflectometry (TDR) is used for electrical
2.3.38 or 2.3.39. First, a qualitative method involves dropping
, high-
performance testing, but when a larger impedance tolerance (±10%) is permitted,
purity acetonitrile onto a test coupon or finished printed board and
mechanical testing using microsections of specialized test coupons may be used to
collecting the sample on a microscope glass slide. This slide is then ,
verify the impedance results. The equation for calculating test coupon impedance is
dried and compared to a dry slide without methyl cyanide contamination
given in IPC-2251, and the time domain reflectometry measurement method is given in IPC-2251.
to obtain visual evidence of organic residue. If evidence of organic
IPC-TM-650 Test Method 2.5.5.7.
contamination is , contamination is detected, the nature of the

Multiple , determined by performing infrared spectroscopy using the

3.10.7 Coefficient of Thermal Expansion (CTE) When printed boards with metal cores
Internal Reflection (MIR) method in IPC-TM-650 Test Method 2.3.39.
or reinforcement structures are required to have limited thermal expansion in the planar

direction, the CTE shall be within the temperature range specified in the procurement
3.10.3 Fungus Resistance Finished printed boards or representative portions
documentation and shall be within ± 2 ppm/°C of the specified CTE value. Testing
of printed board surfaces from a batch shall not support the growth of fungi when
shall be conducted in accordance with the strain gage method in IPC-TM-650, Test
tested in accordance with IPC-TM-650, Test Method 2.6.1.
Method 2.4.41.2. Other methods for determining CTE shall be determined by agreement

between the purchaser and the supplier.

3.10.4 Vibration Test Coupons or production printed boards, after being subjected

to the vibration test procedure described below, shall pass the circuit test of
3.10.8 Thermal Shock When specified in the procurement documentation, flexible
3.8.2 and shall not exhibit bow or twist exceeding that permitted in 3.4.3.
printed boards or test coupons shall be tested according to the following procedure.

Specimens shall be subjected to thermal shock testing in accordance with IPC-

Cyclic sweep vibration testing and timed resonance testing shall be performed in
, over the temperature range of -65°C to +125°C [-85°F
TM-650, Test Method 2.6.7.2,
accordance with IPC-TM-650 Test Method 2.6.9, with the printed board mounted
to 257°F]. Metallographic sections are not required to be evaluated in accordance
with the plane perpendicular to the axis of vibration.
with IPC-TM-650, Test Method 2.6.7.2. Specimens removed from the test chamber

shall meet the circuit requirements described in Section 3.8.2, and the resistance
Cyclic Test - The cyclic test shall be a sweep from 20 to 2000 Hz completed in
value shall not vary by more than ±10%.
16 minutes. The input acceleration shall be maintained at 15 Gs between the

frequency range of 20 to 2000 Hz.

3.10.9 Table 3-10 Insulation Resistance (As-Received) The test coupons shall

Timed Resonance - The test coupon or production printed board shall be be tested as follows: The insulation resistance shall not be less than the value

subjected to a timed resonance for 30 minutes with an input of 25 Gs or given in Table 3-17.

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IPC-6013B January 2009

The test coupons or finished printed boards shall be conditioned at 50 ± 5°C

[122 ± 9°F] for 24 hours with no applied humidity. After cooling, the insulation

in IPC- , resistance test shall be performed at room temperature as specified

TM-650, Test Method 2.6.3.

3.10.10 Metal Core (Flat Microsectioning) When specified, horizontal

microsectioning shall be required for metal core printed boards with spacing

between the metal core and plated-through holes to observe the metal core/hole

fill insulation. Test coupons or production printed boards shall be subjected, to

thermal stress testing in accordance with 3.6.1 prior to microsectioning. Wicking, IPC-6013b-3-28-cn

radial cracks, lateral gaps, or voids in the hole-fill insulation shall not reduce the Figure 3-28 Bending test
electrical spacing between adjacent conductive surfaces to less than 100 ÿm

Bending direction (a)

[3,937 ÿin]. Wicking and/or radial cracks extending from the edge of the plated-

through hole into the hole fill shall not exceed 75 ÿm [2,953 ÿin]. Degree of curvature (b)

Number of bending cycles (c)

Mandrel diameter (d)

3.10.11 Ionic Contamination (Resistivity by Solvent Extraction) When specified,

printed boards or test coupons shall be tested for ionic contamination by the The bending point is specified by the user.

solvent extraction method as specified in IPC-TM-650, Test Method 2.3.25,

A bending cycle is defined as: holding one end of the specimen, bending it
Section 4. When testing flexible printed boards for ionic contamination by this
around the mandrel, returning to the starting position, bending 180° in one
method, the contamination level shall not exceed 1.56 mg/ 2 of sodium chloride
direction, and then bending 180° in the opposite direction. This cycle is considered
cm equivalent.
one. Alternatively, (using two ends): holding both ends of the specimen, bending

An equivalent test method may be used in place of the above method ,provided it , them 90° in one direction around the mandrel, returning to the starting

has the same or better sensitivity and uses solvents that have the same ability position, bending them 90° in the opposite direction, and then returning to the

to dissolve flux residues or other contaminants as specified above. starting position. This cycle is considered one.

During the test, the mandrel shall be placed in contact with the specimen on

one side, and then in contact with the specimen on the other side, and the
3.10.12 Simulated Return?
specified number of bending cycles shall be completed. After the bend test, the

flexible or rigid-flexible printed board shall be tested for electrical defects in

3.10.12.1 Through-hole components, when specified, test coupons or production
accordance with Section 3.8 and shall meet the requirements of Section 3.3.
printed boards shall be tested in accordance with IPC-TM-650, Test Method

2.4.36, and then microsectioned, with land lift permitted. Inspect in accordance

, with 3.6
3.10.14 Flexibility Testing should be conducted in accordance with IPC-TM-650,

Test Method 2.4.3.1; IPC-TM-650, Test Method 2.4.3 may be used instead.
3.10.12.2 Table ? Placement components, when specified, shall be , Test
Flexibility testing may also be performed using dedicated equipment designed
100% tested on test coupons or production printed boards.
for test circuits. The overall length of the coupon may vary to accommodate

the test fixture and circuit design. Therefore, the final coupon configuration for
3.10.13 Bend Test Unless otherwise specified by the user, the bend test shall
the final product application should be determined by both the supplier and the
be performed as shown in Figure 3-28. Bend test requirements shall be
purchaser.
specified in the appropriate documents/general drawings. Minimum bend radius

guidance shall be found in IPC-2223. At a minimum, the following parameters The requirements for the flexural resistance test shall be specified in the relevant documents/

shall be specified: general drawings. At least the following parameters shall be specified:

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? Number of flexure cycles 3.12 Rework Rework is permitted for all grades of product. Repair of base material

surface defects or removal of plating material residue or excess copper is permitted

? Bending mandrel diameter or distance between bending spring leaves

for all grades of product, provided that the functional integrity of the printed board is
? Deflection rate
not compromised.
? Flex point

? Rotation stroke 4 Quality Assurance Regulations

The method for determining flex life is the interruption of electrical continuity that
4.1 General Quality Assurance General quality assurance provisions are defined in
occurs during monitoring; or the passage of a predetermined number of flex cycles
IPC-6011 and each sub-specification. This specification specifies requirements for
without interruption of electrical continuity.
flexible printed boards, including the frequency of qualification testing, acceptance

3.10.15 Bond Strength (?? Supported Lands) When flexible printed boards are tested testing, and quality conformance testing.

in accordance with IPC-TM-650, Test Method 2.4.20, the unsupported lands

shall be bonded to the substrate after five cycles of soldering and desoldering. , 4.1.1 Identification The identification is determined by negotiation between the supplier and the buyer (see

It shall be able to withstand a pull of 1.86 kg or 35 kg/cm2 [498 PSI], whichever is Qualification should consist of a capability analysis evaluation (see IPC-9151) and pre-

less. The land area calculation for unsupported holes does not include the area production samples, production samples, or test coupons (see IPC-6011) produced

occupied by the hole. on the same equipment and processes planned for printed boards. Qualification

should include the applicable tests referenced in Tables 4-3 and 4-4. As agreed upon
3.10.16 Bond Strength (Stiffener) Using a sharp instrument (such as a scalpel or
by the purchaser and supplier, qualification may also include documentation or
blade), cut a strip of the specimen approximately 13 mm [0.512 in] wide and 76 mm
specifications that the supplier has provided to other users of similar products.
[2.99 in] long along the flexible circuit toward the stiffener so that it is at right angles to

the direction of peel when approximately halfway, through the peel operation.

4.1.2 Sample Test Coupons If test coupons are used to replace production quantities

based on the use of previously

, standardized test coupons, provide the following
The peel rate is 57 mm/min [2.24 in/minute]. Measurements are recorded at the
information. Sample test coupons may be used for qualification or ongoing production
beginning, middle, and end of the peeling operation and averaged to determine
process control. Layout drawings, databases, or production masters may be obtained
acceptability. The peel strength between the flexible printed circuit board and the
from IPC. Layout drawings and photographic masters for each type (see Section
reinforcement layer should be a minimum of 1.4 kg/25 mm [0.984 in] when using a
1.3.2) are as follows:
thermosetting adhesive and a minimum of 0.38 kg/25 mm [0.984 in] when using a

pressure-sensitive adhesive. Type 1 General Layout Drawing IPC-100041, Photographic Base Drawing IPC-A-41

Type 2 General Layout Drawing IPC-100042, Photographic Base Drawing IPC-A-42

Type 3 General Layout Drawing IPC-100043, Photographic Base Drawing IPC-A-43

3.11 Repairs. Repairs to bare flexible printed boards shall be determined by
Type 4 General Layout Drawing IPC-100043, Photographic Base Drawing IPC-A-43
agreement between the purchaser and supplier per set of purchase documentation
Type 5 General Layout Drawing IPC-100043, Photographic Base Drawing IPC-A-43
(see IPC-7711/21A).

Note: IPC-100001 is a general drawing for drilling and outline layout.

3.11.1 Circuit Maintenance The circuit maintenance of Class 1, Class 2 and Class 3 flexible

printed circuit boards shall be determined by negotiation between the supplier and the buyer.

In principle, 0.09m per side 2 2 Table 4-1 specifies test coupons A through H for qualification and process capability
[ 0.969ft ] or smaller. Repairs to impedance-

controlled circuits should not exceed two locations. Repairs to impedance-controlled evaluation as specified in IPC-A-41, IPC-A-42, and IPC-A-43. Equivalent production

circuits should not violate impedance requirements and must be approved by the printed board coupon descriptions are specified in IPC-2221.

user. Repairs to circuits should not violate minimum electrical spacing requirements.

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Table 4-1 Identification Test

test Request Chapter Type 1 and Type 5 Type 2 Type 3 and Type 4

?Visual inspection 3.3

3.3.1 Whole Whole Whole board

Appearance: Halo at 3.3.1.1 board board Whole board

the 3.3.1.1 Whole Whole Whole board

edge of the rigid 3.3.1.2 board board Whole board

section; Edge of the flexible section; Transition area 3.3.1.3 Whole Whole Whole board

from the rigid 3.3.2 board board Whole board

section 3.3.2.1 Whole Whole Whole board

to the flexible 3.3.2.2 board board Whole board

section; Structural 3.3.2.4 Whole Whole Whole board

defects; 3.3.2.5 board board Whole board

White spots; Microcracks; Foreign inclusions; 3.3.2.6 Whole Whole Whole board

Exposed fabric; 3.3.2.7 board board Whole board

Scratches, indentations, and machining marks; Surface 3.3.2.8 Whole

Whole board Whole board Whole board Whole board
board Whole
Whole board Whole board Whole
board board
Whole boardWhole board

voids; Color 3.3.2.9 /A /A /A

variation in the area 3.3.2.10 Whole board Whole Whole board

of adhesive enhancement 3.3.2.11 Whole board board Whole Whole board

treatment; Pink circle; 3.3.2.11.1 Whole board board Whole Whole board

Coverfilm separation; Covercoat requirements; 3.3.2.11.2 Whole board board Whole Whole board

Covercoat coverage; 3.3.2.11.3 Whole board board Whole Whole board

Covercoat cure and adhesion; 3.3.2.12 Whole board board Whole Whole board

Covercoat 3.3.2.13 Whole board board Whole Whole board

thickness; Solder wicking/plating penetration; 3.3.3 /A board Whole Whole board

Plating and coating 3.3.4 Whole board board Whole Whole board

voids in 3.3.5 Whole board board Whole board

the enhanced 3.3.6 A, B, A/B, CA, B, A/B, CA, B, A/B, C

board hole; Lifted 3.3.7 C C C

land marks; Solderability; Plating adhesion; Junction between gold plating and solder coating on the edge of the printed Only on request Only on request Only on request

board contact 3.3.9 Whole board Whole board Whole board

pad. 3.3.8 3.4

Workmanship Quality Dimensions? 3.4.1 Whole board Whole board Whole board

Requirements: Aperture 3.4.2 Whole board Whole board Whole board

and hole pattern accuracy; Ring 3.4.2.1 Whole board Whole board Whole board

width (outer layer); Solderable ring width (outer layer); Covercoat 3.4.2.2 Whole board Whole board Whole board

adhesive squeeze-out 3.4.2.3 Whole board Whole board Whole board

and covercoat bleed-out; Enhancement board clearance; Hole bow and 3.4.3 Whole board Whole board Whole board

twist (rigid or enhancer board portion only); Conductor accuracy. 3.5

Conductor width and thickness 3.5.1 Whole board Whole board Whole board

Conductor 3.5.2 Whole board Whole board Whole board

spacing 3.5.3 Whole board Whole board Whole board

Conductor defects Reduction 3.5.3.1 Whole board Whole board Whole board

in conductor width Reduction 3.5.3.2 Whole board Whole board Whole board

in conductor 3.5.4 Whole board Whole board Whole board

thickness Nicks and pinholes in the conductor surface ground or power planes 3.5.4.1 Whole board Whole board Whole board

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January 2009 IPC-6013B

test Request Chapter Type 1 and Type 5 Type 2 Type 3 and Type 4

Surface mount pad (rectangular) 3.5.4.2.1 Whole Whole Whole board

Surface mount pad (circular) 3.5.4.2.2 board board Whole board

Wire bond pad 3.5.4.3 Whole Whole Whole board

Printed board edge Connector land 3.5.4.4 board board Whole board

Dewetting 3.5.4.5 Whole Whole Whole board

Non- 3.5.4.6 board Whole board Whole board

wetting Final coating 3.5.4.7 board Whole Whole Whole board

Coverage Conductor 3.5.4.8 board Whole board Whole board board Whole board Whole board Whole board
Whole board

edge Plating Width Structural integrity 3.6

Thermal Stress Test 3.6.1 A, B, or A/B A, B, or A/BA, B, or A/B

Microsection Coupon Requirements Plating 3.6.2 A, B, or A/B A, B, or A/BA, B, or A/B
Integrity Plating 3.6.2.1 A, B, or A/BA, B, or A/B
Voids Laminate 3.6.2.2 A, B, or A/B A, B, or A/B
Integrity (Flexible Section) Laminate Integrity 3.6.2.3 A, B, or A/B A, B, or A/B A, B, or A/B
(Rigid Section) Delamination or Bubbles 3.6.2.4 A, B, or A/B A, B, or A/B A, B, or A/B
Etchback Drill Smear 3.6.2.5 A, B, or A/B A, B, or A/B A, B, or A/B
3.6.2.6 A, B, or A/B
Negative 3.6.2.7 A, B, or A/B
Etchback 3.6.2.8 A, B, or A/B
Wicking (Electroplated 3.6.2.9 A, B, or A/B
Copper) Ring Width 3.6.2.10 A, B, or A/B
(Inner Layers) Plating/Coating 3.6.2.12 A, B, or A/B A, B, or A/BA, B, or A/B
Thickness Inner Layer Copper 3.6.2.13 A, B, or A/B A, B, or A/BA, B, or A/B
Foil Minimum Thickness Surface 3.6.2.14 A, B, or A/B A, B, or A/BA, B, or A/B
Conductor 3.6.2.15 A, B, or A/B A, B, or A/B
Minimum 3.6.2.16 A, B, or A/B A, B, or A/B A, B, or A/B
Thickness Metal Core Dielectric Spacing 3.6.2.17 A, B, or A/B A, B, or A/B A, B, or A/B
Blind and 3.8

Buried Via Filling 3.8.1 E E E

Material 3.8.2 D, H D, H D, H
Requirements 3.8.2.1 D, H D, H D, H
Dielectric Withstand Voltage Circuit 3.8.2.2 D, H D, H D.H
Continuity Insulation Resistance (Circuit Shorts) Shorts between 3.8.3 Only on request Only on request Only on request
Circuit/PTH and Metal 3.8.4 E E E
Substrate Moisture, Heat and Insulation Resistance Cleanliness 3.9
Whole board Whole board Whole board

Special 3.10

3.10.1 Only on request Only on request Only on request

requirements: 3.10.2 Only on request Only on request Only on request
Degassing, 3.10.3 Only on request Only on request Only on request
organic 3.10.6 Only on request Only on request Only on request
contamination, mildew resistance, 3.10.7 Only on request Only on request Only on request
impedance 3.10.8 D D D
testing, coefficient of thermal expansion (CTE), 3.10.9 E E E
thermal shock, surface insulation resistance (as received), ionic 3.10.11 Whole board Whole board Whole board

contamination (resistivity measurement by solvent extraction), simulated rework 3.10.12 A, B, or A/B A, B, or A/B

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test Request Chapter Type 1 and Type 5 Type 2 Type 3 and Type 4

Bending flexibility 3.10.13 H H H

Flexing 3.10.14 H H H

resistance Bond strength (unsupported land) 3.10.15 A, B, or A/B A, B, or A/B A, B, or A/B

Bond strength (reinforcement 3.10.16 Only on request Only on request Only on request

plate) Repair 3.11 Only on request Only on request Only on request

Circuit repair 3.11.1 Only on request Only on request Only on request

and rework 3.12 Only on request Only on request Only on request

4.2 Acceptance test and frequency Acceptance test and frequency should be 4.2.1 C=0 Zero Acceptance Number Sampling Plan

Using quality conformance coupons and/or finished printed boards, The sample plan provides the lot tolerance percentage defect (LTPD)

The requirements of this specification and IPC-6011 are further amended in accordance with the provisions of 4-3. ) is greater than or equal to a level of “user risk” of 0.10.

The quality conformance test coupons are in IPC-2221 The index value at the top of each sample size column is related to the AQL.

There are regulations that indicate the purpose of each coupon and its use in production assembly. All samples in a batch (see Table 4-2) should be

When “Sampling” is indicated in Table 4-3, the C=0 zero acceptance , Only when the requirements are met can it be accepted.

number sampling plan specified in Table 4-2 shall be used. If more information on sampling is required,

Information on the scheme (H0862) can be obtained by contacting the U.S. Quality Control
Note: For Type 2 to Type 4 flexible circuit boards, IPC-6013
association.
The revised version adds a new method for verifying the structural integrity after thermal stress

Test coupon sample requirements.

Table 4-2 Sampling plan for C = 0 of batch printed circuit boards of various levels

Level Level Level 3

Batch quantity 2.51 1 4.01 6.51 1.51 2 2.51 4.01 0.101 1.01 2.51 4.01

** ** **
1-8 5 3 2 5 3 5 3
**
9-15 5 3 2 5 5 3 13 5 3
**
16- 25 5 3 3 8 5 3 13 5 3
**
26- 50 5 5 5 8 5 5 13 5 5
**
51- 90 7 6 5 8 7 6 13 7 6

91- 150 11 7 6 12 11 7 125 13 11 7

151-280 13 10 7 19 13 10 125 20 13 10

281-500 16 11 9 twenty one 16 11 125 29 16 11

501-1,200 19 15 11 27 19 15 125 34 19 15

1201-3200 twenty three 18 13 35 twenty three 18 192 42 twenty three 18

3201-10,000 29 twenty two 15 38 29 twenty two 294 50 29 twenty two

10,001-35,000 35 29 15 46 35 29 345 60 35 29
NOTE 1. Index values are related to AQL values. If the user determines that a particular product is “critical” and requires a smaller index value, the user should specify this requirement in the procurement documentation and should include it in the distribution document.

Provide a general diagram to illustrate the “critical” requirements.

** Indicates testing of the entire lot.

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Table 4-3 Acceptance inspection and frequency

Test samples Inspection frequency

Requirements and? Finished product printing Printed circuit board testing

1 1
test Law Chapter Plate making Test coupons Level 1 Level 2 Level 3 Remark

Verifiable
3.2.1-
Material Manufacturer's certificate SPC procedures or
3.2.14
Proof of consistency

?Visual inspection

Rigid segment edge 3.3.1.1 × Sampling (4.0) Sampling (2.5) Sampling (2.5) Each printed board

Flexible segment edge 3.3.1.2 × Sampling (4.0) Sampling (2.5) Sampling (2.5) Each printed board

Transition from rigid segment to flexible segment

3.3.1.3 × Sampling (4.0) Sampling (2.5) Sampling (2.5) Each printed board
area

Structural defects 3.3.2 × Sampling (4.0) Sampling (2.5) Sampling (2.5) Each printed board

Only applicable to

3.3.3 Voids in plating and coating within holes × Sampling (4.0) Sampling (2.5) Sampling (1.0) Types 2, 3, and 4,

Each board in production

Connection pad lift 3.3.4 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

mark 3.3.5 × (Retain coupons) Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

Printed board edge contact piece gold plating

layer and solder coating layer 3.3.8 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production
Department

Workmanship quality 3.3.9 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board
Physical properties

Each board in production

Coating adhesion 3.3.7 × C Sampling (6.5) Sampling (4.0) Sampling (4.0)
(1 coupon)

Each board in production

Cover coating curing and adhesion 3.3.2.11.2 × G Sampling (6.5) Sampling (4.0) Sampling (4.0)
(1 coupon)
Solderability

Surface 3.3.6 M Sampling (4.0) Sampling (2.5) Sampling (2.5) Each panel in production

holes 3.3.6 A or A / B or S Sampling (4.0) Sampling (2.5) Sampling (2.5) Each panel in production
Size requirements

Dimensional requirements: Flexible printed circuit board 3.4 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

Aperture and hole pattern 3.4.1 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

accuracy Ring width 3.4.2 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

(outer layer) Solderable ring 3.4.2.1 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board

width (outer layer) Bow and twist (only refers to rigidity)

3.4.3 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board
or reinforcement board part)

Conductor accuracy (inner and outer layers)

Conductor 3.5 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board

defects: Reduction in conductor 3.5.3.1 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board

width; Reduction in conductor 3.5.3.2 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board

thickness; 3.5.2 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board

Conductor spacing; Defects in ground or power planes.

3.5.4.1 × Sampling (6.5) Sampling (4.0) Sampling (4.0) Each printed board
Mouth and pinhole

Each board in production

Surface mount pads 3.5.4.2 × Sampling (6.5) Sampling (4.0) Sampling (2.5)
10 fewer assessments

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Test samples Inspection frequency

Requirements and? Finished product printing Printed circuit board testing

test Law Chapter Plate making Test coupons Level 1 1 1 Remark

Level 2 Level 3

Edge connector pads 3.5.4.4 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board

3.5.4.5
Dewetting/Non-wetting/Final coating
3.5.4.6 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board
Coverage
3.5.4.7

Conductor edge plating widening 3.5.4.8 × Sampling (6.5) Sampling (4.0) Sampling (2.5) Each printed board
(Type 3, 4) Structural integrity after thermal stress (microsection ) 6

Flexible and rigid laminates 3.6.2.3

A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
Integrity 3.6.2.4

Etchback, desmear and negative etchback 3.6.2.6

A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
(Types 3 and 4 only) 3.6.2.7

3.6.2.1
Plating integrity and wicking A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
3.6.2.9

Plating voids 3.6.2.2 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production

3.6.2.10
3,5
Hole ring and hole break (inner layer) A and B or 2 A/ B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
3.6.2.10.1

Plating/coating thickness 3.6.2.12 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
Minimum thickness of inner 3.6.2.13 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production

copper foil Minimum thickness of 3.6.2.14 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production
surface 3.6.2.15 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production

conductor Metal 3.6.2.16 A and B or A / B Sampling (2.5) Sampling (1.5) Sampling (0.1) Each panel in production

core Dielectric spacing Buried hole material filling 3.6.2.17 A and B or A / B Sampling (6.5) Sampling (4.0) Sampling (4.0) Each panel in production
(Type 2) Structural integrity after thermal stress (microsection ) 6

Plating integrity 3.6.2.1 B or A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production
Plating voids 3.6.2.2 B or A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production

Laminate integrity
3.6.2.3 B or A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production
(Flexible section)

4
Plating/Coating Thickness 3.6.2.12 B or A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production B or

Surface Conductor Minimum 3.6.2.14 A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production
Thickness Dielectric Spacing 3.6.2.16 B or A / B Sampling (6.5) Sampling (4.0) Sampling (2.5) Each panel in production
Power Requirements

2 2 2
Continuity 3.8.2.1 × Sampling (2.5) 100% 100%
2 2 2
insulation resistance 3.8.2.2 × Sampling (2.5) 100% 100%

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Test samples Inspection frequency

Requirements and? Finished product printing Printed circuit board testing

1 1
test Law Chapter Plate making Special requirements Level 1 Level 2 Level 3 Remark

for test coupons

Dielectric withstand 3.8.1

voltage circuit/PTH and metal base

3.8.3 ×
Short circuit between boards

Moisture and heat and insulation 3.8.4

resistance 3.9

Cleanliness 3.10.8

Thermal shock Surface insulation resistance

3.10.9
(Receiving state)

Ionic contamination (Solvent extraction

3.10.11 Applicable only if required by the contract
Resistivity measurement)

Organic 3.10.2

contamination, 3.10.3

mildew 3.10.1

resistance, 3.10.6

degassing resistance, thermal expansion 3.10.7

coefficient 3.11

(CTE), repair, 3.11.1

circuit repair and rework 3.12

Note 1. The numbers in brackets are AQL levels.

Note 2. For Type 1 and Type 2 flexible printed boards, visual inspection or AOI may be used instead of electrical testing.

Note 3. For Class 2 products, the degree of damage can be assessed after vertical microsectioning. Note 4. The , Assessment by means other than horizontal microsectioning.

measurement position must be larger than the collimation source.

NOTE 5. A and B or two A/B coupons should be taken from opposite corners of each production plate and oriented in different axes (one on the X axis and the other on the Y axis). For designs with only one hole pattern, both coupons should reflect that hole pattern.

type.

Note 6. All via structures must be evaluated after thermal stress.

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4.2.2 Arbitration Test Prepare two more boards from the same production board. 5. Note

Sets of microscopic sections to assess the effects of single or essentially accidental

5.1 Order Information The purchase document should clearly state the following:
Or defects caused in the preparation of microsections.

a. Name, version number, edition and current valid procurement document

All arbitration microsections must be free of defects before they can be accepted.
date.

4.3 Quality consistency testing should be performed

b. According to user requirements, detailed changes outside this specification
The test consists of the tests specified in Table 4-4.
More and additional conditions.

There are regulations requiring that machines that meet all the requirements of IPC-QL-653
c. Part identification and marking instructions.
The structure is completed. Level 3 testing can be extended to Level 2 reliability testing.

d. Prepare delivery information when necessary.

and evaluation.

e. Special testing requirements and frequency.

4.3.1 The selection of test coupons should be based on the

Two sets of test coupons are selected from the printed boards of the same type, which should be able to 5.2 Superseded Specifications This specification supersedes IPC-6013A.

It can represent the products produced during the inspection cycle and have passed the acceptance test. Revision 1 and Revision 2 of IPC-FC-250 and IPC-RF-

The most complex graphics printed circuit board. 245.

Table 4-4 Quality consistency test

Test coupons Test frequency

Requirements and?

test Law Chapter Type 1,5 Type 2-4 Level Level 2 Level 3

3.10.12
1 Simulated Rework B or A/B When requested Two coupons per quarter Two coupons per month

Bond Strength (Unsupported Land) 3.10.15 B or A / B When requested When requested Two coupons per quarter Two coupons per month

Bonding strength (reinforced board) 3.10.16 Printed board When required When required When required
3.8.1
When dielectric withstand voltage is required, two E and two coupons
coupons per quarter E per month

Moisture and heat and insulation resistance 3.8.4 E E Maintain electrical functionality Two coupons per quarter Two coupons per month

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Appendix A

Appendix A summarizes the performance requirements of IPC-6013B in alphabetical order. Special conditions, lengthy requirements, and guidance information may be simplified or omitted in this appendix. Complete specification requirements

are provided in the referenced sections of this appendix.

Require

Characteristic inspection Level 1 Level 2 Level 3 Request Chapter

Hole breakouts in lands not exceeding 90°,

When assessed by visual inspection, the as assessed by visual inspection, and with a
Ring width after etching (outer layer of The minimum ring width should be 50ÿm Section 3.4.2 and
hole on the connecting plate shall not be 50 ÿm [1,970 ÿin] ring width over at least 270° of
plated-through hole) [1,970 ÿ in]. Table 3-8
broken by more than 180°. the circumference, are permitted. Hole

breakouts in lands not exceeding

Hole breakouts on lands are not greater 90°, as assessed by visual inspection, are
Ring width after etching (outer layer The minimum ring width should be 150ÿm Section 3.4.2 and
than 90° when assessed by visual permitted as long as the reduction in width
of unsupported hole) [5,906 ÿ in]. Table 3-8
inspection. Hole at the land/

breakouts are permitted as long as the reduction conductor junction is below the width reduction

Ring width after etching (inner layer in land/conductor connection is below the width limit permitted in 3.5.3.1. The minimum ring width should be 25ÿm Section 3.4.2 and

of plated hole) reduction limit allowed in Section 3.5.3.1. As [984 ÿ in]. Table 3-8

specified in the

Bend testing appropriate documentation/general drawing Section 3.10.13

Bond strength
The peel strength between the flexible printed circuit board and the stiffener shall be ÿ1.4kg/25mm[0.984in]. Section 3.10.16
(stiffener) Bond

strength (unsupported lands) Bow According to IPC-TM-650 test method 2.4.20, the unsupported land shall be able to withstand a tensile force of 1.86 kg or 35 kg/cm after five cycles of ,
2 Section 3.10.15
and twist (rigid soldering and desoldering. [498PSI], whichever is less.

or stiffener portion
Surface mount applications: Maximum 0.75% (or as agreed upon by both parties).

only) Material Section 3.4.3

Other applications: Maximum 1.5% (or as agreed upon by the supplier and the buyer).
characterization Circuit

repair Circuit/shorts between Section 3.2

2 2
plated-through 0.09m [0.969ft] Metal- Section 3.11.1
] No more than 2 repairs are required within the specified range; and the impedance and minimum electrical spacing requirements are not violated.

holes core flexible printed boards tested in Section 3.8.2

and metal substrate Cleanliness accordance with IPC-9252 shall withstand 500V (DC) between the circuit/plated-through hole and the metal-core substrate without sparking or dielectric
Section 3.8.3
breakdown. Type 4 and Type 5 flexible printed boards

shall be tested and evaluated in accordance with Section 3.10.11. When printed boards with metal cores or Section 3.9

reinforcement structures are required to have limited thermal expansion in the planar direction, the CTE shall be within ±2ppm/°C of the specified CTE value

within the temperature range specified in the procurement documentation. Unless otherwise agreed upon between the purchaser and the supplier, the test method
Coefficient of thermal expansion Section 3.10.7
shall be in accordance with IPC-TM-650, Test Method 2.4.41.2, Strain Calculation Method.

Bond enhancement Color variation

Mottling or color variation is acceptable; random areas of lack of treatment should not exceed 10%. Section 3.3.2.8
Conductor accuracy

in treated areas Meets visual inspection and dimensional requirements, conductor pattern and thickness as specified in the procurement documentation, Section 3.5

and no plating growth on the edges of solder-coated and tin-lead-plated conductors when tested in accordance with IPC-TM-650, Test Method 2.4.1.
Conductor edge plating widening Section 3.5.4.8

The reduction in conductor cross-sectional area shall not exceed 20% of the minimum value; and the total
The reduction in the cross-sectional area of the conductor

defect length shall not exceed 10% of the conductor length or 13.0 mm [0.512 in] (whichever is less).
Conductor defects shall not exceed 30% of the minimum value. Section 3.5.3

No cracks, splits or tears.

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Require

Characteristic inspection Level 1 Level 2 Level 3 Request Chapter

Due to the rough edges of the conductor, copper thorns

Due to the roughness of the conductor edge, copper thorns, etc., the minimum conductor spacing may be
Conductor spacing For reasons such as Section 3.5.2
Reduced by 50%.
A 20% reduction.

Conductor surface Section 3.5.4

The reduction in conductor thickness is not greater than the maximum

Reduction in conductor thickness The reduction in conductor thickness shall not exceed 20% of the minimum conductor thickness. Section 3.5.3.2
30% of the minimum conductor thickness.

The conductor width is not reduced by more than the maximum

Reduction in conductor width The conductor width shall not be reduced by more than 20% of the minimum width. Section 3.5.3.1
30% of the minimum width.

Structural defects The resistance value of white spots, micro cracks, blister Section 3.3.2

and delamination circuits shall not exceed the value specified in the procurement documents; the evaluation current through the conductor shall not be greater than
Connectivity Section 3.8.2.1
The current value specified in IPC-2221 for the thinnest conductor in the circuit.

The conductors shall not be exposed where the coating is required. No more than two conductors per side, with a maximum Section 3.3.2.11.1

length of no more than 0.25mm

Blisters cannot bridge conductors [0.00984in], more than Without reducing the electrical spacing between conductors

25%.

Maximum percentage of allowable shedding: Maximum percentage of allowable shedding: Maximum percentage of allowable shedding:

Bare copper 10%; Bare copper 5%; Bare copper 0%;

Cover coating curing and
Gold or nickel 25%; Gold or nickel 10%; Gold or nickel 5%; Section 3.3.2.11.2
Adhesion
Base material 10%; Base material 5%; Substrate 0%;

Hot melt metal 50%. Hot melt metal 25%. Hot melt metal 10%.

Cover coating requirements See Sections 3.3.2.11.1 through 3.3.2.11.3. Not measured Section 3.3.2.11

Cover coating thickness unless otherwise specified in the procurement documentation. Cover Section 3.3.2.11.3

film is uniform and free of separation. Unlaminated is acceptable provided it meets Section 3.3.2.4 and the following requirements: Not too large.

Covering film separation Within the area of 0.8mm×0.8mm[0.0315×0.0315in], 25mm×25mm[0.984×0.984in] Section 3.3.2.10

No more than 3, and no more than 25% of the conductor spacing,

The defect does not cause the conductor spacing to drop below the minimum and does not grow due to thermal testing simulating the assembly process.
microcracks Section 3.3.2.2
For Class 2 and Class 3 products, the span of microcracks shall not exceed 50% of the distance between adjacent conductors.

If the area affected by delamination and blistering does not exceed 1% of the area of each side of the printed board, and it does not cause the gaps between the conductive patterns to

If the distance is reduced to below the minimum conductor spacing, it is acceptable for all grades of products.
Layering/bubbling Section 3.3.2.3
After the heat test during assembly, delamination and blistering shall not expand. For Class 2 and Class 3 products, blistering and

The span of the delamination should not be greater than 25% of the spacing between adjacent conductive patterns.

Welding connection area: 15% Welding connection area: 5%

Dehumidification Section 3.5.4.5
It is allowed on conductors and conductive layers.

Dielectric spacing The procurement documents should specify the minimum dielectric spacing. Section 3.6.2.16

Dielectric withstand See Table 3-16. The dielectric withstand voltage test should be conducted in accordance with IPC-TM-650 Test Method 2.5.7. This should comply Section 3.8.1

voltage Dimension with the procurement documents. Section 3.4

requirements Printed board edge contact piece

Copper: 2.5mm[0.0984in] Copper: 1.25mm[0.04291in] Copper: 0.8mm[0.031in]

Gold plating and solder coating Section 3.3.8

Gold: 2.5mm[0.0984in] Gold: 1.25mm[0.04291in] Gold: 0.8mm[0.031in]

The junction of the layers

No cuts or scratches that expose the underlying nickel or copper; pits, dents, indentations, or depressions no larger than

Edge connector pads 0.15 mm [0.00591 in], not exceeding 3 locations per land and not occurring on more than 30% of lands is acceptable. , Section 3.5.4.4

No burrs, nicks or delamination (discontinuities to facilitate circuit removal) exceeding those permitted in the procurement documentation.
Flexible segment edge Section 3.3.1.2
There should be no tearing on the flexible parts of Type 1 and Type 2 flexible plates and Type 3 and Type 4 flexible plates.

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Require

Characteristic inspection Level 1 Level 2 Level 3 Request Chapter

If the penetration depth does not exceed 50% of the distance between the edge and the nearest conductor or 2.5 mm [0.0984 in], whichever is greater,
Rigid segment edge Section 3.3.1.1
Small values are acceptable.

Electrical Section 3.8

Performance Etchback (Type 3 and

Between 5 ÿm [197 ÿin] (exposed copper) and 80 ÿm [3,150 ÿin] (maximum material removal). Section 3.6.2.6

Type 4)

A 5% exposed copper area is permitted outside the termination area or areas requiring solder fillet.
Final coating coverage Section 3.5.4.7
The requirements of J-STD-003 shall be met.

Flexibility In accordance with the provisions of the appropriate documents/general drawings, in accordance with IPC-TM-650 Test Section 3.10.14

Method 2.4.3. Translucent foreign inclusions shall be acceptable.

Foreign inclusions Section 3.3.2.4
Reduction of the distance between conductors below the minimum spacing specified in Section 3.5.2 shall be acceptable. No mold growth when

Anti-fungal tested in accordance with IPC-TM-650, Test Method 2.6.1. Section 3.10.3

halo Penetration does not exceed 2.5 mm [0.0984 in] or 50% of the distance from the edge to the nearest conductor, whichever is less. Section 3.3.1.1

aperture and hole pattern accuracy shall comply with the provisions of the Section 3.4.1

procurement documents. Time domain reflectometer (TDR) can be used for electrical performance testing, but when the resistance is allowed

Impedance test For larger tolerances (±10%), mechanical testing can be performed using microsections of special test coupons to verify Section 3.10.6

Impedance results.

Receiving state: Maintain electrical function. Receiving state: 500Mÿ

Surface insulation resistance
After exposure to damp heat: Maintains electrical Section 3.10.9
(Receiving state) After exposure to moisture and heat: 100Mÿ After exposure to moisture and heat: 500Mÿ
functionality

Ionic contamination (solvent extraction Test the sodium equivalent in accordance with IPC-TM-650 Test Method 2.3.25. , Pollution level is less than or equal to 1.56 ÿg/cm2 chlorine
Section 3.10.11
Resistivity measurement method) The insulation

resistance between conductors shall comply with the value specified in the procurement documents; the manual test voltage shall be at least 200V, plus
Insulation resistance (short circuit
The pressure time is at least 5S; in automatic testing, use the maximum rated voltage of the printed circuit board; if not specified, use Section 3.8.2.2
road)
Use the default values in Table 1-1.

Laminate integrity

The substrate voids in Area B (see Figure 3-14) do not exceed 50 ÿm [197 ÿin]. Section 3.6.2.3
(Flexible section)

Laminate integrity
See Section 3.6.2.4 and Figure 3-14. Section 3.6.2.4
(rigid section)

Connector pad lift There are no lifted lands on the delivered flexible printed circuit boards (not subjected to thermal stress testing). Conductive Section 3.3.4

marking markings must be compatible with the printed circuit board material and not compromise electrical spacing requirements. Section 3.3.5

material Manufacturer's certification

White spots should be acceptable. When the white spots in the laminate substrate exceed 50% of the spacing between non-common conductors,

white spots Grade 1 product is a process warning that indicates a variation in material, equipment operation, workmanship or process, but Section 3.3.2.1

Not a defect.

Wicking, radial cracks, lateral gaps or voids in the area of the insulating void-filling material should not cause adjacent conductors to
metal core Section 3.6.2.15
Surface electrical spacing is reduced to less than 100 ÿm [3,937 ÿin].

The minimum thickness of the inner copper foil shall comply with Table 3-13. Section 3.6.2.13

The minimum thickness of the surface conductor shall comply with Table 3-14. Section 3.6.2.14

There is no white spot, blister or delamination exceeding the allowance in Section 3.3.2; the insulation resistance meets the requirements of Table 3-17; damp heat and
Moisture and heat and insulation resistance Section 3.8.4
Insulation resistance testing is performed in accordance with IPC-TM-650 Test Method 2.6.3.

If the purchase documents do not specify If the purchase documents do not specify

Negative etchback Etch, the negative etch cannot exceed Etch, the negative etch cannot exceed Etch, the negative etch cannot exceed Section 3.6.2.8

25.0 ÿm[984 ÿin] 25.0 ÿm[984 ÿin] 13.0 ÿm[512 ÿin]

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IPC-6013B January 2009

Require

Characteristic inspection Level 1 Level 2 Level 3 Request Chapter

On the ground or power plane

Maximum size 1.5mm [0.0591in] Maximum size 1.0mm [0.0394in] Section 3.5.4.1
Notches and pinholes

For tin, tin-lead reflow or solder coated surfaces, ensure that the minimum solderable area or area outside the annular ring requirement is
Non-wetting Section 3.5.4.6
Areas are permitted.

organic pollution Tested in accordance with IPC-TM-650 Test Method 2.3.38 or 2.3.39, no evidence of organic contamination. Tested in accordance with Section 3.10.2

procurement documentation; total weight loss (TML) due to outgassing is not greater than 1.0%, and can be collected.
Degassing Section 3.10.1
The volatile condensable matter (CVCM) is less than 0.1%.

Pink Circle Acceptable Section 3.3.2.9

when tested in accordance with IPC-TM-650 Test Method 2.4.1, there shall be no protective plating or conductor pattern.
Coating adhesion Section 3.3.7
There are signs of partial peeling of the foil.

The requirements of Table 3-2 or the requirements specified in the procurement documents shall be met.
Plating/coating thickness Section 3.6.2.12
Measure and evaluate according to the copper plating void acceptance criteria in Section 3.3.3.

Copper plating: ÿ10% of holes Copper plating: ÿ 5% of the holes allow a ,

Each hole is allowed to have a maximum of maximum of 1 empty hole per hole Copper plating: No voids

In-hole plating and coating 3 holes. Hole.

Section 3.3.3
Hollow Coating: less than 15% pores Coating: less than 5% pores Coating: Less than 5% pores

A maximum of 5 per hole is allowed A maximum of 3 per hole is allowed A maximum of 1 is allowed per hole.

Hollow. Hollow. Hollow.

There is no delamination between layers (except for the notes in Section 3.6.2.1

Plating integrity Table 3-12). The area of contamination or inclusions should not exceed 50% of each interconnect surface and should not appear on the metal core.
Section 3.6.2.2
The interface between the copper foil layer and the copper plating layer on the hole wall.

Regardless of length or size, each sample shall contain no more than one void.

Plating voids Meet the requirements of Table 3-12. The length of the plating voids shall not exceed 5% of the total thickness of the flexible printed circuit board. Section 3.6.2.2

There should be no plating voids at the interface between the inner layer and the plated hole wall.

Repair Determined by negotiation between the supply and demand parties. Section 3.11

attachment after microsectioning

See Table 3-12 and Sections 3.6.2.1 to 3.6.2.18. Section 3.6.2
Board

requires blind and buried vias resin No filling requirement. For Class 2 and Class 3 products, buried vias shall be filled with at least laminating resin or similar vias.
Section 3.6.2.17
Stuffing The material filling is 60%.

Rework The functional integrity of the printed board is not affected. Section 3.12

scratches, dents and machining Exposed conductors or fiber breaks do not exceed the values allowed in 3.3.2.4 and 3.3.2.5; and the dielectric spacing is not reduced.
Section 3.3.2.6
trace Less than the specified minimum requirement.

Decontamination (Type 3 and 4 only)

The resin at the conductor interface should be completely removed (see Figure 3-16). Section 3.6.2.7
Stencil)

Solder Wicking/ Plating Migration

Max. 500 ÿm [19,685 ÿin] Max. 300 ÿm [11,811 ÿin] Max. 100 ÿm [3,937 ÿin] Section 3.3.2.12
shift

Solderability Solderability testing and accelerated aging testing are performed in accordance with J-STD-003. Section 3.3.6

Solderable hole ring (outer layer) Meet the requirements of Table 3-10. Special Section 3.4.2.1

requirements are specified in the procurement documents. When using Section 3.10

thermosetting adhesive, the total void area should not exceed 10% of the total area of the reinforcement board.
reinforcement plate Section 3.3.2.13
When bonding using this type of bond, the total void area should not exceed 1/3 of the total area of the reinforcement.

Enhance the structural integrity The outer ring width shall not be reduced below the value specified in 3.4.2. The structural Section 3.4.2.3

of the plate clearance holes integrity requirements for the thermal stress post-assessment coupons specified in 3.6.2 shall be met. Section 3.6

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January 2009 IPC-6013B

Require

Characteristic inspection Level 1 Level 2 Level 3 Request Chapter

The longest dimension does not exceed 800 ÿm [31,500 ÿin], does not form conductor bridges, and does not exceed the maximum value on each side of the printed board.
Surface voids Section 3.3.2.7
5% of the total area.

Small defects along the edge of the pad

The defects along the edge of the pad are not greater than 30%; the defects within the pad are not
Surface mount pads Less than 30%; defects within the pad are not Section 3.5.4.2
Greater than 10%.
Greater than 20%.

Tested/evaluated in accordance with IPC-TM-650 Test Method 2.6.7.2, temperature range -65 to +125°C
thermal shock Section 3.10.8
[-85 ÿ 257° F].

The specimens were baked at 120-150°C [248-302°F] for 6 hours, depending on the thickness of the printed board, and tested according to IPC- ,
TM-650 Test Method 2.6.8. After microsectioning, the specimens were tested at 100X ± 5%. Section 3.6.1
Thermal stress test
Inspection of copper foil and plating of plated through holes shall be conducted under magnification. Arbitration inspection shall be conducted at 200X ±5%

carried out at a magnification of .

From rigid segment to flexible segment

Defects beyond the permissible range shall be determined through negotiation between the supplier and the purchaser, or specified in the procurement documents. Section 3.3.1.3
transition zone

The processed products should be tested and the quality of the products should be consistent and meet the requirements of Sections 3.3.1 to 3.3.9.
Visual inspection Section 3.3
If the

conductor spacing is not reduced below the minimum requirement, the exposed fabric may There should be no exposed
Exposed fabric Section 3.3.2.5
take over. fabric

Workmanship quality It should be free from defects and of uniform quality, without visible dust, foreign matter, oil stains or fingerprints. Section 3.3.9

45
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ANSI/IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits

Defining submission/approval forms

This table is intended to timely collect widely used Applicant Information:

to revise this standard by adding new terms and definitions.

Name:
Individuals or organizations are welcome to express their opinions.

Please fill out this form and send your feedback to:
Company Name:

IPC
City:
3000 Lakeside Drive, Suite 309S Bannockburn,
Country:
IL 60015-1249 Fax: 847-615-7105

telephone number:

date:

? Submission of new terms and definitions.

Supplement to existing terms and definitions.

? Modification of existing terms and definitions.

the term definition

If there is insufficient space , Please write on the back or on an additional page.

Illustration: ? Not Applicable? Required? To be provided

? Include: Electronic file name:

Documents to which these terms and definitions apply:

Committees relevant to this term and definition:

Filled in by IPC internally

IPC Office Committee 2-30

Date Received: Date of Initial Review:
Comments Collated: Comment Resolution:
Returned for Action: Committee Action:

Revision Inclusion: ? Accepted ? Rejected ? Accept Modify

IEC Classif cation

Classification Code ? Serial Number

Terms and De ?nition Committee Final Approval Authorization: Committee 2-30 has
approved the above term for release in the next revision.
Name: Committee: IPC 2-30 Date:
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Membership Application Form

Thank you for becoming an IPC member and for your support of IPC! IPC membership is for the entire company. Becoming an IPC member means that all employees of the company

listed on this application will receive the benefits of membership.

In order to enable IPC to serve its members faster and better, please select the column below that best reflects the situation of your organization and fill it out according to

the prompts.

ÿ Printed circuit board manufacturers

You manufacture and sell printed circuit boards (PCBs) or other electronic interconnect products, and sell these products to other companies. What products does your company

manufacture and sell?

ÿ Single-sided and double-sided rigid multilayer printed circuit boards ÿ Flexible printed circuit board ÿ Other interconnect products

Chairman/General Manager:

ÿ Electronic Manufacturing Services (EMS) companies

Produces printed circuit assemblies under contract and offers other electronic interconnect products for sale.

Chairman/General Manager:

ÿ OEM-Original Equipment Manufacturer

Procurement, use and/or manufacture of printed circuit boards or other electronic interconnect products to manufacture and sell end products.

Product Series:

ÿ Industry Suppliers

Provide raw materials, machinery, equipment or technical services used to manufacture or assemble electronic interconnect products.

Which industry do you serve? ÿ PCB ÿ EMS ÿ Both

Product Varieties:

ÿ Government agencies/research institutes

A non-profit organization that designs, researches, and uses electronic interconnect products.

ÿ Consulting Company

What services are provided:

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Membership Application Form

Unit situation:

Unit Name:

address:

Telephone: fax:

Contact: Position:

e-mail: Website:

Membership fee details:

Membership Fees

Your company will begin to enjoy all IPC membership benefits from the date IPC receives your application and dues payment. Your membership will last for

one or two years, depending on your choice of payment method. Membership dues are in RMB only.

Please select one:

Original Non-profit organizations such as government agencies

Member: ÿ One-year membership USD and research institutes ÿ One-year
1050 ÿ Two-year membership USD (Save 10%) membership USD 275 ÿ Two-year (Save 10%)

1890 Additional Member: (If another entity in the same group is an IPC membership USD 495 Consulting firms
member) ÿ One-year membership (with fewer than 6 employees) ÿ One-
USD 850 ÿ Two-year membership (Save 10%) year membership USD 625 ÿ Two-year membership USD (Save
1125 10%)

USD 1530 Enterprises with annual sales of less

than US$5 million ÿ One-year
membership USD 625 ÿ Two-year membership USD 112510%)
(Save

Please complete this form and fax or email to:

Head of Membership Department

IPC-IPC Technology Consulting (Shanghai) Co., Ltd.

Tel: 86-21-54973435*605

Fax: 86-21-54973437

www.ipc.org\china.ipc.org
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Standard Improvement Form IPC-601 3B CN

The purpose of this table is to make this standard Individual or collective submissions to IPC are welcome If you can provide improvement suggestion , Please fill in the following

Industrial users to IPC technology Suggestions. We will collect all form and submit it to:

IPC
The committee provides recommendations. Recommendations are submitted to the appropriate committee.
3000 Lakeside Drive, Suite 309S
Bannockburn, IL 60015-1249 Fax:

847-615-7105 Email:

[email protected]
_____________________________________________________________________________________________

1. I would like to suggest changes to the following:

___ Require , Number of chapters

___Which test method__________, number of chapters __________

The above chapter numbers are proven to be:

___Unclear___Other ___not applicable ___Incorrect

_____________________________________________________________________________________________

2. Specific change suggestions:

______________________________________________________________________________________________________

______________________________________________________________________________________________________

______________________________________________________________________________________________________

______________________________________________________________________________________________________
3. Other suggestions for improving the standard:

______________________________________________________________________________________________________

______________________________________________________________________________________________________

______________________________________________________________________________________________________

______________________________________________________________________________________________________
Submitted by:

Name Telephone

company e-mail

address

City/Country/Continent date
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Association Connecting Electronics Industries

? Shanghai Office Beijing Office

16AB, Shengquan Building, No. 28 Tanjiadu Road, B05, Chaolin Building, No. 15, Ronghua Middle Road, Beijing Economic and

Shanghai Tel: (86 21) 54973435 Fax: Technological Development Zone Tel:

(86 21) 54973437 Website: (86 10) 67885326 Fax: (86 10) 67885326
3000 Lakeside Drive, Suite 309 S
www.IPC.org.CN
Bannockburn, IL 60015 Suzhou Office

847-615-7100 tel Shenzhen Room 17D1, Kaiyuan Building, 1400 Donghuan Road,

847-615-7105 fax Office Room 1807, Fangda Building, South District, High-tech Park, Suzhou Tel: (86 512) 67164877 Fax: (86

Nanshan District, Shenzhen Tel: (86 755) 512) 67164877

www.ipc.org ISB
#978-1-61193-017-7 86141218 / 19 Fax: (86 755) 86141226