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Compal Confidential: PT-Note Schematic Document TBT Sku

The document is a confidential engineering drawing for the Compal model QILP2, detailing the schematic and trade secret information related to the motherboard LA-8262P. It includes various components, voltage rails, and board ID tables, emphasizing that the information is proprietary and cannot be disclosed without authorization. The document is dated May 24, 2012, and is part of a larger set of 48 sheets.

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petk
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22 views48 pages

Compal Confidential: PT-Note Schematic Document TBT Sku

The document is a confidential engineering drawing for the Compal model QILP2, detailing the schematic and trade secret information related to the motherboard LA-8262P. It includes various components, voltage rails, and board ID tables, emphasizing that the information is proprietary and cannot be disclosed without authorization. The document is dated May 24, 2012, and is part of a larger set of 48 sheets.

Uploaded by

petk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 48

A B C D E

Compal Confidential
1
Model Name : QILP2 1

File Name : LA-8262P

Compal Confidential 2

PT-Note Schematic Document


TBT SKU
2012-04-18
3 3

REV:1.0_0418B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 1 of 48
A B C D E
A B C D E

Compal Confidential ZZZ Sub-board


Model Name : PT-Note LA8262
1.Power on & DCIN Board
File Name : block diagram DAZ_PCB
DAZ0PT00200

2.Card Reader Board


3.FP board
1
4.Think light board 1

5. C-logo
n-VIDIA Intel
VRAM 128*16 N13P-GLP PCI-E X16 Ivy Bridge Dual Channel
DDR3*8 29mm * 29mm DDR3-1600(1.5V) DDR3-SO-DIMM X2
BGA
Page 21~Page 30 Page 10~Page 11

Page 04~Page 09

FDI DMI 2Channel Speaker


HDA Audio Codec
ALC 3202 Digital MIC
HDMI
mHDMI Connector Audio combo Jack
LVDS Intel USB3.0
LVDS Connector Panther Point USB PORT 3.0 x1
2
DP 2

USB2.0 USB 3.0 connector


PCI-E USB PORT 2.0 x 1
1X 4 SATA
Page 12~Page 20
mDP Connector Cactus Ridge USB PORT 3.0 x1 USB 3.0 connector
SPI ROM LPC BUS USB PORT 2.0 x 1 On Sub-board
Page 33~Page 36 BIOS 4M+2M
TPM
EC Finger Printer To Sub-board
Card Reader To Sub-board 1X ENE KB9012
RTS5229

G-Sensor CMOS Camera


Realtek 1X Int.KBD
RTL8111F
C-logo
3
Click Pad Mini PCIE (WWAN) 3

RJ45 CONN Mini PCIE (WLAN)


Track Point Thermal Sensor
1X Fintek 75303M
Mini PCIE (WLAN)

PCI Express USB(BT)


Mini card PCI-E(WLAN) SATA HDD CONN
Slot 1 BT/WLAN combo
PCI Express USB
SATA ODD CONN
4 4

Mini card SATA


Slot 2 WWAN/mSATA Mini PCIE (mSATA)

SIM Card Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019JH A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 24, 2012 Sheet 2 of 48
A B C D E
A B C D E

Voltage Rails BOARD ID Table


+5VS
+3VS
Board ID PCB Revision
+1.8VS
0 N/A
1
+1.5VS
1 0.2 1

Power plane +1.05VS


2 0.3
+VGFX_CORE_AXE
3
+5VALW +3.3VM +CPU_CORE
4
+B +3VALW +1.5V +1.05VM +VCCSA
5
+0.75VS
6
7
+3VS_VGA GPU
State
+1.05VS_VGA
+1.5VS_VGA
+VGA_CORE
S0
EC SM Bus1 address EC SM Bus2 address
O O O O O
Device Address HEX Device Address HEX
S3 Smart Battery 16H EMC1403-2(DDR,WLAN) 1001-101xb 9AH
O O O O X Smart Charger 12H SB-TSI 96H
M3 GPU 9EH
O O O O X
2 2
S4 O O O X X
S5 - AC
SM Bus Controller 0
O O X X X Device Address HEX

S5 - BATT ONLY X X X X X
G3 - NO AC & BATT
X X X X X
SM Bus Controller 1
Device Address HEX
USB3.0 USB2.0 NOTE
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS DDR DIMM1 A0
DDR DIMM2 A2 1 0
Full ON H H H ON ON ON
ROM A8
2 1 * USB3.0/2.0 Conn
3 3
S3 (Suspend to RAM) L H H ON ON OFF
3 2 USB3.0/2.0 Conn
S4 (Suspend to Disk) L L H ON OFF OFF
4 3
S5 (Soft OFF) L L L ON OFF OFF
4

BOM Structure @ : Un-pop. 5 USB Camera

UMA@ : UMA only 6 X


PX@ : Muxluss
7 X
ME@ : ME components 8
H2G@ :
S2G@ : 9 * WWAN

TPM@ : TPM Function. 10 WLAN


BT@ : BT module. 11 Finger Printer

4 ID4@ : LID S4 Function. 12 4

AOAC@ : AOACFunction.
sensor@ : sensor Function. 13 BT

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

SBA@ : SBA Function. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
NOSBA@ : NO SBA Function. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 3 of 48
A B C D E
A B C D E

+1.05VS

PEG_ICOMPI and RCOMPO signals should be shorted and routed

1
with - max length = 500 mils - typical impedance = 43 mohms
1 R6 1
PEG_ICOMPO signals should be routed with - max length = 500 mils
24.9_0402_1% UCPU1I
- typical impedance = 14.5 mohms

2
UCPU1A
G3 PEG_COMP BG17 M4
PEG_ICOMPI VSS[181] VSS[250]
PEG_ICOMPO G1 BG21 VSS[182] VSS[251] M58
14 DMI_CRX_PTX_N0 M2 DMI_RX#[0] PEG_RCOMPO G4 BG24 VSS[183] VSS[252] M6
14 DMI_CRX_PTX_N1 P6 DMI_RX#[1] BG28 VSS[184] VSS[253] N1
14 DMI_CRX_PTX_N2 P1 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] 21 BG37 VSS[185] VSS[254] N17
14 DMI_CRX_PTX_N3 P10 H22 PCIE_CRX_GTX_N15 BG41 N21
DMI_RX#[3] PEG_RX#[0] PCIE_CRX_GTX_N14 VSS[186] VSS[255]
PEG_RX#[1] J21 BG45 VSS[187] VSS[256] N25
14 DMI_CRX_PTX_P0 N3 B22 PCIE_CRX_GTX_N13 BG49 N28
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12 VSS[188] VSS[257]
14 DMI_CRX_PTX_P1 P7 DMI_RX[1] PEG_RX#[3] D21 PEG Static Lane Reversal - CFG2 is for the 16x BG53 VSS[189] VSS[258] N33

DMI
14 DMI_CRX_PTX_P2 P3 A19 PCIE_CRX_GTX_N11 BG9 N36
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10 VSS[190] VSS[259]
14 DMI_CRX_PTX_P3 P11 DMI_RX[3] PEG_RX#[5] D17 C29 VSS[191] VSS[260] N40
B14 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches C35 N43
PEG_RX#[6] PCIE_CRX_GTX_N8 VSS[192] VSS[261]
14 DMI_CTX_PRX_N0 K1 DMI_TX#[0] PEG_RX#[7] D13 CFG2 socket pin map definition C40 VSS[193] VSS[262] N47
M8 A11 PCIE_CRX_GTX_N7 D10 N48
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS[194] VSS[263]
N4 B10 PCIE_CRX_GTX_N6 D14 N51
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS[195] VSS[264]
R2 G8 PCIE_CRX_GTX_N5 0:Lane Reversed D18 N52
14

14
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 K3
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
A8
B6
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 * D22
D26
VSS[196]
VSS[197]
VSS[198]
VSS[265]
VSS[266]
VSS[267]
N56
N61
M7 H8 PCIE_CRX_GTX_N2 D29 P14
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS[199] VSS[268]
P4 E5 PCIE_CRX_GTX_N1 D35 P16
14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS[200] VSS[269]
T3 K7 PCIE_CRX_GTX_N0 D4 P18
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS[201] VSS[270]
PCIE_CRX_GTX_P[0..15] 21 D40 VSS[202] VSS[271] P21
K22 PCIE_CRX_GTX_P15 D43 P58
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
K19
C21
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P13
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[272]
VSS[273]
VSS[274]
P59
P9
FDI_CTX_PRX_N0 U7 D19 PCIE_CRX_GTX_P12 D54 R17
14 FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] VSS[206] VSS[275]
FDI_CTX_PRX_N1 W11 C19 PCIE_CRX_GTX_P11 D58 R20
2 14 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] VSS[207] VSS[276] 2
FDI_CTX_PRX_N2 W1 D16 PCIE_CRX_GTX_P10 D6 R4
14 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS[208] VSS[277]
FDI_CTX_PRX_N3 AA6 C13 PCIE_CRX_GTX_P9 E25 R46
14 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS[209] VSS[278]
FDI_CTX_PRX_N4 W6 D12 PCIE_CRX_GTX_P8 E29 T1
14 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] VSS[210] VSS[279]
FDI_CTX_PRX_N5 PCIE_CRX_GTX_P7
PCI EXPRESS -- GRAPHICS

14 FDI_CTX_PRX_N5 V4 FDI1_TX#[1] PEG_RX[8] C11 E3 VSS[211] VSS[280] T47


FDI_CTX_PRX_N6 Y2 C9 PCIE_CRX_GTX_P6 E35 T50
14 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS[212] VSS[281]
FDI_CTX_PRX_N7 AC9 F8 PCIE_CRX_GTX_P5 E40 T51
14 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] VSS[213] VSS[282]
Intel(R) FDI

C8 PCIE_CRX_GTX_P4 F13 T52


PEG_RX[11] PCIE_CRX_GTX_P3 VSS[214] VSS[283]
PEG_RX[12] C5 F15 VSS[215] VSS[284] T53
FDI_CTX_PRX_P0 U6 H6 PCIE_CRX_GTX_P2 F19 T55
14 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS[216] VSS[285]
FDI_CTX_PRX_P1 W10 F6 PCIE_CRX_GTX_P1 F29 T56
14 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS[217] VSS[286]
FDI_CTX_PRX_P2 W3 K6 PCIE_CRX_GTX_P0 F35 U13
14 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS[218] VSS[287]
FDI_CTX_PRX_P3 AA7 F40 U8
14 FDI_CTX_PRX_P3 FDI0_TX[3] PX@ PCIE_CTX_GRX_N[0..15] 21 VSS[219] VSS[288]
FDI_CTX_PRX_P4 W7 G22 PCIE_CTX_GRX_C_N15 C1 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N15 F55 V20
14 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] PX@ VSS[220] VSS[289]
FDI_CTX_PRX_P5 T4 C23 PCIE_CTX_GRX_C_N14 C2 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N14 G51 V61
14 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PX@ VSS[221] VSS[290]
FDI_CTX_PRX_P6 AA3 D23 PCIE_CTX_GRX_C_N13 C3 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N13 G6 W13
14 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] PX@ VSS[222] VSS[291]
FDI_CTX_PRX_P7 AC8 F21 PCIE_CTX_GRX_C_N12 C4 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N12 G61 W15
14 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PX@ VSS[223] VSS[292]
H19 PCIE_CTX_GRX_C_N11 C5 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N11 H10 W18
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N10 VSS[224] VSS[293]
14 FDI_FSYNC0 AA11 FDI0_FSYNC PEG_TX#[5] C17 2 1 H14 VSS[225] VSS[294] W21
FDI_FSYNC1 AC12 K15 PCIE_CTX_GRX_C_N9 C7 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N9 H17 W46
14 FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] PX@ VSS[226] VSS[295]
F17 PCIE_CTX_GRX_C_N8 C8 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N8 H21 W8
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N7 VSS[227] VSS[296]
14 FDI_INT U11 FDI_INT PEG_TX#[8] F14 2 1 H4 VSS[228] VSS[297] Y4
A15 PCIE_CTX_GRX_C_N6 C10 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N6 H53 Y47
FDI_LSYNC0 PEG_TX#[9] PCIE_CTX_GRX_C_N5 C11 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N5 VSS[229] VSS[298]
14 FDI_LSYNC0 AA10 FDI0_LSYNC PEG_TX#[10] J14 2 1 H58 VSS[230] VSS[299] Y58
FDI_LSYNC1 AG8 H13 PCIE_CTX_GRX_C_N4 C12 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N4 J1 Y59
14 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] PX@ VSS[231] VSS[300]
M10 PCIE_CTX_GRX_C_N3 C13 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_N3 J49 G48
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N2 VSS[232] VSS[301]
PEG_TX#[13] F10 2 1 J55 VSS[233]
+1.05VS D9 PCIE_CTX_GRX_C_N1 C15 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N1 K11
PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_N0 VSS[234]
PEG_TX#[15] J4 2 1 K21 VSS[235]
1 2 +EDP_COM AF3 K51
eDP_COMPIO PX@ PCIE_CTX_GRX_P[0..15] 21 VSS[236]
R7 24.9_0402_1% AD2 F22 PCIE_CTX_GRX_C_P15 C17 2 1 0.1U_0402_10V6K PCIE_CTX_GRX_P15 K8 A5 T90 PAD @
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_C_P14 C18 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P14 VSS[237] VSS_NCTF_1 T91 PAD @
AG11 eDP_HPD# PEG_TX[1] A23 2 1 L16 VSS[238] VSS_NCTF_2 A57
D24 PCIE_CTX_GRX_C_P13 C19 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P13 L20 BC61
3 PEG_TX[2] PCIE_CTX_GRX_C_P12 C20 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P12 VSS[239] VSS_NCTF_3 3
PEG_TX[3] E21 2 1 L22 VSS[240] VSS_NCTF_4 BD3
AG4 G19 PCIE_CTX_GRX_C_P11 C21 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P11 L26 BD59
eDP_AUX# PEG_TX[4] PCIE_CTX_GRX_C_P10 C22 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P10 VSS[241] VSS_NCTF_5
AF4 B18 2 1 L30 BE4

NCTF
eDP_AUX PEG_TX[5] PCIE_CTX_GRX_C_P9 C23 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P9 VSS[242] VSS_NCTF_6
PEG_TX[6] K17 2 1 L34 VSS[243] VSS_NCTF_7 BE58
eDP

G17 PCIE_CTX_GRX_C_P8 C24 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P8 L38 BG5 T95 PAD @
PEG_TX[7] PCIE_CTX_GRX_C_P7 C25 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P7 VSS[244] VSS_NCTF_8 T96 PAD @
AC3 eDP_TX#[0] PEG_TX[8] E14 2 1 L43 VSS[245] VSS_NCTF_9 BG57
AC4 C15 PCIE_CTX_GRX_C_P6 C26 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P6 L48 C3 T97 PAD @
eDP_TX#[1] PEG_TX[9] PCIE_CTX_GRX_C_P5 C27 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P5 VSS[246] VSS_NCTF_10
AE11 eDP_TX#[2] PEG_TX[10] K13 2 1 L61 VSS[247] VSS_NCTF_11 C58
AE7 G13 PCIE_CTX_GRX_C_P4 C28 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P4 M11 D59
eDP_TX#[3] PEG_TX[11] PCIE_CTX_GRX_C_P3 C29 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P3 VSS[248] VSS_NCTF_12 T103PAD @
PEG_TX[12] K10 2 1 M15 VSS[249] VSS_NCTF_13 E1
AC1 G10 PCIE_CTX_GRX_C_P2 C30 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P2 E61 T98 PAD @
eDP_TX[0] PEG_TX[13] PCIE_CTX_GRX_C_P1 C31 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P1 VSS_NCTF_14
AA4 eDP_TX[1] PEG_TX[14] D8 2 1
AE10 K4 PCIE_CTX_GRX_C_P0 C32 2 1 PX@ 0.1U_0402_10V6K PCIE_CTX_GRX_P0
eDP_TX[2] PEG_TX[15]
AE6 eDP_TX[3]

IVY-BRIDGE_BGA1023 IVY-BRIDGE_BGA1023
CPU1@ CPU1@

UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1

CPU5@ CPU6@ CPU7@ CPU8@ CPU9@ CPU10@ CPU11@


SAN i3-2350M 2.3GHz
i3-3110M 2.4GHz i5-3210M 2.5GHz i5-3320M 2.6GHz i5-3360M 2.8GHz i7-3520M 2.9GHz SAN i2-2370M 2.4GHz
SA00004QX50 SA00005M820 SA00005JZ20 SA00005JL00 SA00005Jk50 SA00005JJ30 SA000059I30
4 4

UCPU1 UCPU1 UCPU1

Security Classification Compal Secret Data Compal Electronics, Inc.


CPU2@ CPU3@ CPU4@ 2011/05/16 2013/05/16 Title
Issued Date Deciphered Date
2.3G 2.6G i5-2430M
SA000058T00 SA000059K10 SA00004QV00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 4 of 48
A B C D E
5 4 3 2 1

UCPU1B

J3 CLK_CPU_DMI_R 33_0402_5% R8 1 2
PROC_DETECT (Processor Detect): pulled to BCLK CLK_CPU_DMI 13
H2 CLK_CPU_DMI#_R 33_0402_5% R12 1 2
BCLK# CLK_CPU_DMI# 13

MISC
ground on the processor package. There is no

CLOCKS
D D
connection to the processor silicon for this F49
signal. System board designers may use this 17 H_SNB_IVB# PROC_SELECT#
AG3 R9 2 1 1K_0402_5%
signal to determine if the processor is DPLL_REF_CLK R10
DPLL_REF_CLK# AG1 2 1 1K_0402_5% +1.05VS
present R11 2 110K_0402_5% C57 PROC_DETECT#
+1.05VS @

PAD~D T1 @ H_CATERR# C49 CATERR#

THERMAL
R13
62_0402_5% A48 AT30 H_DRAMRST#
17,43 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6

1
R15 BF44 SM_RCOMP0 140_0402_1% 1 2 R16 @ C82

DDR3
MISC
H_PROCHOT#_R SM_RCOMP[0] SM_RCOMP1 25.5_0402_1%1
43 H_PROCHOT# 1 2 C45 PROCHOT# SM_RCOMP[1] BE43 2 R17
56_0402_5% BG43 SM_RCOMP2 200_0402_1% 1 2 R18 100P_0402_50V8J
SM_RCOMP[2] 2
DDR3 Compensation Signals
H_THERMTRIP# D45
17 H_THERMTRIP# THERMTRIP#
PU/PD for JTAG signals +1.05VS
N53 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# N55 ESD XDP_TMS R20 2 1 51_0402_5%
TCK L56 XDP_TCK C Reserve XDP_TDI R21 2 1 51_0402_5%
L55 XDP_TMS XDP_TDO R22 2 1 51_0402_5%
TMS

PWR MANAGEMENT
J58 XDP_TRST#
TRST# +3VS XDP_TCK R24 2 1 51_0402_5%

JTAG & BPM


14 H_PM_SYNC C48 M60 XDP_TDI XDP_TRST# R25 2 1 51_0402_5%
PM_SYNC TDI

1
L59 XDP_TDO
TDO R27
1K_0402_5%
17 H_CPUPWRGD R14 1 2 0_0402_5% H_CPUPWRGD_R B46
C short@ UNCOREPWRGOOD XDP_DBRESET# C
K58 XDP_DBRESET# 12,14

2
DBR#
2

1 R29
C5236 R28 1 2 VDDPWRGOOD_R BE45 G58 XDP_BPM#0
@ 130_0402_1% SM_DRAMPWROK BPM#[0] XDP_BPM#1
10K_0402_5% BPM#[1] E55
100P_0402_50V8J E59 XDP_BPM#2 JDB1
2 BPM#[2] XDP_BPM#3 XDP_PREQ#
G55 1
1

BPM#[3] XDP_BPM#4 XDP_PRDY# 1


BPM#[4] G59 2 2
BUF_CPU_RST# D44 H60 XDP_BPM#5 3
RESET# BPM#[5] XDP_BPM#6 3
BPM#[6] J59 4 4
J61 XDP_BPM#7 5
BPM#[7] 5
ESD 6
7
6
7
C Reserve 8 8
9 9
H_CPUPWRGD R52 @ 1K_0402_1%
1 2 10 10
R531 1 @ 2 0_0402_5% 11
12,14,43 PBTN_OUT# @ 11
IVY-BRIDGE_BGA1023 R54 1 2 1K_0402_1% 12
+1.05VS 7 XDP_CFG0 @ 12
CPU1@ 14 SYS_PWROK R397 1 2 0_0402_5% 13
R389 @ 0_0402_5% CLK_XDP_CLK_R 13
13 CLK_XDP_CLK 1 2 14 14
R400 @ 0_0402_5% CLK_XDP_CLK#_R
13 CLK_XDP_CLK# 1 2 15 15
+1.05VS 16
PCH_PLTRST# R55 1 @ 16
2 1K_0402_1% 17 17
XDP_DBRESET#
0110 Modify for S5 18
19
18
XDP_TDO 19
20 20

1
+3VALW C5237 XDP_TRST#
Buffered reset to CPU 0.1U_0402_16V4Z XDP_TDI
21 21
22 22
@ XDP_TMS 23

2
+1.5V_CPU_VDDQ 23
24 24
1

C33 +3VS 25 25
1

0.1U_0402_16V4Z XDP_TCK 26
@ R30 26
27
2

+3VS 200_0402_5% G1
U1 +1.05VS ESD 28 G2

1
B
R31
C34 R532, ACES_88717-2601 B
2
5

10K_0402_5% @ 0.1U_0402_16V4Z ME@


C39 Reserve
1

1 2 1
P

2
@ B
O 4PM_SYS_PWRGD_BUF R32
14 PM_DRAM_PWRGD 2 75_0402_5%
A
G

5
74AHC1G09GW_TSSOP5 R34 U3
3

43_0402_5% 1

P
@ R33 BUF_CPU_RST# BUFO_CPU_RST# NC
1 2 4 Y
39_0402_5%
A 2PCH_PLTRST# PCH_PLTRST# 16,45

G
R532 1 2 0_0402_5% SN74LVC1G07DCKR_SC70-5
1 2

C38

3
0.1U_0402_16V4Z
D @
2

9 RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# 2
G
Q4 S
2N7002K_SOT23-3
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 5 of 48
5 4 3 2 1
5 4 3 2 1

UCPU1C
D D
10 DDR_A_D[0..63]
UCPU1D
DDR_A_D0 AG6 SA_DQ[0] 11 DDR_B_D[0..63]
DDR_A_D1 AJ6 AU36 M_CLK_DDR0
SA_DQ[1] SA_CK[0] M_CLK_DDR0 10
DDR_A_D2 AP11 AV36 M_CLK_DDR#0 DDR_B_D0 AL4
SA_DQ[2] SA_CK#[0] M_CLK_DDR#0 10 SB_DQ[0]
DDR_A_D3 AL6 AY26 DDR_CKE0_DIMMA DDR_B_D1 AL1 BA34 M_CLK_DDR2
SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA 10 SB_DQ[1] SB_CK[0] M_CLK_DDR2 11
DDR_A_D4 AJ10 DDR_B_D2 AN3 AY34 M_CLK_DDR#2
SA_DQ[4] SB_DQ[2] SB_CK#[0] M_CLK_DDR#2 11
DDR_A_D5 AJ8 DDR_B_D3 AR4 AR22 DDR_CKE2_DIMMB
SA_DQ[5] SB_DQ[3] SB_CKE[0] DDR_CKE2_DIMMB 11
DDR_A_D6 AL8 DDR_B_D4 AK4
DDR_A_D7 SA_DQ[6] DDR_B_D5 SB_DQ[4]
AL7 SA_DQ[7] AK3 SB_DQ[5]
DDR_A_D8 AR11 DDR_B_D6 AN4
DDR_A_D9 SA_DQ[8] M_CLK_DDR1 DDR_B_D7 SB_DQ[6]
AP6 SA_DQ[9] SA_CK[1] AT40 M_CLK_DDR1 10 AR1 SB_DQ[7]
DDR_A_D10 AU6 AU40 M_CLK_DDR#1 DDR_B_D8 AU4
SA_DQ[10] SA_CK#[1] M_CLK_DDR#1 10 SB_DQ[8]
DDR_A_D11 AV9 BB26 DDR_CKE1_DIMMA DDR_B_D9 AT2 BA36 M_CLK_DDR3
SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA 10 SB_DQ[9] SB_CK[1] M_CLK_DDR3 11
DDR_A_D12 AR6 DDR_B_D10 AV4 BB36 M_CLK_DDR#3
SA_DQ[12] SB_DQ[10] SB_CK#[1] M_CLK_DDR#3 11
DDR_A_D13 AP8 DDR_B_D11 BA4 BF27 DDR_CKE3_DIMMB
SA_DQ[13] SB_DQ[11] SB_CKE[1] DDR_CKE3_DIMMB 11
DDR_A_D14 AT13 DDR_B_D12 AU3
DDR_A_D15 SA_DQ[14] DDR_B_D13 SB_DQ[12]
AU13 SA_DQ[15] AR3 SB_DQ[13]
DDR_A_D16 BC7 DDR_B_D14 AY2
DDR_A_D17 SA_DQ[16] DDR_CS0_DIMMA# DDR_B_D15 SB_DQ[14]
BB7 SA_DQ[17] SA_CS#[0] BB40 DDR_CS0_DIMMA# 10 BA3 SB_DQ[15]
DDR_A_D18 BA13 BC41 DDR_CS1_DIMMA# DDR_B_D16 BE9
SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# 10 SB_DQ[16]
DDR_A_D19 BB11 DDR_B_D17 BD9 BE41 DDR_CS2_DIMMB#
SA_DQ[19] SB_DQ[17] SB_CS#[0] DDR_CS2_DIMMB# 11
DDR_A_D20 BA7 DDR_B_D18 BD13 BE47 DDR_CS3_DIMMB#
SA_DQ[20] SB_DQ[18] SB_CS#[1] DDR_CS3_DIMMB# 11
DDR_A_D21 BA9 DDR_B_D19 BF12
DDR_A_D22 SA_DQ[21] DDR_B_D20 SB_DQ[19]
BB9 SA_DQ[22] BF8 SB_DQ[20]
DDR_A_D23 AY13 DDR_B_D21 BD10
DDR_A_D24 SA_DQ[23] M_ODT0 DDR_B_D22 SB_DQ[21]
AV14 SA_DQ[24] SA_ODT[0] AY40 M_ODT0 10 BD14 SB_DQ[22]
DDR_A_D25 AR14 BA41 M_ODT1 DDR_B_D23 BE13
SA_DQ[25] SA_ODT[1] M_ODT1 10 SB_DQ[23]
DDR_A_D26 AY17 DDR_B_D24 BF16 AT43 M_ODT2
SA_DQ[26] SB_DQ[24] SB_ODT[0] M_ODT2 11
DDR_A_D27 AR19 DDR_B_D25 BE17 BG47 M_ODT3
SA_DQ[27] SB_DQ[25] SB_ODT[1] M_ODT3 11
DDR_A_D28 BA14 DDR_B_D26 BE18
DDR_A_D29 SA_DQ[28] DDR_B_D27 SB_DQ[26]
AU14 SA_DQ[29] BE21 SB_DQ[27]
DDR_A_D30 BB14 DDR_B_D28 BE14
SA_DQ[30] DDR_A_DQS#[0..7] 10 SB_DQ[28]
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D29 BG14
DDR_A_D32 SA_DQ[31] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D30 SB_DQ[29]
C
BA45 SA_DQ[32] SA_DQS#[1] AR8 BG18 SB_DQ[30] DDR_B_DQS#[0..7] 11 C
DDR_A_D33 AR43 AV11 DDR_A_DQS#2 DDR_B_D31 BF19 AL3 DDR_B_DQS#0
DDR_A_D34 SA_DQ[33] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D32 SB_DQ[31] SB_DQS#[0] DDR_B_DQS#1
AW48 SA_DQ[34] SA_DQS#[3] AT17 BD50 SB_DQ[32] SB_DQS#[1] AV3
DDR_A_D35 BC48 AV45 DDR_A_DQS#4 DDR_B_D33 BF48 BG11 DDR_B_DQS#2
DDR_A_D36 SA_DQ[35] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D34 SB_DQ[33] SB_DQS#[2] DDR_B_DQS#3
BC45 SA_DQ[36] SA_DQS#[5] AY51 BD53 SB_DQ[34] SB_DQS#[3] BD17
DDR_A_D37 AR45 AT55 DDR_A_DQS#6 DDR_B_D35 BF52 BG51 DDR_B_DQS#4
DDR SYSTEM MEMORY A

DDR_A_D38 SA_DQ[37] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D36 SB_DQ[35] SB_DQS#[4] DDR_B_DQS#5


AT48 SA_DQ[38] SA_DQS#[7] AK55 BD49 SB_DQ[36] SB_DQS#[5] BA59
DDR_A_D39 AY48 DDR_B_D37 BE49 AT60 DDR_B_DQS#6
SA_DQ[39] SB_DQ[37] SB_DQS#[6]

DDR SYSTEM MEMORY B


DDR_A_D40 BA49 DDR_B_D38 BD54 AK59 DDR_B_DQS#7
DDR_A_D41 SA_DQ[40] DDR_B_D39 SB_DQ[38] SB_DQS#[7]
AV49 SA_DQ[41] BE53 SB_DQ[39]
DDR_A_D42 BB51 DDR_B_D40 BF56
DDR_A_D43 SA_DQ[42] DDR_B_D41 SB_DQ[40]
AY53 SA_DQ[43] BE57 SB_DQ[41]
DDR_A_D44 BB49 DDR_B_D42 BC59
SA_DQ[44] DDR_A_DQS[0..7] 10 SB_DQ[42]
DDR_A_D45 AU49 AJ11 DDR_A_DQS0 DDR_B_D43 AY60
DDR_A_D46 SA_DQ[45] SA_DQS[0] DDR_A_DQS1 DDR_B_D44 SB_DQ[43]
BA53 SA_DQ[46] SA_DQS[1] AR10 BE54 SB_DQ[44]
DDR_A_D47 BB55 AY11 DDR_A_DQS2 DDR_B_D45 BG54
SA_DQ[47] SA_DQS[2] SB_DQ[45] DDR_B_DQS[0..7] 11
DDR_A_D48 BA55 AU17 DDR_A_DQS3 DDR_B_D46 BA58 AM2 DDR_B_DQS0
DDR_A_D49 SA_DQ[48] SA_DQS[3] DDR_A_DQS4 DDR_B_D47 SB_DQ[46] SB_DQS[0] DDR_B_DQS1
AV56 SA_DQ[49] SA_DQS[4] AW45 AW59 SB_DQ[47] SB_DQS[1] AV1
DDR_A_D50 AP50 AV51 DDR_A_DQS5 DDR_B_D48 AW58 BE11 DDR_B_DQS2
DDR_A_D51 SA_DQ[50] SA_DQS[5] DDR_A_DQS6 DDR_B_D49 SB_DQ[48] SB_DQS[2] DDR_B_DQS3
AP53 SA_DQ[51] SA_DQS[6] AT56 AU58 SB_DQ[49] SB_DQS[3] BD18
DDR_A_D52 AV54 AK54 DDR_A_DQS7 DDR_B_D50 AN61 BE51 DDR_B_DQS4
DDR_A_D53 SA_DQ[52] SA_DQS[7] DDR_B_D51 SB_DQ[50] SB_DQS[4] DDR_B_DQS5
AT54 SA_DQ[53] AN59 SB_DQ[51] SB_DQS[5] BA61
DDR_A_D54 AP56 DDR_B_D52 AU59 AR59 DDR_B_DQS6
DDR_A_D55 SA_DQ[54] DDR_B_D53 SB_DQ[52] SB_DQS[6] DDR_B_DQS7
AP52 SA_DQ[55] AU61 SB_DQ[53] SB_DQS[7] AK61
DDR_A_D56 AN57 DDR_B_D54 AN58
DDR_A_D57 SA_DQ[56] DDR_B_D55 SB_DQ[54]
AN53 SA_DQ[57] AR58 SB_DQ[55]
DDR_A_D58 AG56 DDR_B_D56 AK58
DDR_A_D59 SA_DQ[58] DDR_B_D57 SB_DQ[56]
AG53 SA_DQ[59] AL58 SB_DQ[57]
DDR_A_D60 AN55 DDR_B_D58 AG58
SA_DQ[60] DDR_A_MA[0..15] 10 SB_DQ[58]
DDR_A_D61 AN52 BG35 DDR_A_MA0 DDR_B_D59 AG59
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AG55 SA_DQ[62] SA_MA[1] BB34 AM60 SB_DQ[60] DDR_B_MA[0..15] 11
DDR_A_D63 AK56 BE35 DDR_A_MA2 DDR_B_D61 AL59 BF32 DDR_B_MA0
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
SA_MA[3] BD35 AF61 SB_DQ[62] SB_MA[1] BE33
AT34 DDR_A_MA4 DDR_B_D63 AH60 BD33 DDR_B_MA2
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[5] AU34 SB_MA[3] AU30
B BB32 DDR_A_MA6 BD30 DDR_B_MA4 B
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
10 DDR_A_BS0 BD37 SA_BS[0] SA_MA[7] AT32 SB_MA[5] AV30
BF36 AY32 DDR_A_MA8 BG30 DDR_B_MA6
10 DDR_A_BS1 SA_BS[1] SA_MA[8] SB_MA[6]
BA28 AV32 DDR_A_MA9 BG39 BD29 DDR_B_MA7
10 DDR_A_BS2 SA_BS[2] SA_MA[9] 11 DDR_B_BS0 SB_BS[0] SB_MA[7]
BE37 DDR_A_MA10 BD42 BE30 DDR_B_MA8
SA_MA[10] 11 DDR_B_BS1 SB_BS[1] SB_MA[8]
BA30 DDR_A_MA11 AT22 BE28 DDR_B_MA9
SA_MA[11] 11 DDR_B_BS2 SB_BS[2] SB_MA[9]
BC30 DDR_A_MA12 BD43 DDR_B_MA10
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
10 DDR_A_CAS# BE39 SA_CAS# SA_MA[13] AW41 SB_MA[11] AT28
BD39 AY28 DDR_A_MA14 AV28 DDR_B_MA12
10 DDR_A_RAS# SA_RAS# SA_MA[14] SB_MA[12]
AT41 AU26 DDR_A_MA15 AV43 BD46 DDR_B_MA13
10 DDR_A_WE# SA_WE# SA_MA[15] 11 DDR_B_CAS# SB_CAS# SB_MA[13]
BF40 AT26 DDR_B_MA14
11 DDR_B_RAS# SB_RAS# SB_MA[14]
BD45 AU22 DDR_B_MA15
11 DDR_B_WE# SB_WE# SB_MA[15]

IVY-BRIDGE_BGA1023
CPU1@ IVY-BRIDGE_BGA1023
+1.5V CPU1@

@ R36
1

0_0402_5%
1 2 R37
1K_0402_5%

R38
2

1K_0402_5%
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# 10,11


2

Q5
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A A

9,13 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH


1

C35
0.047U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 6 of 48
5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor

CFG2

UCPU1E

1
D D
R41
1K_0402_1%~D
CFG0 B50 N59 PX@
5 XDP_CFG0 CFG[0] BCLK_ITP
C51 N58

2
CFG2 CFG[1] BCLK_ITP#
B54 CFG[2]
D53 CFG[3]
CFG4 A51 N42
CFG5 CFG[4] RSVD30
C53 CFG[5] RSVD31 L42
CFG6 C55 L45
CFG7 CFG[6] RSVD32
H49 CFG[7] RSVD33 L47 PEG Static Lane Reversal - CFG2 is for the 16x
A55 CFG[8]
H51 CFG[9]
K49 CFG[10] RSVD34 M13 1:(Default) Normal Operation; Lane #
+CPU_CORE
K53 CFG[11] RSVD35 M14 CFG2 definition matches socket pin map
R43 F53 U14
49.9_0402_1% CFG[12] RSVD36 definition
G53 CFG[13] RSVD37 W14
2 1 L51
F51
CFG[14] RSVD38 P13 *0:Lane Reversed
CFG[15]
2

D52 CFG[16]
R91 L53 AT49 CFG4
100_0402_1%~D CFG[17] RSVD39
RSVD40 K24
@

1
RESERVED
VCC_VAL_SENSE H43
1

VCC_VAL_SENSE
2 R44 1 VSS_VAL_SENSE K43 VSS_VAL_SENSE RSVD41 AH2 @ R42
AG13 1K_0402_1%~D
49.9_0402_1% RSVD42
RSVD43 AM14
VCC_AXG_VAL_SENSE H45 AM15

2
VSS_AXG_VAL_SENSE VAXG_VAL_SENSE RSVD44
K45 VSSAXG_VAL_SENSE

RSVD45 N50
T20 @ F48
PAD~D VCC_DIE_SENSE
+VCC_GFXCORE_AXG Display Port Presence Strap
C
H48 RSVD6 C
R45 K48
49.9_0402_1% RSVD7
2 1 DC_TEST_A4 A4
C4 CFG4
* 1 : Disabled; No Physical Display Port
DC_TEST_C4 attached to Embedded Display Port
2

BA19 RSVD8 DC_TEST_D3 D3


R89 AV19 D1
RSVD9 DC_TEST_D1
100_0402_1%~D AT21 RSVD10 DC_TEST_A58 A58 0 : Enabled; An external Display Port device is
@ BB21 A59
BB19
RSVD11 DC_TEST_A59
C59
connected to the Embedded Display Port
1

RSVD12 DC_TEST_C59
2 R46 1 AY21 RSVD13 DC_TEST_A61 A61
BA22 RSVD14 DC_TEST_C61 C61
49.9_0402_1% AY22 D61
RSVD15 DC_TEST_D61 CFG6
AU19 RSVD16 DC_TEST_BD61 BD61
AU21 RSVD17 DC_TEST_BE61 BE61
BD21 BE59 CFG5
RSVD18 DC_TEST_BE59
BD22 RSVD19 DC_TEST_BG61 BG61

1
BD25 RSVD20 DC_TEST_BG59 BG59
BD26 BG58 @ R49 @ R50
RSVD21 DC_TEST_BG58 1K_0402_1%~D 1K_0402_1%~D
BG22 RSVD22 DC_TEST_BG4 BG4
BE22 RSVD23 DC_TEST_BG3 BG3
BG26 BE3

2
RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
BF23 RSVD26 DC_TEST_BE1 BE1
BE24 RSVD27 DC_TEST_BD1 BD1

IVY-BRIDGE_BGA1023
CPU1@ PCIE Port Bifurcation Straps

*11: (Default) x16 - Device 1 functions 1 and 2 disabled


CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
B B
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
@ R51
1K_0402_1%~D

2
PEG DEFER TRAINING

CFG7
*1: (Default) PEG Train immediately
following xxRESETB de assertion

0: PEG Wait for BIOS for training

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 7 of 48
5 4 3 2 1
5 4 3 2 1

UCPU1F POWER +1.05VS

+CPU_CORE
VCCIO[1] AF46
VCCIO[3] AG48
VCCIO[4] AG50
A26 VCC[1] VCCIO[5] AG51
D A29 VCC[2] VCCIO[6] AJ17 D
A31 VCC[3] VCCIO[7] AJ21
A34 VCC[4] VCCIO[8] AJ25
CPU_CORE A35
A38
VCC[5]
VCC[6]
VCCIO[9]
VCCIO[10]
AJ43
AJ47
A39 AK50
GFX_CORE A42
VCC[7]
VCC[8]
VCCIO[11]
VCCIO[12] AK51
C26 VCC[9] VCCIO[13] AL14
VCCP1.05 C27
C32
VCC[10] VCCIO[14] AL15
AL16
VCC[11] VCCIO[15]
C34 VCC[12] VCCIO[16] AL20
C37 VCC[13] VCCIO[17] AL22
VGA_CORE C39
C42
VCC[14]
VCC[15]
VCCIO[18]
VCCIO[19]
AL26
AL45
D27 VCC[16] VCCIO[20] AL48
D32 AM16
All Capacitor place on Power side. D34
VCC[17]
VCC[18]
VCCIO[21]
VCCIO[22] AM17
D37 VCC[19] VCCIO[23] AM21
D39 AM43

PEG IO AND DDR IO


VCC[20] VCCIO[24]
D42 VCC[21] VCCIO[25] AM47
E26 VCC[22] VCCIO[26] AN20
E28 VCC[23] VCCIO[27] AN42
E32 VCC[24] VCCIO[28] AN45
E34 VCC[25] VCCIO[29] AN48
E37 VCC[26]
E38 VCC[27]

CORE SUPPLY
F25 VCC[28]
F26 VCC[29]
F28 VCC[30]
F32 VCC[31]
F34 VCC[32]
F37 VCC[33] VCCIO[30] AA14
F38 VCC[34] VCCIO[31] AA15
F42 VCC[35] VCCIO[32] AB17
C
G42 VCC[36] VCCIO[33] AB20 C
H25 VCC[37] VCCIO[34] AC13
H26 VCC[38] VCCIO[35] AD16
H28 VCC[39] VCCIO[36] AD18
H29 VCC[40] VCCIO[37] AD21
H32 VCC[41] VCCIO[38] AE14
H34 VCC[42] VCCIO[39] AE15
H35 VCC[43] VCCIO[40] AF16
H37 VCC[44] VCCIO[41] AF18
H38 VCC[45] VCCIO[42] AF20
H40 VCC[46] VCCIO[43] AG15
J25 VCC[47] VCCIO[44] AG16
J26 VCC[48] VCCIO[45] AG17
J28 VCC[49] VCCIO[46] AG20
J29 VCC[50] VCCIO[47] AG21
J32 VCC[51] VCCIO[48] AJ14
J34 AJ15 Chief river VCCIO_SEL pull-H
VCC[52] VCCIO[49]
J35 VCC[53]
J37 VCC[54]
J38 VCC[55]
J40 +1.05VS +3VS
VCC[56]
J42 VCC[57]
K26 VCC[58] VCCIO50 W16

1
K27 VCC[59] VCCIO51 W17
K29 R5157
VCC[60]
K32 VCC[61] 10K_0402_5%
K34 VCC[62]
K35

2
VCC[63]
K37 VCC[64]
K39 VCC[66]
K42 BC22 H_VCCP_SEL
VCC[67] VCCIO_SEL
L25 VCC[68]
L28 VCC[69]
L33 VCC[70]
L36 +1.05VS
VCC[71] +1.05VS
B L40 VCC[72]
B
N26 VCC[73]

RAILS
QUIET
N30 VCC[74] VCCPQE[1] AM25
N34 VCC[75] VCCPQE[2] AN22
N38 VCC[76]

1
1 2
C106 R56 R57 Place the PU
1U_0402_6.3V6K 75_0402_5%
130_0402_1%~D resistors
R58 close to CPU

2
43_0402_5%
A44 H_CPU_SVIDALRT# 1 2
VIDALERT# VR_SVID_ALRT# 57
B43 H_CPU_SVIDCLK R59 2 1 0_0402_5%
VIDSCLK VR_SVID_CLK 57
SVID
VIDSOUT C44 H_CPU_SVIDDAT R60 2 short@ 1 0_0402_5% VR_SVID_DAT 57
short@
+CPU_CORE

1
Place the PU
1 R79 2 R61
resistors
100_0402_1%~D
100_0402_1%~D close to CPU
@

2
VCC_SENSE F43 VCCSENSE_R R62 2 1 0_0402_5% VCCSENSE 57
SENSE LINES

G43 VSSSENSE_R R63 2 short@ 1 0_0402_5%


VSS_SENSE short@ VSSSENSE 57
1 2 +1.05VS

1
R617 10_0402_1% R64 Place the PU
VCCIO_SENSE AN16 VCCIO_SENSE 55 100_0402_1%~D resistors
VSS_SENSE_VCCIO AN17 VSS_SENSE_VCCIO 55
close to VR

2
VSS_SENSE_VCCIO 1 2
A A
R618 10_0402_1%
IVY-BRIDGE_BGA1023

CPU1@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 8 of 48
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V_CPU_VDDQ M3 Support R86 1 @ 2 0_0402_5%


@ J1
+VREF_DQ_DIMMA
1 2

PAD-OPEN 4x4m

D
+V_DDR_REFA_R 3 1
1 2 R66 @ C107
48,55,56 SUSP 0_0402_5% R65 U7 AO4430L_SO8 220_0402_5% 0.1U_0402_10V6K BSS138_NL_SOT23-3

2
Q2204

G
8 1

2
7 2

2
6 3 DRAMRST_CNTRL_PCH
+3VALW +VSB 5

1
D

4
1
2 RUN_ON_CPU1.5VS3#

1
R68 Q7 G R76 1 @ 2 0_0402_5%
D R67 82K_0402_5% 2N7002K_SOT23-3 S D
100K_0402_5% @ +VREF_DQ_DIMMB

3
R175

2
15K_0402_1%

D
RUN_ON_CPU1.5VS3 1 2 +V_DDR_REFB_R 3 1
RUN_ON_CPU1.5VS3#

1
BSS138_NL_SOT23-3

1
Q2205

G
2
1
@ D R69 C108
R71 2 1 0_0402_5% 2 D 330K_0402_5% 0.047U_0603_25V7K
43 CPU1.5V_S3_GATE

2
G 2 @ DRAMRST_CNTRL_PCH 6,13

2
Q6 S G Q8
1 @ 2 2N7002K_SOT23-3 S 2N7002K_SOT23-3
23,43,48,51,53,55,56 SUSP#

3
0_0402_5% R70 @

3
+1.5V_CPU_VDDQ
RUN_ON_CPU1.5VS3# 5 +1.5V
+V_SM_VREF should
have 20 mil trace
POWER

1
width R72 2 @ 1 0_0402_5%
UCPU1G R98 @ R73
+VCC_GFXCORE_AXG 1K_0402_1%~D 1K_0402_1%~D

2
S

D
AY43 +V_SM_VREF_CNT 3 1 +V_SM_VREF
SM_VREF Q11 UCPU1H
AA46

VREF
VAXG[1]

1
AB47 AO3414_SOT23-3
VAXG[2]

1
BE7 +V_DDR_REFA_R C115 @ @ R75

G
AB50

2
VAXG[3] SA_DIMM_VREFDQ

1
AB51 VAXG[4] SB_DIMM_VREFDQ BG7 +V_DDR_REFB_R 0.1U_0402_16V4Z 1K_0402_1%~D
AB52 R92

2
VAXG[5] 1K_0402_1%~D RUN_ON_CPU1.5VS3
AB53 A13 AM38

2
VAXG[6] VSS[1] VSS[91]
AB55 VAXG[7] A17 VSS[2] VSS[92] AM4
AB56 A21 AM42

2
VAXG[8] VSS[3] VSS[93]

1
AB58 VAXG[9] A25 VSS[4] VSS[94] AM45
AB59 @ R173 @ R129 A28 AM48
VAXG[10] 1K_0402_1%~D 1K_0402_1%~D VSS[5] VSS[95]
AC61 VAXG[11] A33 VSS[6] VSS[96] AM58
AD47 VAXG[12] A37 VSS[7] VSS[97] AN1
AD48 A40 AN21

2
VAXG[13] VSS[8] VSS[98]
AD50 VAXG[14] A45 VSS[9] VSS[99] AN25
AD51 AJ28 A49 AN28

- 1.5V RAILS
C VAXG[15] VDDQ[1] VSS[10] VSS[100] C
AD52 VAXG[16] VDDQ[2] AJ33 A53 VSS[11] VSS[101] AN33
AD53 VAXG[17] VDDQ[3] AJ36 A9 VSS[12] VSS[102] AN36
AD55 VAXG[18] VDDQ[4] AJ40 AA1 VSS[13] VSS[103] AN40
AD56 VAXG[19] VDDQ[5] AL30 AA13 VSS[14] VSS[104] AN43
AD58 VAXG[20] VDDQ[6] AL34 AA50 VSS[15] VSS[105] AN47
AD59 VAXG[21] VDDQ[7] AL38 AA51 VSS[16] VSS[106] AN50
AE46 VAXG[22] VDDQ[8] AL42 AA52 VSS[17] VSS[107] AN54
N45 VAXG[23] VDDQ[9] AM33 AA53 VSS[18] VSS[108] AP10
P47 VAXG[24] VDDQ[10] AM36 AA55 VSS[19] VSS[109] AP51
P48 VAXG[25] VDDQ[11] AM40 AA56 VSS[20] VSS[110] AP55
+1.5V_CPU_VDDQ
P50 VAXG[26] VDDQ[12] AN30 AA8 VSS[21] VSS[111] AP7
P51 VAXG[27] VDDQ[13] AN34 AB16 VSS[22] VSS[112] AR13
P52 VAXG[28] VDDQ[14] AN38 AB18 VSS[23] VSS[113] AR17
P53 AR26 AB21 AR21
DDR3

VAXG[29] VDDQ[15] VSS[24] VSS[114]


P55 AR28 AB48 AR41
GRAPHICS

VAXG[30] VDDQ[16] VSS[25] VSS[115]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
P56 VAXG[31] VDDQ[17] AR30 AB61 VSS[26] VSS[116] AR48

1
C129

C130

C131

C135

C134

C133

C137

C136
P61 VAXG[32] VDDQ[18] AR32 AC10 VSS[27] VSS[117] AR61
T48 AR34 + C132 AC14 AR7
VAXG[33] VDDQ[19] VSS[28] VSS[118]

1
T58 AR36 330U_D2_2VM_R9M AC46 AT14
VAXG[34] VDDQ[20] VSS[29] VSS[119]
T59 AR40 AC6 AT19

2
VAXG[35] VDDQ[21] VSS[30] VSS[120]
T61 AV41 AD17 AT36

2
VAXG[36] VDDQ[22] VSS[31] VSS[121]
U46 VAXG[37] VDDQ[23] AW26 C132 AD20 VSS[32] VSS[122] AT4
V47 BA40 AD4 AT45
V48
V50
VAXG[38]
VAXG[39]
VAXG[40]
VDDQ[24]
VDDQ[25]
VDDQ[26]
BB28
BG33
1'S : SGA20331E10
2'S : SGA00002680
AD61
AE13
VSS[33]
VSS[34]
VSS[35]
VSS VSS[123]
VSS[124]
VSS[125]
AT52
AT58
V51 VAXG[41] AE8 VSS[36] VSS[126] AU1
V52 VAXG[42] AF1 VSS[37] VSS[127] AU11
V53 VAXG[43] AF17 VSS[38] VSS[128] AU28
V55 VAXG[44] AF21 VSS[39] VSS[129] AU32
V56 VAXG[45] AF47 VSS[40] VSS[130] AU51
C139
1U_0402_6.3V6K

C140
1U_0402_6.3V6K

C141
1U_0402_6.3V6K

C142
1U_0402_6.3V6K

C143
1U_0402_6.3V6K

C144
1U_0402_6.3V6K

C146
1U_0402_6.3V6K

C147
1U_0402_6.3V6K

C148
1U_0402_6.3V6K

C145
1U_0402_6.3V6K
V58 VAXG[46] AF48 VSS[41] VSS[131] AU7
V59 VAXG[47] AF50 VSS[42] VSS[132] AV17
1

1
W50 VAXG[48] AF51 VSS[43] VSS[133] AV21
W51 VAXG[49] AF52 VSS[44] VSS[134] AV22
W52 AF53 AV34
2

2
VAXG[50] VSS[45] VSS[135]
W53 AF55 AV40
+VCC_GFXCORE_AXG W55
VAXG[51]
VAXG[52] AF56
VSS[46]
VSS[47]
VSS[136]
VSS[137] AV48
W56 VAXG[53] AF58 VSS[48] VSS[138] AV55
W61 VAXG[54] AF59 VSS[49] VSS[139] AW13
Y48 VAXG[55] AG10 VSS[50] VSS[140] AW43
B 0110 BOM change Y61 VAXG[56] AG14
AG18
VSS[51] VSS[141] AW61
AW7
B
VSS[52] VSS[142]
AG47 VSS[53] VSS[143] AY14
+1.5V_CPU_VDDQ
1 R620 2 1 R88 2 AG52 VSS[54] VSS[144] AY19
AG61 VSS[55] VSS[145] AY30
100_0402_1%~D 100_0402_1%~D +1.5V_CPU_VDDQ +1.5V AG7 AY36
VSS[56] VSS[146]
QUIET RAILS

AM28 AH4 AY4


SENSE
LINES

@ VCCDQ[1] VSS[57] VSS[147]


VCC_AXG_SENSE F45 AN26 AH58 AY41
57 VCC_AXG_SENSE VAXG_SENSE VCCDQ[2] VSS[58] VSS[148]
VSS_AXG_SENSE G45 C150 2 1 0.1U_0402_10V7K AJ13 AY45
57 VSS_AXG_SENSE VSSAXG_SENSE VSS[59] VSS[149]
AJ16 VSS[60] VSS[150] AY49
1 2 AJ20 VSS[61] VSS[151] AY55
1 R619 2 C151 2 1 0.1U_0402_10V7K AJ22 VSS[62] VSS[152] AY58
+1.8VS AJ26 AY9
C149 VSS[63] VSS[153]
100_0402_1%~D 1U_0402_6.3V6K AJ30 BA1
1.8V RAIL

C152 VSS[64] VSS[154]


2 1 0.1U_0402_10V7K AJ34 VSS[65] VSS[155] BA11
10U_0603_6.3V6M

BB3 VCCPLL[1] AJ38 VSS[66] VSS[156] BA17


BC1 VCCPLL[2] AJ42 VSS[67] VSS[157] BA21
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

BC4 C157 2 1 0.1U_0402_10V7K AJ45 BA26


VCCPLL[3] VSS[68] VSS[158]
1

1
22U_0805_6.3V6M

C633

AJ48 VSS[69] VSS[159] BA32


C153

C154

C155

@ AJ7 BA48
VSS[70] VSS[160]
AK1 BA51
2

VSS[71] VSS[161]
VDDQ_SENSE BC43 AK52 VSS[72] VSS[162] BB53
VSS_SENSE_VDDQ BA43 AL10 VSS[73] VSS[163] BC13
SENSE LINES

AL13 VSS[74] VSS[164] BC5


L17 VCCSA[1] AL17 VSS[75] VSS[165] BC57
+VCCSA L21 AL21 BD12
VCCSA[2] VSS[76] VSS[166]
N16 VCCSA[3] AL25 VSS[77] VSS[167] BD16
N20 VCCSA[4] AL28 VSS[78] VSS[168] BD19
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

N22 AL33 BD23


SA RAIL

VCCSA[5] VSS[79] VSS[169]


C162

C161

C159

C160

C163

P17 VCCSA[6] AL36 VSS[80] VSS[170] BD27


1

C158 P20 U10 AL40 BD32


VCCSA[7] VCCSA_SENSE +VCCSA_SENSE 54 VSS[81] VSS[171]
1

330U_D2_2VM_R9M~D + R16 AL43 BD36


VCCSA[8] VSS[82] VSS[172]
R18 VCCSA[9] AL47 VSS[83] VSS[173] BD40
1

R21 AL61 BD44


2

VCCSA[10] @ R78 VSS[84] VSS[174]


U15 AM13 BD48
VCCSA VID

VCCSA[11] VSS[85] VSS[175]


V16 VCCSA[12] 0_0402_5%~D AM20 VSS[86] VSS[176] BD52
V17 D48 VCCSA_VID0 AM22 BD56
VCCSA[13] VCCSA_VID[0] VSS[87] VSS[177]
lines

V18 D49 VCCSA_VID1 VID[0] VID[1] 2011 2012 AM26 BD8


2

VCCSA[14] VCCSA_VID[1] 0 0 0.90 V Yes Yes VSS[88] VSS[178]


V21 VCCSA[15] AM30 VSS[89] VSS[179] BE5
W20 0 1 0.80 V Yes Yes AM34 BG13
VCCSA[16] 1 0 0.725 V No Yes VSS[90] VSS[180]
R99 1 1 0.675 V No Yes
A A
0_0402_5%
1 2 H_VCCSA_VID0 54
C164

1U_0402_6.3V6K

C165
1U_0402_6.3V6K

C166
1U_0402_6.3V6K

C167
1U_0402_6.3V6K

C168
1U_0402_6.3V6K

1 short@ 2
IVY-BRIDGE_BGA1023 H_VCCSA_VID1 54
short@
IVY-BRIDGE_BGA1023
1

R100
CPU1@ 0_0402_5%
CPU1@
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/05/16 Deciphered Date 2013/05/16 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 9 of 48
5 4 3 2 1
5 4 3 2 1

+VREF_DQ_DIMMA +1.5V +1.5V +1.5V

PN:SP07000M100 6 DDR_A_D[0..63]

1
H4.0 standard DDR3 SO-DIMM A 6 DDR_A_DQS[0..7]
R80
JDIMM1 1K_0402_1%
6 DDR_A_DQS#[0..7] +VREF_DQ_DIMMA
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1
0.1U_0402_10V6K

3 4 DDR_A_D4
6 DDR_A_MA[0..15]

2
VSS2 DQ4
2.2U_0603_6.3V4Z
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
C169

C170
DDR_A_D1 7 8
DQ1 VSS3
1

D
1 9 VSS4 DQS#0 10 DDR_A_DQS#0 D

1
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 14
2

DDR_A_D2 VSS5 VSS6 DDR_A_D6 R81


15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7 1K_0402_1%
DQ3 DQ7
19 20

2
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 DQ8 DQ12 22
DDR_A_D9 23 24 DDR_A_D13
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,11
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
C C

6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA


CKE0 CKE1 DDR_CKE1_DIMMA 6
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
6 DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11 +1.5V
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
DDR_A_MA8 89 90 DDR_A_MA6
A8 A6

10U_0603_6.3V6M
DDR_A_MA5 91 92 DDR_A_MA4 1
A5 A4

C171

C172

C173

C174

C175

C178

C179

C180

C181

C182

C183

C184
93 VDD7 VDD8 94

1
DDR_A_MA3 95 96 DDR_A_MA2 + C185
DDR_A_MA1 A3 A2 DDR_A_MA0 220U_D2_2VY_R15M
97 A1 A0 98
99 100

2
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1 2 @
6 M_CLK_DDR0 101 CK0 CK1 102 M_CLK_DDR1 6
6 M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 6
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6 +1.5V
6 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# 6
111 VDD13 VDD14 112
6 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# @ @
WE# S0# DDR_CS0_DIMMA# 6

1
6 DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 6
R82
DDR_A_MA13
117
119
VDD15
A13
VDD16
ODT1
118
120 M_ODT1
M_ODT1 6
1K_0402_1% PN : SGA00004L00
6 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CA
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128
0.1U_0402_10V6K

2.2U_0603_6.3V4Z
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C176

C177
B DDR_A_D33 DDR_A_D37 B
131 DQ33 DQ37 132
1

133 VSS29 VSS30 134


DDR_A_DQS#4 135 136 DDR_A_DM4 R83
DDR_A_DQS4 DQS#4 DM4 1K_0402_1% +0.75VS
137 138
2

DQS4 VSS31 DDR_A_D38 DDR_A_DM0


139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39 DDR_A_DM1
141 DQ34 DQ39 142
DDR_A_D35 143 144 DDR_A_DM2
DQ35 VSS33 DDR_A_D44 DDR_A_DM3
145 VSS34 DQ44 146

C186
1U_0402_6.3V6K

C187

C188

1U_0402_6.3V6K
C189

1U_0402_6.3V6K
DDR_A_D40 147 148 DDR_A_D45 DDR_A_DM4
DQ40 DQ45

1U_0402_6.3V6K
DDR_A_D41 149 150 DDR_A_DM5
DQ41 VSS35

1
151 152 DDR_A_DQS#5 DDR_A_DM6
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5 DDR_A_DM7
153 DM5 DQS5 154
155 156

2
DDR_A_D42 VSS37 VSS38 DDR_A_D46
157 DQ42 DQ46 158
DDR_A_D43 159 160 DDR_A_D47
DQ43 DQ47
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
A A
1 R90 2 195 VSS51 VSS52 196
10K_0402_5% 197 198
SA0 EVENT# SMB_DATA_S3
+3VS 199 VDDSPD SDA 200 SMB_DATA_S3 11,13,41,44
2.2U_0603_6.3V4Z

0.1U_0402_10V6K

201 202 SMB_CLK_S3


SA1 SCL SMB_CLK_S3 11,13,41,44
C190

C191

203 VTT1 VTT2 204 +0.75VS


1

1
10K_0402_5%

R93

@ 205 206
G1 G2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

BELLW_80011-1021
ME@ 2010/08/25 2012/08/25 Title
Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 10 of 48
5 4 3 2 1
5 4 3 2 1

+VREF_DQ_DIMMB
PN:SP07000N600 6 DDR_B_D[0..63]
+1.5V +1.5V
H8 standard 6 DDR_B_DQS[0..7]

+VREF_DQ_DIMMB
JDIMM2 DDR3 SO-DIMM B 6 DDR_B_DQS#[0..7]
1 VREF_DQ VSS1 2
3 4 DDR_B_D4
VSS2 DQ4 6 DDR_B_MA[0..15]
2.2U_0603_6.3V4Z

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS3 8

1
9 10 DDR_B_DQS#0
VSS4 DQS#0
C192

C193
DDR_B_DM0 11 12 DDR_B_DQS0
D DM0 DQS0 D
13 14
2

2
DDR_B_D2 VSS5 VSS6 DDR_B_D6
15 DQ2 DQ6 16
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST# +1.5V
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,10
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DQ10 DQ14

1
DDR_B_D11 35 36 DDR_B_D15
DQ11 DQ15 R94
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20 1K_0402_1%
DDR_B_D17 DQ16 DQ20 DDR_B_D21 +VREF_DQ_DIMMB
41 DQ17 DQ21 42
43 44

2
DDR_B_DQS#2 VSS15 VSS16 DDR_B_DM2
45 DQS#2 DM2 46
DDR_B_DQS2 47 48
DQS2 VSS17 DDR_B_D22
49 VSS18 DQ22 50

1
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS19 54
55 56 DDR_B_D28 R95
DDR_B_D24 VSS20 DQ28 DDR_B_D29 1K_0402_1%
57 DQ24 DQ29 58
DDR_B_D25 59 60

2
DQ25 VSS21 DDR_B_DQS#3
61 VSS22 DQS#3 62
DDR_B_DM3 63 64 DDR_B_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72

C C

6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB


CKE0 CKE1 DDR_CKE3_DIMMB 6
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0 +1.5V
97 A1 A0 98
99 VDD9 VDD10 100
6 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3
CK0 CK1 M_CLK_DDR3 6

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
6 M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 6

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
105 VDD11 VDD12 106

C196

C197

C198

C199

C200

C201

C202

C203

C204

C205

C206

C207
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 6

1
DDR_B_BS0 DDR_B_RAS# +1.5V
6 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 6
111 VDD13 VDD14 112
6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB#
DDR_CS2_DIMMB# 6

2
WE# S0#

1
6 DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 6
117 118 R96 @ @
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
119 A13 ODT1 120 M_ODT3 6
6 DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126 0.1U_0402_10V6K

2.2U_0603_6.3V4Z
127 VSS27 VSS28 128
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
C194

C195
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37
1

1
133 VSS29 VSS30 134
B DDR_B_DQS#4 DDR_B_DM4 R97 B
135 DQS#4 DM4 136
DDR_B_DQS4 137 138 1K_0402_1%
2

2
DQS4 VSS31 DDR_B_D38
139 140

2
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45 +0.75VS
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5 DDR_B_DM0
153 DM5 DQS5 154
155 156 DDR_B_DM1
VSS37 VSS38

C209

C211
DDR_B_D42 157 158 DDR_B_D46 DDR_B_DM2
DQ42 DQ46

C208 1U_0402_6.3V6K

C210 1U_0402_6.3V6K
DDR_B_D43 159 160 DDR_B_D47 DDR_B_DM3
DQ43 DQ47 DDR_B_DM4
161 VSS39 VSS40 162

1
DDR_B_D48 163 164 DDR_B_D52 DDR_B_DM5
DQ48 DQ52

1U_0402_6.3V6K

1U_0402_6.3V6K
DDR_B_D49 165 166 DDR_B_D53 DDR_B_DM6
DQ49 DQ53 DDR_B_DM7
167 168

2
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 DQS#6 DM6 170
DDR_B_DQS6 171 172
DQS6 VSS43 DDR_B_D54
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
1 R103 2 197 SA0 EVENT# 198
A 10K_0402_5% SMB_DATA_S3 A
199 VDDSPD SDA 200 SMB_DATA_S3 10,13,41,44
1 2 201 202 SMB_CLK_S3
+3VS SA1 SCL SMB_CLK_S3 10,13,41,44
R107 10K_0402_5% 203 204 +0.75VS
VTT1 VTT2
2.2U_0603_6.3V4Z

C212

C213
1

1
0.1U_0402_10V6K

205 G1 G2 206
@ BELLW_80011-5021
Security Classification Compal Secret Data Compal Electronics, Inc.
2

ME@
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 11 of 48

5 4 3 2 1
5 4 3 2 1

PCH_RTCX1
W=20mils W=20mils UH1A
1 2 PCH_RTCX2
+RTCVCC +RTCBATT

SHORT PADS
CLRP2
R109 10M_0402_5%
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 43,45,46

1
R111 Y1 A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 43,45,46

LPC
1K_0402_5% 1 2 C217 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD2 43,45,46
1 2 1U_0603_10V4Z C37 LPC_AD3
LPC_AD3 43,45,46

2
PCH_RTCRST# FWH3 / LAD3
1 2 D20 RTCRST#

1
32.768KHZ_12.5PF_CM31532768DZFT R114 20K_0402_5% D36 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# 43,45,46
1

C216 CLRP1 1 2 PCH_SRTCRST# G22


1U_0603_10V4Z SHORT PADS R115 20K_0402_5% SRTCRST# +3VS
1 1 E36
2
LDRQ0#

1
SHORT PADS
CLRP3

RTC
SM_INTRUDER# K22 K36 2 R116 1 10K_0402_5%
2

12/27 C214 C215 C218 INTRUDER# LDRQ1# / GPIO23


D 20P_0402_50V8 20P_0402_50V8 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ SERIRQ SERIRQ 43,45 D

2
2 2 INTVRMEN SERIRQ

AM3 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 45


HDA_BIT_CLK SATA0RXN SATA_DTX_C_IRX_P0
N34 HDA_BCLK SATA0RXP AM1 SATA_DTX_C_IRX_P0 45
SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 1 C219 SATA_ITX_DRX_N0 HDD

SATA 6G
SATA0TXN AP7 2 SATA_ITX_DRX_N0 45
HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C220 SATA_ITX_DRX_P0
Y1: HDA_SYNC SATA0TXP SATA_ITX_DRX_P0 45
+RTCVCC HDA_SPKR SATA_DTX_C_IRX_N1
P/N : SJ10000BM00 38 HDA_SPKR T10 SPKR SATA1RXN AM10
AM8 SATA_DTX_C_IRX_P1
SATA_DTX_C_IRX_N1 45
SATA_DTX_C_IRX_P1 45
R112 1 SATA1RXP
2 1M_0402_5% SM_INTRUDER# HDA_RST# K34 HDA_RST# SATA1TXN AP11 SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2 1 C221 SATA_ITX_DRX_N1_CONN
SATA_ITX_DRX_N1_CONN 45 ODD
AP10 SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 2 1 C222 SATA_ITX_DRX_P1_CONN SATA_ITX_DRX_P1_CONN 45
R113 1 SATA1TXP
2 330K_0402_5% PCH_INTVRMEN
38 HDA_SDIN0 HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_N2 41
HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_P2
INTVRMEN(DCP_SUS) SATA2RXP AD5 SATA_DTX_C_IRX_P2 41 mSATA
R119 G34 AH5 SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 1 C223 SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN SATA_ITX_DRX_N2_CONN 41
H Integrated VRM enable ME_FLASH 1 2 AH4 SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 1 C224 SATA_ITX_DRX_P2_CONN
* L Integrated VRM disable
43 ME_FLASH
0_0402_5% C34 HDA_SDIN2
SATA2TXP SATA_ITX_DRX_P2_CONN 41

IHDA
SATA3RXN AB8
(INTVRMEN should always be pull high.) A34 HDA_SDIN3 SATA3RXP AB10
SATA3TXN AF3
41 PCH_WLBT_OFF_5# SATA3TXP AF1
HDA_SDOUT A36 HDA_SDO

SATA
+3VS SATA4RXN Y7 Boot BIOS Strap bit1 BBS1
@ Y5
R121 2 SATA4RXP
+3VS 1 10K_0402_5% PCH_WLBT_OFF_5# C36
HDA_DOCK_EN# / GPIO33 SATA4TXN AD3 GPIO51 GPIO19 Boot BIOS
R117 1 @ 2 1K_0402_5% HDA_SPKR AD1
+3V_PCH R5018 1 2 1K_0402_5% PCH_GPIO13 N32 HDA_DOCK_RST# / GPIO13
SATA4TXP
Bit11 Bit10 Destination
HIGH= Enable ( No Reboot ) @ Y3
SATA5RXN
LOW= Disable (Default) 0 1 Reserved
* SATA5RXP
SATA5TXN
Y1
AB3
PCH_JTAG_TCK J3 AB1 1 0 Reserved
JTAG_TCK SATA5TXP
C C
PCH_JTAG_TMS R123 1 1 SPI (Default)
H7 JTAG_TMS SATAICOMPO Y11
37.4_0402_1% +1.05VS_VCC_SATA *

JTAG
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2 0 0 LPC
+3V_PCH JTAG_TDI SATAICOMPI
+5VS PCH_JTAG_TDO H1
R118 2 @ 1 1K_0402_5% HDA_SDOUT JTAG_TDO R125 +1.05VS_SATA3
SATA3RCOMPO AB12
49.9_0402_1%
Low = Disabled (Default) SATA3_COMP
* High = Enabled [Flash
SATA3COMPI AB13 1 2

Descriptor Security SPI_CLK_PCH_R T3 AH1 RBIAS_SATA3 1 2


SPI_CLK SATA3RBIAS
2
G

Overide] Q9 R127
BSS138_NL_SOT23-3 SPI_SB_CS0# Y14 750_0402_1%
HDA_SYNC_R HDA_SYNC SPI_CS0#
3 1
SPI_SB_CS1#
S

T1 SPI_CS1#

SPI
P3 PCH_SATALED# 2 R130 1 +3VS
SATALED# 10K_0402_5%
1

+3V_PCH SPI_SI PCH_GPIO21 R132 1


V4 SPI_MOSI SATA0GP / GPIO21 V14 2 +3VS
R5017 10K_0402_5%
R120 2 1 1K_0402_5% HDA_SYNC 1M_0402_5% SPI_SO_R U3 P1 ODD_DET# 2 R133 1 +3VS
SPI_MISO SATA1GP / GPIO19 10K_0402_5%
This signal has a weak internal pull-down Q9
2

PANTHER-POINT_FCBGA989 ODD_DET# 45
On Die PLL VR Select is supplied by P/N : SB501380020 S IC BD82HM77 QPRG C1 BGA 989P PCH A39
1.5V when smapled high
* 1.8V when sampled low
Needs to be pulled High for Huron River
platfrom
For SBA SBA: 8M +4 M
8M 1'S : SA000039A20 Winbond
+3VSPI +3VS +3VM NOSBA: 8M
B 8M 2'S : SA000046400 E-ON Check BOM
B

NOSBA@
R5182 1 2 0_0402_5%
R124
33_0402_5%
4M 1'S : SA00003K800 Winbond R5183 1 2 0_0402_5%
HDA_BIT_CLK JDB2 SBA@
38 HDA_BITCLK_AUDIO 1
R126
2
1
4M 2'S : SA00004LI00 E-ON
33_0402_5% 1
2 2
1 2 HDA_SYNC_R 3 +3VSPI
38 HDA_SYNC_AUDIO 3
R128 4 C225 1 2 0.1U_0402_16V4Z SBA@
33_0402_5% 5
4 8M SPI_WP#1 R104 1 2 3.3K_0402_5%
14,43 EC_RSMRST# 5
1 2 HDA_RST# 6 U5
38 HDA_RST_AUDIO# 6
R131 7 SPI_SB_CS0# R5168 1 2 0_0402_5% CS0# 1 8 SPI_HOLD#1 R106 1 SBA@ 2 3.3K_0402_5%
33_0402_5% 7 SPI_SO_R R5169 1 CS# VCC
8 8 2 33_0402_5% SPI_SO_L 2 SO HOLD# 7 SPI_HOLD# R5170 0_0402_5%
38 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT 9 SPI_WP# 3 6 SPI_CLK_PCH 1 2 SPI_CLK_PCH_R SPI_WP# R5171 1 2 3.3K_0402_5%
5,14,43 PBTN_OUT# 9 WP# SCLK
R85 1 @ 2 1K_0402_1% 10 4 5 SPI_SI_R 1 2 SPI_SI
R761 1 10 GND SI
2 0_0402_5% 11 11
R5172 33_0402_5% SPI_HOLD# R5173 1 2 3.3K_0402_5%
+1.05VS @ 12 32M W25Q32BVSSIG SOIC 8P
12 SPI_CLK_PCH_R
13 13
+3V_PCH R290 1 @ 2 0_0402_5% 14 14

2
15 15
16 R143
EC_RSMRST# R84 1 @ 16 +3VSPI
2 1K_0402_1% 17 17 33_0402_5%
XDP_DBRESET# 18
5,14 XDP_DBRESET#
19
18 4M @

1
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TDO 19 SBA@ U2202
20 20 2
21 SPI_SB_CS1# R5174 1 2 0_0402_5% CS1# 1 8
PCH_JTAG_TDI 21 SPI_SO_R R5191 1 CS# VCC
22 22 2 33_0402_5% SPI_SO1 2 SO HOLD# 7 SPI_HOLD#1 SBA@ C80
1

PCH_JTAG_TMS 23 SPI_WP#1 3 6 SPI_CLK1 R5175 1 2 0_0402_5% SPI_CLK_PCH_R 22P_0402_50V8J


R134 R135 R136 23 SBA@ WP# SCLK SPI_SI1 R5176 1 1
24 24 4 GND SI 5 2 33_0402_5% SPI_SI @
@ 200_0402_5% @ 200_0402_5% @ 200_0402_5% 25
PCH_JTAG_TCK 25 32M W25Q32BVSSIG SOIC 8P SBA@
26 26
Reserve for EMI please close to UH1
A SBA@ A
27
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TCK G1


28 G2
1

ACES_88717-2601
R138 R139 R140 R122 ME@
@ 100_0402_1% @ 100_0402_1% @ 100_0402_1% 51_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


2

Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 12 of 48
5 4 3 2 1
5 4 3 2 1

UH1B SMB_ALERT# Q2A


2N7002DW-T/R7_SOT363-6
46 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 10K_0402_5% 6 1 SMB_CLK_S3
PERN1 SMB_CLK_S3 10,11,41,44
46 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 SMB_ALERT# 2 1 +3V_PCH
C230 PCIE_PTX_DRX_N1 PERP1 SMBALERT# / GPIO11
Card reader 1 2 0.1U_0402_10V7K AV32 2.2K_0402_5% 2.2K_0402_5%
46 PCIE_PTX_C_DRX_N1
46 PCIE_PTX_C_DRX_P1
C234 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 AU32
PETN1
H14 PCH_SMBCLK R148 1 R149 2 1 2 R150 DIMM1

2
PETP1 SMBCLK
41 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
+3V_PCH
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 R151 R147
WLAN
41 PCIE_PRX_DTX_P2
41 PCIE_PTX_C_DRX_N2
C233 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2
BF34
BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C229 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
41 PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 10,11,41,44

SMBUS
SML0ALERT# / GPIO60 A12 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 6,9
BG36 2N7002DW-T/R7_SOT363-6
PERN3 PCH_SML0CLK
BJ36 PERP3 SML0CLK C8 2 R152 1 +3V_PCH Q2B
D 1K_0402_5% D
AV34 PETN3
AU34 G12 PCH_SML0DATA
PETP3 SML0DATA R153 10K_0402_5% Q10A
PCIE_PRX_DTX_N4 BF36 2 1 2N7002DW-T/R7_SOT363-6
39 PCIE_PRX_DTX_N4 PERN4 +3V_PCH
LAN 39 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_P4 BE36 6 1 EC_SMB_CK2
PERP4 EC_SMB_CK2 21,42,43
C231 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
39 PCIE_PTX_C_DRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT#
C232 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 2.2K_0402_5%
39 PCIE_PTX_C_DRX_P4 1 BB34 PETP4
E14 PCH_SML1CLK 1 R154 2 VGA

2
SML1CLK / GPIO58

PCI-E*
PCIE_PRX_DTX_N5
33 PCIE_PRX_DTX_N5
33 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_P5
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75 M16 PCH_SML1DATA
+3V_PCH
1 2
+3VS EC

5
C237 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_N5 AY36 R155
33 PCIE_PTX_C_DRX_N5
33 PCIE_PTX_C_DRX_P5
C283 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_P5 BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 21,42,43
33 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_N6 BJ38
PCIE_PRX_DTX_P6 PERN6 2N7002DW-T/R7_SOT363-6
33 PCIE_PRX_DTX_P6 BG38 PERP6

Controller
C286 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_N6 AU36 M7
33 PCIE_PTX_C_DRX_N6
33 PCIE_PTX_C_DRX_P6
C293 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_P6 AV36
PETN6
PETP6
CL_CLK1 +3V_PCH 2.2K_0402_5%
Q10B
Thunderbolt
PCH_SML0CLK 2 R206 1 +3V_PCH

Link
Thunderbolt 33 PCIE_PRX_DTX_N7 PCIE_PRX_DTX_N7 BG40 T11
PERN7 CL_DATA1

2
33 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_P7 BJ40 2.2K_0402_5%
C241 PCIE_PTX_DRX_N7 PERP7 PCH_SML0DATA
33 PCIE_PTX_C_DRX_N7 1 TB@2 0.1U_0402_10V7K AY40 PETN7
R156 2 R250 1 +3V_PCH
C284 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_P7 BB40 P10 10K_0402_5%
33 PCIE_PTX_C_DRX_P7 PETP7 CL_RST1#
33 PCIE_PRX_DTX_N8 PCIE_PRX_DTX_N8 BE38

1
PCIE_PRX_DTX_P8 PERN8 R5189
33 PCIE_PRX_DTX_P8 BC38 PERP8
C287 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_N8 AW38 0_0402_5%
33 PCIE_PTX_C_DRX_N8 PETN8
C302 1 TB@2 0.1U_0402_10V7K PCIE_PTX_DRX_P8 AY38 1 2
33 PCIE_PTX_C_DRX_P8 PETP8 short@ CLK_REQ_VGA# 21

PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 2 @ 1


33_0402_5% R2171 2 CLK_PCIE_CR#_R Y40 R5190 10K_0402_5%
46 CLK_PCIE_CR# CLKOUT_PCIE0N
33_0402_5% R2651 2 CLK_PCIE_CR_R Y39
46 CLK_PCIE_CR CLKOUT_PCIE0P
Card reader AB37 CLK_PCIE_VGA#_R R5177 1 2 0_0402_5%
C CLKOUT_PEG_A_N short@ CLK_PCIE_VGA# 21 C
R160 1 10K_0402_5% CARD_CLKREQ#_R CLK_PCIE_VGA_R R5178 1 2 0_0402_5%

CLOCKS
+3V_PCH 2 J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA 21
R381 1 short@
46 CARD_CLKREQ1# 2 0_0402_5%
short@
R208 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI#
41 CLK_PCIE_WLAN1# short@ CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5 +3VS
R212 1 2 0_0402_5% CLK_PCIE_WLAN1_R AB47 AU22 CLK_CPU_DMI
41 CLK_PCIE_WLAN1 short@ CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
WLAN
41 WLAN_CLKREQ# R215 1 2 0_0402_5% WLAN_CLKREQ1# M1
R167 short@ PCIECLKRQ1# / GPIO18
+3VS 2 1 10K_0402_5% CLKOUT_DP_N AM12

1
AM13 @
CLKOUT_DP_P R5019
AA48 CLKOUT_PCIE2N
AA47 10K_0402_5% +3VS
CLKOUT_PCIE2P CLK_BUF_CPU_DMI# R168 1 10K_0402_5%
CLKIN_DMI_N BF18 2
+3VS R169 2 1 10K_0402_5% PCH_GPIO20 V10 BE18 CLK_BUF_CPU_DMI R170 1 2 10K_0402_5% U32

2
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
1 NC VCC 8 1
2 7 ROM_WP C696
R369 1 CLK_PCIE_LAN#_R CLKIN_DMI2# NC WP SMB_CLK_S3
39 CLK_PCIE_LAN# 2 0_0402_5% Y37 CLKOUT_PCIE3N CLKIN_GND1_N BJ30 R172 1 2 10K_0402_5%
16,21,33,39,41,43,46 PLT_RST# 3 PROT# SCL 6 0.1U_0402_16V4Z
R370 1 short@
39 CLK_PCIE_LAN 2 0_0402_5% CLK_PCIE_LAN_R Y36 CLKOUT_PCIE3P CLKIN_GND1_P BG30 CLKIN_DMI2 R174 1 2 10K_0402_5% 4 GND SDA 5 SMB_DATA_S3
short@ 2
LAN
+3V_PCH R176 2 1 10K_0402_5% LAN_CLKREQ# A8 PCA24S08D_SO8
R371 1 PCIECLKRQ3# / GPIO25
39 CLKREQ_LAN# 2 0_0402_5% CLKIN_DOT_96N G24 CLK_BUF_DREF_96M# R177 1 2 10K_0402_5% EEPROM SA00004MK00
short@ E24 CLK_BUF_DREF_96M R178 1 2 10K_0402_5% EEPROM SA00004ML00
R373 1 CLKIN_DOT_96P
33 CLK_PCIE4# 2 0_0402_5% CLK_PCIE4#_R Y43 CLKOUT_PCIE4N
R372 1 short@
33 CLK_PCIE4 2 0_0402_5% CLK_PCIE4_R Y45 CLKOUT_PCIE4P
short@ AK7 CLK_BUF_PCIE_SATA# R181 1 2 10K_0402_5%
R184 CLKIN_SATA_N
+3V_PCH 2 1 10K_0402_5% TB_CLKREQ# L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLK_BUF_PCIE_SATA R183 1 2 10K_0402_5%
Thunderbolt
R374 1 2 0_0402_5%
33 CLKREQ_TB# short@
V45 K45 CLK_BUF_ICH_14M R185 1 2 10K_0402_5%
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P

+3V_PCH R186 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK


PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 16
B B
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49

R188 2 1 10K_0402_5% PCH_GPIO56 E6 R189 +1.05VS_VCCDIFFCLKN


+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1%
Y47 XCLK_RCOMP 1 2
@ XCLK_RCOMP XTAL25_IN
V40 CLKOUT_PCIE6N
R195 2 1 10K_0402_5% V42 CLKOUT_PCIE6P XTAL25_OUT 1 2
+3V_PCH R190 2 1 10K_0402_5% PCH_GPIO45 T13 R187 1M_0402_5%
PCIECLKRQ6# / GPIO45 Y3
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43 4 NC OSC 3
R193 1 10K_0402_5%
FLEX CLOCKS

+3V_PCH 2 V37 CLKOUT_PCIE7P


@ F47 1 2
ON_ODD_DET CLKOUTFLEX1 / GPIO65 OSC NC
45 ON_ODD_DET K12 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47
CLK_XDP_CLK# AK14 1 25MHZ_12PF_X3G025000DC1H~D 1
5 CLK_XDP_CLK# CLKOUT_ITPXDP_N
CLK_XDP_CLK AK13 K49 DGPU_PRSNT#
5 CLK_XDP_CLK CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 DGPU_PRSNT# 17
C235 C236
15P_0402_50V8J 15P_0402_50V8J
PANTHER-POINT_FCBGA989 2 2

Y3 : SJ10000B700

R196 C238
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A

Reserve for EMI please close to PCH

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 13 of 48
5 4 3 2 1
5 4 3 2 1

D D

UH1C

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4


DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
4 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 4
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5
4 DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 4
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
4 DMI_CTX_PRX_P2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 4
4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_P0
FDI_RXP0 BG14 FDI_CTX_PRX_P0 4
DMI_CRX_PTX_N0 AW24 BB14 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 4
4 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4
+3VS 4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7
5

DMI_CRX_PTX_P2 AY18
4 DMI_CRX_PTX_P2 DMI2TXP
2 DMI_CRX_PTX_P3 AU18
P

43 PCH_PWROK B 4 DMI_CRX_PTX_P3 DMI3TXP


4 SYS_PWROK AW16 FDI_INT
Y SYS_PWROK 5 FDI_INT FDI_INT 4 +RTCVCC
57 VGATE 1 A
G

+1.05VS_PCH BJ24 AV12 FDI_FSYNC0


DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4
3

1
U2 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4
NC7SZ08P5X_NL_SC70-5 R197 49.9_0402_1% R198
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5%
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4 C
R199 750_0402_1%
R200 4mil width and place BB10 FDI_LSYNC1
FDI_LSYNC1 4

2
100K_0402_1% SYS_PWROK FDI_LSYNC1 DSWODVREN - On Die DSW VR Enable
2 1
within 500mil of the H Enable
PCH * L Disable
SUSACK# is only used on platform A18 DSWODVREN
DSWVRMEN
that support the Deep Sx state.

1
T763PAD

System Power Management


SUSACK# C12 E22 PCH_DPWROK R210 2 1 0_0402_5% PCH_RSMRST#_R R202
SUSACK# DPWROK short@
330K_0402_5%
@
5,12 XDP_DBRESET# K3 B9 WAKE# PCIE_WAKE# 33,39

2
SYS_RESET# WAKE# R205
1 2 +3V_PCH
10K_0402_5%
SYS_PWROK P12 N3 PM_CLKRUN#_R
1 2 R207 +3VS
SYS_PWROK CLKRUN# / GPIO32 8.2K_0402_5%

PCH_PWROK L22 G8 SUS_STAT# PAD T767


NOSBA@ PWROK SUS_STAT# / GPIO61
R5070 0_0402_5% 2 1
2 1 R209 APWROK L10 N14 SUSCLK
43 PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK 43
+3V_PCH SBA@ 0_0402_5% Can be left NC
when IAMT is not
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# support on the
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 43
R279
0_0402_5%
platfrom
R213 2 1 PCH_RSMRST#_R C21 H4 PM_SLP_S4#
12,43 EC_RSMRST# short@ RSMRST# SLP_S4# PM_SLP_S4# 43
2 1 10K_0402_5% SUSWARN#

2 1 R214 AC_PRESENT_R SUSWARN# K16 SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# F4 PM_SLP_S3#


PM_SLP_S3# 43
200K_0402_1% R382
0_0402_5%
B R216 PCH_RSMRST#_R B
2 1 5,12,43 PBTN_OUT# 2 1 PBTN_OUT#_R E20 PWRBTN# SLP_A# G10 SLP_A# 2 1 PCH_SLPA# 43
10K_0402_5% short@ R221
0_0402_5%
1 2 AC_PRESENT_R H20 G16 PM_SLP_SUS# PAD T766 SBA@
43,46,49 ACIN ACPRESENT / GPIO31 SLP_SUS#
D1
CH751H-40PT_SOD323-2
2 1 PCH_GPIO72 E10 BATLOW# / GPIO72 PMSYNCH AP14 H_PM_SYNC
H_PM_SYNC 5
R219
+3V_PCH 10K_0402_5% Can be left NC if no use
+3V_PCH 2 1 RI# A10 RI# SLP_LAN# / GPIO29 K14 PCH_GPIO29 integrated LAN.
@
R256 2 1 PM_DRAM_PWRGD R220
200_0402_5% 10K_0402_5% PANTHER-POINT_FCBGA989

+3VS

@
R268 2 1
200_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 14 of 48
5 4 3 2 1
5 4 3 2 1

PORT STRAP

LVDS L_DDC_DATA

PORT B SDVO_CTRLDATA

PORT C DDPC_CTRLDATA
D D
+3VS
43 ENBKL
PORT D DDPD_CTRLDATA

2
R494
1

100K_0402_1%
R5020 R5021
2.2K_0402_5% 2.2K_0402_5%

1
UH1D
ENBKL J47 AP43 +3VS
2

PCH_ENVDD L_BKLTEN SDVO_TVCLKINN


31 PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45
EDID_CLK
EDID_DATA PCH_PWM P45 AM42
31 PCH_PWM L_BKLTCTL SDVO_STALLN

1
SDVO_STALLP AM40
EDID_CLK T40 R5060 R5059
31 EDID_CLK L_DDC_CLK
EDID_DATA K47 AP39 2.2K_0402_5% 2.2K_0402_5%
31 EDID_DATA L_DDC_DATA SDVO_INTN
SDVO_INTP AP40
+3VS R5022 1 2 2.2K_0402_5% CTRL_CLK T45

2
R5023 1 L_CTRL_CLK
2 2.2K_0402_5% CTRL_DATA P39 L_CTRL_DATA
R227 2 1 LVDS_IBG AF37 P38 HDMICLK_NB HDMICLK_NB 32
2.37K_0402_1% LVD_IBG SDVO_CTRLCLK HDMIDAT_NB
AF36 LVD_VBG SDVO_CTRLDATA M39 HDMIDAT_NB 32
LVD_VREF AE48 LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49
DDPB_AUXP AT47
AT40 TMDS_B_HPD
DDPB_HPD TMDS_B_HPD 32
31 LVDS_ACLK# AK39 LVDSA_CLK#

LVDS
31 LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCH C295 1 2 0.1U_0402_10V6K
HDMI_TX2-_CK 32
DDPB_0P AV40 TMDS_B_DATA2_PCH C294 1 2 0.1U_0402_10V6K
HDMI_TX2+_CK 32
AN48 AV45 TMDS_B_DATA1#_PCH C539 1 2 0.1U_0402_10V6K +3VS
31 LVDS_A0# LVDSA_DATA#0 DDPB_1N HDMI_TX1-_CK 32
31 LVDS_A1# AM47 AV46 TMDS_B_DATA1_PCH C538 1 2 0.1U_0402_10V6K
HDMI_TX1+_CK 32 HDMI

Digital Display Interface


C LVDSA_DATA#1 DDPB_1P C
31 LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCH C535 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK 32
AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0_PCH C534 1 2 0.1U_0402_10V6K
HDMI_TX0+_CK 32

2
DDPB_3N AV47 TMDS_B_CLK#_PCH C537 1 2 0.1U_0402_10V6K
HDMI_CLK-_CK 32
31 LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH C536 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK 32
R5115 R5147
31 LVDS_A1 AM49 LVDSA_DATA1 2.2K_0402_5% 2.2K_0402_5%
31 LVDS_A2 AK49 LVDSA_DATA2
AJ47 P46 PCH_DPC_CLK PCH_DPC_CLK 34

1
LVDSA_DATA3 DDPC_CTRLCLK PCH_DPC_DAT
DDPC_CTRLDATA P42 PCH_DPC_DAT 34
AF40 PCH_DPC_CLK
31 LVDS_BCLK# LVDSB_CLK#
AF39 AP47 PCH_DPC_AUXN PCH_DPC_AUXN 33
31 LVDS_BCLK LVDSB_CLK DDPC_AUXN
AP49 PCH_DPC_AUXP PCH_DPC_AUXP 33 PCH_DPC_DAT
DDPC_AUXP DPC_HPD
31 LVDS_B0# AH45 LVDSB_DATA#0 DDPC_HPD AT38 DPC_HPD 33
31 LVDS_B1# AH47 LVDSB_DATA#1
AF49 AY47 PCH_DPC_N0_C TB@ C239 1 2 0.1U_0402_10V6K
31 LVDS_B2# LVDSB_DATA#2 DDPC_0N PCH_DPC_N0 33
AF45 AY49 PCH_DPC_P0_C TB@ C240 1 2 0.1U_0402_10V6K
LVDSB_DATA#3 DDPC_0P PCH_DPC_P0 33
AY43 PCH_DPC_N1_C TB@ C529 1 2 0.1U_0402_10V6K
DDPC_1N PCH_DPC_N1 33
AH43 AY45 PCH_DPC_P1_C TB@ C528 1 2 0.1U_0402_10V6K
31 LVDS_B0 LVDSB_DATA0 DDPC_1P PCH_DPC_P1 33
AH49 BA47 PCH_DPC_N2_C TB@ C530 1 2 0.1U_0402_10V6K DP to thunder bolt
31 LVDS_B1 LVDSB_DATA1 DDPC_2N PCH_DPC_N2 33
AF47 BA48 PCH_DPC_P2_C TB@ C531 1 2 0.1U_0402_10V6K
31 LVDS_B2 LVDSB_DATA2 DDPC_2P PCH_DPC_P2 33
AF43 BB47 PCH_DPC_N3_C TB@ C533 1 2 0.1U_0402_10V6K
LVDSB_DATA3 DDPC_3N PCH_DPC_N3 33
BB49 PCH_DPC_P3_C TB@ C532 1 2 0.1U_0402_10V6K
DDPC_3P PCH_DPC_P3 33

N48 CRT_BLUE DDPD_CTRLCLK M43


P49 CRT_GREEN DDPD_CTRLDATA M36
T49 CRT_RED

DDPD_AUXN AT45
CRT

T39 CRT_DDC_CLK DDPD_AUXP AT43


M40 CRT_DDC_DATA DDPD_HPD BH41
B B
DDPD_0N BB43
M47 CRT_HSYNC DDPD_0P BB45
M49 CRT_VSYNC DDPD_1N BF44
DDPD_1P BE44
DDPD_2N BF42
CRT_IREF T43 BE42
DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
DDPD_3P BG42
1

PANTHER-POINT_FCBGA989
R5029
1K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 15 of 48
5 4 3 2 1
5 4 3 2 1

UH1E
+3VS AY7
RSVD1
RSVD2 AV7
RP1 BG26 AU3
PCI_PIRQA# TP1 RSVD3
8 1 BJ26 TP2 RSVD4 BG4
7 2 PCI_PIRQD# BH25
PCI_PIRQC# TP3
6 3 BJ16 TP4 RSVD5 AT10
5 4 PCI_PIRQB# BG16 BC8
TP5 RSVD6
AH38 TP6
8.2K_0804_8P4R_5% AH37 AU2
TP7 RSVD7
AK43 TP8 RSVD8 AT4
D D
AK45 TP9 RSVD9 AT3
RP2 C18 AT1
DGPU_PWR_EN_R TP10 RSVD10
8 1 N30 TP11 RSVD11 AY3
7 2 PCH_GPIO4 H3 AT5
ODD_DA# TP12 RSVD12
6 3 AH12 TP13 RSVD13 AV3
5 4 BT_DET# AM4 AV1
TP14 RSVD14
AM5 TP15 RSVD15 BB1
8.2K_0804_8P4R_5% Y13 BA3
TP16 RSVD16
K24 TP17 RSVD17 BB5
R235 1 2 8.2K_0402_5% WL_OFF# L24 BB3
TP18 RSVD18
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8

RSVD
R5030 1 2 8.2K_0402_5% DGPU_PWR_EN1 BD4
RSVD21
RSVD22 BF6
R5067 1 @ 2 8.2K_0402_5% PCH_GPIO5
B21 TP21 RSVD23 AV5
R5031 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R M20 AV10
TP22 RSVD24
AY16 TP23 Follow Edge
R5064 1 2 8.2K_0402_5% PCH_GPIO51 BG46 AT8
TP24 RSVD25
R5072 1 2 8.2K_0402_5% PCH_GPIO53 AY5 USB3.0 USB2.0 NOTE
RSVD26
RSVD27 BA2
R5032 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R BE28 USB3Rn1
37 USB3_RX2_N BC30 USB3Rn2 RSVD28 AT12
@ 46 USB3_RX3_N BE32 BF3 1 0
USB3Rn3 RSVD29
BJ32 USB3Rn4 USB DEBUG=PORT1 AND PORT9
BC28 USB3Rp1
37 USB3_RX2_P BE30 USB3Rp2 2 1 * USB3.0/2.0 Conn
46 USB3_RX3_P BF32 USB3Rp3
WL_OFF# R5033 1 @ 2 1K_0402_5% BG32 C24
USB3Rp4 USBP0N
AV26 USB3Tn1 USBP0P A24 3 2 To Sub board USB3.0/2.0 Conn
BB26 C25 USB20_N1
C 37 USB3_TX2_N USB3Tn2 USBP1N USB20_N1 37 C
AU28 B25 USB20_P1 USB2 (USB3 COMBO)
46 USB3_TX3_N USB3Tn3 USBP1P USB20_P1 37
A16 swap overide Strap/Top-Block AY30 C26 USB20_N2 4 3
USB3Tn4 USBP2N USB20_N2 46
Swap Override jumper AU26 A26 USB20_P2 USB2 (USB3 COMBO) to SB board
USB3Tp1 USBP2P USB20_P2 46
37 USB3_TX2_P AY26 USB3Tp2 USBP3N K28
Low=A16 swap 46 USB3_TX3_P AV28 USB3Tp3 USBP3P H28 4 Sensor HUB
override/Top-Block AW30 USB3Tp4 USBP4N E28 USB20_N4
PCI_GNT3# Swap Override enabled USBP4P D28 USB20_P4 Sensor HUB
High=Default * C28 USB20_N5 5 USB Camera
USBP5N USB20_N5 31
A28 USB20_P5 USB Camera
USBP5P USB20_P5 31
USBP6N C29
B29 Port6, Port7 HM76 doesn't support 6
PCI_PIRQA# K40
USBP6P
N28
X
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30 7
PCI_PIRQD# G38
PIRQC# USBP8N
K30
USB20_N8 31
Screen touch
X
PIRQD# USBP8P USB20_P8 31
G30 USB20_N9
USBP9N USB20_N9 41
R5068 2 1 0_0402_5% DGPU_HOLD_RST#_RC46 E30 USB20_P9 WWAN 8 Screen touch
21 DGPU_HOLD_RST# REQ1# / GPIO50 USBP9P USB20_P9 41

USB
R5075 short@
56 NVDD_PWR_EN 2 1 0_0402_5% DGPU_PWR_EN1 C44 REQ2# / GPIO52 USBP10N C30 USB20_N10
USB20_N10 41
R5069 short@ 1 0_0402_5% DGPU_PWR_EN_R USB20_P10
21,23 DGPU_PWR_EN 2
short@
E40 REQ3# / GPIO54 USBP10P A30 USB20_P10 41 WLAN
USBP11N L32 USB20_N11 46 9 * WWAN
PCH_GPIO51 D47 K32 Finger Printer
GNT1# / GPIO51 USBP11P USB20_P11 46
PCH_GPIO53 E42 G32
GNT2# / GPIO53 USBP12N USB20_N12
WL_OFF# F46 E32 10 WLAN
WL_OFF# GNT3# / GPIO55 USBP12P USB20_P12
USBP13N C32 USB20_N13
BT_DET# USBP13P A32 USB20_P13 Bluetooth
X
BT_DET# G42 PIRQE# / GPIO2 11 Finger Printer
ODD_DA# G40
43,45 ODD_DA# PIRQF# / GPIO3
1 PCH_GPIO4 C42 C33 USBRBIAS 1 2
@ C83 PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R5034 22.6_0402_1%
D44 PIRQH# / GPIO5 12
100P_0402_50V8J B33
2 USBRBIAS
B 43 PCI_PME# K10 PME# 13 Bluetooth
X B
ESD PCH_PLTRST# C6 A14 USB_OC0#
5,45 PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC0# 37
C Reserve OC1# / GPIO40 K20 USB_OC1#
USB_OC1# 46 * Port 1 & Port9 for debug
B17 USB_OC2#
R5035 33_0402_5%CLK_PCI_LPBACK_R OC2# / GPIO41 USB_OC3#
13 CLK_PCI_LPBACK 1 2 H49 CLKOUT_PCI0 OC3# / GPIO42 C16
R5036 1 2 33_0402_5%CLK_PCI_EC_R H43 L16 USB_OC4#
43 CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43
R384 2 @ 1 33_0402_5%CLK_PCI_DB_R J48 A16 USB_OC5#
46 CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9
R388 2 TPM@ 1 33_0402_5%CLK_PCI_TPM_R K42 D14 USB_OC6#
45 CLK_PCI_TPM CLKOUT_PCI3 OC6# / GPIO10
H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14

PANTHER-POINT_FCBGA989 +3V_PCH

USB_OC5# R35 1 2 10K_0402_5%


1 2 USB_OC2# R40 1 2 10K_0402_5%
R5038 USB_OC7# R47 1 2 10K_0402_5%
NVDD_PWR_EN R5076 2 1 0_0402_5% DGPU_PWR_EN_R 0_0402_5% USB_OC0# R48 1 2 10K_0402_5%

@ +3VS

USB_OC6# R74 1 2 10K_0402_5%


5

U8 USB_OC1# R77 1 2 10K_0402_5%


2 PCH_PLTRST# USB_OC3# R101 1 2 10K_0402_5%
P

B USB_OC4# R165 10K_0402_5%


13,21,33,39,41,43,46 PLT_RST# 4 Y 1 2
A 1
G
1

@
3
1

C5037 R5039
1U_0402_6.3V4Z 100K_0402_5%
2

@ MC74VHC1G08DFT2G SC70 5P
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 16 of 48

5 4 3 2 1
5 4 3 2 1

+3VS

PCH_GPIO69
R1943 R1944 R5066

10K_0402_5%

10K_0402_5%

10K_0402_5%
2

2
+3VS

1 TB SKU

1
KB_RST# R266 1 2 10K_0402_5% 0120 update TB@ @ @
PCH_GPIO69
@
D R259 EC_SMI# ODD_EN# R1942 PCH_GPIO70 D
1 2 1K_0402_5% 2 1 10K_0402_5%

PCH_GPIO71
Weak internal pull-high
UH1F

+3VS R253 1 2 10K_0402_5% PCH_GPIO0 T7 C40 ODD_EN# ODD_EN# 45


BMBUSY# / GPIO0 TACH4 / GPIO68 R1947 R5040
GPIO28

10K_0402_5%
10K_0402_5%
On-Die PLL Voltage Regulator R257 1 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69

2
This signal has a weak internal pull up +3VS
R258 1 2 10K_0402_5% PA0_WAKEUP H36 C41 PCH_GPIO70
TACH2 / GPIO6 TACH6 / GPIO70
H On-Die voltage regulator enable
* L On-Die PLL Voltage Regulator disable 43 EC_SCI# EC_SCI# E38 TACH3 / GPIO7 TACH7 / GPIO71 A40 PCH_GPIO71

1
R5042 1 @ 2 1K_0402_5% PCH_GPIO28 43 EC_SMI# EC_SMI# C10 GPIO8
R260 @ @
10K_0402_5%
+3V_PCH R261 1 @ 2 10K_0402_5% TB_Force_PWR C4 LAN_PHY_PWR_CTRL / GPIO12

1
R262 1 @ 2 1K_0402_5% EC_LID_OUT# G2 P4
GPIO15 A20GATE GATEA20 43
AU16 PCH_PECI_R 1 @ 2
PECI H_PECI 5,43
+3VS R264 1 2 10K_0402_5% PCH_GPIO16 U2 0_0402_5% R263
SATA4GP / GPIO16 KB_RST#
43,48,56 DGPU_PWROK RCIN# P5 KB_RST# 43

GPIO
From GPU Power IC +3VS R404 1 2 10K_0402_5% DGPU_PWROK D40 AY11
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5

CPU/MISC
+3VS R5041 1 2 10K_0402_5% TB_GPIO6 T5 AY10 PCH_THRMTRIP#_R 1 2 H_THERMTRIP# H_THERMTRIP# 5
SCLOCK / GPIO22 THRMTRIP# R269 390_0402_5% PCH_THRMTRIP#_R 21
0315 Change to GPIO12 +3V_PCH R5073 1 2 10K_0402_5% PCH_GPIO24 E8 T14
GPIO24 INIT3_3V# INIT3_3V
TB_Force_PWR +3V_PCH R5074 1 @ 2 10K_0402_5% mSATA_PCH E16 AY1 NV_CLE
C 33 TB_Force_PWR GPIO27 DF_TVS C
This signal has weak internal
+3V_PCH 1 R5043 2 10K_0402_5% PCH_GPIO28 P8 GPIO28 PU, can't pull low
TS_VSS1 AH8
+3VS 1 R5044 2 10K_0402_5% PCH_BT_ON# K1
EC_LID_OUT# STP_PCI# / GPIO34
43 EC_LID_OUT# TS_VSS2 AK11
1 R273 2 10K_0402_5% 3G_DET# K4 GPIO35
TS_VSS3 AH10
1R5048 @ 2 10K_0402_5% PCH_WLBT_OFF_51# V8 SATA2GP / GPIO36
R5054 AK10 Intel schematic reviwe recommand.
0_0402_5% R5045 TS_VSS4
+3VS 1 2 10K_0402_5% PCH_GPIO37 M5 SATA3GP / GPIO37
1 2 PCH_GPIO0 @
33 TB_PLUG_EVENT short@ PCH_GPIO38 N2 P37
SLOAD / GPIO38 NC_1
R277 1 2 10K_0402_5% 3G_OFF# M3 SDATAOUT0 / GPIO39
R5046 1 2 10K_0402_5% TB_GPIO7 V13 BG2
TB_GPIO6 SDATAOUT1 / GPIO48 VSS_NCTF_15
33 TB_GPIO6
R5047 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
TB_GPIO7 SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
33 TB_GPIO7
+3V_PCH R281 1 2 10K_0402_5% GPIO57 D6 BH3
GPIO57 VSS_NCTF_17
FOR PROCESSOR SELECT
VSS_NCTF_18 BH47
R5050
10K_0402_5% T81 PAD A4 BJ4 PAD T64
mSATA_PCH VSS_NCTF_1 VSS_NCTF_19 +1.8VS
43 mSATA_DETEC# 1 2
0308 A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

2
R5051 EC_LID_OUT# change to GPIO15 T78 PAD A45 BJ45 PAD T62
0_0402_5% VSS_NCTF_3 VSS_NCTF_21 R4914

NCTF
1 2 mSATA_PCH T79 PAD A46 BJ46 PAD T63 2.2K_0402_5%
41 mSATA_DET# short@ VSS_NCTF_4 VSS_NCTF_22
mSATA_PCH change to GPIO27 R241
T84 PAD A5 BJ5 PAD T68

1
B VSS_NCTF_5 VSS_NCTF_23 NV_CLE B
1 2 H_SNB_IVB# 5
A6 BJ6 1K_0402_5%
PCH_WLBT_OFF_51# VSS_NCTF_6 VSS_NCTF_24
41 PCH_WLBT_OFF_51#
B3 VSS_NCTF_7 VSS_NCTF_25 C2 CLOSE TO THE BRANCHING POINT
3G_DET# B47 C48
41 3G_DET# VSS_NCTF_8 VSS_NCTF_26
3G_OFF#
41 3G_OFF#
PCH_BT_ON# BD1 D1 PAD T72
PCH_BT_ON# VSS_NCTF_9 VSS_NCTF_27
PA0_WAKEUP BD49 D49 PAD T73
PA0_WAKEUP VSS_NCTF_10 VSS_NCTF_28
R5063 T86 PAD BE1 E1 PAD T70
10K_0402_5% VSS_NCTF_11 VSS_NCTF_29
1 2 PCH_GPIO37 T116 PAD BE49 E49 PAD T71
VSS_NCTF_12 VSS_NCTF_30
T76 PAD BF1 F1
VSS_NCTF_13 VSS_NCTF_31
T77 PAD BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989

+3VS

PCH_GPIO38 PCH_GPIO67 Function GPU_ID


1

R5167 R5179
10K_0402_5% 10K_0402_5%
UMA@ UMA@
A 0 0 PX4.0 0 A
2

PCH_GPIO38
0 1 Reserved 1 DGPU_PRSNT#
DGPU_PRSNT# 13
1

1 0 DIS 2 R5180 R5181


10K_0402_5% 10K_0402_5%
1 1 UMA 3 PX@ PX@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 17 of 48
5 4 3 2 1
5 4 3 2 1

PCH Power Rail Table


+1.05VS UH1G POWER +3VS S0 Iccmax
+1.05VS_PCH Voltage Rail Voltage Current
1300mA (A)
+1.05VS_PCH AA23 U48 +VCCADAC
VCCCORE[1] 1mA VCCADAC

0.01U_0402_16V7K
AC23 VCCCORE[2]
V_PROC_IO 1.05 0.001

1
1U_0402_6.3V6K

C5039

1U_0402_6.3V6K

C5040

1U_0402_6.3V6K

C5044

C5041

0.1U_0402_10V7K
C5042

10U_0603_6.3V6M
C5043
AD21

CRT
VCCCORE[3]

1
10U_0603_6.3V6M

C5038
AD23 VCCCORE[4] VSSADAC U47
AF21 V5REF 5 0.001

VCC CORE

2
VCCCORE[5]
AF23

2
D VCCCORE[6] +3VS D
AG21 VCCCORE[7]
AG23 V5REF_Sus 5 0.001
VCCCORE[8] +VCCA_LVDS
AG24 VCCCORE[9] 1mA VCCALVDS AK36
AG26 VCCCORE[10]
AG27 AK37 Vcc3_3 3.3 0.266
VCCCORE[11] VSSALVDS
AG29 VCCCORE[12]
AJ23 VCCCORE[13]

LVDS
AJ26 VCCCORE[14] VCCTX_LVDS[1] AM37 VccADAC 3.3 0.001
AJ27 +1.8VS
VCCCORE[15]
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38
AJ31 VCCCORE[17]
VccADPLLA 1.05 0.08
+1.05VS_PCH AP36 +VCCTX_LVDS
60mA VCCTX_LVDS[3]

1
22U_0805_6.3V6M
C5047
AP37 VccADPLLB 1.05 0.08
+1.05VS_VCCDPLLEXP VCCTX_LVDS[4] C5045 C5046
AN19 VCCIO[28] 0.01U_0402_16V7K 0.01U_0402_16V7K

2
VccCore 1.05 1.3
PAD T87 @ +VCCAPLLEXP BJ22 +3VS
VCCAPLLEXP
This pin can be left as no connect in V33 +3VS_VCC3_3_6 VccDMI 1.05 0.042
VCC3_3[6]

HVCMOS
AN16
On-Die VR enabled mode (default). VCCIO[15]

1
AN17 VCCIO[16]
VccIO 1.05 2.925
V34 C5048
VCC3_3[7]
0.1U_0402_10V7K

2
AN21 VCCIO[17]
VccASW 1.05 1.01
AN26 VCCIO[18]
VccSPI 3.3 0.02
AN27 2925mA AT16 +VCCAFDI_VRM
VCCIO[19] VCCVRM[3]
+1.05VS_PCH AP21 +VCCP_VCCDMI +1.05VS_PCH VccDSW 3.3 0.003
C VCCIO[20] C
+1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI
VCCIO[21] VCCDMI[1]
VccpNAND 1.8 0.19

1
+1.05VS_PCH
1U_0402_6.3V6K

C5050

1U_0402_6.3V6K

C5051

1U_0402_6.3V6K

C5052

1U_0402_6.3V6K

C5054

DMI
AP24 VCCIO[22]
1

1
10U_0603_6.3V6M

C5049

VCCIO
C5053
AP26 20mA VCCCLKDMI AB36 +1.05VS_VCC_DMI_CCI 1U_0402_6.3V6K VccRTC 3.3 6 uA

2
VCCIO[23]
2

1
AT24 1/3
VCCIO[24] C5055 VccSus3_3 3.3 0.119
1U_0402_6.3V6K

2
AN33 VCCIO[25]
VccSusHDA 3.3 / 1.5 0.01
AN34 VCCIO[26] VCCDFTERM[1] AG16
+3VS +VCCPNAND +1.8VS
VccVRM 1.8 / 1.5 0.16
+3VS_VCCA3GBG BH29 AG17
VCC3_3[3] 190mA VCCDFTERM[2]

DFT / SPI
1

C5056 VccCLKDMI 1.05 0.02


0.1U_0402_10V7K AJ16
VCCDFTERM[3]

1
C5057
2

+VCCAFDI_VRM AP16 0.1U_0402_10V7K VccSSC 1.05 0.095


VCCVRM[2]
AJ17

2
T768PAD VCCDFTERM[4] SBA@
+1.05VS_VCCAPLL_FDI BG6 2 1 +3VM VccDIFFCLKN 1.05 0.055
VccAFDIPLL R393
+1.05VS_PCH 0_0402_5%
+1.05VS_VCCDPLL_FDI AP17 VccALVDS 3.3 0.001
VCCIO[27] +3V_VCCPSPI
V1 2 1
FDI

20mA VCCSPI +3VS


R386
+VCCP_VCCDMI AU20 0_0402_5% VccTX_LVDS 1.8 0.06
VCCDMI[2]

1
NOSBA@
C5059
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B

+VCCAFDI_VRM 2
+1.5VS
R5053 0_0603_5%

2 1 +VCCAFDI_VRM

short@

VCCVRM==>1.5V FOR MOBILE


VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 18 of 48
5 4 3 2 1
5 4 3 2 1

Have internal VRM


+3VS +1.05VS_PCH

2 @ 1 R5055 +VCCACLK
0_0402_5%
L3
10UH_LQM21FN100M70L_20%
+3VS_VCC_CLKF33 +3V_PCH
1 2 UH1J POWER +1.05VS_PCH

1
+3VALW +3V_PCH

10U_0603_6.3V6M

C5060

1U_0402_6.3V6K

C5061
AD49 N26 +1.05VS_VCCUSBCORE @
VCCACLK VCCIO[29]

1
2

1
C5063 P26 2 1
0.1U_0402_10V7K VCCIO[30] C5064
T16 3mA

2
C5062 VCCDSW3_3 1U_0402_6.3V6K 2MM J20
P28
L3,L5,L6

2
D
0.1U_0402_10V7K VCCIO[31] D

S
+PCH_VCCDSW Q120

D
2 1 V12 T27 3 1
SHI00003900 DCPSUSBYP VCCIO[32]
@ T29 SI2301BDS-T1-E3_SOT23-3
+3VS_VCC_CLKF33 VCCIO[33] +3V_PCH @ @ @

G
T38

2
VCC3_3[5]

1
10U_0603_6.3V6M

C5241

1U_0402_6.3V6K
C5242
T764PAD T23
119mA VCCSUS3_3[7]

0.1U_0402_10V7K
+VCCAPLL_CPY_PCH BH23

2
VCCAPLLDMI2 +3V_PCH

C5066
VCCSUS3_3[8] T24

1
+1.05VS_PCH +VCCDPLL_CPY AL29 VCCIO[14]
VCCSUS3_3[9] V23 43 PCH_PWR_EN# 2 R711 1

0.1U_0402_10V7K
USB

1
+VCCSUS1 AL24 V24 C5067 0_0402_5% 1
DCPSUS[3] VCCSUS3_3[10]

C5104
0.1U_0402_10V7K @

1
C5068 P24

2
+1.05VS_PCH 1U_0402_6.3V6K VCCSUS3_3[6] +1.05VS_PCH
@ 2 @
AA19
J20/J21 CLOSE

2
+1.05VM VCCASW[1] +1.05VS_VCCAUPLL
VCCIO[34] T26
NOSBA@ AA21 1010mA
VCCASW[2]
1 2
R1132 1 20_0603_5% AA24 M26 +PCH_V5REF_SUS C5072
VCCASW[3] 1mA V5REF_SUS

22U_0805_6.3V6M

22U_0805_6.3V6M
R1133 0_0603_5% 1U_0402_6.3V6K

1
+5VALW +5V_PCH

C5070

C5071
NOSBA@ AA26 @

Clock and Miscellaneous


VCCASW[4] +VCCA_USBSUS @
DCPSUS[4] AN23 1 2
AA27

2
VCCASW[5]
VCCSUS3_3[1] AN24 +3V_PCH 2 1
AA29 VCCASW[6] 2MM J21
AA31 VCCASW[7]

S
Q121

D
3 1
+PCH_V5REF_RUN +3V_PCH
AC26 VCCASW[8] 1mA V5REF P34
SI2301BDS-T1-E3_SOT23-3

1
1U_0402_6.3V6K

C5073

1U_0402_6.3V6K

C5074

1U_0402_6.3V6K

C5075
@ @ @

G
AC27

2
VCCASW[9]

1
10U_0603_6.3V6M

C5243

1U_0402_6.3V6K
C5244
C
VCCSUS3_3[2] N20 C

1
PCI/GPIO/LPC
AC29 C5076
2

2
VCCASW[10] 1U_0402_6.3V6K PCH_PWR_EN#
N22 2 R710 1

2
+1.05VS_PCH VCCSUS3_3[3]

0.1U_0402_10V7K
AC31

2
L5 VCCASW[11] +3VS 0_0402_5%
VCCSUS3_3[4] P20 1

C5103
10UH_LQM21FN100M70L_20% AD29 @
+VCCA_DPLL_L +1.05VS_VCCA_A_DPL VCCASW[12]
1 2 VCCSUS3_3[5] P22
AD31 VCCASW[13]

1
L6 C5078 2 @
1 2 +1.05VS_VCCA_B_DPL W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]

2
+3VS
220U_B2_2.5VM_R35

C5079
1U_0402_6.3V6K

C5080

220U_B2_2.5VM_R35

C5081
1U_0402_6.3V6K

C5082

10UH_LQM21FN100M70L_20% W23 W16


VCCASW[15] VCC3_3[8]
1

1
1

+ + W24 T34 +3VS_VCCPPCI


VCCASW[16] VCC3_3[4]

1
W26 C5083
2

VCCASW[17] 0.1U_0402_10V7K +5V_PCH +3V_PCH +5VS +3VS


+3VS
W29

2
VCCASW[18]

2
W31 AJ2 +VCC3_3_2
VCCASW[19] VCC3_3[2] +1.05VS_SATA3 +1.05VS_PCH R5056 D4602 R5057 D3

1
W33 100_0402_5% CH751H-40PT_SOD323-2 100_0402_5% CH751H-40PT_SOD323-2
+VCCDIFFCLK VCCASW[20] C5084
+1.05VS_PCH VCCIO[5] AF13
0.1U_0402_10V7K

1
1
+VCCRTCEXT N16 +PCH_V5REF_SUS +PCH_V5REF_RUN
DCPRTC
1

C5085 AH13 C296


VCCIO[12]
1

0.1U_0402_10V7K
1U_0402_6.3V6K C297 1U_0402_6.3V6K

2
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 1
2

VCCVRM[4] VCCIO[13]

1
C5069

1U_0402_6.3V6K
C5077
2

+1.05VS_VCCDIFFCLKN
+1.05VS_PCH +1.05VS_VCCDIFFCLKN AF14

2
+1.05VS_VCCA_A_DPL VCCIO[6] PAD T765
PADT765 2
BD47 VCCADPLLA
1

80mA

SATA
AK1 +VCCSATAPLL
C298 +1.05VS_VCCA_B_DPL VCCAPLLSATA +VCCAFDI_VRM
B
BF47 VCCADPLLB 80mA B
1U_0402_6.3V6K
2

AF11 +VCCAFDI_VRM
+VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS_PCH
AF17 VCCIO[7]
AF33 VCCDIFFCLKN[1]
+1.05VS_PCH +1.05VS_SSCVCC AF34 55mA AC16 +1.05VS_VCC_SATA
+1.05VS_VCCDIFFCLKN VCCDIFFCLKN[2] VCCIO[2]
AG34 VCCDIFFCLKN[3] FOR SBA
1

AC17
VCCIO[3] +3VALW TO +3VM

1
C301 C300
1U_0402_6.3V6K +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
2

R5058 VCCSSC 95mA VCCIO[4]

2
0_0402_5% +3VALW
@ +VCCSST V16 @ +3VM
+1.05VM_VCCSUS DCPSST +1.05VM
+1.05VS_PCH 2 1
1

2 1
C5111 C5086 +1.05VM_VCCSUS T17 T21
DCPSUS[1] VCCASW[22]
1

1
1U_0402_6.3V6K 0.1U_0402_10V7K V19 2MM J17 SBA@ SBA@
2

DCPSUS[2]

1
10U_0603_6.3V6M

C5235

1U_0402_6.3V6K
C5233
@ R5143
MISC

+1.05VS_PCH

S
Q119 470_0603_5%

D
V21 3 1
2

VCCASW[23] @

2
CPU

+V_CPU_IO BJ8 SI2301BDS-T1-E3_SOT23-3


V_PROC_IO 1mA

2
+5VALW SBA@

G
T19

2
VCCASW[21]
1

1
+RTCVCC +3V_PCH D
4.7U_0603_6.3V6K

C5087
0.1U_0402_10V7K

C5088
0.1U_0402_10V7K

C5089

R387
0_0402_5% 2N7002H_SOT23-3
2
A22 P32 +VCCSUSHDA 2 1 Q17 G
RTC

10mA VCCSUSHDA
2

VCCRTC
HDA

short@ R5140 SLP_A R5102 @ S

3
1U_0402_6.3V6K

C5090
0.1U_0402_10V7K

C5091
0.1U_0402_10V7K

C5092
1

PANTHER-POINT_FCBGA989 C5093 20K_0402_5% 20K_0402_5%


0.1U_0402_16V4Z SBA@ SBA@
1
2

1
C5234
D 0.1U_0603_25V7K SLP_A
2 SBA@
43,53 M_PWR_ON 2
A G Q118 A
S
SBA@ 2N7002K_SOT23-3

3
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/25 2012/08/25 Title
Issued Date Deciphered Date SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 19 of 48
5 4 3 2 1
5 4 3 2 1

UH1I

AY4 VSS[159] VSS[259] H46


AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
UH1H B11 VSS[163] VSS[263] K46
D D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38 B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4 B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46 B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17 BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42 BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8 BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48 BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13 BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18 BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22 BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26 BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28 BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30 BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34 BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39 BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42 BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46 BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7 BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24 H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16 BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20 BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24 BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30 BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38 BH43 VSS[227] VSS[329] N24
B B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8 D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18 D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2 D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22 D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26 D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28 D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36 D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48 D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12 E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22 G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28 G20 VSS[245] VSS[351] BG28
G26 VSS[246] VSS[352] BJ28
PANTHER-POINT_FCBGA989 G28 VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30 VSS[255]
H32 VSS[256]
H34 VSS[257]
F3 VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 20 of 48
5 4 3 2 1
5 4 3 2 1

+3VS_VGA

U65A
PCH_THRMTRIP#_R 17

1
PCIE_CTX_GRX_N[0..15]
4 PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P0 AN12 Part 1 of 7
PEX_RX0

3
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 AM12 P6 GPU_VID4 RV208
4 PCIE_CTX_GRX_P[0..15] PEX_RX0_N GPIO0 GPU_VID4 56
PCIE_CTX_GRX_P1 AN14 M3 GPU_VID3 10K_0402_5% QV7B
PCIE_CRX_GTX_N[0..15] PEX_RX1 GPIO1 GPU_VID3 56
PCIE_CTX_GRX_N1 AM14 L6 PX@ DMN66D0LDW-7 2N_SOT363-6
4 PCIE_CRX_GTX_N[0..15]

2
PCIE_CTX_GRX_P2 PEX_RX1_N GPIO2 VGA_GPIO3 0_0402_5% 1
AP14 PEX_RX2 GPIO3 P5 2DPRSLPVR_VGA DPRSLPVR_VGA 56 5
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N2 AP15 P7 RV113 @ PX@
4 PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4

6
PCIE_CTX_GRX_P3 AN15 L7 GPU_VID1 QV7A
GPU_VID1 56

4
PCIE_CTX_GRX_N3 PEX_RX3 GPIO5 GPU_VID2 DMN66D0LDW-7 2N_SOT363-6
AM15 PEX_RX3_N GPIO6 M7 GPU_VID2 56
PCIE_CTX_GRX_P4 AN17 N8 PX@
PCIE_CTX_GRX_N4 PEX_RX4 GPIO7 OVERT#
AM17 PEX_RX4_N GPIO8 M1 2
PCIE_CTX_GRX_P5 AP17 M2 GC6_EVENT#_R
D
PCIE_CTX_GRX_N5 PEX_RX5 GPIO9 PX@ D
AP18 L1

1
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO10 GPU_VID0 DV3
AN18 M5 GPU_VID0 56

GPIO
PCIE_CTX_GRX_N6 PEX_RX6 GPIO11 VGA_GPIO12
AM18 PEX_RX6_N GPIO12 N3 2 1 VGA_AC_DET 43,56
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5
PEX_RX7 GPIO13 GPU_VID5 56
PCIE_CTX_GRX_N7 AM20 N4 CH751H-40PT_SOD323-2
PCIE_CTX_GRX_P8 PEX_RX7_N GPIO14 VGA_GPIO15 100K_0402_5% 1
AP20 PEX_RX8 GPIO15 P2 2 RV17 @
PCIE_CTX_GRX_N8 AP21 R8 VGA_GPIO16 0_0402_5% 1 2 RV114 @ DPRSLPVR_VGA
PCIE_CTX_GRX_P9 PEX_RX8_N GPIO16
AN21 PEX_RX9 GPIO17 M6
PCIE_CTX_GRX_N9 AM21 R1
PCIE_CTX_GRX_P10 PEX_RX9_N GPIO18
AN23 PEX_RX10 GPIO19 P3
PCIE_CTX_GRX_N10 AM23 P4
PCIE_CTX_GRX_P11 PEX_RX10_N GPIO20
AP23 PEX_RX11 GPIO21 P1
PCIE_CTX_GRX_N11 AP24
PCIE_CTX_GRX_P12 PEX_RX11_N
AN24 PEX_RX12
PCIE_CTX_GRX_N12 AM24
+3VS_VGA PCIE_CTX_GRX_P13 PEX_RX12_N
AN26 PEX_RX13
PCIE_CTX_GRX_N13 AM26
+3VS_VGA PCIE_CTX_GRX_P14 PEX_RX13_N +3VS_VGA
AP26 PEX_RX14
PCIE_CTX_GRX_N14 AP27 PEX_RX14_N
2

PCIE_CTX_GRX_P15 AN27 AK9


RV24 RV25 PCIE_CTX_GRX_N15 PEX_RX15 DACA_RED GC6_EVENT#_R PX@
AM27 PEX_RX15_N DACA_GREEN AL10 1 2
2.2K_0402_5% 2.2K_0402_5% AL9 RV49 10K_0402_5%
PX@ PX@ DACA_BLUE VGA_EDID_CLK PX@
1 2

DACs
5

PCIE_CRX_GTX_P0 CV6 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P0 AK14 RV3 2.2K_0402_5%


1

QV1B PCIE_CRX_GTX_N0 CV7 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N0 PEX_TX0 VGA_EDID_DATA PX@


1 2 AJ14 PEX_TX0_N DACA_HSYNC AM9 1 2
VGA_SMB_CK2 4 3 PCIE_CRX_GTX_P1 CV8 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P1 AH14 AN9 RV4 2.2K_0402_5%
EC_SMB_CK2 13,42,43 PEX_TX1 DACA_VSYNC
PCIE_CRX_GTX_N1 CV9 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N1 AG14 VGA_CRT_DATA 1 2 PX@
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P2 CV10 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P2 PEX_TX1_N 10K_0402_5% RV10 2.2K_0402_5%
1 2 AK15 PEX_TX2
PX@ PCIE_CRX_GTX_N2 CV11 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N2 AJ15 AG10 +DACA_VDD 2 RV107 1 VGA_CRT_CLK 1 2 PX@
PEX_TX2_N DACA_VDD

PCI EXPRESS
PCIE_CRX_GTX_P3 CV12 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P3 AL16 AP9 RV11 2.2K_0402_5%
PCIE_CRX_GTX_N3 CV13 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N3 PEX_TX3 DACA_VREF PX@ I2CB_SCL PX@
1 2 AK16 PEX_TX3_N DACA_RSET AP8 1 2
PCIE_CRX_GTX_P4 CV15 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P4 AK17 RV12 2.2K_0402_5%
PEX_TX4
2

PCIE_CRX_GTX_N4 CV17 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N4 AJ17 I2CB_SDA 1 2 PX@


QV1A PCIE_CRX_GTX_P5 CV19 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P5 PEX_TX4_N RV13 2.2K_0402_5%
1 2 AH17 PEX_TX5
VGA_SMB_DA2 1 6 PCIE_CRX_GTX_N5 CV14 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N5 AG17 OVERT# 1 2 PX@
EC_SMB_DA2 13,42,43 PEX_TX5_N
PCIE_CRX_GTX_P6 CV16 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P6 AK18 RV1 10K_0402_5%
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N6 CV18 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N6 PEX_TX6 VGA_GPIO12 PX@
1 2 AJ18 PEX_TX6_N 1 2
C PX@ PCIE_CRX_GTX_P7 CV20 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P7 AL19 RV2 10K_0402_5% C
PCIE_CRX_GTX_N7 CV22 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N7 PEX_TX7 VGA_CRT_CLK
1 2 AK19 PEX_TX7_N I2CA_SCL R4
PCIE_CRX_GTX_P8 CV24 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P8 AK20 R5 VGA_CRT_DATA
PCIE_CRX_GTX_N8 CV26 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N8 PEX_TX8 I2CA_SDA
1 2 AJ20 PEX_TX8_N
PCIE_CRX_GTX_P9 CV21 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL
PCIE_CRX_GTX_N9 CV23 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N9 PEX_TX9 I2CB_SCL I2CB_SDA
1 2 AG20 PEX_TX9_N I2CB_SDA R6
PCIE_CRX_GTX_P10 CV25 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P10 AK21

I2C
PCIE_CRX_GTX_N10 CV27 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N10 PEX_TX10 VGA_EDID_CLK
1 2 AJ21 PEX_TX10_N I2CC_SCL R2
PCIE_CRX_GTX_P11 CV29 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P11 AL22 R3 VGA_EDID_DATA
PCIE_CRX_GTX_N11 CV31 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N11 PEX_TX11 I2CC_SDA
1 2 AK22 PEX_TX11_N
PCIE_CRX_GTX_P12 CV33 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P12 AK23 T4 VGA_SMB_CK2
PCIE_CRX_GTX_N12 CV28 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N12 PEX_TX12 I2CS_SCL VGA_SMB_DA2
1 2 AJ23 PEX_TX12_N I2CS_SDA T3
PCIE_CRX_GTX_P13 CV30 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P13 AH23 +1.05VS_VGA
PCIE_CRX_GTX_N13 CV32 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N13 PEX_TX13
1 2 AG23 PEX_TX13_N
PCIE_CRX_GTX_P14 CV36 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P14 AK24 30 ohms @100MHz (ESR=0.05)
PCIE_CRX_GTX_N14 CV41 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N14 PEX_TX14
1 2 AJ24 PEX_TX14_N
PCIE_CRX_GTX_P15 CV34 1 2 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_P15 AL25 60mA LV7 PX@
PCIE_CRX_GTX_N15 CV35 0.1U_0402_10V7K PX@ PCIE_CRX_C_GTX_N15 PEX_TX15 +PLLVDD
1 2 AK25 PEX_TX15_N 1 2
+3VS_VGA +3VS_VGA RV112 @ FBMA-10-100505-300T 0402

22U_0805_6.3V6M
0.1U_0402_10V7K

CV131
PLLVDD AD8 1 2 1 1

CV40
AJ11 45mA 0_0402_5%
PEX_WAKE_N
SP_PLLVDD AE8
CLK_PCIE_VGA PX@ PX@
13 CLK_PCIE_VGA AL13 PEX_REFCLK 45mA Near GPU
2

@ CLK_PCIE_VGA# +SP_PLLVDD 2 2
13 CLK_PCIE_VGA# AK13 PEX_REFCLK_N VID_PLLVDD AD7
RV105 CLK_REQ_GPU#

CLK
AK12 PEX_CLKREQ_N
10K_0402_5%
PEX_TSTCLK_OUT XTALIN
Differential signal 1 2 AJ26 PEX_TSTCLK_OUT XTAL_IN H3
5

RV20 200_0402_1% PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT


1

PEX_TSTCLK_OUT_N XTAL_OUT
2 Default leave empty @
Under GPU
P

13,16,33,39,41,43,46 PLT_RST# B
4 PLT_RST_VGA# AJ12 J4 XTALOUT
Y PEX_TERMP PEX_RST_N XTAL_OUTBUFF XTALSSIN
16 DGPU_HOLD_RST# 1 A AP29 PEX_TERMP XTAL_SSIN H1
G

1
3

UV2 RV18 RV26 RV27


2

NC7SZ08P5X_NL_SC70-5 100K_0402_5% 10K_0402_5% 10K_0402_5%


PX@ PX@ RV22 N13P-GLP-A1_FCBGA908
PX@ PX@ PX@
2

2
2.49K_0402_1%
B B
PX@
1

PX@
RV29
Under GPU(below 150mils)
16,23 DGPU_PWR_EN 2 1
PX@
150mA
10K_0402_5% +1.05VS_VGA 1 2 +SP_PLLVDD

22U_0805_6.3V6M
LV1

0.1U_0402_10V7K

0.1U_0402_10V7K
4.7U_0402_6.3V6M
+3VS_VGA

CV4

CV5
CV112

CV113
2 BLM18PG330SN1D_0603 1 1 1 1
180ohms (ESR=0.2) Bead
CV139
0.1U_0402_10V7K PX@ PX@ PX@
2 PX@
2

PX@ 1 2 2 2
RV30
10K_0402_5%
2

PX@
G

13 CLK_REQ_VGA# 1 3 CLK_REQ_GPU# PX@


1 2
D

RV23 10M_0402_5%
2

QV2
2N7002H 1N_SOT23-3 RV32
PX@ 10K_0402_5% YV1
@ 4 3 XTAL_OUT
NC OSC
1 2
1

RV110 0_0402_5% XTALIN 1 2


@ OSC NC
1 27MHZ 16PF +-30PPM X3G027000FG1H-HX 1
PX@
CV37 PX@ CV38 PX@
27P_0402_50V8J 27P_0402_50V8J
2 2

A
YV1 : SJ10000CV00 A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 21 of 48
5 4 3 2 1
5 4 3 2 1

U65D

D Part 4 of 7 D
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28
AN5 IFPA_TXD1 NC AJ4
AM5 IFPA_TXD1_N NC AJ5
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15

NC
AJ6 IFPA_TXD3 NC D19
AH6 IFPA_TXD3_N NC D20
NC D23
NC D26
AJ9 IFPB_TXC NC H31
AH9 IFPB_TXC_N NC T8
AP6 IFPB_TXD4 NC V32
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N
AK8 IFPB_TXD7
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA VCCSENSE_VGA 56
VDD_SENSE
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA VSSSENSE_VGA 56
IFPC_L1 GND_SENSE
AJ2 IFPC_L1_N
AH3 IFPC_L2 trace width: 16mils
AH4
AG5
IFPC_L2_N differential voltage sensing.
IFPC_L3
C
AG4 IFPC_L3_N differential signal routing. C
TEST
AM1 AK11 TESTMODE
IFPD_L0 TESTMODE
AM2 IFPD_L0_N
AM3 IFPD_L1 JTAG_TCK AM10 TV2

1
AM4 IFPD_L1_N JTAG_TDI AM11 TV3
AL3 IFPD_L2 JTAG_TDO AP12 TV4
AL4 AP11 10K_0402_5%
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
IFPD_L3 JTAG_TRST_N RV34 10K_0402_5% PX@
AK5

2
IFPD_L3_N

LVDS/TMDS
PX@

AD2 IFPE_L0
AD3 IFPE_L0_N
AD1
AC1
IFPE_L1 SERIAL
IFPE_L1_N ROM_CS
AC2 IFPE_L2 ROM_CS_N H6
AC3 H4 ROM_SCLK ROM_SCLK 30
IFPE_L2_N ROM_SCLK ROM_SI
AC4 IFPE_L3 ROM_SI H5 ROM_SI 30
AC5 H7 ROM_SO ROM_SO 30
IFPE_L3_N ROM_SO

AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5
AD4
IFPF_L1_N GENERAL RV35 PX@ 10K_0402_5%
IFPF_L2
AD5 IFPF_L2_N BUFRST_N L2 2 1
AG1 IFPF_L3
AF1 IFPF_L3_N CEC L3 1 2 +3VS_VGA
RV230 PX@ 10K_0402_5% 09/14 3V3 on N13P-GL/ for CEC signal
MULTI_STRAP_REF0_GND J1 1 2
B RV38 PX@ 40.2K_0402_1% B
AG3 IFPC_AUX_I2CW_SCL
AG2 IFPC_AUX_I2CW_SDA_N
J2 STRAP0 STRAP0 30
STRAP0 STRAP1
STRAP1 J7 STRAP1 30
AK3 J6 STRAP2 STRAP2 30
IFPD_AUX_I2CX_SCL STRAP2 STRAP3
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5 STRAP3 30
J3 STRAP4 STRAP4 30
STRAP4
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N

N13P-GLP-A1_FCBGA908
PX@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 22 of 48
5 4 3 2 1
5 4 3 2 1

+1.5VS_VGA U65E
Near GPU
Near GPU Part 5 of 7 2000mA +1.05VS_VGA
D 3.5A D

AA27 FBVDDQ_0 PEX_IOVDD_0 AG19

CV273
22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 FBVDDQ_1 PEX_IOVDD_1 AG21

CV269

CV270

CV271

CV272

CV43

CV44

CV45

CV46

CV47

CV48

CV49

CV50

CV51

CV52
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 2 2 2 2 AB27 FBVDDQ_2 PEX_IOVDD_2 AG22 1 1 1 1 1 1 2 2 2 2
AB33 FBVDDQ_3 PEX_IOVDD_3 AG24
AC27 FBVDDQ_4 PEX_IOVDD_4 AH21
@ PX@ PX@ PX@ PX@ AD27 AH25 PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 1 1 1 1 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AE27 FBVDDQ_6
AF27 FBVDDQ_7
+1.5VS_VGA AG27 AG13
FBVDDQ_8 PEX_IOVDDQ_0
4.7uF X7R 0402 * 2 B13 FBVDDQ_9 PEX_IOVDDQ_1 AG15 Under GPU(below 150mils) +1.05VS_VGA
B16 FBVDDQ_10 PEX_IOVDDQ_2 AG16

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
Under GPU(below 150mils) B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18

CV54

CV53

CV56

CV55
1uF X7R 0402 * 2 0.1uF X7R 0402 * 8 E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25 1 1 1 1
0.1U_0402_10V7K E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
CV267

CV268

CV277

CV278

CV279

CV280

CV292

CV287

CV294

CV284

CV285

CV286
1U_0603_6.3V6M

1U_0603_6.3V6M

PX@ PX@ PX@ PX@


4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26


2 2 2 2
H11 FBVDDQ_16 PEX_IOVDDQ_8 AH27
PX@ PX@ H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ H13 AK27
2 PX@ 2 PX@ 2 2 2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_10
H14 AL27

POWER
FBVDDQ_19 PEX_IOVDDQ_11
H15 FBVDDQ_20 PEX_IOVDDQ_12 AM28 Under GPU(below 150mils)
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
H18 FBVDDQ_22
H19 +3VS_VGA +1.05VS_VGA
FBVDDQ_23 LV2 PX@
H20 FBVDDQ_24 120mA
+PEX_PLLHVDD RV138 1 2 0_0402_5% +PEX_PLLVDD

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H21 FBVDDQ_25 PEX_PLL_HVDD AH12 2 1

CV70

CV74

CV73

1U_0603_10V6K
PX@

0.1U_0402_10V7K

4.7U_0805_25V6-K
H22 FBVDDQ_26 1 1 1

CV3
CV65

CV66
H23 1 1 1 BLM18PG121SN1D_0603
FBVDDQ_27
H24 FBVDDQ_28 120ohms @100MHz (ESR=0.18)
H8 AG12 +PEX_SVDD3V3 PX@ PX@ PX@
FBVDDQ_29 PEX_SVDD_3V3 2 2 2 PX@ PX@ PX@
H9
rise 1.5v system source voltage to 1.55-1.57V L27
FBVDDQ_30
FBVDDQ_31
2 2 2
M27 FBVDDQ_32
N27 AG26 +PEX_PLLVDD
FBVDDQ_33 PEX_PLLVDD
P27 FBVDDQ_34
R27 FBVDDQ_35 Place near balls
C T27 FBVDDQ_36
C
T30 J8 +3VS_VGA
FBVDDQ_37 VDD33_0 RV5
T33 FBVDDQ_38 VDD33_1 K8 Place near balls Place near GPU
V27 L8 0_0603_5%
FBVDDQ_39 VDD33_2 +VDD33
0919 Follow NV recommanded W27 FBVDDQ_40 VDD33_3 M8 2 1

1U_0402_6.3V6K
0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
W30 FBVDDQ_41
+1.5VS_VGA

CV109

CV111

CV293

CV75
W33 1 1 1 1 short@
FBVDDQ_42
Y27 FBVDDQ_43
IFPAB_PLLVDD AH8 +IFPAB_PLLVDD RV48 1 2 10K_0402_5% PX@
@ AJ8 RV40 1 2 1K_0402_1% @
FB_VDDQ_SENSE IFPAB_RSET 2 PX@ 2 PX@ 2 PX@ 2 PX@
2 RV141 1
0_0402_5%
IFPA_IOVDD AG8 +IFPAB_IOVDD RV65 1 2 10K_0402_5% PX@
IFPB_IOVDD AG9
2 RV142 1 @ FB_VSS_SENSE F1
0_0402_5% FB_VDDQ_SENSE

IFPC_PLLVDD AF7 +IFPC_PLLVDD RV42 1 2 10K_0402_5% PX@


+1.5VS_VGA F2 AF8 RV43 2 1 1K_0402_1% @
FB_GND_SENSE IFPC_RSET

IFPC_IOVDD AF6 +IFPC_IOVDD RV44 1 2 10K_0402_5% PX@


1 2 J27 FB_CAL_PD_VDDQ
RV6 PX@ 40.2_0402_1%
CALIBRATION PIN DDR3 AG7 +IFPD_PLLVDD RV45 1 2 10K_0402_5% PX@
IFPD_PLLVDD RV46 1
1 2 H27 FB_CAL_PU_GND IFPD_RSET AN2 2 1K_0402_1% @
RV8 PX@ 42.2_0402_1%
FB_CAL_x_PD_VDDQ 40.2Ohm AG6 +IFPD_IOVDD RV47 1 2 10K_0402_5% PX@
IFPD_IOVDD
1 2 H25 FB_CAL_TERM_GND
RV9 PX@ 51.1_0402_1%
FB_CAL_x_PU_GND 42.2Ohm AB8 +IFPEF_PLLVDD RV72 1 2 10K_0402_5% PX@
IFPEF_PLVDD RV50 1
IFPEF_RSET AD6 2 1K_0402_1% PX@
FB_CAL_xTERM_GND 51.1Ohm Place near balls AC7
IFPE_IOVDD +IFPE_IOVDD RV73 1
IFPF_IOVDD AC8 2 10K_0402_5% PX@

+3VS to +3VS_VGA
N13P-GLP-A1_FCBGA908
B B

PX@ +3VS +3VS_VGA

QV5
SI2301BDS-T1-E3_SOT23-3
+5VALW PX@
CV57 PX@
10U_0603_6.3V6M

1
R1109

S
0_0402_5%

D
3 1 2 1
@ R1103

1
2 1 100K_0402_5%
9,43,48,51,53,55,56 SUSP#
PX@

G
2

2
RV205 RV206
DGPU_PWR_EN# 1 2 470_0603_5%
10K_0402_5% @

1 2
1
D

CV241
PX@ 1
Q128 D QV6 RV207 @

0.1U_0402_10V7K
16,21 DGPU_PWR_EN 2 1 2
G SSM3K7002FU_SC70-3 2 2 1DGPU_PWR_EN#
R1104 S PX@ PX@ G

3
0_0402_5% 2 S SSM3K7002FU_SC70-3 10K_0402_5%

3
1
PX@ @

R1105

CV242
100K_0402_5%

0.1U_0402_10V7K
1
PX@

2
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 23 of 48
5 4 3 2 1
5 4 3 2 1

D D

U65F

Part 6 of 7
A2 GND_0 GND_100 D2
AA17 GND_1 GND_101 D31
AA18 GND_2 GND_102 D33
AA20 E10 U65G +VGA_CORE
GND_3 GND_103 +VGA_CORE
AA22 GND_4 GND_104 E22
AB12 GND_5 GND_105 E25
AB14 E5 Part 7 of 7 V17
GND_6 GND_106 VDD_56
AB16 GND_7 GND_107 E7 AA12 VDD_0 VDD_57 V18
AB19 GND_8 GND_108 F28 AA14 VDD_1 VDD_58 V20
AB2 GND_9 GND_109 F7 AA16 VDD_2 VDD_59 V22
AB21 GND_10 GND_110 G10 AA19 VDD_3 VDD_60 W12
A33 GND_11 GND_111 G13 AA21 VDD_4 VDD_61 W14
AB23 GND_12 GND_112 G16 AA23 VDD_5 VDD_62 W16
AB28 GND_13 GND_113 G19 AB13 VDD_6 VDD_63 W19
AB30 GND_14 GND_114 G2 AB15 VDD_7 VDD_64 W21
AB32 GND_15 GND_115 G22 AB17 VDD_8 VDD_65 W23
AB5 GND_16 GND_116 G25 AB18 VDD_9 VDD_66 Y13
AB7 GND_17 GND_117 G28 AB20 VDD_10 VDD_67 Y15
AC13 GND_18 GND_118 G3 AB22 VDD_11 VDD_68 Y17
AC15 GND_19 GND_119 G30 AC12 VDD_12 VDD_69 Y18
AC17 GND_20 GND_120 G32 AC14 VDD_13 VDD_70 Y20
AC18 GND_21 GND_121 G33 AC16 VDD_14 VDD_71 Y22
AA13 GND_22 GND_122 G5 AC19 VDD_15
AC20 GND_23 GND_123 G7 AC21 VDD_16
AC22 GND_24 GND_124 K2 AC23 VDD_17 XVDD_1 U1
AE2 GND_25 GND_125 K28 M12 VDD_18 XVDD_2 U2
AE28 GND_26 GND_126 K30 M14 VDD_19 XVDD_3 U3

POWER
AE30 GND_27 GND_127 K32 M16 VDD_20 XVDD_4 U4
AE32 GND_28 GND_128 K33 M19 VDD_21 XVDD_5 U5
AE33 GND_29 GND_129 K5 M21 VDD_22 XVDD_6 U6
C AE5 GND_30 GND_130 K7 M23 VDD_23 XVDD_7 U7 C
AE7 GND_31 GND_131 M13 N13 VDD_24 XVDD_8 U8
AH10 GND_32 GND_132 M15 N15 VDD_25
AA15 GND_33 GND_133 M17 N17 VDD_26
AH13 GND_34 GND_134 M18 N18 VDD_27 XVDD_9 V1
AH16 GND_35 GND_135 M20 N20 VDD_28 XVDD_10 V2
AH19 GND_36 GND_136 M22 N22 VDD_29 XVDD_11 V3
AH2 GND_37 GND_137 N12 P12 VDD_30 XVDD_12 V4
AH22 GND_38 GND_138 N14 P14 VDD_31 XVDD_13 V5
AH24 GND_39 GND_139 N16 P16 VDD_32 XVDD_14 V6
AH28 GND_40 GND_140 N19 P19 VDD_33 XVDD_15 V7
AH29 GND_41 GND_141 N2 P21 VDD_34 XVDD_16 V8
AH30 GND_42 GND_142 N21 P23 VDD_35
GND

AH32 GND_43 GND_143 N23 R13 VDD_36


AH33 GND_44 GND_144 N28 R15 VDD_37 XVDD_17 W2
AH5 GND_45 GND_145 N30 R17 VDD_38 XVDD_18 W3
AH7 GND_46 GND_146 N32 R18 VDD_39 XVDD_19 W4
AJ7 GND_47 GND_147 N33 R20 VDD_40 XVDD_20 W5
AK10 GND_48 GND_148 N5 R22 VDD_41 XVDD_21 W7
AK7 GND_49 GND_149 N7 T12 VDD_42 XVDD_22 W8
AL12 GND_50 GND_150 P13 T14 VDD_43
AL14 GND_51 GND_151 P15 T16 VDD_44
AL15 GND_52 GND_152 P17 T19 VDD_45 XVDD_23 Y1
AL17 GND_53 GND_153 P18 T21 VDD_46 XVDD_24 Y2
AL18 GND_54 GND_154 P20 T23 VDD_47 XVDD_25 Y3
AL2 GND_55 GND_155 P22 U13 VDD_48 XVDD_26 Y4
AL20 GND_56 GND_156 R12 U15 VDD_49 XVDD_27 Y5
AL21 GND_57 GND_157 R14 U17 VDD_50 XVDD_28 Y6
AL23 GND_58 GND_158 R16 U18 VDD_51 XVDD_29 Y7
AL24 GND_59 GND_159 R19 U20 VDD_52 XVDD_30 Y8
AL26 GND_60 GND_160 R21 U22 VDD_53
AL28 GND_61 GND_161 R23 V13 VDD_54
AL30 GND_62 GND_162 T13 V15 VDD_55 XVDD_31 AA1
AL32 GND_63 GND_163 T15 XVDD_32 AA2
AL33 GND_64 GND_164 T17 XVDD_33 AA3
AL5 GND_65 GND_165 T18 XVDD_34 AA4
AM13 GND_66 GND_166 T2 XVDD_35 AA5
B
AM16 GND_67 GND_167 T20 XVDD_36 AA6 B
AM19 GND_68 GND_168 T22 XVDD_37 AA7
AM22 GND_69 GND_169 AG11 XVDD_38 AA8
AM25 GND_70 GND_170 T28
AN1 GND_71 GND_171 T32
AN10 GND_72 GND_172 T5
AN13 T7 N13P-GLP-A1_FCBGA908
GND_73 GND_173 PX@
AN16 GND_74 GND_174 U12
AN19 GND_75 GND_175 U14
AN22 GND_76 GND_176 U16
AN25 GND_77 GND_177 U19
AN30 GND_78 GND_178 U21
AN34 GND_79 GND_179 U23
AN4 GND_80 GND_180 V12
AN7 GND_81 GND_181 V14
AP2 GND_82 GND_182 V16
AP33 GND_83 GND_183 V19
B1 GND_84 GND_184 V21
B10 GND_85 GND_185 V23
B22 GND_86 GND_186 W13
B25 GND_87 GND_187 W15
B28 GND_88 GND_188 W17
B31 GND_89 GND_189 W18
B34 GND_90 GND_190 W20
B4 GND_91 GND_191 W22
B7 GND_92 GND_192 W28
C10 GND_93 GND_193 Y12
C13 GND_94 GND_194 Y14
C19 GND_95 GND_195 Y16
C22 GND_96 GND_196 Y19
C25 GND_97 GND_197 Y21
C28 GND_98 GND_198 Y23
C7 GND_99 GND_199 AH11
GND_OPT C16
GND_OPT W32

A N13P-GLP-A1_FCBGA908 A
PX@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 24 of 48
5 4 3 2 1
5 4 3 2 1

FBA_D[0..63] FBA_MA[15..0] 26,27 FBC_D[0..63] FBC_MA[15..0] 28,29


26,27 FBA_D[0..63] 28,29 FBC_D[0..63]
FBA_BA[2..0] 26,27 FBC_BA[2..0] 28,29

U65C
D D
U65B
Part 3 of 7
Part 2 of 7 FBC_D0 G9 D13 FBC_CS0#_L
FBB_D0 FBB_CMD0 FBC_CS0#_L 28
FBA_D0 L28 U30 FBA_CS0#_L FBC_D1 E9 E14
FBA_D0 FBA_CMD0 FBA_CS0#_L 26 FBB_D1 FBB_CMD1
FBA_D1 M29 T31 FBC_D2 G8 F14 FBC_ODT_L
FBA_D1 FBA_CMD1 FBB_D2 FBB_CMD2 FBC_ODT_L 28
FBA_D2 L29 U29 FBA_ODT_L FBC_D3 F9 A12 FBC_CKE_L
FBA_D2 FBA_CMD2 FBA_ODT_L 26 FBB_D3 FBB_CMD3 FBC_CKE_L 28
FBA_D3 M28 R34 FBA_CKE_L FBC_D4 F11 B12 FBC_MA14
FBA_D3 FBA_CMD3 FBA_CKE_L 26 FBB_D4 FBB_CMD4
FBA_D4 N31 R33 FBA_MA14 FBC_D5 G11 C14 FBC_RST#
FBA_D4 FBA_CMD4 FBB_D5 FBB_CMD5 FBC_RST# 28,29
FBA_D5 P29 U32 FBA_RST# FBC_D6 F12 B14 FBC_MA9
FBA_D5 FBA_CMD5 FBA_RST# 26,27 FBB_D6 FBB_CMD6
FBA_D6 R29 U33 FBA_MA9 FBC_D7 G12 G15 FBC_MA7
FBA_D7 FBA_D6 FBA_CMD6 FBA_MA7 FBC_D8 FBB_D7 FBB_CMD7 FBC_MA2
P28 FBA_D7 FBA_CMD7 U28 G6 FBB_D8 FBB_CMD8 F15
FBA_D8 J28 V28 FBA_MA2 FBC_D9 F5 E15 FBC_MA0
FBA_D9 FBA_D8 FBA_CMD8 FBA_MA0 FBC_D10 FBB_D9 FBB_CMD9 FBC_MA4
H29 FBA_D9 FBA_CMD9 V29 E6 FBB_D10 FBB_CMD10 D15
FBA_D10 J29 V30 FBA_MA4 FBC_D11 F6 A14 FBC_MA1
FBA_D11 FBA_D10 FBA_CMD10 FBA_MA1 FBC_D12 FBB_D11 FBB_CMD11 FBC_BA0
H28 FBA_D11 FBA_CMD11 U34 F4 FBB_D12 FBB_CMD12 D14
FBA_D12 G29 U31 FBA_BA0 FBC_D13 G4 A15 FBC_WE#
FBA_D12 FBA_CMD12 FBB_D13 FBB_CMD13 FBC_WE# 28,29
FBA_D13 E31 V34 FBA_WE# FBC_D14 E2 B15 FBC_MA15
FBA_D13 FBA_CMD13 FBA_WE# 26,27 FBB_D14 FBB_CMD14
FBA_D14 E32 V33 FBA_MA15 FBC_D15 F3 C17 FBC_CAS#
FBA_D14 FBA_CMD14 FBB_D15 FBB_CMD15 FBC_CAS# 28,29
FBA_D15 F30 Y32 FBA_CAS# FBC_D16 C2 D18 FBC_CS0#_H
FBA_D15 FBA_CMD15 FBA_CAS# 26,27 FBB_D16 FBB_CMD16 FBC_CS0#_H 29
FBA_D16 C34 AA31 FBA_CS0#_H FBC_D17 D4 E18
FBA_D16 FBA_CMD16 FBA_CS0#_H 27 FBB_D17 FBB_CMD17
FBA_D17 D32 AA29 FBC_D18 D3 F18 FBC_ODT_H
FBA_D17 FBA_CMD17 FBB_D18 FBB_CMD18 FBC_ODT_H 29
FBA_D18 B33 AA28 FBA_ODT_H FBC_D19 C1 A20 FBC_CKE_H
FBA_D18 FBA_CMD18 FBA_ODT_H 27 FBB_D19 FBB_CMD19 FBC_CKE_H 29
FBA_D19 C33 AC34 FBA_CKE_H FBC_D20 B3 B20 FBC_MA13
FBA_D19 FBA_CMD19 FBA_CKE_H 27 FBB_D20 FBB_CMD20
FBA_D20 F33 AC33 FBA_MA13 FBC_D21 C4 C18 FBC_MA8
FBA_D21 FBA_D20 FBA_CMD20 FBA_MA8 FBC_D22 FBB_D21 FBB_CMD21 FBC_MA6
F32 FBA_D21 FBA_CMD21 AA32 B5 FBB_D22 FBB_CMD22 B18
FBA_D22 H33 AA33 FBA_MA6 FBC_D23 C5 G18 FBC_MA11
FBA_D23 FBA_D22 FBA_CMD22 FBA_MA11 FBC_D24 FBB_D23 FBB_CMD23 FBC_MA5
H32 Y28 A11 G17
FBA_D23 FBA_CMD23 FBB_D24 FBB_CMD24 Mode D - Mirror Mode Mapping
MEMORY INTERFACE

FBA_D24 P34 Y29 FBA_MA5 FBC_D25 C11 F17 FBC_MA3

MEMORY INTERFACE B
FBA_D25 FBA_D24 FBA_CMD24 FBA_MA3 FBC_D26 FBB_D25 FBB_CMD25 FBC_BA2
P32 FBA_D25 FBA_CMD25 W31 D11 FBB_D26 FBB_CMD26 D16
FBA_D26 P31 Y30 FBA_BA2 FBC_D27 B11 A18 FBC_BA1 DATA Bus
FBA_D27 FBA_D26 FBA_CMD26 FBA_BA1 FBC_D28 FBB_D27 FBB_CMD27 FBC_MA12
P33 FBA_D27 FBA_CMD27 AA34 D8 FBB_D28 FBB_CMD28 D17
FBA_D28 L31 Y31 FBA_MA12 FBC_D29 A8 A17 FBC_MA10 Address 0..31 32..63
FBA_D29 FBA_D28 FBA_CMD28 FBA_MA10 FBC_D30 FBB_D29 FBB_CMD29 FBC_RAS#
L34 FBA_D29 FBA_CMD29 Y34 C8 FBB_D30 FBB_CMD30 B17 FBC_RAS# 28,29
FBA_D30 L32 Y33 FBA_RAS# FBC_D31 B8 E17 FBx_CMD0 CS0#_L
FBA_D30 FBA_CMD30 FBA_RAS# 26,27 FBB_D31 FBB_CMD31
FBA_D31 L33 V31 FBC_D32 F24
FBA_D32 FBA_D31 FBA_CMD31 FBC_D33 FBB_D32
AG28 FBA_D32 G23 FBB_D33 FBx_CMD1
FBA_D33 AF29 FBC_D34 E24
FBA_D34 FBA_D33 FBC_D35 FBB_D34
C AG29 FBA_D34 G24 FBB_D35 FBB_CMD_RFU0 C12 FBx_CMD2 ODT_L C
FBA_D35 AF28 R32 FBC_D36 D21 C20
FBA_D36 FBA_D35 FBA_CMD_RFU0 FBC_D37 FBB_D36 FBB_CMD_RFU1
AD30 FBA_D36 FBA_CMD_RFU1 AC32 E21 FBB_D37 +1.5VS_VGA
FBx_CMD3 CKE_L
FBA_D37 AD29 FBC_D38 G21
FBA_D38 FBA_D37 +1.5VS_VGA FBC_D39 FBB_D38
AC29 FBA_D38 F21 FBB_D39 FBx_CMD4 A14 A14
FBA_D39 AD28 FBC_D40 G27 G14 RV60 1 2 60.4_0402_1% @
FBA_D39 FBB_D40 FBB_DEBUG0
A

FBA_D40 AJ29 R28 RV58 1 2 60.4_0402_1% @ FBC_D41 D27 G20 RV61 1 2 60.4_0402_1% @ FBx_CMD5 RST RST
FBA_D41 FBA_D40 FBA_DEBUG0 RV59 1 FBC_D42 FBB_D41 FBB_DEBUG1
AK29 FBA_D41 FBA_DEBUG1 AC28 2 60.4_0402_1% @ G26 FBB_D42 can be unstuff by default
FBA_D42 AJ30 can be unstuff by default FBC_D43 E27 FBx_CMD6 A9 A9
FBA_D43 FBA_D42 FBC_D44 FBB_D43
AK28 FBA_D43 E29 FBB_D44
FBA_D44 AM29 FBC_D45 F29 D12 FBC_CLK0 FBx_CMD7 A7 A7
FBA_D44 FBB_D45 FBB_CLK0 FBC_CLK0 28
FBA_D45 AM31 R30 FBA_CLK0 FBC_D46 E30 E12 FBC_CLK0#
FBA_D45 FBA_CLK0 FBA_CLK0 26 FBB_D46 FBB_CLK0_N FBC_CLK0# 28
FBA_D46 AN29 R31 FBA_CLK0# FBC_D47 D30 E20 FBC_CLK1 FBx_CMD8 A2 A2
FBA_D46 FBA_CLK0_N FBA_CLK0# 26 FBB_D47 FBB_CLK1 FBC_CLK1 29
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D48 A32 F20 FBC_CLK1#
FBA_D47 FBA_CLK1 FBA_CLK1 27 FBB_D48 FBB_CLK1_N FBC_CLK1# 29
FBA_D48 AN31 AC31 FBA_CLK1# FBC_D49 C31 FBx_CMD9 A0 A0
FBA_D48 FBA_CLK1_N FBA_CLK1# 27 FBB_D49
FBA_D49 AN32 FBC_D50 C32
FBA_D50 FBA_D49 FBC_D51 FBB_D50
AP30 FBA_D50 B32 FBB_D51 FBx_CMD10 A4 A4
FBA_D51 AP32 FBC_D52 D29 F8
FBA_D52 FBA_D51 FBC_D53 FBB_D52 FBB_WCK01
AM33 FBA_D52 FBA_WCK01 K31 A29 FBB_D53 FBB_WCK01_N E8 FBx_CMD11 A1 A1
FBA_D53 AL31 L30 FBC_D54 C29 A5
FBA_D54 FBA_D53 FBA_WCK01_N FBC_D55 FBB_D54 FBB_WCK23
AK33 FBA_D54 FBA_WCK23 H34 B29 FBB_D55 FBB_WCK23_N A6 FBx_CMD12 BA0 BA0
FBA_D55 AK32 J34 FBC_D56 B21 D24
FBA_D56 FBA_D55 FBA_WCK23_N FBC_D57 FBB_D56 FBB_WCK45
AD34 FBA_D56 FBA_WCK45 AG30 C23 FBB_D57 FBB_WCK45_N D25 FBx_CMD13 WE# WE#
FBA_D57 AD32 AG31 FBC_D58 A21 B27
FBA_D58 FBA_D57 FBA_WCK45_N FBC_D59 FBB_D58 FBB_WCK67
AC30 FBA_D58 FBA_WCK67 AJ34 C21 FBB_D59 FBB_WCK67_N C27 FBx_CMD14 A15 A15
FBA_D59 AD33 AK34 FBC_D60 B24
FBA_D60 FBA_D59 FBA_WCK67_N FBC_D61 FBB_D60
AF31 FBA_D60 +1.05VS_VGA +FB_PLLAVDD
C24 FBB_D61 FBx_CMD15 CAS# CAS#
FBA_D61 AG34 FBC_D62 B26
FBA_D62 FBA_D61 FBC_D63 FBB_D62
AG32 FBA_D62
Place close to BGA C26 FBB_D63 FBB_WCKB01 D6 FBx_CMD16 CS0#_H
FBA_D63 AG33 J30 200mA D7
FBA_D63 FBA_WCKB01 BLM18PG330SN1D_0603 FBC_DQM0 FBB_WCKB01_N
FBA_WCKB01_N J31 E11 FBB_DQM0 FBB_WCKB23 C6 FBx_CMD17
FBA_DQM0 P30 J32 1 2 +FB_PLLAVDD FBC_DQM1 E3 B6
FBA_DQM1 FBA_DQM0 FBA_WCKB23 LV3 FBC_DQM2 FBB_DQM1 FBB_WCKB23_N
F31 FBA_DQM1 FBA_WCKB23_N J33 A3 FBB_DQM2 FBB_WCKB45 F26 FBx_CMD18 ODT_H
FBA_DQM2 F34 AH31 PX@ FBC_DQM3 C9 E26
FBA_DQM3 FBA_DQM2 FBA_WCKB45 FBC_DQM4 FBB_DQM3 FBB_WCKB45_N
M32 FBA_DQM3 FBA_WCKB45_N AJ31 F23 FBB_DQM4 FBB_WCKB67 A26 FBx_CMD19 CKE_H
FBA_DQM4 AD31 AJ32 FBC_DQM5 F27 A27
FBA_DQM5 FBA_DQM4 FBA_WCKB67 FBC_DQM6 FBB_DQM5 FBB_WCKB67_N
AL29 FBA_DQM5 FBA_WCKB67_N AJ33 C30 FBB_DQM6 FBx_CMD20 A13 A13
FBA_DQM6 AM32 FBC_DQM7 A24
B
FBA_DQM7 FBA_DQM6 FBB_DQM7 B
AF34 FBA_DQM7 FBx_CMD21 A8 A8
RV66 PX@ 10K_0402_5% FBC_DQS0 D10
FBA_DQS0 FB_CLAMP FBC_DQS1 FBB_DQS_WP0
M31 FBA_DQS_WP0 FB_CLAMP E1 2 1 D5 FBB_DQS_WP1 FBx_CMD22 A6 A6
FBA_DQS1 G31 +FB_PLLAVDD FBC_DQS2 C3
FBA_DQS2 FBA_DQS_WP1 FBC_DQS3 FBB_DQS_WP2
E33 FBA_DQS_WP2 B9 FBB_DQS_WP3 FBx_CMD23 A11 A11
FBA_DQS3 M33 CV106 0.1U_0402_10V7K PX@ FBC_DQS4 E23 H17 +FB_PLLAVDD
FBA_DQS4 FBA_DQS_WP3 FBC_DQS5 FBB_DQS_WP4 FBB_PLL_AVDD
FBx_CMD24 A5 A5

0.1U_0402_10V7K
AE31 FBA_DQS_WP4 FB_DLL_AVDD K27 1 2 E28 FBB_DQS_WP5

CV108
FBA_DQS5 AK30 FBC_DQS6 B30 1
FBA_DQS6 FBA_DQS_WP5 FBC_DQS7 FBB_DQS_WP6
AN33 FBA_DQS_WP6
Place close to ball A23 FBB_DQS_WP7 FBx_CMD25 A3 A3
FBA_DQS7 AF33 FBA_DQS_WP7 FBC_DQS#0
FBA_PLL_AVDD U27 +FB_PLLAVDD D9 FBB_DQS_RN0 2 PX@
FBx_CMD26 BA2 BA2
FBA_DQS#0 FBC_DQS#1
22U_0805_6.3V6M
0.1U_0402_10V7K

M30 FBA_DQS_RN0 E4 FBB_DQS_RN1


CV107

CV110

FBA_DQS#1 FBC_DQS#2 BA1


1U_0402_6.3V6K

H30 FBA_DQS_RN1 1 1 1 B2 FBB_DQS_RN2 FBx_CMD27 BA1


CV39

FBA_DQS#2 E34 FBC_DQS#3 A9


FBA_DQS#3 FBA_DQS_RN2 FBC_DQS#4 FBB_DQS_RN3
M34 FBA_DQS_RN3 FB_VREF H26 D22 FBB_DQS_RN4 FBx_CMD28 A12 A12
FBA_DQS#4 AF30 FBC_DQS#5 D28 Place close to ball
FBA_DQS#5 AK31 FBA_DQS_RN4 2 PX@ 2 PX@ 2 PX@ FBC_DQS#6 FBB_DQS_RN5
FBA_DQS_RN5 A30 FBB_DQS_RN6 FBx_CMD29 A10 A10
FBA_DQS#6 AM34 FBC_DQS#7 B23
FBA_DQS#7 AF32 FBA_DQS_RN6 FBB_DQS_RN7
FBA_DQS_RN7 FBx_CMD30 RAS# RAS#
Place close to ball Place close to BGA
N13P-GLP-A1_FCBGA908
N13P-GLP-A1_FCBGA908 PX@
PX@

28,29 FBC_DQM[7..0]
26,27 FBA_DQM[7..0] 28,29 FBC_DQS[7..0]
26,27 FBA_DQS[7..0] 28,29 FBC_DQS#[7..0]
26,27 FBA_DQS#[7..0] 30ohms (ESR=0.01) Bead
P/N;SM010007W00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 25 of 48
5 4 3 2 1
5 4 3 2 1

FBA_D[0..63] 25,27
D
Memory Partition A - Lower 32 bits FBA_MA[15..0] 25,27
D

FBA_BA[2..0] 25,27
UV3 UV4
FBA_DQM[7..0] 25,27
+1.5VS_VGA +FBA_VREF0 M8 E3 FBA_D4 +FBA_VREF0 M8 E3 FBA_D19
VREFCA DQL0 VREFCA DQL0 FBA_DQS[7..0] 25,27
H1 F7 FBA_D1 H1 F7 FBA_D20
VREFDQ DQL1 FBA_D7 VREFDQ DQL1 FBA_D17
DQL2 F2 DQL2 F2 FBA_DQS#[7..0] 25,27

1
FBA_MA0 N3 F8 FBA_D0 FBA_MA0 N3 F8 FBA_D21 Group2 (IN1)
RV79 FBA_MA1 A0 DQL3 FBA_D6 FBA_MA1 A0 DQL3 FBA_D16
P7 A1 DQL4 H3 Group0 (IN3) P7 A1 DQL4 H3
FBA_MA2 P3 H8 FBA_D3 FBA_MA2 P3 H8 FBA_D23
1.1K_0402_1% FBA_MA3 A2 DQL5 FBA_D5 FBA_MA3 A2 DQL5 FBA_D18
N2 A3 DQL6 G2 N2 A3 DQL6 G2
PX@ 2 FBA_MA4 P8 H7 FBA_D2 FBA_MA4 P8 H7 FBA_D22
+FBA_VREF0 FBA_MA5 A4 DQL7 FBA_MA5 A4 DQL7
P2 A5 P2 A5
FBA_MA6 R8 FBA_MA6 R8
A6 A6
1

CV118
0.01U_0402_25V7K 1 FBA_MA7 R2 D7 FBA_D29 FBA_MA7 R2 D7 FBA_D10
RV68 FBA_MA8 A7 DQU0 FBA_D25 FBA_MA8 A7 DQU0 FBA_D15
T8 A8 DQU1 C3 T8 A8 DQU1 C3
FBA_MA9 R3 C8 FBA_D28 FBA_MA9 R3 C8 FBA_D8
1.1K_0402_1% PX@ FBA_MA10 A9 DQU2 FBA_D26 FBA_MA10 A9 DQU2 FBA_D13
2
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 Group1 (TOP)
PX@ FBA_MA11 R7 A7 FBA_D31 Group3 (BOT) FBA_MA11 R7 A7 FBA_D9
2

FBA_MA12 A11 DQU4 FBA_D24 FBA_MA12 A11 DQU4 FBA_D12


N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBA_MA13 T3 B8 FBA_D30 FBA_MA13 T3 B8 FBA_D11
FBA_MA14 A13 DQU6 FBA_D27 FBA_MA14 A13 DQU6 FBA_D14
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBA_MA15 M7 FBA_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA

FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBA_CLK0 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8
2

VDD N1 VDD N1
RV80 FBA_CLK0 J7 N9 FBA_CLK0 J7 N9
25 FBA_CLK0 CK VDD CK VDD
160_0402_1% FBA_CLK0# K7 R1 FBA_CLK0# K7 R1
25 FBA_CLK0# CK VDD CK VDD
FBA_CKE_L K9 R9 FBA_CKE_L K9 R9
25 FBA_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
C PX@ C
1

FBA_CLK0# FBA_ODT_L K1 A1 FBA_ODT_L K1 A1


25 FBA_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_L L2 A8 FBA_CS0#_L L2 A8
25 FBA_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1
25,27 FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9 FBA_ODT_L
25,27 FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2
25,27 FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 FBA_CKE_L
FBA_DQS0 VDDQ FBA_DQS2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
FBA_DQS3 C7 H9 FBA_DQS1 C7 H9
DQSU VDDQ DQSU VDDQ

2
RV67 RV76
FBA_DQM0 E7 A9 FBA_DQM2 E7 A9 10K_0402_5% 10K_0402_5%
FBA_DQM3 DML VSS FBA_DQM1 DML VSS PX@ PX@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1

1
VSS VSS
VSS G8 VSS G8
FBA_DQS#0 G3 J2 FBA_DQS#2 G3 J2
FBA_DQS#3 B7 DQSL VSS FBA_DQS#1 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8
VSS M1 VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9
25,27 FBA_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV78 RV77 L1 B9 RV69 L1 B9


10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
PX@ PX@ L9 D8 L9 D8
NCZQ1 VSSQ PX@ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
B B
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@

+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE


0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV119

CV120

CV121

CV123

CV162

CV161

CV159

CV134

CV129

CV160

CV133

CV132

CV164

CV136

CV163

CV137

CV135

CV157

CV155

CV138

CV142

CV143

CV144

CV158
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PX@ PX@ PX@ PX@ PX@ @ PX@ PX@ PX@ PX@ PX@ PX@ PX@ @ PX@ PX@ PX@ @ @ @ PX@ @ @ PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 26 of 48
5 4 3 2 1
5 4 3 2 1

D D

Memory Partition A - Upper 32 FBA_D[0..63] 25,26

bits UV5 UV6


FBA_MA[15..0] 25,26
+1.5VS_VGA
FBA_BA[2..0] 25,26
+FBA_VREF1 M8 E3 FBA_D36 +FBA_VREF1 M8 E3 FBA_D63
VREFCA DQL0 FBA_D34 VREFCA DQL0 FBA_D58
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBA_DQM[7..0] 25,26

1
F2 FBA_D37 F2 FBA_D60
RV70 FBA_MA0 DQL2 FBA_D35 FBA_MA0 DQL2 FBA_D59
N3 A0 DQL3 F8 N3 A0 DQL3 F8 FBA_DQS[7..0] 25,26
FBA_MA1 P7 H3 FBA_D39 Group4 (IN1) FBA_MA1 P7 H3 FBA_D61 Group7 (IN3)
1.1K_0402_1% FBA_MA2 A1 DQL4 FBA_D32 FBA_MA2 A1 DQL4 FBA_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8 FBA_DQS#[7..0] 25,26
PX@ FBA_MA3 N2 G2 FBA_D38 FBA_MA3 N2 G2 FBA_D62
2

+FBA_VREF1 FBA_MA4 A3 DQL6 FBA_D33 FBA_MA4 A3 DQL6 FBA_D57


P8 A4 DQL7 H7 P8 A4 DQL7 H7
FBA_MA5 P2 FBA_MA5 P2
A5 A5
1

CV178
FBA_MA6 FBA_MA6
0.01U_0402_25V7K

1 R8 A6 R8 A6
RV82 FBA_MA7 R2 D7 FBA_D45 FBA_MA7 R2 D7 FBA_D55
FBA_MA8 A7 DQU0 FBA_D42 FBA_MA8 A7 DQU0 FBA_D51
T8 A8 DQU1 C3 T8 A8 DQU1 C3
1.1K_0402_1% PX@ FBA_MA9 R3 C8 FBA_D46 FBA_MA9 R3 C8 FBA_D54
PX@ 2 FBA_MA10 A9 DQU2 FBA_D41 FBA_MA10 A9 DQU2 FBA_D49
L7 C2 Group5 (TOP) L7 C2
2

FBA_MA11 A10/AP DQU3 FBA_D47 FBA_MA11 A10/AP DQU3 FBA_D52


R7 A11 DQU4 A7 R7 A11 DQU4 A7 Group6 (BOT)
FBA_MA12 N7 A2 FBA_D43 FBA_MA12 N7 A2 FBA_D50
FBA_MA13 A12 DQU5 FBA_D44 FBA_MA13 A12 DQU5 FBA_D53
T3 A13 DQU6 B8 T3 A13 DQU6 B8
FBA_MA14 T7 A3 FBA_D40 FBA_MA14 T7 A3 FBA_D48
FBA_MA15 A14 DQU7 FBA_MA15 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+1.5VS_VGA +1.5VS_VGA

FBA_BA0 M2 B2 FBA_BA0 M2 B2
FBA_BA1 BA0 VDD FBA_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBA_CLK1 FBA_BA2 M3 G7 FBA_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2
C
VDD K8 VDD K8 C
2

VDD N1 VDD N1
RV83 FBA_CLK1 J7 N9 FBA_CLK1 J7 N9
25 FBA_CLK1 CK VDD CK VDD
160_0402_1% FBA_CLK1# K7 R1 FBA_CLK1# K7 R1
25 FBA_CLK1# CK VDD CK VDD
FBA_CKE_H K9 R9 FBA_CKE_H K9 R9
25 FBA_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
PX@
1

FBA_CLK1# FBA_ODT_H K1 A1 FBA_ODT_H K1 A1


25 FBA_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBA_CS0#_H L2 A8 FBA_CS0#_H L2 A8
25 FBA_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
FBA_RAS# J3 C1 FBA_RAS# J3 C1
25,26 FBA_RAS# RAS VDDQ RAS VDDQ
FBA_CAS# K3 C9 FBA_CAS# K3 C9
25,26 FBA_CAS# CAS VDDQ CAS VDDQ
FBA_WE# L3 D2 FBA_WE# L3 D2
25,26 FBA_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1
FBA_DQS4 F3 H2 FBA_DQS7 F3 H2
FBA_DQS5 DQSL VDDQ FBA_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

FBA_DQM4 E7 A9 FBA_DQM7 E7 A9
FBA_DQM5 DML VSS FBA_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1
VSS G8 VSS G8
FBA_DQS#4 G3 J2 FBA_DQS#7 G3 J2
FBA_DQS#5 B7 DQSL VSS FBA_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8
VSS M1 VSS M1
FBA_CKE_H M9 M9
VSS VSS
VSS P1 VSS P1
FBA_RST# T2 P9 FBA_RST# T2 P9
25,26 FBA_RST# RESET VSS RESET VSS
FBA_ODT_H T1 T1
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
RV84 RV87 J1 B1 J1 B1
10K_0402_5% 10K_0402_5% RV86 NC/ODT1 VSSQ RV85 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
PX@ PX@ L9 D8 L9 D8
PX@ NCZQ1 VSSQ PX@ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
B VSSQ E8 VSSQ E8 B
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@

+1.5VS_VGA UV5 SIDE +1.5VS_VGA UV6 SIDE


0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV145

CV174

CV296

CV301

CV291

CV302

CV299

CV290

CV300

CV297

CV298

CV165

CV177

CV170

CV166

CV172

CV179

CV173

CV169

CV180

CV167

CV171

CV168

CV175
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ @ PX@ PX@ @ @ @ @ PX@ PX@ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 27 of 48
5 4 3 2 1
5 4 3 2 1

D D
FBC_D[0..63] 25,29
Memory Partition C - Lower 32 bits FBC_MA[15..0] 25,29

FBC_BA[2..0] 25,29

FBC_DQM[7..0] 25,29
+1.5VS_VGA UV7 UV8
FBC_DQS[7..0] 25,29
+FBB_VREF0 M8 E3 FBC_D4 +FBB_VREF0 M8 E3 FBC_D16
VREFCA DQL0 VREFCA DQL0 FBC_DQS#[7..0] 25,29

1
H1 F7 FBC_D3 H1 F7 FBC_D21
RV111 VREFDQ DQL1 FBC_D7 VREFDQ DQL1 FBC_D18
DQL2 F2 DQL2 F2
FBC_MA0 N3 F8 FBC_D0 Group0 (IN3)FBC_MA0 N3 F8 FBC_D17
1.1K_0402_1% FBC_MA1 A0 DQL3 FBC_D5 FBC_MA1 A0 DQL3 FBC_D20
P7 A1 DQL4 H3 P7 A1 DQL4 H3 Group2 (IN1)
PX@ FBC_MA2 P3 H8 FBC_D1 FBC_MA2 P3 H8 FBC_D23
2 +FBB_VREF0 FBC_MA3 A2 DQL5 FBC_D6 FBC_MA3 A2 DQL5 FBC_D19
N2 A3 DQL6 G2 N2 A3 DQL6 G2
FBC_MA4 P8 H7 FBC_D2 FBC_MA4 P8 H7 FBC_D22
A4 DQL7 A4 DQL7
1

CV202
FBC_MA5 FBC_MA5
0.01U_0402_25V7K
1 P2 A5 P2 A5
RV115 FBC_MA6 R8 FBC_MA6 R8
FBC_MA7 A6 FBC_D28 FBC_MA7 A6 FBC_D8
R2 A7 DQU0 D7 R2 A7 DQU0 D7
1.1K_0402_1% FBC_MA8 T8 C3 FBC_D27 FBC_MA8 T8 C3 FBC_D15
PX@ 2 PX@ FBC_MA9 A8 DQU1 FBC_D31 FBC_MA9 A8 DQU1 FBC_D11
R3 C8 R3 C8
2

FBC_MA10 A9 DQU2 FBC_D25 FBC_MA10 A9 DQU2 FBC_D12


L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBC_MA11 R7 A7 FBC_D29 Group3 (BOT)FBC_MA11 R7 A7 FBC_D9 Group1 (TOP)
FBC_MA12 A11 DQU4 FBC_D24 FBC_MA12 A11 DQU4 FBC_D13
N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D30 FBC_MA13 T3 B8 FBC_D10
FBC_MA14 A13 DQU6 FBC_D26 FBC_MA14 A13 DQU6 FBC_D14
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA

FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBC_CLK0 FBC_BA2 M3 G7 FBC_BA2 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8
2

RV89 FBC_CLK0
310mA VDD N1
FBC_CLK0 VDD N1
C
25 FBC_CLK0 J7 CK VDD N9 J7 CK VDD N9 C
160_0402_1% FBC_CLK0# K7 R1 FBC_CLK0# K7 R1
25 FBC_CLK0# CK VDD CK VDD
PX@ FBC_CKE_L K9 R9 FBC_CKE_L K9 R9
25 FBC_CKE_L CKE/CKE0 VDD CKE/CKE0 VDD
1

FBC_CLK0# FBC_ODT_L K1 A1 FBC_ODT_L K1 A1


25 FBC_ODT_L ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CS0#_L L2 A8 FBC_CS0#_L L2 A8
25 FBC_CS0#_L CS/CS0 VDDQ CS/CS0 VDDQ
FBC_RAS# J3 C1 FBC_RAS# J3 C1
25,29 FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
25,29 FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2
25,29 FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1
FBC_DQS0 F3 H2 FBC_DQS2 F3 H2 FBC_ODT_L
FBC_DQS3 DQSL VDDQ FBC_DQS1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

FBC_CKE_L
FBC_DQM0 E7 A9 FBC_DQM2 E7 A9
FBC_DQM3 DML VSS FBC_DQM1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1

1
G8 G8 RV117 RV116
FBC_DQS#0 G3 VSS FBC_DQS#2 G3 VSS 10K_0402_5% 10K_0402_5%
DQSL VSS J2 DQSL VSS J2
FBC_DQS#3 B7 J8 FBC_DQS#1 B7 J8 PX@ PX@
DQSU VSS DQSU VSS
VSS M1 VSS M1
M9 M9

2
VSS VSS
VSS P1 VSS P1
FBC_RST# T2 P9 FBC_RST# T2 P9
25,29 FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV91 RV90 L1 B9 RV88 L1 B9


10K_0402_5% NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
PX@ PX@ L9 D8 PX@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
B VSSQ G1 VSSQ G1 B
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@

+1.5VS_VGA UV7 SIDE +1.5VS_VGA UV8 SIDE


0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV191

CV183

CV199

CV189

CV205

CV188

CV190

CV206

CV181

CV182

CV185

CV194

CV192

CV203

CV195

CV184

CV197

CV186

CV187

CV198

CV200

CV201

CV204

CV193
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PX@
@ @ PX@ PX@ PX@ @ @ @ PX@ @ @ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 28 of 48
5 4 3 2 1
5 4 3 2 1

Memory Partition C - Upper 32 bits FBC_D[0..63] 25,28

FBC_MA[15..0] 25,28
D D
FBC_BA[2..0] 25,28
UV9 UV10

+1.5VS_VGA FBC_DQM[7..0] 25,28


+FBB_VREF1 M8 E3 FBC_D39 +FBB_VREF1 M8 E3 FBC_D60
VREFCA DQL0 FBC_D33 VREFCA DQL0 FBC_D57
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 FBC_DQS[7..0] 25,28
F2 FBC_D38 F2 FBC_D63
DQL2 DQL2

1
FBC_MA0 N3 F8 FBC_D32 FBC_MA0 N3 F8 FBC_D58
A0 DQL3 A0 DQL3 FBC_DQS#[7..0] 25,28
RV120 FBC_MA1 P7 H3 FBC_D36 Group4 (IN1) FBC_MA1 P7 H3 FBC_D61 Group7 (IN3)
FBC_MA2 A1 DQL4 FBC_D35 FBC_MA2 A1 DQL4 FBC_D56
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% FBC_MA3 N2 G2 FBC_D37 FBC_MA3 N2 G2 FBC_D62
PX@ FBC_MA4 A3 DQL6 FBC_D34 FBC_MA4 A3 DQL6 FBC_D59
P8 H7 P8 H7

2
+FBB_VREF1 FBC_MA5 A4 DQL7 FBC_MA5 A4 DQL7
P2 A5 P2 A5
FBC_MA6 R8 FBC_MA6 R8
1 A6 A6

CV229
FBC_MA7 FBC_D47 FBC_MA7 FBC_D54

0.01U_0402_25V7K
1 R2 A7 DQU0 D7 R2 A7 DQU0 D7
RV127 FBC_MA8 T8 C3 FBC_D43 FBC_MA8 T8 C3 FBC_D51
FBC_MA9 A8 DQU1 FBC_D46 FBC_MA9 A8 DQU1 FBC_D55
R3 A9 DQU2 C8 R3 A9 DQU2 C8
1.1K_0402_1% PX@ FBC_MA10 L7 C2 FBC_D42 FBC_MA10 L7 C2 FBC_D49
PX@ 2 FBC_MA11 A10/AP DQU3 FBC_D40 FBC_MA11 A10/AP DQU3 FBC_D52
R7 A7 Group5 (TOP) R7 A7 Group6 (BOT)
2

FBC_MA12 A11 DQU4 FBC_D45 FBC_MA12 A11 DQU4 FBC_D50


N7 A12 DQU5 A2 N7 A12 DQU5 A2
FBC_MA13 T3 B8 FBC_D44 FBC_MA13 T3 B8 FBC_D53
FBC_MA14 A13 DQU6 FBC_D41 FBC_MA14 A13 DQU6 FBC_D48
T7 A14 DQU7 A3 T7 A14 DQU7 A3
FBC_MA15 M7 FBC_MA15 M7
A15/BA3 +1.5VS_VGA A15/BA3 +1.5VS_VGA

FBC_BA0 M2 B2 FBC_BA0 M2 B2
FBC_BA1 BA0 VDD FBC_BA1 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBC_BA2 M3 G7 FBC_BA2 M3 G7
FBC_CLK1 BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
2

FBC_CLK1 J7 N9 FBC_CLK1 J7 N9
25 FBC_CLK1 CK VDD CK VDD
RV129 FBC_CLK1# K7 R1 FBC_CLK1# K7 R1
25 FBC_CLK1# CK VDD CK VDD
160_0402_1% FBC_CKE_H K9 R9 FBC_CKE_H K9 R9
25 FBC_CKE_H CKE/CKE0 VDD CKE/CKE0 VDD
PX@
1

FBC_ODT_H K1 A1 FBC_ODT_H K1 A1
25 FBC_ODT_H ODT/ODT0 VDDQ ODT/ODT0 VDDQ
FBC_CLK1# FBC_CS0#_H L2 A8 FBC_CS0#_H L2 A8
25 FBC_CS0#_H CS/CS0 VDDQ CS/CS0 VDDQ
C FBC_RAS# J3 C1 FBC_RAS# J3 C1 C
25,28 FBC_RAS# RAS VDDQ RAS VDDQ
FBC_CAS# K3 C9 FBC_CAS# K3 C9
25,28 FBC_CAS# CAS VDDQ CAS VDDQ
FBC_WE# L3 D2 FBC_WE# L3 D2
25,28 FBC_WE# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1
FBC_DQS4 F3 H2 FBC_DQS7 F3 H2
FBC_DQS5 DQSL VDDQ FBC_DQS6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

FBC_DQM4 E7 A9 FBC_DQM7 E7 A9
FBC_DQM5 DML VSS FBC_DQM6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1
VSS G8 VSS G8
FBC_DQS#4 G3 J2 FBC_DQS#7 G3 J2
FBC_DQS#5 B7 DQSL VSS FBC_DQS#6 B7 DQSL VSS
DQSU VSS J8 DQSU VSS J8
FBC_ODT_H M1 M1
VSS VSS
VSS M9 VSS M9
VSS P1 VSS P1
FBC_CKE_H FBC_RST# T2 P9 FBC_RST# T2 P9
25,28 FBC_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

RV118 RV119
10K_0402_5% 10K_0402_5%
1

1
PX@ PX@ J1 B1 J1 B1
RV123 NC/ODT1 VSSQ RV128 NC/ODT1 VSSQ
L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9
243_0402_1% J9 D1 243_0402_1% J9 D1
2

PX@ NC/CE1 VSSQ PX@ NC/CE1 VSSQ


L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
B B

+1.5VS_VGA UV9 SIDE +1.5VS_VGA UV10 SIDE


0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
CV209

CV227

CV213

CV233

CV226

CV207

CV230

CV220

CV221

CV228

CV225

CV210

CV208

CV223

CV211

CV222

CV212

CV231

CV224

CV214

CV215

CV217

CV218

CV232
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PX@ @ PX@ PX@ PX@ PX@ @ PX@ PX@ @ PX@ PX@ @ PX@ @ @ PX@ @ PX@ PX@ PX@ PX@ PX@ PX@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/06/30 Deciphered Date 2013/06/30 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 29 of 48
5 4 3 2 1
A B C D E

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM

2
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
RV92 PX@ RV93 @ RV94 PX@ RV121 @ RV122 @
45.3K_0402_1% 45.3K_0402_1% 4.99K_0402_1% 20K_0402_1% 20K_0402_1% ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
1 1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]

1
22 STRAP0 STRAP0 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
22 STRAP1 STRAP1
22 STRAP2 STRAP2 STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
22 STRAP3 STRAP3
22 STRAP4 STRAP4 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
PCIE_SPEED_
STRAP4 +3VS_VGA RESERVED CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V
2

2
RV95 @ RV96 PX@ RV97 @ RV124 @ RV125 @
45.3K_0402_1% 45.3K_0402_1% 10K_0402_1% 4.99K_0402_1% 10K_0402_1%

Resistor Values Pull-up to +3VS_VGA Pull-down to Gnd


1

1
5K 1000 0000
10K 1001 0001
15K 1010 0010
+3VS_VGA 20K 1011 0011
2 2
25K 1100 0100
30K 1101 0101
35K 1110 0110
2

RV98 @ RV99 @ RV100 @ 45K 1111 0111


4.99K_0402_1% 30K_0402_1% 4.99K_0402_1%
1

22 ROM_SI ROM_SI
22 ROM_SO ROM_SO
ROM_SCLK
22 ROM_SCLK SUB_VENDOR 3GIO_PADCFG VGA_DEVICE
2

0 No VBIOS ROM 0110 0 3D Device (Class Code 302h)


RV101 X76@ RV102 PX@ RV103 PX@ 3GIO_PADCFG[3:0]
X76 45.3K_0402_1% 30K_0402_1% 15K_0402_1%
1 BIOS ROM is present (Default) Notebook Default 1 VGA Device (Default)
1

3
FB_0_BAR_SIZE PEX_PLL_EN_TERM XCLK_417 3

0 Reserved 0 Disable (Default) 0 277MHz (Default)


For N13P-GLP strap table
1 Reserved 1 Enable 1 Reserved
GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK

128M* 16* 8 Samsung (2Gb) RV92 RV96 RV94 RV101 RV102 RV103 2 256MB (Default)
900 MHz 2GB K4W2G1646C-HC11 PU 45K PD 45K PU 5K N/A N/A PD 45K PD 30K PD 15K PCIE_MAX_SPEED SLOT_CLK_CFG
N13P-GLP
128M* 16* 8 Hynix (2Gb) RV92 RV96 RV94 RV101 RV102 RV103 3 Reserved 0 Limit to PCIE Gen1 0 GPU and MCH don't share a
900 MHz 2GB H5TQ1G63DFR-11C PU 45K PD 45K PU 5K N/A N/A PD 35K PD 30K PD 15K
common reference clock
USER Straps 1 PCIE Gen 2/3 Capable
GPU and MCH share a
X76 1 common reference clock
1000-1100 SMBUS_ALT_ADDR
User[3:0] (Default)
Customer defined 0 0x9E (Default)
RV101 X76@ ZZZ ZZZ

1 0x9C (Multi-GPU usage)


4 4

34.8K_0402_1% Samsung Hynix


SD034348280 S2G@
X7636539L02
H2G@
X7636539L01
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 30 of 48
A B C D E
5 4 3 2 1

PN:SP02000FQ00
R497
D 0_0402_5% D
+5VS 1 2 JLCD1
@ 1 2 EDID_CLK
+LCDVDD_CONN 1 2 EDID_CLK 15
R498 3 4 EDID_DATA
3 4 EDID_DATA 15
INVPWM 0_0402_5% 5 6
5 6 LVDS_A0#
+3VS 1 2 7 7 8 8 LVDS_A0# 15
@ 9 10 LVDS_A0
470P_0402_50V7K

470P_0402_50V7K

+3VS 9 10 LVDS_A0 15
TP_POWER 11 12 LVDS_A1#
11 12 LVDS_A1# 15
DISPOFF# 16 USB20_P8 USB20_P8 13 14 LVDS_A1
13 14 LVDS_A1 15
16 USB20_N8 USB20_N8 15 16 LVDS_A2#
15 16 LVDS_A2# 15
C635 17 18 LVDS_A2
17 18 LVDS_A2 15
@ @ For Logo +3VALW 1K_0402_5% 2 1 R614 19 20
19 20
1

C636 43,46 LOGO_LED# LOGO_LED# 21 22 LVDS_ACLK#


21 22 LVDS_ACLK# 15
23 24 LVDS_ACLK
23 24 LVDS_ACLK 15
TL_LED# 25 26
2

25 26 LVDS_B0#
For Think light +5VS 2 R474 1 27 27 28 28 LVDS_B0# 15
+3VS_CMOS 75_0603_1% 29 30 LVDS_B0
29 30 LVDS_B0 15
For EMI 16 USB20_N5 USB20_N5 31 32 LVDS_B1#
31 32 LVDS_B1# 15
CMOS 16 USB20_P5 USB20_P5 33 34 LVDS_B1
33 34 LVDS_B1 15
35 36 LVDS_B2#
35 36 LVDS_B2# 15
W=60mils INVPWM 37 38 LVDS_B2
37 38 LVDS_B2 15
DISPOFF# 39 40
39 40 LVDS_BCLK#
+3VS 41 41 42 42 LVDS_BCLK# 15
B+ LVDS_BCLK
DMIC 43 43 44 44 LVDS_BCLK 15
45 45 46 46
(60 MIL) 47 48 DMIC_DATA DMIC_DATA 38
47 48 DMIC_CLK
49 49 50 50 DMIC_CLK 38 DMIC

1
USB20_N8 @

1
51 C647

2
USB20_P8 GND
52 GND @ 0.1U_0402_16V4Z

2
3

ACES_88107-50001-CP
D36
PJDLC05_SOT23-3 C846 C845
4.7U_0805_25V6-K 680P_0402_50V7K

0202 ESD Reserve


1

C C

SCA00000U10 LCD POWER CIRCUIT


+LCDVDD +3VS
+5VALW

R475
1

150_0603_1% R476 C637


100K_0402_5% 4.7U_0805_10V4Z
2
1

S
D R478 220K_0402_5% G
2 1 2 2 Q32
Q28 G SI2301BDS-T1-E3_SOT23-3
2N7002K_SOT23-3 S
1

DTC124EK C639
3

D
W=60mils
OUT

0.1U_0402_16V4Z
2

+LCDVDD +LCDVDD_CONN
L15
15 PCH_ENVDD 2 IN
1 2
GND

Q33 FBMA-L11-201209-221LMA30T_0805 (15 MIL)


1

DTC124EKAT146_SC59-3 TL_LED#
3

C640 C641
R482 @
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2

+3VS
2

1
@ D
680P_0402_50V7K

1
2 TL_LED 43
C847 Q29 G
2N7002K_SOT23-3 S

2
B B

1
+3VS

R490 R485 @
0_0402_5% 100K_0402_5%
1

1 2

2
R484
10K_0402_5%
D9 @
2

2 1 INVPWM
15 PCH_PWM
CH751H-40PT_SOD323-2
For GMCH DPST
1

@
R496 R495 CMOS Camera Conn (20 MIL)
10K_0402_5% 10K_0402_5%
@ CMOS SUSPEND 2.4mA
2

+3VS_CMOS
(20 MIL)

D
+3VS 3 1
1 @

1
Q35 C642 C643

G
2
SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z 10U_0603_6.3V6M

2
2
+3VS 4.7V
43 CMOS_ON#

1
R488 R491
1

0_0402_5% 150K_0402_5% C644


1 2 R489 0.1U_0402_16V4Z
2

@
4.7K_0402_5%
D6
2

BKOFF# 2 1 DISPOFF#
43 BKOFF#
CH751H-40PT_SOD323-2
1

@
R492 R493
10K_0402_5% 10K_0402_5%
@
A A
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 31 of 48
5 4 3 2 1
5 4 3 2 1

WCM-2012-670T_4P
HDMI_CLK+_CK 4 3 HDMI_CLK+_CONN 680 +-5% 8P4R
15 HDMI_CLK+_CK 4 3 HDMI_TX0+_CONN 5 4
HDMI_TX0-_CONN 6 3
15 HDMI_CLK-_CK HDMI_CLK-_CK 1 2 HDMI_CLK-_CONN HDMI_CLK+_CONN 7 2
1 2 HDMI_CLK-_CONN 8 1
L38
RP5
D
WCM-2012-670T_4P 680 +-5% 8P4R D
15 HDMI_TX0+_CK HDMI_TX0+_CK 4 3 HDMI_TX0+_CONN HDMI_TX2+_CONN 5 4
4 3 HDMI_TX2-_CONN 6 3
HDMI_TX1+_CONN 7 2
15 HDMI_TX0-_CK HDMI_TX0-_CK 1 2 HDMI_TX0-_CONN HDMI_TX1-_CONN 8 1
1 2
L36 RP6

WCM-2012-670T_4P +3VS

1
HDMI_TX1+_CK HDMI_TX1+_CONN D
15 HDMI_TX1+_CK 4 4 3 3
Q40 2
SSM3K7002FU_SC70-3 G
15 HDMI_TX1-_CK HDMI_TX1-_CK 1 2 HDMI_TX1-_CONN S

3
1 2
L37

WCM-2012-670T_4P
15 HDMI_TX2+_CK HDMI_TX2+_CK 4 3 HDMI_TX2+_CONN
4 3

15 HDMI_TX2-_CK HDMI_TX2-_CK 1 2 HDMI_TX2-_CONN


1 2
L35

L35, L36, L37, L38


S COM FI_ KINGCORE WCM-2012HS-900T
C +5VS C
+3VS P/N : SM070001S00 +HDMI_VCC
F2
D15
1.1A_6V_SMD1812P110TF
2 1 1 2
Pull up R for PCH SIDE
RB491D_SC59-3
2

15 HDMICLK_NB 1 6 HDMICLK_R
+5VS_HDMI
5

2N7002DW-T/R7_SOT363-6 +3VS
Q21A C708

1
15 HDMIDAT_NB 4 3 HDMIDAT_R 0.1U_0402_16V4Z

2
2
Q21B 2N7002DW-T/R7_SOT363-6

2
R524 R525 R523
1M_0402_5% 2.2K_0402_5% 2.2K_0402_5%
TYPE C Connector
mHDMI PN:SP060005H00

1
2
G
1
TMDS_B_HPD 3 1
D35 15 TMDS_B_HPD ACON_HMR4E-CK3201

D
HDMICLK_R 1 1 109 HDMICLK_R
HDMI_DET 19 23
HDMIDAT_R 2 2 98 HDMIDAT_R Q37 HP_DET GND
18 +V5 GND 22
SSM3K7002FU_SC70-3 17 21
+5VS_HDMI 4 4 77 +5VS_HDMI HDMIDAT_R RESERVED GND
16 SDA GND 20
HDMICLK_R 15 SCL

2
B HDMI_DET B
5 5 66 HDMI_DET 14 CEC
20K_0402_5% 13 DDC/CEC_GND
3 3 HDMI_CLK-_CONN 12 CK-
R527 HDMI_CLK+_CONN 11
8 CK+
10

1
HDMI_TX0-_CONN CK_SHIELD
9 D0-
YSCLAMP0524P_SLP2510P8-10-9 HDMI_TX0+_CONN 8 D0+
7 D0_SHIELD
HDMI_TX1-_CONN 6
HDMI_TX1+_CONN D1-
5 D1+
D39 4
HDMI_TX0+_CONN 1 1 109 HDMI_TX0+_CONN HDMI_TX2-_CONN D1_SHIELD
3 D2-
HDMI_TX2+_CONN 2
HDMI_TX0-_CONN 2 2 98 HDMI_TX0-_CONN D2+
1 D2_SHIELD
HDMI_CLK+_CONN 4 4 77 HDMI_CLK+_CONN JHDMI1
HDMI_CLK-_CONN 5 5 66 HDMI_CLK-_CONN

3 3 ME@
SWAP
8

YSCLAMP0524P_SLP2510P8-10-9
D33
HDMI_TX2+_CONN 1 1 109 HDMI_TX2+_CONN

A
HDMI_TX2-_CONN 2 2 98 HDMI_TX2-_CONN A

HDMI_TX1+_CONN 4 4 77 HDMI_TX1+_CONN

HDMI_TX1-_CONN 5 5 66 HDMI_TX1-_CONN

3 3
8
Security Classification Compal Secret Data Compal Electronics, Inc.
2010/08/25 2012/08/25 Title

YSCLAMP0524P_SLP2510P8-10-9
1'SPN: SC300001Y00 Issued Date Deciphered Date
SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2'SPN: SC300002800 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 32 of 48
5 4 3 2 1
5 4 3 2 1

256K AT25256B-SSHL-T
PN:SA00005G500 +3VS_LC

U4906
EE_CS_N 1 8
EE_DO CS# VCC HOLD# +3VS_LC
2 SO HOLD# 7 1 TB@
WP# 3 6 EE_CLK C5131
+3VS_LC WP# SCK EE_DI 0.1U_0402_16V4Z
4 GND SI 5
TB@
AT25256B-SSHL-T_SO8 2 TMU_CLK_IN
U4907A 2R5106 1
TB@ TB@ 10K_0402_5%
1 R5097 2 EE_DO AD23 MONDC0 PCIe_RST_0_N N6
3.3K_0402_5% AC24 T1
TB@ MONDC1 PCIe_RST_1_N
PCIe_RST_2_N Y5
D
1 R5099 2 EE_CS_N W18 MONOBS_P PCIe_RST_3_N U2 D
3.3K_0402_5% TB_XTAL25_IN W16 W6 CLKREQ_TB#
MONOBS_N PCIE_CLKREQ_OD_N CLKREQ_TB# 13
TB@
1 R5101 2 WP# 1 TB@ 2 TB_XTAL25_OUT EE_DI R4 AA4
3.3K_0402_5% R5105 1M_0402_5% EE_DO EE_DI TMU_CLK_OUT TMU_CLK_IN
P5 Y3

TB@ Y4902 TB@


EE_CS_N
EE_CLK
AD3
EE_DO
EE_CS_N
MISC TMU_CLK_IN
PA_HV_EN +3V_POC
W4 EE_CLK GPIO_0__PA_HV_EN__BYP0 G2 PA_HV_EN 60
1 R5100 2 HOLD# 4 3 M1 PB_HV_EN TB@
3.3K_0402_5% NC OSC R1 GPIO_1__PB_HV_EN__BYP0 TBT_GO2SX_R TB_WAKE#
1 2 0_0402_5% N4 TEST_EN GPIO_2__GO2SX Y1 0_0402_5% 1 @ 2 R5205 TBT_GO2SX 43 2 R5187 1
R2 short@ FORCE_PWR
1 OSC NC 2 1 2 0_0402_5% AB5 TEST_PWR_GOOD GPIO_3 W2 R5201 1 2 0_0402_5% TB_Force_PWR 17
10K_0402_5%
TB@ short@ TB@ TB_WAKE# 0_0402_5% 1 short@
GPIO_4_WAKE_OD_N J4 2 R5196 PCIE_WAKE# 14,39
TB@
2 R5186 1 CR_JTCK TB@ 1 TB@ 2 R5107 1 U20 AA2 CIO_PLUG_EVENT @ CIO_PWR_EN# 2 R5163 1
10K_0402_5% 25MHZ_12PF_X3G025000DC1H~D 1K_0402_1% RSENSE GPIO_5_CIO_PLUG_EVENT TB_SMB_DAT 10K_0402_5%
1 W20 RBIAS GPIO_6_OD__CIO_SDA_OD AB1
TB@ C5130 C5132 AC2 TB_SMB_CLK TB@
R5185 CR_JTMS 20P_0402_50V8 20P_0402_50V8 TB_XTAL25_IN GPIO_7_OD__CIO_SCL_OD CIO_PWR_EN# TBT_OK2GO2SX_R 2 R5164 1
2 1 AA24 XTAL_25_IN GPIO__8_EN_CIO_PWR_N_OD P3 CIO_PWR_EN# 35
10K_0402_5% 2 TB_XTAL25_OUT TBT_OK2GO2SX_R 0_0402_5% 1 @
AB23 XTAL_25_OUT GPIO_9__OK2GO2SX_N_OD M5 2 R5204 TBT_OK2GO2SX 43
10K_0402_5%
TB@ 2 PA_CIO_SEL TB@
GPIO_10__PA_CIO_SEL__BYP1 M3 PA_CIO_SEL 34,36
2 R5133 1 CR_JTDI CR_JTCK AA6 L2 PB_CIO_SEL PA_DP_PWRDN 2 R5110 1
10K_0402_5% CR_JTMS TCK GPIO_11__PB_CIO_SEL__BYP1 PA_DP_PWRDN 10K_0402_5%
AB3 TMS GPIO_12__PA_DP_PWRDN__BYP2 H3 PA_DP_PWRDN 34
CR_JTDI V1 L4 PB_DP_PWRDN TB@
R5184 TB@ CR_JTDO TDI GPIO_13__PB_DP_PWRDN__BYP2 GPIO14 PB_DP_PWRDN
R2 TDO GPIO_14 T3 2 R5166 1
1 2 CR_JTDO V5 GPIO15 10K_0402_5%
1K_0402_5% GPIO_15 TBT_RESET#
Y7 THERMDA PWR_ON_POC_RSTN J2 TBT_RESET# 43 Tigger after SUSP# asserted for 30ms
U4 K5 EN_LC_PWR
NC EN_LC_PWR EN_LC_PWR 35
@
TBT_GO2SX_R 2 R5159 1
PCH_DPC_P3 E14 A14 10K_0402_5%
15 PCH_DPC_P3 DPSNK0_3_P DPSRC_3_P
PCH_DPC_N3 D13 B15
15 PCH_DPC_N3 DPSNK0_3_N DPSRC_3_N
PCH_DPC_P2 E16 A12 TB@
15 PCH_DPC_P2 DPSNK0_2_P DPSRC_2_P
PCH_DPC_N2 D15 B13 TBT_GO2SX_R 2 R5206 1
15 PCH_DPC_N2 DPSNK0_2_N DPSRC_2_N 10K_0402_5%
PCH_DPC_P1 E18 A10
15 PCH_DPC_P1 DPSNK0_1_P DPSRC_1_P

SOURCE PORT 0
PCH_DPC_N1 R267 TB@

SINK PORT 0
15 PCH_DPC_N1 D17 DPSNK0_1_N DPSRC_1_N B11
PA_HV_EN 1 2
PCH_DPC_P0 E20 A8 1K_0402_5%
15 PCH_DPC_P0 DPSNK0_0_P DPSRC_0_P
PCH_DPC_N0 D19 B9 TB@

Display Port
15 PCH_DPC_N0 DPSNK0_0_N DPSRC_0_N EN_LC_PWR 2 R5160 1
C 15 PCH_DPC_AUXP C5178 1 2 0.1U_0402_10V7K PCH_DPC_AUXP_C A6 C2 100K_0402_5% C
C5182 PCH_DPC_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
15 PCH_DPC_AUXN 1 2 0.1U_0402_10V7K B5 DPSNK0_AUX_N DPSRC_AUX_N D3 TB@
FORCE_PWR 2 R5161 1
U6 V3 10K_0402_5%
15 DPC_HPD DPSNK0_HPD DPSRC_HPD_OD TB@
1 PB_CIO_SEL 2 R5109 1

1
E6 TB@ 10K_0402_5%
TB@ DPSNK1_3_P R5114 TB@
D5 DPSNK1_3_N
R5113 10K_0402_5% GPIO14 2 R5111 1
100K_0402_5% E8 10K_0402_5%
DPSNK1_2_P TB@
D7
2

2
DPSNK1_2_N GPIO15 R5112 1
2
E10 10K_0402_5%
DPSNK1_1_P TB@
D9

SINK PORT 1
DPSNK1_1_N PB_HV_EN R5108 1
2
E12 10K_0402_5%
DPSNK1_0_P
D11 DPSNK1_0_N
A4 DPSNK1_AUX_P
B3 DPSNK1_AUX_N
T5 DPSNK1_HPD

TB@ C5166 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P5_C AD5 AB9


13 PCIE_PRX_DTX_P5 PETP_0 PERP_0 PCIE_PTX_C_DRX_P5 13
TB@ C5167 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_N5_C AD7 AA10
13 PCIE_PRX_DTX_N5 PETN_0 PERN_0 PCIE_PTX_C_DRX_N5 13
TB@ C5168 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P6_C AD9 AA12
13 PCIE_PRX_DTX_P6 PETP_1 PERP_1 PCIE_PTX_C_DRX_P6 13
TB@ C5169 2 0.1U_0402_10V7K PCIE_PRX_DTX_N6_C
TRANSMIT

13 PCIE_PRX_DTX_N6 1 AD11 PETN_1 PERN_1 AB13 PCIE_PTX_C_DRX_N6 13


TB@ C5184 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P7_C AD13 PCIe AB15

RECEIVE
13 PCIE_PRX_DTX_P7 PETP_2 PERP_2 PCIE_PTX_C_DRX_P7 13
TB@ C5185 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_N7_C AD15 AA16
13 PCIE_PRX_DTX_N7 PETN_2 PERN_2 PCIE_PTX_C_DRX_N7 13
TB@ C5186 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P8_C AD17 AA18
13 PCIE_PRX_DTX_P8 PETP_3 PERP_3 PCIE_PTX_C_DRX_P8 13
TB@ C5187 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_N8_C AD19 AB19
13 PCIE_PRX_DTX_N8 PETN_3 PERN_3 PCIE_PTX_C_DRX_N8 13

B 13,16,21,39,41,43,46 PLT_RST# R6 PERST_N REFCLK_100_IN_P AB21 CLK_PCIE4 13 B


AD21 TB_SMB_CLK R5202 1 2 0_0402_5%
REFCLK_100_IN_N CLK_PCIE4# 13 short@ TB_GPIO7 17
CACTUS-RIDGE_FCBGA288
TB@ TB_SMB_DAT R5203 1 2 0_0402_5%
short@ TB_GPIO6 17

SA00005QT00 S IC DSL3310 QQ3Z B1 FCBGA288P CONVERGED


0112 Modify

+3V_POC
+3V_POC

TB@

1
TB@ 1 2
R5165 C5222 0.1U_0402_16V7K
10K_0402_5%

5
CIO_PLUG_EVENT 2

P
2
B TB_PLUG_EVENT
Y 4 TB_PLUG_EVENT 17
CIO_PWR_EN 1 A

G
1
D TB@

3
CIO_PWR_EN# 2 Q113 U4909
G SSM3K7002FU_SC70-3 NC7SZ08P5X_NL_SC70-5
S TB@

3
A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 33 of 48
5 4 3 2 1
5 4 3 2 1

HDMI_CLKDAT_EN 36

5
PA_AUX_N 1 6 3 4
D PCH_DPC_DAT 15 D
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
TB@ Q111A TB@ Q111B

HDMI_CLKDAT_EN 36

5
PA_AUX_P 1 6 3 4
PCH_DPC_CLK 15
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
TB@ Q112A TB@ Q112B

+3V_POC
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
TB@ TB@ TB@ TB@ TB@ TB@ TB@
1 1 1 1 1 1 1
C5133

C5134

C5135

C5136

C5137

C5138

C5139
C C
36 PA_DPSRC_HPD

2 2 2 2 2 2 2

TB@
U4908 U4907B
C5140 2 1 0.22U_0402_6.3V6K PA_DPSRC_3P_C A18 A22
PA_DPSRC_3P C5141 2 PA_DPSRC_3N_C PA_DPSRC_3_P PB_DPSRC_3_P
3 VDD D0+A 31 1 0.22U_0402_6.3V6K B19 PA_DPSRC_3_N PB_DPSRC_3_N B23
9 30 PA_DPSRC_3N
VDD D0-A

DPSRC Port A
PA_DPSRC_1P C5142 2 1 0.22U_0402_6.3V6K PA_DPSRC_1P_C

DPSRC Port B
12 VDD D1+A 27 A16 PA_DPSRC_1_P PB_DPSRC_1_P A20
16 A 26 PA_DPSRC_1N C5143 2 1 0.22U_0402_6.3V6K PA_DPSRC_1N_C B17 B21
VDD D1-A PA_DPSRC_1_N PB_DPSRC_1_N
20 VDD
29 19 PA_AUX_P C5144 2 1 0.22U_0402_6.3V6K PA_AUX_P_C F3 D1
VDD AUX+A PA_AUX_N C5145 2 PA_AUX_N_C PA_AUX_P PB_AUX_P
AUX-A 18 1 0.22U_0402_6.3V6K F1 PA_AUX_N PB_AUX_N E2
HPD_A 17
PA_SRC_3P 1 PA_DPSRC_HPD H1 K3 PB_DPSRC_HPD
36 PA_SRC_3P D0+ PA_DPSRC_HPD PB_DPSRC_HPD
PA_SRC_3N 2 25 B_D0+
36 PA_SRC_3N D0- D0+B
PA_LSTX_SRC_1P 4 24 B_D0- TBLT_R2C_0P C5146 2 1 0.22U_0402_6.3V6K TBLT_R2C_0P_C G24 R24
36 PA_LSTX_SRC_1P D1+ D0-B 36 TBLT_R2C_0P PA_CIO0_TX_P__DPSRC_0_P PB_CIO2_TX_P__DPSRC_0_P
PA_LSRX_SRC_1N 5 23 PA_LSTX_LSEO1 TBLT_R2C_0N C5147 2 1 0.22U_0402_6.3V6K TBLT_R2C_0N_C E24 N24
36 PA_LSRX_SRC_1N D1- D1+B 36 TBLT_R2C_0N PA_CIO0_TX_N__DPSRC_0_N PB_CIO2_TX_N__DPSRC_0_N
B 22 PA_LSRX_LSOE1
DPA_AUX_P D1-B TBLT_C2R_0P C5148 2 TBLT_C2R_0P_C
36 DPA_AUX_P 6 AUX+ 36 TBLT_C2R_0P 1 0.22U_0402_6.3V6K G22 PA_CIO0_RX_P PB_CIO2_RX_P R22
DPA_AUX_N 7 15 B_AUX+ TBLT_C2R_0N C5149 2 1 0.22U_0402_6.3V6K TBLT_C2R_0N_C E22 N22

PORT0
36 DPA_AUX_N AUX- AUX+B 36 TBLT_C2R_0N PA_CIO0_RX_N PB_CIO2_RX_N

PORT2
HPD_IN 8 14 B_AUX-
HPD AUX-B PA_CFG1_LSEO0 PB_CONFIG1_CIO2

CIO
HPD_B 13 36 PA_CFG1_LSEO0 K1 PA_CONFIG1__CIO_0_LSEO PB_CONFIG1__CIO_2_LSEO P1
10 PA_CFG2_LSOE0 G4 H5 PB_CONFIG2_CIO2
33 PA_DP_PWRDN SEL 36 PA_CFG2_LSOE0 PA_CONFIG2__CIO_0_LSOE PB_CONFIG2__CIO_2_LSOE
11 HPD_SEL GND 21
+3V_POC
33,36 PA_CIO_SEL 32 AUX_SEL GND 28
33 TBLT_R2C_1P C5150 2 1 0.22U_0402_6.3V6K TBLT_R2C_1P_C L24 W24
GPAD 36 TBLT_R2C_1P PA_CIO1_TX_P__DPSRC_2_P PB_CIO3_TX_P__DPSRC_2_P
TBLT_R2C_1N C5151 2 1 0.22U_0402_6.3V6K TBLT_R2C_1N_C J24 U24
36 TBLT_R2C_1N PA_CIO1_TX_N__DPSRC_2_N PB_CIO3_TX_N__DPSRC_2_N
PI3VEDP212ZLEX_TQFN32_6X3~D
1 2 DPA_AUX_N TB@ TBLT_C2R_1P C5152 2 1 0.22U_0402_6.3V6K TBLT_C2R_1P_C L22 W22
36 TBLT_C2R_1P PA_CIO1_RX_P PB_CIO3_RX_P
TBLT_C2R_1N C5153 2 1 0.22U_0402_6.3V6K TBLT_C2R_1N_C J22 U22

PORT1
36 TBLT_C2R_1N PA_CIO1_RX_N PB_CIO3_RX_N

PORT3
R2216 100K_0402_1%
PA_CIO_SEL N2 L6
TB@ PA_LSTX__CIO_1_LSEO PB_LSTX__CIO_3_LSEO
B L : Port A DP TB@ J6 PA_LSRX__CIO_1_LSOE PB_LSRX__CIO_3_LSOE G6 PB_LSRX_CIO3
B

1 2 DPA_AUX_P H : Port B TB TB@


B_D0+ 1 R5118 2 CACTUS-RIDGE_FCBGA288
R2217 100K_0402_1% 49.9_0402_1% +3V_POC TB@
TB@ TB@
B_D0- 1 R5119 2
2

1 2 HPD_IN 49.9_0402_1% TB@


R5120
R5117 10K_0402_5% TB@ 10K_0402_5% PB_DPSRC_HPD 2 R5124 1
TB@ B_AUX+ 1 R5121 2 10K_0402_5%
1K_0402_5% TB@
1

TB@ PB_CONFIG1_CIO2 2 R5126 1


B_AUX- 1 R5122 2 10K_0402_5%
1K_0402_5% TB@
1

TB@ PB_CONFIG2_CIO2 2 R5128 1


R5123 10K_0402_5%
1M_0402_5% TB@
PB_LSRX_CIO3 2 R5130 1
TB@ 0112 Del& Modify 10K_0402_5%
2

2 R5125 1 TBLT_R2C_0P TB@


470K_0402_5%
TB@ +3V_POC
2 R5127 1 TBLT_R2C_0N TB@
470K_0402_5% 1 2
TB@ C5226 0.1U_0402_16V7K
2 R5129 1 TBLT_R2C_1P
5

470K_0402_5%
TB@ 2
P

TBLT_R2C_1N B
2 R5131 1 Y 4
470K_0402_5% 1 A
G
3

U4916
NC7SZ08P5X_NL_SC70-5
TB@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 34 of 48
5 4 3 2 1
5 4 3 2 1

U4907D
+1.05VS_LC
A2 VSSPE VSS K9
A24 VSSPE VSS K13
B1 VSSPE VSS L8
+1.05VS_CIO
B7 VSSPE VSS L12
+1.05VS_LC +1.05VS_CIO
C4 L16

1000P_0402_50V7K
VSSPE VSS
U4907C C6 VSSPE VSS M9

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
TB@ TB@ TB@ TB@ TB@ TB@ TB@ TB@ C8 M13
VSSPE VSS
1 1 1 J8 VCC1P0_ON VCC1P0 W10 1 1 C10 VSSPE VSS M17

1
1U_0402_6.3V6K
C5224

1U_0402_6.3V6K
C5225

C5162

C5164

C5155

C5156

1U_0402_6.3V6K
C5230

1U_0402_6.3V6K
C5231
C5163
J10 VCC1P0_ON VCC1P0 V11 C12 VSSPE VSS N8
TB@ J12 U10 C14 N12
VCC1P0_ON VCC1P0 VSSPE VSS
J14 T11 C16 N16
2

2
2 2 VCC1P0_ON VCC1P0 2 2 VSSPE VSS
J16 VCC1P0_ON VCC1P0 R14 C18 VSSPE VSS P9
K17 VCC1P0_ON VCC1P0 R10 C20 VSSPE VSS P13
D D
T15 VCC1P0_ON VCC1P0 P15 C22 VSSPE VSS P17
U14 VCC1P0_ON VCC1P0 P11 C24 VSSPE VSS R8
V7 VCC1P0_ON VCC1P0 N14 D21 VSSPE VSS R12
W8 N10 D23 R16

1000P_0402_50V7K
VCC1P0_ON VCC1P0 TB@ TB@ VSSPE VSS
G10 VCC1P0_PE VCC1P0 M15 E4 VSSPE VSS T9

0.01U_0402_16V7K

0.01U_0402_16V7K
TB@ TB@ G12 M11 F5 T13

VCC
VCC1P0_PE VCC1P0 VSSPE VSS

1
0.01U_0402_16V7K

0.01U_0402_16V7K

C5223

C5165
G14 L14 F7 T17
VCC1P0_PE VCC1P0 VSSPE GND VSS
1

1
C5179

C103

C5180

G16 VCC1P0_PE VCC1P0 L10 F9 VSSPE VSS U8


TB@ G18 K15 F11 U12

2
VCC1P0_PE VCC1P0 +3VS_LC VSSPE VSS
H19 K11 F13 U16
2

VCC1P0_PE VCC1P0 VSSPE VSS


K19 VCC1P0_PE F15 VSSPE VSS V9
M19 VCC1P0_PE VCC3P3 M7 F17 VSSPE VSS AD1
P19 VCC1P0_PE VCC3P3 P7 F19 VSSPE VSSPE Y11
T19 VCC1P0_PE VCC3P3 T7 F21 VSSPE VSSPE Y13
+3VS_LC
V15 VCC1P0_PE VCC3P3_CIO L18 F23 VSSPE VSSPE Y15
V19 N18 G20 Y17

1000P_0402_50V7K
VCC1P0_PE VCC3P3_CIO VSSPE VSSPE
W12 VCC1P0_PE VCC3P3_CIO R18 H21 VSSPE VSSPE Y19

0.1U_0402_10V7K
W14 H11 TB@ TB@ TB@ TB@ H23 Y21
VCC1P0_PE VCC3P3_DP VSSPE VSSPE

0.01U_0402_16V7K
G8 VCC1P0_DPAUX VCC3P3_DP H13 1 J18 VSSPE VSSPE Y23

1
C5197

C5183

0.1U_0402_10V7K
C5229

0.1U_0402_10V7K
C5232
C5196
H9 VCC1P0_DPAUX VCC3P3_DP H15 J20 VSSPE VSSPE AA8
+3V_POC
VCC3P3_DP H17 K21 VSSPE VSSPE AA14
H7 K23 AA20

2
VCC3P3_DPAUX TB@ 2 VSSPE VSSPE
VCC3P3_POC K7 L20 VSSPE VSSPE AA22
M21 VSSPE VSSPE AB7
CACTUS-RIDGE_FCBGA288 M23 AB11
VSSPE VSSPE

0.1U_0402_10V7K
TB@ N20 AB17
TB@ VSSPE VSSPE
1 P21 VSSPE VSSPE AC4

C5181
P23 VSSPE VSSPE AC6
R20 VSSPE VSSPE AC8
T21 VSSPE VSSPE AC10
2
T23 VSSPE VSSPE AC12
U18 VSSPE VSSPE AC14
V13 VSSPE VSSPE AC16
C V17 VSSPE VSSPE AC18 C
V21 VSSPE VSSPE AC20
V23 VSSPE VSSPE AC22
Y9
+1.05VS TO +1.05VS_LC 1A
VSSPE
CACTUS-RIDGE_FCBGA288

Q109
+1.05VS TB@
SI3456DDV-T1-GE3_TSOP6 +1.05VS_LC
TB@
D

6
S

5 4
2
1
1
G

C5214

0.1U_0402_10V6K

R5150 @
3

+5VS TB@ TB@ 100_0603_5%


1

1
10U_0603_6.3V6M

C5216

10U_0603_6.3V6M

C5213

TB@
2
2

TB@ R5148 D
20K_0402_5% 2 EN_LC_PWR#
G
R5151 S SSM3K7002FU_SC70-3
3

1 2 @
Q76
TB@
1

150K_0402_5%
1

D TB@ C5212
EN_LC_PWR# 2 Q77 TB@ 0.1U_0402_10V6K
2

G SSM3K7002FU_SC70-3
S
3

B B

+1.05VS TO +1.05VS_CIO 3A

Q107

+3VS +3V_POC
+3V_POC TO +3VS_LC 250mA 0112 Del +1.05VS SI3456DDV-T1-GE3_TSOP6
TB@
+1.05VS_CIO

+3V_POC +3VS_LC

D
6

S
Q106 TB@ 5 4
TB@ 2
1

10U_0603_6.3V6M
SI2301BDS-T1-E3_SOT23-3 1
1

1
1U_0402_6.3V6K
C5215

10U_0603_6.3V6M
+5VS R5154@ TB@ @

C5220

0.1U_0402_10V6K
S

470_0603_5% TB@ R5155


D

3 1

1
C5218
TB@ 470_0603_5%
2

1
C5221
TB@ +5VS
2

R5152
G
2

2
20K_0402_5%

2
1

D TB@

1
D
2EN_LC_PWR# R5153
R5149 TB@ G 20K_0402_5% 2 CIO_PWR_EN#
EN_LC_PWR#1 2 S SSM3K7002FU_SC70-3 G
3

Q1 @ TB@ R5156 S SSM3K7002FU_SC70-3

3
200K_0402_1% 1 2 @
Q80
200K_0402_1%
1

1
D TB@ TB@ TB@
1

1 D
2 Q105 TB@ C5219
33 EN_LC_PWR
G SSM3K7002FU_SC70-3 C5217 CIO_PWR_EN# 2 Q78 0.1U_0402_10V6K
33 CIO_PWR_EN#

2
S 0.1U_0402_10V6K G SSM3K7002FU_SC70-3
3

A S A
3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 35 of 48
5 4 3 2 1
5 4 3 2 1

+3V_POC +12V

TB@ TB@ 0417 change to 0805 type

0.1U_0402_16V7K~N
D D

4.7U_0805_25V6-K
0.1U_0402_16V7K~N
@ 1 TB@ 1

1
+5VS

10U_0603_6.3V6M

CT133

10U_0603_6.3V6M

CT134

CT1
CT131

CT132
@

2
1
2 2
R5146 +5VS +3V_POC
10K_0402_5%

19
20
1

6
7
+3V_POC UT6 +VCC_DP_L +mDP_PWR

2
HDMI_CLKDAT_EN R5162 R5195

VHV
VHV
V3P3
V3P3
34 HDMI_CLKDAT_EN LT7
Q2207B 10K_0402_5% 10K_0402_5% TB@ TB@ TB@ TB@

1
2N7002DW-T/R7_SOT363-6 2 RT91 1 10K_0402_5% 5 12 1 2

0.1U_0402_16V7K~N

0.1U_0402_16V7K~N

0.01U_0402_16V7K~N
+12V TB@ +3V_POC EN OUT
R5193 HV_EN 11 14

2
HV_EN OUT
10K_0402_5% +3V_POC 1 RT95 2 0_0402_5% 17 S0
T249 1 1 1

1
0_0402_5%

CT129

CT130

CT127
5 DP_AUX_EN TB@ 1 TB@ 18 +VCC3V3_PA
V3P3OUT

1
R5194 2 8 @ C5199 TB@

2
Q2207A 10K_0402_5% ISET_V3P3 PAD~D TB@
Q2417 3 9 15
4

ISET_S3 RSVD

6
2N7002DW-T/R7_SOT363-6 TB@ Q2418 10 16 2 2 2 0.01U_0402_16V7K

2
ISET_S0 RSVD
1 BC846B_SOT23-3

36.5K_0402_1%

17.8K_0402_1%

17.8K_0402_1%

TPad
2

GND
GND
GND
GND
GND
2PA_CFG1_LSEO0 3 TB@

1
RT96

RT94
R5243 BC846B_SOT23-3 TB@ TPS22980RGPR_VQFN20_4X4

1
2
3
4
13

21
2.05K_0402_1% RT92 TB@ Check BOM
TB@ 0308 change to 0402 type

2
TB@ TB@

TB@

17.8K_0402_1%

17.8K_0402_1%
LT7 P/N: SM01000KM00

1
Co-layout

RT98

RT97
TB@ waiting to change new symbol
1 R182 2

2
TB@ TB@
0_0402_5%
U4910
TBLT_R2C_R_0P 1 2 TBLT_R2C_L_0P
34 TBLT_R2C_0P 1 2
LANE0
TBLT_R2C_R_0N 4 3 TBLT_R2C_L_0N
34 TBLT_R2C_0N 4 3
C @ WCM-2012HS-900T_4P C
TB@
1 R191 2
0_0402_5%

TB@
1 R192 2
0_0402_5%
TBT, HDMI, DP mode table
WCM-2012HS-900T_4P
HPD CFG1 CFG2 LSRX Mode
PA_LSTX_SRC_R_1P 4 3 PA_LSTX_SRC_L_1P
34 PA_LSTX_SRC_1P 4 3
LANE1
34 PA_LSRX_SRC_1N
PA_LSRX_SRC_R_1N 1 1 2 2 PA_LSRX_SRC_L_1N 1 0 0 X DP
@
U4911
TB@ 1 1 X X HDMI
1 R194 2
0_0402_5%
0 0 1 1 TBT
TB@
1 R201 2
0_0402_5% Check BOM (LT7 &LT8)
0308 change to 0402 type
U4912 0315 Reserve 12.1ohm 0402
TBLT_R2C_R_1P TBLT_R2C_L_1P +mDP_PWR
34 TBLT_R2C_1P 1 1 2 2 0417 change LT8 to short pad
LANE2 33,34 PA_CIO_SEL
R5138 @ 12.1_0402_1%
TBLT_R2C_R_1N 4 4 TBLT_R2C_L_1N W=40mils +mDP_PWR
34 TBLT_R2C_1N
@ 3 3 2
LT8
1

1
WCM-2012HS-900T_4P 0_0402_5%
TB@ TB@ TB@ C5204 RT01

1.5K_0402_5%

1.5K_0402_5%
2 1

1
1 R203 2 short@
0.1U_0402_16V4Z

2
R5135

R5136
0_0402_5%
TB@
1 R224 2
0_0402_5% JAE_DP3R020SU32JQ

2
D4608 TB@
TB@ @ U4914 BAR90-02LRH_TSLP-2-7-2 24

GROUND
1 R204 2 1 1 2 TBLT_C2R_L_1N 2 1 23
34 TBLT_C2R_1N 2
0_0402_5% 22
2 1 21
WCM-2012HS-900T_4P 4 3 TBLT_C2R_L_1P D4609
B 34 TBLT_C2R_1P 4 3 B

650NH +-5% LQW18CNR65J00D


PA_SRC_R_3P 4 3 PA_SRC_L_3P BAR90-02LRH_TSLP-2-7-2 +mDP_PWR 20 DP_PWR
34 PA_SRC_3P 4 3 WCM-2012HS-900T_4P
TB@ TB@ RT01 19 RETURN

1
1 R222 2 TBLT_C2R_D_1N 18 AUXCH_N
PA_SRC_R_3N 1 1 2 PA_SRC_L_3N LANE3 0_0402_5% TBLT_R2C_L_1N 17 LANE2_N
34 PA_SRC_3N 2
@ L4903 L4904 TBLT_C2R_D_1P 16 AUXCH_P
U4913 650NH +-5% LQW18CNR65J00D TBLT_R2C_L_1P 15 LANE2_P
TB@ 14 GND
1 R218 2 13 GND

2
0_0402_5% PA_SRC_L_3N 12 LANE3_N
PA_LSRX_SRC_L_1N 11 LANE1_N
34 DPA_AUX_N
PA_SRC_L_3P 10 LANE3_P
34 DPA_AUX_P
PA_LSTX_SRC_L_1P 9 LANE1_P
1 1 8 GND
TB@ 0.01U_0402_50V7K C5205 2 1 7 GND
D43 TB@ C5206 C5207

30P_0402_50V8J
6 CONFIG2
TBLT_R2C_L_1N 1 1 109 TBLT_R2C_L_1N 30P_0402_50V8J TBLT_R2C_L_0N 5 LANE0_N
TB@ 2 2 4 CONFIG1
TBLT_R2C_L_1P 2 2 98 TBLT_R2C_L_1P 1 R229 2 TBLT_R2C_L_0P 3 LANE0_P
0_0402_5% 2 HPD

0.01U_0402_16V7K
TBLT_R2C_L_0N 4 4 77 TBLT_R2C_L_0N 1 GND

1
WCM-2012HS-900T_4P

100K_0402_5%

C5208
R5139
TBLT_R2C_L_0P 5 5 66 TBLT_R2C_L_0P 4 3 TBLT_C2R_L_0N
34 TBLT_C2R_0N 4 3
3 3

2
1 1 2 TBLT_C2R_L_0P TB@ JmDP1
34 TBLT_C2R_0P

2
8 @ 2 ME@

1
U4915 TB@

1K_0402_5%

1K_0402_5%

0.01U_0402_50V7K
TB@

1
YSCLAMP0524P_SLP2510P8-10-9 1 R230 2

R5141

R5142

C5209
@ 0_0402_5%
Standard Type:

2
PN: DC021111041

2
D44 PA_CFG2_LSOE0 TB@
34 PA_CFG2_LSOE0
TBLT_C2R_L_0P 1 1 109 TBLT_C2R_L_0P

330P_0402_50V7K

330P_0402_50V7K
TBLT_C2R_L_0N 2 2 98 TBLT_C2R_L_0N

1
1M_0402_5%

1M_0402_5%
TB@ TB@ TB@ TB@

1
+3V_POC +3V_POC

R5144

R5145

C5210

C5211
PA_SRC_L_3P 4 4 77 PA_SRC_L_3P

PA_SRC_L_3N 5 5 66 PA_SRC_L_3N

2
1

+3VS
2

2
3 3 R5192
1

10K_0402_5%
8 R5188
A 10K_0402_5% A
2

1
YSCLAMP0524P_SLP2510P8-10-9
34 PA_CFG1_LSEO0
@ R5116
2
6

1M_0402_5%

2
D42 Q2415A

G
TBLT_C2R_D_1N 1 1 109 TBLT_C2R_D_1N 2N7002DW-T/R7_SOT363-6

2
2 mDP_HPD 1 3
Q2415B PA_DPSRC_HPD 34
TBLT_C2R_D_1P 2 2 98 TBLT_C2R_D_1P

S
3

2N7002DW-T/R7_SOT363-6
1

PA_LSRX_SRC_L_1N 4 4 77 PA_LSRX_SRC_L_1N SSM3K7002FU_SC70-3


Q108
PA_LSTX_SRC_L_1P 5 5 66 PA_LSTX_SRC_L_1P 5

3 3
4

8 Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
YSCLAMP0524P_SLP2510P8-10-9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
@ Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 36 of 48
5 4 3 2 1
5 4 3 2 1

JUSB1USB3.0/USB2.0
1'SPN: SC300001Y00
2'SPN: SC300002800
16 USB3_TX2_N C4606 1 2 0.1U_0402_16V7K USB3TXDN2 USB3TXDN2_C

D2410
USB3RXDN2_C 1 1 109 USB3RXDN2_C 4 3

D USB3RXDP2_C 2 2 98 USB3RXDP2_C DLW21SN670HQ2L_4P D


1 2
USB3TXDN2_C 4 4 77 USB3TXDN2_C
L4603
USB3TXDP2_C 5 5 66 USB3TXDP2_C 16 USB3_TX2_P C4605 1 2 0.1U_0402_16V7K USB3TXDP2 USB3TXDP2_C

3 3
USB3_RX2_N USB3RXDN2_C
8 16 USB3_RX2_N

YSCLAMP0524P_SLP2510P8-10-9 4 3

DLW21SN670HQ2L_4P
1 2

L4604
USB3_RX2_P USB3RXDP2_C
16 USB3_RX2_P

D2405
1 4 USB20_P1_C
I/O1 I/O3

L4606
2 5 +USB_VCCA USB20_N1 1 2 USB20_N1_C
GND VDD 16 USB20_N1 1 2

USB20_P1 4 3 USB20_P1_C
16 USB20_P1 4 3
3 6 USB20_N1_C
C
I/O2 I/O4 WCM2012F2S-900T04_0805 C
AZC099-04S.R7G_SOT23-6

1'S PN: SC300001G00


L4603, L4604, L4606
2'S PN: SC300002E00 S COM FI_ KINGCORE WCM-2012HS-900T
P/N : SM070001S00

DC23300A900
80mils JUSB1
+5VALW 1
+USB_VCCA +USB_VCCA VBUS
USB20_N1_C 2
U34 USB20_P1_C D-
3 D+
1 GND VOUT 8 4 GND
C771 0.1U_0402_16V4Z 2 7 USB3RXDN2_C 5
VIN VOUT USB3RXDP2_C SSRX- USB30_GND2
2 1 3 VIN VOUT 6 6 SSRX+ GND 10

C2435

470P_0402_50V7K
USB_ON# 4 5 USB_OC0# 7 11 USB30_GND2
B EN FLG USB_OC0# 16 GND GND B
1 USB3TXDN2_C 8 12 USB30_GND2
G547I2P81U_MSOP8 USB3TXDP2_C SSTX- GND USB30_GND2
1 1 9 SSTX+ GND 13
1

C770 C2434 +
1

2
@ 1000P_0402_50V7K 150U_D2_6.3VM C4613 USB3_DC23300A900
Low Active 0.1U_0402_16V4Z ME@ R4611 C4612
2

2 2 2
0_0402_5% 0.1U_0402_16V4Z
2
43,46 USB_ON# short@

1
PN : SGA20151300

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2011/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 37 of 48
5 4 3 2 1
5 4 3 2 1

+5VS +5VDDA_CODEC +5VDDA_CODEC


HDA_RST_AUDIO#

1
R943
2 HDA_SYNC_AUDIO
EMI
CHB1608U301_0603 +3VS +3VDD_CODEC +IOVDD_CODEC +3VDD_CODEC
R1355 R927 HDA_SDOUT_AUDIO

4.7U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
2 1 1 2 0_0603_5% 0_0402_5%

C646

C648
HDA_BITCLK_AUDIO

C5094

C5095
1 2 1 2

1U_0603_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 2 2 1 short@ short@
1 1 1 1 1 1 1 1

C693

C654

C655
C5110

C650

C651

C652

C653
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
@ @
2 2 2 2 2 2 2 2
Place near Pin25 Place near Pin38
R929
+5VS 1 2 +5VS_PVDD
D CHB1608U301_0603 D
Place near Pin1 Place near Pin9

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 1 1

C657

C656
C5096
Vendor Recommand add 10UF
1 2 2
Power down (PD#) power stage for save power
0V: Power down power stage +3VDD_CODEC +MIC1_VREFO_L
3.3V: Power up power stage
+IOVDD_CODEC

2
U9 Vendor recommend. 2.2K

39

46

25

38

9
R930
2.2K_0402_5%

PVDD1

PVDD2

AVDD1

AVDD2

DVDD

DVDD-IO
Vendor recommend. 2.2u

1
+3VS
MIC_JD R941 1 COMBOJACK
external MIC
2 0_0402_5% 47 EAPD/COMB-JACK LINE1-R(PORT-C-R) 24
short@ EC_MUTE# C5097 2.2U_0603_6.3V6K
43 EC_MUTE# 4 PD# LINE1-L(PORT-C-L) 23
2

HDA_SDOUT_AUDIO 5 22 MIC_EXTL_C 2 1 2 1 EXT_MIC


12 HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) EXT_MIC 46
R5071 HDA_BITCLK_AUDIO 6 21 MIC_EXTR_C 2 1 R933 1K_0402_5%
12 HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L)
4.7K_0402_5% HDA_SDIN0 2 1 SDATA_IN 8 17
12 HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
@ 22_0402_5% R938 16 C5098 2.2U_0603_6.3V6K
MIC2-L(PORT-F-L)

2
15
1

LINE2-R(PORT-E-R) R931
12 HDA_SYNC_AUDIO 10 SYNC LINE2-L(PORT-E-L) 14
HDA_RST_AUDIO# 11 470K_0402_5%
12 HDA_RST_AUDIO# RESET#
PC_BEEP 12 PCBEEP SPK_L2+
40

1
SPK-OUT-L+
1

41 SPK_L1-
R5065 JDREF SPK-OUT-L- SPK_R1-
20K_0402_1%
2 1
R942
19 JDREF SPK-OUT-R- 44
SPK_R2+
Internal Speaker
4.7K_0402_5% 20 MONO-OUT(PORT-H) SPK-OUT-R+ 45
@ PLUG_IN 2 1 SENSEA 13
46 PLUG_IN SENSE A
MIC Sense 39.2K_0402_1% R940 18
2

CBN SENSE B HP_OUTR


35 CBN HPOUT-R(PORT-A-R) 33
R940 place near pin13 2 1 CBP 36 CBP HPOUT-L(PORT-A-L) 32 HP_OUTL HP_OUTR 46
Headphone
2.2U_0603_6.3V6K 2 1C666 34 48 HP_OUTL 46
C 2.2U_0603_6.3V6K 2 CPVEE SPDIF-OUT C
1C5099 28 LDO-CAP 0131 move R to Sub.
4.7U_0603_6.3V6K C5100 R937
GNDA 3 DMIC_CLK_R 1 2
GPIO1/DMIC-CLK DMIC_CLK 31
29 0_0402_5%
MIC2-VREFO DMIC_DATA
30 MIC1-VREFO-R GPIO0/DMIC-DATA 2 DMIC_DATA 31

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+MIC1_VREFO_L 31 MIC1-VREFO-L
1 1

C658

C660
Place next to pin 27
27 @ @
VREF 2 2

1U_0603_10V4Z

0.1U_0402_16V4Z
42 PVSS1 AVSS1 26
AVSS2 37 1 1

C659
43 PVSS2

C5101
7 DVSS THERMAL PAD 49
2 2
0118 RF reserve
ALC3202-GR_MQFN48_6X6 C660 Place clise to LVDS conn.

ALC3202 VC3 EMI


@
R949
SA000058310 1 2 2 1 GNDA_S 46
@ 0_0402_5%
VENDOR recommand R948 2MM J14
1 2
@ 0_0402_5%
R947
1 2
PC Beep C1138 0.1U_0402_16V4Z @ 0_0402_5% Combo Jack detect (normal open)
43 BEEP# 1 2 PC_BEEP_C_R 1 R1124 2PC_BEEP_C 1 2 PC_BEEP
1000P_0402_50V7K

B 33_0402_5% @ B
EC Beep C5102 1U_0603_10V4Z Pin Assignment Location Function
2 1 R1123 47K_0402_5%
C1141
1

12 HDA_SPKR 1 2 MIC_JD 1 2 EXT_MIC


SPK-OUT (Pin40/41/44/45) Internal Int Speaker 2MM J11
ICH Beep C1140 0.1U_0402_16V4Z R1131 @

4.7U_0603_6.3V6K
2

10K_0402_5% GND GNDA 2


Capless HP-OUT (Pin32/33) External Headphone out
2

C1134
@
1
MIC1(Pin21/22) External Mic in

Vendor Recommand connect to GNDA

Rdc < 0.05 ohms


PN :SCA00000G00 Rated Current >
2A
wide 25MIL Speaker PN:SP02000T600
JSPK1
SPK_R1-_CONN SPK_L1-_CONN SPK_R1- L1101 1 2 FBMA-L11-160808-121LMA30T SPK_R1-_CONN 1 1
2 2
SPK_R2+_CONN SPK_L2+_CONN SPK_R2+ L1102 1 2 FBMA-L11-160808-121LMA30T SPK_R2+_CONN 3 3
4 4
SPK_L1- L1103 1 2 FBMA-L11-160808-121LMA30T SPK_L1-_CONN 5 GND
3

6 GND
SPK_L2+ L1104 1 2 FBMA-L11-160808-121LMA30T SPK_L2+_CONN
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

ACES_50305-00441-001

D59 D60 Width 20 mil


C1135

C1136

C1137
1

ME@
C1139

PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
1

@ @ EMI
2

A Internal Speaker 0905 updated A

Reserve for ESD request.

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/11/30 Deciphered Date 2011/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 38 of 48
5 4 3 2 1
5 4 3 2 1

D D
+LAN_VDD10 Layout Notice : Place as close
L32 chip as possible.
+LAN_REGOUT 1 2
2.2UH +-5% NLC252018T-2R2J-N
+3VALW +3V_LAN

2
Layout Note: LL1 must be
within 200mil to Pin36, C670 C671
CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
J3

1
200mil to LL1 X5R
+LAN_REGOUT: Width 1 2
=60mil 1 2
U26
JUMP_43X79

@
13 PCIE_PRX_DTX_P4 C672 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P4 22 31
HSOP LED3/EEDO LAN_SK_LINK#
LED1/EESK 37 LAN_SK_LINK# 40
13 PCIE_PRX_DTX_N4 C673 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N4 23 40 LAN_ACTIVITY# LAN_ACTIVITY# 40 Rising time (10%~90%)1mS <Rising time <100mS
HSON LED0
17 30 R563 2 1 10K_0402_5% +LAN_VDD10 +LAN_EVDD10
13 PCIE_PTX_C_DRX_P4 HSIP EECS
18 32 R564 2 1 10K_0402_5%
13 PCIE_PTX_C_DRX_N4 HSIN EEDI
2 1 Close to Pin 12,27,39,42,47,48
0_0603_5% L33

2
16 1 LAN_MDI0+
13 CLKREQ_LAN# CLKREQB MDIP0 LAN_MDI0+ 40
2 LAN_MDI0- C674 C675
MDIN0 LAN_MDI0- 40 +3V_LAN
25 4 LAN_MDI1+ 1U_0402_6.3V4Z 0.1U_0402_16V4Z
13,16,21,33,41,43,46 PLT_RST# LAN_MDI1+ 40

1
PERSTB MDIP1 LAN_MDI1-
MDIN1 5 LAN_MDI1- 40
19 7 LAN_MDI2+
13 CLK_PCIE_LAN REFCLK_P NC/MDIP2 LAN_MDI2+ 40
20 8 LAN_MDI2- Close to Pin 21 1 2
13 CLK_PCIE_LAN# REFCLK_N NC/MDIN2 LAN_MDI2- 40
10 LAN_MDI3+ 0.1U_0402_16V4Z C676
NC/MDIP3 LAN_MDI3+ 40
11 LAN_MDI3- 1 2
NC/MDIN3 LAN_MDI3- 40
LAN_X1 43 0.1U_0402_16V4Z C677
C CKXTAL1 C
1 2
LAN_X2 44 13 +LAN_VDD10 0.1U_0402_16V4Z C678
CKXTAL2 DVDD10
DVDD10 29 1 2
41 0.1U_0402_16V4Z C679
DVDD10 +3V_LAN +LAN_VDDREG
43 LAN_WAKE# 28 LANWAKEB 1 2
14,33 PCIE_WAKE# 1 R567 2 0_0402_5% 0.1U_0402_16V4Z C680
@ ISOLATEB 26 27 +3V_LAN 2 1 1 2
ISOLATEB DVDD33 0_0603_5% L34 0.1U_0402_16V4Z C681
DVDD33 39

2
14 12 +3V_LAN C682 C683
NC/SMBCLK AVDD33
2 R568 1 10K_0402_5% 15 42 4.7U_0603_6.3V6K 0.1U_0402_16V4Z

1
NC/SMBDATA AVDD33
+3V_LAN 1 R569 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 X5R
AVDD33 48

ENSWREG 33 ENSWREG
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 VDDREG Close to Pin 3,6,9,13,29,41,45
35 VDDREG AVDD10 3 +LAN_VDD10
6 +LAN_VDD10
AVDD10
AVDD10 9
1 2 46 45 +3VS +3V_LAN 1 2
R570 2.49K_0402_1% RSET AVDD10 0.1U_0402_16V4Z C684
24 36 +LAN_REGOUT 1 2
GND REGOUT

1
49 0.1U_0402_16V4Z C685
PGND R571 R572 1 2
1K_0402_1% 0_0402_5% 0.1U_0402_16V4Z C686
RTL8111F-CGT_QFN48_6x6 1 2
0.1U_0402_16V4Z C687

2
ISOLATEB ENSWREG 1 2
0.1U_0402_16V4Z C688
SA00004Y700 1 2
R574 0.1U_0402_16V4Z C689
B R573 B
0_0402_5% 1 2
15K_0402_5% @ 0.1U_0402_16V4Z C690

Y4
4 3 LAN_X2
NC OSC
LAN_X1 1 2 H: Enable internal Regular
OSC NC
1
L: Disable
1 25MHZ_12PF_X3G025000DC1H~D C692
15P_0402_50V8J
C691 2
15P_0402_50V8J
2 SJ10000B700

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019JH A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 24, 2012 Sheet 39 of 48
5 4 3 2 1
5 4 3 2 1

SP050006F00
UL1 CL1
0_0402_5%
1 TCT1 MCT1 24 2 1 1 2
LAN_MDI0+ short@ RL1 75_0402_1% RJ45_MIDI0+
39 LAN_MDI0+ 2 TD1+ MX1+ 23
D
39 LAN_MDI0- LAN_MDI0- 3 22 CL2 RJ45_MIDI0- D
TD1- MX1- 0_0402_5%
4 TCT2 MCT2 21 2 1 1 2
LAN_MDI1+ 5 20 short@ RL2 75_0402_1% RJ45_MIDI1+
39 LAN_MDI1+ TD2+ MX2+
39 LAN_MDI1- LAN_MDI1- 6 19 CL3 RJ45_MIDI1-
TD2- MX2- 0_0402_5%
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI2+ 8 17 short@ RL3 75_0402_1% RJ45_MIDI2+
39 LAN_MDI2+ TD3+ MX3+
39 LAN_MDI2- LAN_MDI2- 9 16 CL4 RJ45_MIDI2-
TD3- MX3- 0_0402_5%
10 TCT4 MCT4 15 2 1 1 2
LAN_MDI3+ 11 14 short@ RL4 75_0402_1% RJ45_MIDI3+
39 LAN_MDI3+ TD4+ MX4+
39 LAN_MDI3- LAN_MDI3- 12 13 RJ45_MIDI3-
TD4- MX4-

RJ45_GND1 2

1
SUPERWORLD_SWG150401
CL5 CL8
Place CL5 colse 0.01U_0402_16V7K 1000P_1206_2KV7K
2

to LAN chip

C C

DC231111211
D20
For EMI's request LAN Conn.
AZC099-04S.R7G_SOT23-6 CL7 68P_0402_50V8J
LAN_MDI1+ 1 4 LAN_MDI0+ 2 1
I/O1 I/O3
JLAN1
LAN_SK_LINK# 2 1 LAN_SK_LINK#_R 11
39 LAN_SK_LINK# Green LED-
2 5 RL7
GND VDD 330_0402_5% RL6 1
+3V_LAN 2 0_0402_5% 12 Green LED+
short@
RJ45_MIDI3- 8
LAN_MDI0- LAN_MDI1- PR4-
3 I/O2 I/O4 6
RJ45_MIDI3+ 7 PR4+
RL5,RL7 Vendor recommand 510 ohm RJ45_MIDI1- 6
D23 PR2-
AZC099-04S.R7G_SOT23-6 RJ45_MIDI2- 5
LAN_MDI2+ LAN_MDI3+ PR3-
1 I/O1 I/O3 4
RJ45_MIDI2+ 4 PR3+
For EMI's request
RJ45_MIDI1+ 3 PR2+
2 GND VDD 5
CL6 68P_0402_50V8J RJ45_MIDI0- 2
B PR1- B
2 1 SHLD2 14
RJ45_MIDI0+ 1
LAN_MDI3- LAN_MDI2- PR1+
3 I/O2 I/O4 6 SHLD1 13
LAN_ACTIVITY# 2 1 LAN_ACTIVITY#_R 10
39 LAN_ACTIVITY# Yellow LED-
RL5
330_0402_5% RL8 1 2 0_0402_5% 9
short@ Yellow LED+
+3V_LAN SANTA_130451-0L

D20/D23 ME@

1'S PN:SC300001G00
2'S PN:SC300002E00

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019JH A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 24, 2012 Sheet 40 of 48
5 4 3 2 1
A B C D E

Mini-Express Card for WLAN/WiMAX(Half) +3VS

+1.5VS
BT Connector
Mini-Express Card(WLAN/WiMAX)

2
JUMP_43X79
J4
0131 remove BT

2
+3VS_WLAN
+3VS_AOAC
PN:SP07000LL00 @ +3VS_AOAC

1
R548 100K_0402_5%
2 1

1
JMIN1
43 WLAN_WAKE# 1 1 2 2
R528 1 @ 2 0_0402_5% WLAN_ACT_R 3 4
WLAN_ACT 3 4
12 PCH_WLBT_OFF_5# R540 1 2 0_0402_5% BT_OFF#_R 5 6
WLAN_CLKREQ# 5 6
1 13 WLAN_CLKREQ# 7 7 8 8 1
9 9 10 10 11/09 add AOAC function.
13 CLK_PCIE_WLAN1# 11 11 12 12
13 CLK_PCIE_WLAN1 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 RF_OFF# 43
21 22 PLT_RST#
21 22 PLT_RST# 13,16,21,33,39,43,46
13 PCIE_PRX_DTX_N2 23 23 24 24
13 PCIE_PRX_DTX_P2 25 25 26 26
27 27 28 28
29 30 SMB_CLK_S3
29 30 SMB_CLK_S3 10,11,13,44
31 32 SMB_DATA_S3
13 PCIE_PTX_C_DRX_N2 31 32 SMB_DATA_S3 10,11,13,44
13 PCIE_PTX_C_DRX_P2 33 33 34 34
35 35 36 36 USB20_N10 16
+3VS_WLAN 37 38
37 38 USB20_P10 16
39 39 40 40
41 41 42 42
43 43 44 44
100_0402_1% 45 46
R542 45 46
47 47 48 48
EC_TX_P80_DATA 11/09 add AOAC function.
43,46 EC_TX_P80_DATA
EC_RX_P80_CLK
1
1
2
2
49
51
49 50 50
52
For AOAC assessment
43,46 EC_RX_P80_CLK 51 52
R543
100_0402_1% 53 54
GND1 GND2
17 PCH_WLBT_OFF_51# 2 1

R383 ACES_51700-0520W-001 +VSB +3VALW +3VS_AOAC

2
1K_0402_5% For EC to detect
R544 ME@ @
debug card 100K_0402_5% R5197 1 2 0_0805_5%

1
insert.
R5198

D
470K_0402_5% 6

S
AOAC@ 1 5 4
2 2
C5238 2

2
1U_0402_6.3V6K 1 Q2413
AOAC@ SI3456DDV-T1-GE3_TSOP6

G
2 AOAC@
AOAC enable +3VS_AOAC always ON

3
R5199
AOAC disable +3VS_AOAC same +3VS WLAN_EN 1 2
0_0402_5%
Mini-Express Card for WWAN/mSATA(Full)

1
AOAC@

1
D 1
43 AOAC_WLAN 2
+3VS G R5200 C5239
Q2414 S 1.5M_0402_5% .1U_0603_25V7K
Mini-Express Card(WWAN 3G) 2N7002K_SOT23-3 AOAC@ 2 AOAC@

2
AOAC@
2

JUMP_43X79 +3VS_WWAN
J6
2

1
+3VS_WWAN
1

@
C702 C700 @ C42
PN:SP07000LL00
1

10U_0805_10V4Z 10U_0805_10V4Z 47P_0402_50V8J

2
JMIN2
1 2 +1.5VS
1 2
3 3 4 4
5 5 6 6
7 8 +UIM_PWR
7 8 UIM_DATA
9 9 10 10
11 12 UIM_CLK
11 12 UIM_RST
13 13 14 14
15 16 UIM_VPP
15 16 D17 @
17 17 18 18
19 20 R547 1 2 0_0402_5% CM1293-04SO_SOT23-6
19 20 3G_OFF# 17
10/07 P23 B+ 21 22 PLT_RST# @
SATA_DTX_IRX_P2_R 21 22 UIM_DATA +UIM_PWR
23 23 24 24 1 CH1 CH4 4 2 1
3 SATA_DTX_IRX_N2_R 25 26 R546 3
P25 B- 25 26 10K_0402_5%
27 27 28 28
P32 A- 29 30 SMB_CLK_S3 +3VS
SATA_ITX_DRX_N2_R 29 30 SMB_DATA_S3
31 31 32 32 2 Vn Vp 5
SATA_ITX_DRX_P2_R 33 34
P33 A+ 33 34
35 35 36 36 USB20_N9 16
37 37 38 38 USB20_P9 16
+3VS_WWAN 39 40 3 6
39 40 CH2 CH3 +3VS
41 41 42 42
17 3G_DET# 43 44 DAN217T146_SC59-3
43 44 JSIM1
45 45 46 46 40mil 3
47 48 4 1 +UIM_PWR 1
47 48 +1.5VS UIM_VPP GND VCC UIM_RST
49 49 50 50 5 VPP RST 2 2
17 mSATA_DET# mSATA_DET# 51 52 UIM_DATA 6 3 UIM_CLK
51 52 I/O CLK

4.7U_0805_10V4Z
7 @ D18
DET
53 GND1 GND2 54
1

C703
1

1
C701 C704 @ C45
ACES_51700-0520W-001 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J 8 C705
2

ME@ 9/5 GND 0.1U_0402_16V4Z


9

2
GND

+3VS
TAITW_PMPAT6-06GLBS7N14H0
2

+3VS ME@
R677 C47 47P_0402_50V8J
4.7K_0402_5% UIM_RST 1 2

C699 C48 @ 47P_0402_50V8J


1

0.01U_0402_16V7K UIM_CLK 1 2
2

U25 C706
0.1U_0402_16V4Z R559 R560 PN:SP07000LM00 C49 @ 47P_0402_50V8J
7 6
U25
2

EN VCC 4.7K_0402_5% 4.7K_0402_5% UIM_DATA


4
18 CAD VCC 10 1 2 4
SATA_ITX_DRX_P2_CONN 1
VCC 16
20
@ @
1'S TI : SA00003P100 @
12 SATA_ITX_DRX_P2_CONN
1

SATA_ITX_DRX_N2_CONN AINP VCC


12 SATA_ITX_DRX_N2_CONN
0.01U_0402_16V7K
2 AINM
9
RF
C707 SATA_DTX_IRX_N2 PA
12 SATA_DTX_C_IRX_N2 2 1 4 BOUTM PB 8
2 1 SATA_DTX_IRX_P2 5
12 SATA_DTX_C_IRX_P2 C698 BOUTP C776 2
AOUTP 15 SATA_ITX_DRX_P2_C 1 0.01U_0402_16V7K SATA_ITX_DRX_P2_R
0.01U_0402_16V7K 3 14 SATA_ITX_DRX_N2_C C775 2 1 0.01U_0402_16V7K SATA_ITX_DRX_N2_R
GND AOUTM
13
17
GND
GND BINP 11 SATA_DTX_IRX_P2_C
SATA_DTX_IRX_N2_C
C840 2
C841 2
1 0.01U_0402_16V7K SATA_DTX_IRX_P2_R
Security Classification Compal Secret Data Compal Electronics, Inc.
19 GND BINM 12 1 0.01U_0402_16V7K SATA_DTX_IRX_N2_R Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
21 EP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
TI_SN75LVCP412ARTJR_QFN20_4X4~D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 41 of 48
A B C D E
5 4 3 2 1

+3VS REMOTE1+
TOP DDR3
Close U30 Fintek thermal sensor 1

1
C

1
1
REMOTE1+
+3VS placed near by TOP PCH R642
C759
2200P_0402_50V7K
2
B
Q46
MMST3904-7-F_SOT323-3
@ 2 E
10K_0402_5%

3
C760 @ REMOTE1-
2200P_0402_50V7K U30

2
2 REMOTE1-

1 10 EC_SMB_CK2
D VDD SMCLK EC_SMB_CK2 13,21,43 D
REMOTE1+ EC_SMB_DA2
REMOTE2+
2 DP1 SMDATA 9 EC_SMB_DA2 13,21,43
REMOTE2+
TOP WWAN

2
1 REMOTE1- 3 8 1
DN1 ALERT#

1
C763 R649 C
C761 0.1U_0402_16V4Z REMOTE2+ 4 7 1 2 MAINPWON 43,49,50,52 C762 2 Q47

1
2200P_0402_50V7K DP2 THERM# 2200P_0402_50V7K B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 0_0402_5% @ 2 E
5 6

3
DN2 GND REMOTE2-
@

F75303M MSOP10
REMOTE1,2+/-:
Address 1001_101xb Trace width/space:10/10 mil
TOP VRAM & CPU CORE Trace length:<8"

FAN +5VS DROOP


+5VS
C764 10U_0603_6.3V6M
1 2
C C
+5VS
U4
1 VEN GND 8

1
2 VIN 7 D7
+VCC_FAN1 GND 1SS355TE-17_SOD323-2
3 VO GND 6
43 EN_DFAN1 1 2 EN_DFAN1_R 4 VSET GND 5 @
R53 1
100_0402_5% G996P11U_SO8 D8

2
C56 1 2 @
2200P_0402_50V7K +3VS BAS16_SOT23-3
2
C59 1 2 1U_0603_10V4Z

1
C46 1 2 0.1U_0402_16V4Z
R632
10K_0402_5% 40mil
+3VS JFAN1

2
+VCC_FAN1 1 1
43 EC_TACH 2 2
1 43 EC_FAN_ID 3 3
4 4
1

C58 5
1000P_0402_50V7K G5
6 G6
R616 2
10K_0402_5% ACES_50273-00401-001
@
2

EC_FAN_ID ME@

B
SP02000U900 B

APS G-Sensor
+3VS
1

Q39 SI2301BDS-T1-E3_SOT23-3 R479


100K_0402_5%
S

3 1 U28 R5062
2

56K_0402_5%
1

VOUTX
G

2 12 2 1 GS_VOUTX 43

0.1U_0402_16V7K

0.1U_0402_16V7K
43 GS_SELFTEST
2

C732 R601 ST Xout VOUTY


Yout 10 2 1 GS_VOUTY 43
0.1U_0402_16V4Z 0_0603_5% +3VS +3VS_GS 8 VOUTZ
2

Zout

0.1U_0402_16V7K

0.1U_0402_16V7K
@ short@ R606 R5061

1
R607 150K_0402_5% 1 2 14 56K_0402_5% C734 C735
Vs

1
1

2 1 0_0603_5% 15 Vs
0.1U_0402_16V7K

2
1

C739 0.01U_0402_16V7K +3VS_GS C736 1 C777 C774

2
NC
1

10U_0603_6.3V6M

1 2 NC 4
1

C737 3 9
2

COM NC
10U_0603_6.3V6M

@ R633 5 11
COM NC
1

C738 10K_0402_5% 6 13
2

@ COM NC
7 16
2

@ COM NC @
2

A APS_GND A

R605 C733 LIS34ALTR_LGA16_4X4 2 1

GS_ON# APS_GND 4/8 update footprint for U22 2MM J12


43 GS_ON# 2 1 1 2
APS_GND
150K_0402_5% 0.01U_0402_16V7K

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 42 of 48
5 4 3 2 1
+3VALW +3VEC +3VLP Vcc 3.3V +/- 5%
@ @

2 1 2 1 J18 : Close
R2210 100K +/- 1%
Non - LID S4 Board ID R2213 VAD_BID min V AD_BID typ VAD_BID max
2MM J18 2MM J19 J19 : Open
Logo_LED# 31,46 0 0K +/- 5% 0 V 0 V 0 V SDV
L2201 1 2 0_0603_5% J18 : Open
+3VEC +EC_AVCC
LID S4 J19 : Close 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V FVT

C2203

0.1U_0402_16V4Z

C2204

0.1U_0402_16V4Z

C2205

0.1U_0402_16V4Z

C2206

0.1U_0402_16V4Z

C2208

1000P_0402_50V7K

C2207

1000P_0402_50V7K
1 1
C2201 C2202 18K +/- 5%
0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 1 1
+EC_AVCC 2 0.436 V 0.503 V 0.538 V FVT2
3 33K +/- 5% 0.712 V 0.819 V 0.875 V SIT

1
2 2
L2202 1 2 2 2 2 2 2 D
2 0_0603_5% ECAGND
Logo_LED Q30 56K +/- 5%
2
G 2N7002K_SOT23-3
4 1.036V 1.185V 1.264V SVT

111
125
22
33
96

67
S

9
U2201 +3VALW

3
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
1 21 EC_MUTE# R2202 1 2 10K_0402_5%
17 GATEA20 GATEA20/GPIO00 GPIO0F +3VEC
KB_RST# 2 23 BEEP#
17 KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# 38
12,45 SERIRQ 3 SERIRQ GPIO12 26 WLAN_WAKE# 41
4 27 ACOFF
12,45,46 LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF 49,51
LPC_AD3 5 HDD_DETECT# R2204 1 2 100K_0402_5%
12,45,46 LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output
12,45,46 LPC_AD2 LPC_AD2
LPC_AD1 8 63 BATT_TEMP LID_SW# R2203 1 2 100K_0402_5%
12,45,46 LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP 50
LPC_AD0 10 LPC & MISC 64
12,45,46 LPC_AD0 LPC_AD0 GPIO39 GS_VOUTX 42
C2209 1 2 22P_0402_50V8J R2201 1 2 10_0402_5% 65
ADP_I/GPIO3A ADP_I 50,51
CLK_PCI_EC 12 AD Input 66
16 CLK_PCI_EC CLK_PCI_EC GPIO3B GS_VOUTY 42 +3VLP
PLT_RST# 13 75 BRDID
13,16,21,33,39,41,46 PLT_RST# PCIRST#/GPIO05 GPIO42
R2205 1 2 330K_0402_5% EC_RST# 37 76
+3VEC EC_RST# IMON/GPIO43 IMVP_IMON 57
EC_SCI# 20 +3VALW
17 EC_SCI# EC_SCII#/GPIO0E
1 38 Turbo_V R2206 1 2 47K_0402_5%
50 ADP_PROTECT GPIO1D
C2210 68
DAC_BRIG/GPIO3C TBT_OK2GO2SX 33

1
0.1U_0402_16V4Z 70 EN_DFAN1
EN_DFAN1/GPIO3D EN_DFAN1 42
DA Output 71 R2210
2 IREF/GPIO3E AOAC_WWAN
KSI0 55 72 MUXLESS_STAT R2215 1 2 0_0402_5% 100K_0402_1%
KSI0/GPIO30 CHGVADJ/GPIO3F DGPU_PWROK 17,48,56 +5VALW
KSI1 56
KSI2 KSI1/GPIO31
57

2
KSI3 KSI2/GPIO32 EC_MUTE# USB_ON# R2209 1
58 KSI3/GPIO33 EC_MUTE#/GPIO4A 83 EC_MUTE# 38 2 10K_0402_5% BRDID
KSI4 59 84 USB_ON#
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# 37,46

1
KSI5 60 85
KSI5/GPIO35 CAP_INT#/GPIO4C AOAC_WLAN 41 +5VS
KSI6 61 PS2 Interface 86 R2213
KSI6/GPIO36 EAPD/GPIO4D TBT_RESET# 33
KSI7 62 87 TP_CLK 56K_0402_5%
KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK 44
KSO0 39 88 TP_DATA T21 PAD~D TP_CLK R2211 1 2 4.7K_0402_5%
KSO[0..15] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 44
KSO1 40 @
44 KSO[0..15]

2
KSO2 KSO1/GPIO21 TP_DATA R2212 1
41 KSO2/GPIO22 2 4.7K_0402_5%
KSI[0..7] KSO3 42 97
44 KSI[0..7] KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 CPU1.5V_S3_GATE 9
KSO4 43 98 BATT_TEMP C2211 1 2 100P_0402_50V8J
KSO4/GPIO24 WOL_EN/GPXIOA01 VGA_AC_DET 21,56
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 99
NTC_V
ME_FLASH 12
ACIN C2212
0417 change to SVT ID
45 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 109 NTC_V 50 1 2 100P_0402_50V8J
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27 SA_PGOOD C2510
47 KSO8/GPIO28 1 2 0.1U_0402_10V6K
KSO9 48 119
T22 KSO9/GPIO29 SPIDI/GPIO5B M_PWR_ON 19,53
@ KSO10 49 120
PAD~D KSO10/GPIO2A SPIDO/GPIO5C PCH_SLPA# 14
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 TL_LED 31
1 2 PLT_RST# @ KSO12 51 128 VR_HOT# R2214 1 2 0_0402_5%
KSO12/GPIO2C SPICS#/GPIO5A RF_OFF# 41 50,57 VR_HOT# H_PROCHOT# 5
KSO13 52
C109 1U_0402_6.3V6K KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E
KSO15 54 73
KSO15/GPIO2F ENBKL/GPIO40 ENBKL 15
@ KSO16 81 74
KSO16/GPIO48 PECI_KB930/GPIO41 ADP_ID 49
V_ALW# 82 89
52 V_ALW# KSO17/GPIO49 FSTCHG/GPIO50 FSTCHG 51

1
1 2 SUSP# 90 2
BATT_CHG_LED#/GPIO52 PCH_PWR_EN# 19 D
CAPS_LED#/GPIO53 91 mSATA_DETEC# 17
EC_SMB_CK1 77 GPIO 92 H_PROCHOT#_EC 2 Q2202 C2223
50,51 EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 HDD_DETECT# 45
C2222 100P_0402_50V8J EC_SMB_DA1 78 93 G 2N7002K_SOT23-3 100P_0402_50V8J
50,51 EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 CP_RESET# 44 1
EC_SMB_CK2 79 SM Bus 95 SYSON S @
13,21,42 EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON 48,53
EC_SMB_DA2 80 121
13,21,42 EC_SMB_DA2 VR_ON 57

3
EC_SMB_DA2/GPIO47 VR_ON/GPIO57
PM_SLP_S4#/GPIO59 127 PM_SLP_S4# 14

ESD Reserve Close to EC 14 PM_SLP_S3# 6


14
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 100
101 EC_LID_OUT#
EC_RSMRST# 12,14
14 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 17
EC_SMI# 15 102
17 EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V 50
16 103 H_PROCHOT#_EC R2243 1 @ 2 0_0402_5%
31 CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT 50
17 104 MAINPWON_R R2247 1 2 0_0402_5%
44 TP_RESET GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON 42,49,50,52
18 GPO 105 BKOFF#
42 GS_ON# GPIO0C BKOFF#/GPXIOA08 BKOFF# 31
19 GPIO 106 PBTN_OUT#
16,45 ODD_DA# GPIO0D PBTN_OUT#/GPXIOA09 PBTN_OUT# 5,12,14
VSB_EN 25 107 POWER REQUEST
50 VSB_EN EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 PCH_APWROK 14
EC_TACH 28 108 SA_PGOOD
42 EC_TACH FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 SA_PGOOD 54
EC_PME# 29
EC_TX_P80_DATA EC_PME#/GPIO15
41,46 EC_TX_P80_DATA 30 EC_TX/GPIO16
EC_RX_P80_CLK 31 110 ACIN
41,46 EC_RX_P80_CLK EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN 14,46,49
PCH_PWROK 32 112 EC_ON
14 PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON 46,52
34 114 ON/OFF
42 EC_FAN_ID SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF 46
36 GPI 115 LID_SW#
42 GS_SELFTEST NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# 46
116 SUSP#
SUSP#/GPXIOD05 SUSP# 9,23,48,51,53,55,56
GPXIOD06 117 TBT_GO2SX 33
118 PECI_KB9012
PECI_KB9012/GPXIOD07
AGND/AGND

EC_RTCX1 122 R87


+3VALW R2221 1 XCLKI/GPIO5D
2 0_0402_5% SUSCLK_R +V18R 43_0402_5% +3VALW
GND/GND
GND/GND
GND/GND
GND/GND

14 SUSCLK 123 XCLKO/GPIO5E V18R 124


1 2 H_PECI 5,17
GND0

1
R2225 1 2 47K_0402_5% KSO1
R2220
1

R2227 1 2 47K_0402_5% KSO2 KB9012QF A3 LQFP 128P_14X14 1 10K_0402_5%


11
24
35
94
113

69

1 C2214
R2228 1 2 2.2K_0402_5% EC_SMB_CK1 R2223 C2213 4.7U_0805_10V4Z

2
ECAGND

100K_0402_5% 20P_0402_50V8
R2230 2
1 2 2.2K_0402_5% EC_SMB_DA1 R2222 1 2 0_0402_5% LAN_WAKE# 39
2

+3VLP R2224 1 @ 2 0_0402_5%

@
R2233 2 2.2K_0402_5% EC_SMB_CK1 EC_PME#

S
1 1 3 PCI_PME# 16
EC_RTCX1
@ Q2203
R2234 1 @ 2 2.2K_0402_5% EC_SMB_DA1 R2229 1 @ 2 10M_0402_5% SUSCLK_R 2N7002K_SOT23-3

G
+3VALW

2
Y2201
0307 reserve for power 1 2
+3VS
32.768KHZ_12.5PF_CM31532768DZFT
@
R2236 1 2 2.2K_0402_5% EC_SMB_CK2
1 1
R2237 1 2 2.2K_0402_5% EC_SMB_DA2 C2218 C2219
18P_0402_50V8J 18P_0402_50V8J
C2220 @1 2 100P_0402_50V8J EC_SMB_CK2 @ @
2 2
C2221 @1 2 100P_0402_50V8J EC_SMB_DA2
R2239 1 2 10K_0402_5% PCH_PWROK
Security Classification Compal Secret Data Compal Electronics, Inc.
Y2201: Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

P/N : SJ10000BM00 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 43 of 48
5 4 3 2 1

INT_KBD Conn.
INT_KBD Conn. IPD_LEFT C814 1 PN:SP01000YH00
2 @100P_0402_50V8J
KSI[0..7]
KSI[0..7] 43
IPD_MIDDLE C819 1 2 @100P_0402_50V8J JKB1
KSO[0..15] KSI1 1
KSO[0..15] 43 1
IPD_RIGHT C805 1 2 @100P_0402_50V8J KSI7 2
KSI6 2
3 3
KSO9 4
KSO2 C778 1 KSI4 4
2 @ 100P_0402_50V8J 5 5
KSI5 6
D
KSO15 C780 1 6 D
2 @ 100P_0402_50V8J KSO1 C779 1 2 @100P_0402_50V8J KSO0 7 7
KSI2 8
KSO6 C782 1 8
2 @ 100P_0402_50V8J KSO7 C781 1 2 @100P_0402_50V8J KSI3 9 9
KSO5 10
KSO8 C784 1 10
2 @ 100P_0402_50V8J KSI2 C783 1 2 @100P_0402_50V8J KSO1 11 11
KSI0 12
KSO13 C786 1 KSO5 KSO2 12
2 @ 100P_0402_50V8J C785 1 2 @100P_0402_50V8J 13 13
KSO4 14
KSO12 C788 1 KSI3 KSO7 14
2 @ 100P_0402_50V8J C787 1 2 @100P_0402_50V8J 15 15
KSO8 16
KSO11 C790 1 16
2 @ 100P_0402_50V8J KSO14 C789 1 2 @100P_0402_50V8J KSO6 17 17
KSO3 18
KSO10 C792 1 18
2 @ 100P_0402_50V8J KSI7 C791 1 2 @100P_0402_50V8J KSO12 19 19
KSO13 20
KSO3 C794 1 20
2 @ 100P_0402_50V8J KSI6 C793 1 2 @100P_0402_50V8J KSO14 21 21
KSO11 22
KSO4 C796 1 KSI5 KSO10 22
2 @ 100P_0402_50V8J C795 1 2 @100P_0402_50V8J 23 23
KSO15 24
KSI0 C798 1 KSI4 24
2 @ 100P_0402_50V8J C797 1 2 @100P_0402_50V8J 25 25
M1(Left BUTTON) IPD_LEFT 26
KSO0 C800 1 26
2 @ 100P_0402_50V8J KSO9 C799 1 2 @100P_0402_50V8J M2(Center BUTTON) IPD_MIDDLE 27 27
M3(Right BUTTON) IPD_RIGHT 28
KSI1 C801 1 28
2 @100P_0402_50V8J 29 29
CONN PIN define need double check 30 30
Reserve for ESD. 31 GND1
32 GND2
JAE_FL4S030HA3R3000A-DT
C ME@ C

Track point Click pad 10PIN


SP01001AL00
PN:SP01001CH00
JTP1
JTP2 1
TP_DATA2 R673 2 1
1 1 10,11,13,41 SMB_CLK_S3 1 0_0402_5% 2 2
TP_RESET 2 TP_DETECT 3
43 TP_RESET 2 +5VS 3
IPD_MIDDLE 3 TP_DATA2 4
IPD_RIGHT 3 TP_CLK2 4
4 4 5 5
IPD_LEFT 5 R674 2 1 0_0402_5% 6
5 10,11,13,41 SMB_DATA_S3 6
TP_CLK2 6 7
6 CP_RESET# 7
7 7 43 CP_RESET# 8 8
+5VS 8 TP_CLK 9 11
B 8 43 TP_CLK 9 GND B
9 TP_DATA 10 12
9 43 TP_DATA 10 GND
10 10
1

11 @ @
GND C849 C850 ACES_51522-01001-001
12 GND 100P_0402_50V8J 100P_0402_50V8J ME@
2

ACES_50524-0100N-001
ME@

+5VS

TP_CLK TP_DATA2
TP_CLK2 R660 1 @ 2 4.7K_0402_5%
TP_DATA TP_CLK2
TP_DATA2 R668 1 2 4.7K_0402_5%
@
3

TP_RESET R672 1 2 4.7K_0402_5% 2


@ D37
R211 PJDLC05_SOT23-3 D38
CP_RESET# 2 1 100K_0402_1% PJDLC05_SOT23-3
@
R671 @
0_0402_5%
TP_DETECT 2 1
1

A A

PN: SCA00000U10 X 2

Security Classification Compal Secret Data Compal Electronics, Inc.


2010/08/25 2012/08/25 Title
Issued Date Deciphered Date SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 44 of 48
5 4 3 2 1
A B C D E F G H

1 PN: SP01001CC00 TPM 1

+3VS
SATA HDD Conn.
JHDD1 TPM@
1 C589 1 2 10U_0603_6.3V6M
SATA_ITX_DRX_P0 GND U5002
12 SATA_ITX_DRX_P0 2 A+
12 SATA_ITX_DRX_N0 SATA_ITX_DRX_N0 3 1 24 C645 1 2 0.1U_0402_16V4Z
A- NC VPS TPM@ +3VS
4 GND 2 NC VPS 10
SATA_DTX_C_IRX_N0 C807 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5 3
12 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 C808 1 SATA_DTX_IRX_P0 B- NC
12 SATA_DTX_C_IRX_P0 2 0.01U_0402_16V7K 6 B+ 7 PP LPCPD# 28 2 @ 1 R680 0_0402_5%
7 27 SERIRQ
GND SERIRQ LPC_AD0 SERIRQ 12,43
6 NC LAD0 26 LPC_AD0 12,43,46
9 23 LPC_AD1
VNC LAD1 LPC_AD1 12,43,46
8 22 LPC_FRAME#
V33 LFRAME# LPC_FRAME# 12,43,46
9 4 20 LPC_AD2
+3VS V33 GND LAD2 LPC_AD2 12,43,46
10 11 17 LPC_AD3
V33 GND LAD3 LPC_AD3 12,43,46
11 GND 18 GND
43 HDD_DETECT# 12 GND NC 25
13 GND 5 NC LCLK 21 CLK_PCI_TPM 16
@ J5 14 8 19
5VS_HDD V5 VNC NC
+5VS 1 1 2 2 15 V5 12 NC NC 15
16 V5 13 NC
JUMP_43X79 17 GND 14 NC LRESET# 16 PCH_PLTRST# 5,16
18 Reserved
19 GND ST33ZP24AR28PVSH_TSSOP28
20 V12
21 24 TPM@
+5VS V12 GND
22 V12 GND 23
2 2
SANTA_196501-1
1 1
SA00005C020
1

C809 C810 C811 C812 C813 ME@


1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
2

@ 2 @ 2

PN:DC010006L00 +5VS
R164
0_0805_5% +5VS_ODD
SATA ODD Conn. @
1 2
3 3
JODD1

1 +VSB Q70
SATA_ITX_DRX_P1_CONN GND SI3456DDV-T1-GE3_TSOP6
12 SATA_ITX_DRX_P1_CONN 2 A+
12 SATA_ITX_DRX_N1_CONN SATA_ITX_DRX_N1_CONN 3 A-

D
4 6

S
GND

2
SATA_DTX_C_IRX_N1 C815 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5 5 4
12 SATA_DTX_C_IRX_N1 B-

1
1U_0402_6.3V6K
C89
SATA_DTX_C_IRX_P1 C817 1 2 0.01U_0402_16V7K SATA_DTX_IRX_P1 6 R760 2
12 SATA_DTX_C_IRX_P1 B+ 470K_0402_5% 1

G
2
7

3
ODD_DETECT#_R GND
8 DP
+5VS_ODD 9
+5VS_ODD V5
10 ODD_EN
ODD_DA#_R V5
16,43 ODD_DA# 2 1 11 MD

2
1.5M_0402_5%
R764
short@ 12 GND

1
R678 13 D
0_0402_5% GND Q71 C816
Q66 17 ODD_EN# 2
14 G 2N7002K_SOT23-3 0.1U_0603_25V7K

2
2N7002K_SOT23-3 GND
15 S

1
GND

3
SANTA_202001-3
D

12 ODD_DET# 1 3

ME@
G

@
2

13 ON_ODD_DET

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 45 of 48
A B C D E F G H
+5VALW

U35
+USB_VCCB Card Reader Sub-Board connector
1 GND VOUT 8
C773 0.1U_0402_16V4Z 2 7
VIN VOUT
2 1 3 6
USB_ON# 4 VIN VOUT
EN FLG 5 USB_OC1#
USB_OC1# 16 Card Reader (PCIE)
G547I2P81U_MSOP8
USB 2.0 (port0)

1
Low Active C772
@ 1000P_0402_50V7K

Combo Jet

2
37,43 USB_ON#

+3VLP PN:SP010014M00
+USB_VCCB

2 +3VEC

R714
100K_0402_5% JPWR1 80mils
D27
1
1

ON/OFF 1
3 ON/OFF 43 43 LID_SW# 2 2
ON/OFFBTN# 1 ACIN# 3
51_ON# 3
2 51_ON# 49 4 4
5 5
DAN202UT106_SC70-3 ON/OFFBTN# 6 6 JCR1

1
7 GND 1 1 2 2
1

D 8 3 4
D GND 3 4
2 5 6
43,52 EC_ON
EC_ON 2
G
14,43,49 ACIN
G
S Q68
ACES_88514-00601-071
ME@ CR
13 PCIE_PRX_DTX_P1
13 PCIE_PRX_DTX_N1 7
9
5
7
6
8 8
10
USB20_N2 16
USB20_P2 16 USB2.0
9 10
S Q53 2N7002K_SOT23-3 13 PCIE_PTX_C_DRX_N1 11 12 CARD_CLKREQ1# 13

3
11 12
2

2N7002K_SOT23-3 13 PCIE_PTX_C_DRX_P1 13 14 PLT_RST# 13,16,21,33,39,41,43


3

R733 ON/OFFBTN# 13 14
15 15 16 16 GNDA_S 38
100K_0402_5% 13 CLK_PCIE_CR 17 17 18 18 EXT_MIC 38
13 CLK_PCIE_CR# 19 19 20 20 HP_OUTL 38

2
21 22 HP_OUTR 38
1

D41 21 22
+3VS 23 23 24 24
PJDLC05_SOT23-3 PLUG_IN 38
25 Gnd1 Gnd2 26

ACES_88107-24001
Power Board connector ME@

1
PN:SCA00001G00

I/O Board PN:SP02000QC00

Finguer Print Board Conn.


+3VS PN:SP010014M00
JFP1
R392 2 short@ 1 0_0402_5% 3VS_FP 1
R391 2 short@ 1
16 USB20_N11 1 0_0402_5% USB20_N11_R 2 2
R390 2 short@ 1 0_0402_5% USB20_P11_R 3 USB20_N11_R
16 USB20_P11 3
4 4
5 USB20_P11_R
31,43 LOGO_LED# 5
6
+3VALW 6
USB3.0 USB 3.0 (port3)
3

7 D34
GND PJDLC05_SOT23-3
8 GND JUSB2
ACES_88514-00601-071 1
ME@ 1
2 2
16 USB3_TX3_N 3 3
16 USB3_TX3_P 4 4
5
1

5
6 6
16 USB3_RX3_N 7 7
16 USB3_RX3_P 8 8
9 9
PN:SCA00001L00 10
11
10
GND
12 GND

ACES_50463-0104A-001
ME@

JDB3 BOTTOM SIDE


+3VALW 1 1
+3VS 2
3
2 SN111005800 by ME drawing
3
12,43,45 LPC_FRAME# 4 4
12,43,45 LPC_AD3 5 5
6 2 SW4 1
12,43,45 LPC_AD2 6
12,43,45 LPC_AD1 7 7
12,43,45 LPC_AD0 8 8
PLT_RST# 9 9
16 CLK_PCI_DB 10 10
41,43 EC_TX_P80_DATA 11 13 PRECHG 4 3
11 GND 49,51,52 PRECHG SKRBAAE010_4P
41,43 EC_RX_P80_CLK 12 12 GND 14

CLK_PCI_DB ACES_85201-1205N

ME@ GND

C5109
12P_0402_50V8J
Debug Conn. @
For Power Reset

Security Classification Compal Secret Data Compal Electronics,Ltd.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title
SCHEMATIC, M/B LA-8262P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 46 of 48
FD1 FD2 FD3 FD4
1 1 1 1

PT-H 19 SCREW HOLE

H_2P3 H_4P3

H1 H2 H4 H19
HOLEA HOLEA HOLEA HOLEA
1

H_2P8

H5
HOLEA
1

H_3P2

H7 H9
HOLEA HOLEA
1

H_3P8

H11
@ HOLEA

0312 Delete All sensor parts.


1

H_4P0
H12 H13 H14 H15 H16 H17
@ HOLEA@ HOLEA@ HOLEA@ HOLEA@ HOLEA@ HOLEA
1

NON-PT-H 4 SCREW HOLE

H_3P3x2P3N H_3P2N
H20 H21
HOLEA HOLEA
1

0307 ME change to 3.2

H_2P6N

H23
HOLEA
1

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 47 of 48
A B C D E

+1.5V to +1.5VS
+5VALW TO +5VS +3VALW TO +3VS SB548000210
SB548000210 +1.5V +1.5VS

+5VALW

S
+5VS +3VALW +3VS

D
3 1
U37 U38

1
8 D Q54
S 1 8 D S 1 C824 C825 C826

G
7 D S 2 7 D S 2

2
1

1
6 D 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R694
S 3 6 D S 3

2
C827 5 D C828 C829 C830 C831 C832 470_0603_5%
2
10U_0805_10V4Z G 4 10U_0805_10V4Z 1U_0603_10V4Z R695
5 D
10U_0805_10V4Z G 4 10U_0805_10V4Z 1U_0603_10V4Z R696 SI2301BDS-T1-E3_SOT23-3 @

2
DMN3030LSS-13_SOP8L-8 470_0603_5% DMN3030LSS-13_SOP8L-8 470_0603_5%
@ @

1 2

1 2

1
1 +VSB +3VALW 1
+VSB D
D D @ 2 SUSP
1

1
@ 2 SUSP @ 2 SUSP G
R697 G R698 G Q57 S
150K_0402_5% Q55 S 470K_0402_5% Q56 S 100K_0402_5% 2N7002K_SOT23-3

3
2N7002K_SOT23-3 2N7002K_SOT23-3 R699

3
2

2
5VS_GATE2 R700 15VS_GATE_R 2 R702 1 2 R701 1 1.5VS_GATE

0.01U_0402_25V7K

0.01U_0402_25V7K
1 0_0402_5% 1
1

1
82K_0402_5%
0_0402_5%

1
D D D C836

C833

C834
SUSP 2 SUSP 2 SUSP# 2 0.1U_0603_25V7K C837

2
G 2 G 2 G 0.1U_0603_25V7K

2
S Q58 S Q59 S Q60
2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3
3

3
+RTCVCC +5VALW
+5VALW
+0.75VS

1
+1.8VS +1.5V +1.05VS @

1
R703 R704 @
100K_0402_5% 100K_0402_5% R705
1

1 R709 100K_0402_5%

2
2 22_0603_5% SUSP 2
9,55,56 SUSP

2
R706 R707 R708 SYSON#

1 2
470_0603_5% 470_0603_5% 470_0603_5% Q67 Q62

1
@ @ @ DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
1 2

1 2

1 2

D @

OUT

OUT
2 SUSP
D D D G
@ 2 SUSP @ 2 SYSON# @ 2 SUSP Q65 S 2 SYSON 2
9,23,43,51,53,55,56 SUSP# IN 43,53 SYSON IN
G G G 2N7002K_SOT23-3

GND

GND
3
Q63 S Q61 S Q64 S
2N7002K_SOT23-3 2N7002K_SOT23-3 2N7002K_SOT23-3
3

3
For Intel S3 Power Reduction.

+1.5V to +1.5VS_VGA Transfer


+1.5V +1.5VS_VGA

300mil(7.2A) J13 @
3 3
2 2 1 1
1 1
C856 JUMP_43X118 C851
10U_0805_6.3V6M 10U_0805_6.3V6M
AO4430: Rdson: 5.5mohm @ VGS=10V PX@
2 PX@ AO4430L_SO8 2

+5VALW U49 300mil(7.2A)


8 1
7 2
1

6 3

2
5 1 1
R1127 1 C853 C854 R1129 @
PX@ 100K_0402_5% C852 10U_0805_10V4Z 0.1U_0402_16V4Z 470_0603_5%

4
10U_0805_10V4Z PX@ PX@
2

2 2 PX@

1
DGPU_PWROK# PX@ 2
DGPU_PWROK# 56
1

R1126 +VSB
0_0402_5% D
2 1 2 R1130 10K_0402_5%
17,43,56 DGPU_PWROK
G PX@ 2 1 2 R783 1

1
PX@ S Q129 PX@ 0_0402_5%
2N7002K_SOT23-3 1 D @
PX@
3
1

C855 @ 2 2 R790 1 DGPU_PWROK#


0.1U_0603_25V7K G 0_0402_5%
R1128 Q127 S
1

100K_0402_5% 2 PX@ 2N7002K_SOT23-3

3
PX@ PX@ D 2 R791 @1 SUSP
2

DGPU_PWROK# 2 R782 1 2 0_0402_5%


0_0402_5% G
S Q126
4 2N7002K_SOT23-3 4
3

SUSP 2 R789 1 PX@


0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2010/08/25 Deciphered Date 2012/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, M/B LA-8262P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019JH
Date: Thursday, May 24, 2012 Sheet 48 of 48
A B C D E

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