Received 28 February 2025; revised 29 March 2025 and 14 April 2025; accepted 20 April 2025.

Date of current version 1 August 2025.

Digital Object Identifier 10.1109/OJCAS.2025.3565921

A Comparative Study of Dynamic Comparators for

Low-Power Successive Approximation ADC
FEI YUAN
Department of Electrical, Computer, and Biomedical Engineering, Toronto Metropolitan University, Toronto, ON M5B 2K3, Canada
This article was recommended by Associate Editor S. Shah.
CORRESPONDING AUTHOR: F. YUAN (e-mail: [email protected])
This work was supported by the Natural Science and Engineering Research Council of Canada.

ABSTRACT This paper provides a critical review and the classification of comparators in low-power low-
data-rate (1 kS/s∼1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs).
Both voltage-domain and time-domain comparators are studied and their pros and cons are examined.
The architecture, comparison time, and power consumption of five widely used voltage-domain dynamic
comparators are studied first. It is followed with an investigation of kickback in comparators. We show
although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converters
(DACs) of SAR ADCs arising from the different resistances of DAC switches gives rise to a differential
clock kickback that occurs earlier than output kickback with more strength hence dictating kickback in
dynamic comparators. If the strength and duration of clock kickback are sufficiently large, the comparator
will yield an erroneous output. The dependence of clock kickback on the input of SAR ADCs in the least
significant bit (LSB) conversion is also investigated. The offset voltage of the dynamic comparators and
its dependence on supply voltage are investigated, and the minimum tuning bits of digitally tuned offset
compensation capacitor arrays is obtained. The noise of dynamic comparators is also investigated and
design trade-offs between noise, power consumption, kickback, and the loading of the comparator on DAC
are examined. The extensive simulation results of the comparators designed in a TSMC 130 nm 1.2 V
CMOS technologies with reduced supply voltages and analyzed using Spectre from Cadence Design
Systems with BSIM 3.3 device models are provided.

INDEX TERMS Successive approximation register analog-to-digital converter, voltage-domain comparator,

and time-domain comparator.

I. INTRODUCTION array DACs where a set of bridged small binary-weighted

LTHOUGH the distinct characteristics of succes- capacitor arrays jointly function as a large binary-weighted
A sive approximation register analog-to-digital converters
(SAR ADCs) including low power consumption and good
capacitor array without large capacitors [8], [9], [10],
and energy-efficient capacitor-switching schemes such as
technology compatibility make them ideal candidates for monotonic capacitor switching where only one capacitor
power-constrained applications [1], [2], [3], [4], the power down-switching per bit conversion is needed [11], [12], [13],
consumption of these ADCs rises exponentially with resolu- input-range adaptive capacitor switching [14], and by-pass
tion, as observed in Fig. 1. The power consumption of a SAR window capacitor switching [15], to name a few. The
ADC is dictated by the power consumption of its digital-to- power consumption of voltage-domain comparators rises
analog converter (DAC), comparator, and SAR. The power rapidly with resolution due to the need for large input
consumption of the DAC can be minimized using top-plate transistors to minimize both the noise and offset voltage of
sampling where the most significant bit (MSB) is deter- the comparators and a pair of digitally tuned capacitor arrays
mined by comparing the inputs of the comparator directly for offset voltage compensation. The power consumption of
without capacitor switching [5], [6], [7], staged capacitor time-domain comparators also rises sharply with resolution


c 2025 The Authors. This work is licensed under a Creative Commons Attribution 4.0 License.
For more information, see https://creativecommons.org/licenses/by/4.0/
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TABLE 1. Breakdown of the power consumption of reported low-power low-data-rate

SAR ADC.

FIGURE 1. Walden figure-of-merit (FoM) and power consumption of low-power SAR

ADC with data rate in the range of 1 kS/s ∼ 1.5 MS/s (data collected from literature in
the last decade).

because the voltages to be compared need to propagate

through a large number voltage-controlled delay stages in
order to generate a large time variable whose polarity
can be determined using an arbiter without difficulty.
As the power consumption of the comparator constitutes
approximately 30% of the overall power consumption of
SAR ADC, as evidenced in Table 1, reducing the power
consumption of the comparator without sacrificing resolution
is pivotal in minimization of the overall power consump-
tion of SAR ADC. To reduce the power consumption of
comparators while continuing to improve resolution, various
architectures of voltage-domain comparators emerged. These
architectures include static comparators [16], [17], semi-
dynamic comparators [18], [19], fully dynamic comparators
with an explicitly clocked latch [6], [20], [21], [22],
[23], [24], [25], [26] or an implicitly clocked latch [27],
[28], [29], [30], [31]. Time-domain comparators to combat
the difficulties encountered in design of low-power high-
resolution voltage-domain comparators also emerged. These
comparators include voltage-controlled delay line (VCDL)
comparators [8], [9], [32], [33], voltage-controlled oscillator
(VCO) comparators [34], [35], [36], and edge-pursuit com- FIGURE 2. Voltages and power consumption of semi-dynamic comparator [18].
parators [37], [38]. An in-depth examination of the pros and Circuit parameters used in simulation: VDD = 0.6 V, Vb = 400 mV, Vinp = 399 mV,
Vinn = 400 mV, Wn = 0.32 μm, Wp = 0.96 μm, and L = 0.13 μm.
cons of these comparators, though critical to the design of
low-power SAR ADC, however, is absent.
This paper provides a comparative study of voltage-
comparators. The former perform the comparison of two
domain dynamic comparators for low-power low-data-rate
voltages directly in the voltage domain whereas the latter
high-resolution SAR ADC [39]. The remainder of the
map the two voltages to be compared to a time variable first
paper is organized as follows: Section II provides an
and then determine the polarity of the time variable in the
overview and the classification of comparators in SAR
time domain.
ADC. The architectures of voltage-domain and time-domain
comparators are studied with an emphasis on the pros and
cons of these comparators. The comparison time and power A. VOLTAGE-DOMAIN COMPARATORS
consumption of dynamic comparators are investigated in Voltage-mode comparators can be loosely classified into
Sections III and IV, respectively. Section V investigates (i) static comparators, (ii) semi-dynamic comparators, and
kickback in dynamic comparators. Section VI studies the (iii) fully dynamic comparators. A static comparator consists
offset voltage of dynamic comparators. Section VII deals of a pre-amplifier followed by a regenerative latch, both are
with the noise of dynamic comparators. The paper is static [16], [17]. These comparators enjoy a low kickback
concluded in Section VIII. from the output, accredited to the isolation provided by the
pre-amplifier between the input and output of the comparator.
II. COMPARATORS IN LOW-POWER SAR ADC: A REVIEW Static comparators, however, are not particularly suitable for
Comparators encountered in SAR ADC can be loosely power-constrained applications due to their non-zero static
classified into voltage-domain comparators and time-domain power consumption.

242 VOLUME 6, 2025

FIGURE 3. Dynamic comparator with 3b offset voltage compensation [24].

A semi-dynamic comparator consists of a static pre-

amplifier and a clocked (dynamic) latch [18], [19]. An
example of such comparators is shown in Fig. 2. The static
FIGURE 4. Impact of the width of input transistors on the power consumption of
pre-amplifier provides both the amplification of the voltages dynamic comparator in Fig. 3 at (a) rising edge and (b) falling edge (bottom). Circuit
to be compared and the isolation between the latch and parameters: VDD = 0.6 V, Wn = 0.32 μm, Wp = 0.96 μm, L = 0.13 μm, A3 · · · A1 =000,
B3 · · · B1 =000, the dimensions of offset cancellation nMOS capacitors C1 , C2 , and C3
the input. The clocked operation of the latch is needed are 1 μm × 1 μm, 2 μm × 1 μm, and 2 μm × 2 μm, respectively, Vinp = 299 mV, and Vinn
to remove the memory of the latch. Without the clocked = 300 mV. The number of the fingers of the input transistors M1/2 of the pre-amplifier
is varied from 1 to 2.
operation, the state of the latch cannot be altered by the small
voltage swing of the output of the pre-amplifier. Similar to
static comparators, semi-dynamic comparators are also less evidenced in Fig. 4. (ii) The impact of the offset voltage is
attractive for power constrained applications due to the non- typically minimized using a pair of digitally tuned capacitor
zero static power consumption of both the pre-amplifier and arrays residing at the internal nodes of the comparator with
the latch, as evidenced in Fig. 2. the size of the capacitor arrays and their unit capacitance
Power efficiency can be further improved by clocking both set by the offset voltage. As these capacitors are charged
the pre-amplifier and latch. The latch can be clocked either / discharged during the operation of the comparator, they
explicitly by the clock or implicitly by the output of the pre- consume a non-negligible amount of dynamic power, as
amplifier. An example of such comparators with an implicitly evidenced in Fig. 5. The area consumption of these capacitor
clocked latch is shown in Fig. 3 [24]. These comparators are arrays is another costly overhead. The fact that offset
hereafter referred to as fully dynamic comparators or simply compensation is only needed when approaching the LSB
dynamic comparators. Fig. 4 shows the implicitly clocked (least significant bit) conversion suggests that the offset
latch stage will consume power after the assertion of the compensation should be disabled in upper-bit conversions
clock and its power consumption will end once regeneration and activated only in lower-bit conversions to reduce power
is completed. consumption. (iii) Kickbacks from the clock and the output
The pre-amplifier and latch of a dynamic comparator of the latch impact the minimum signal that the comparator
can be either cascaded or stacked. The former are termed can detect. Clock kickback often dictates not only because
two-stage dynamic comparators [6], [20], [21], [22], [23], clock injection node is typically more close to the input
[24], [25], [26] whereas the latter are referred to as single- nodes of the comparator but also because clock kickback
stage dynamic comparators [27], [28], [29], [30], [31]. strikes earlier than output kickback, as evidenced in Fig. 6.
Single-stage dynamic comparators are more power-efficient Kickback can cause the polarity of Vdiff = Vinp −Vinn to differ
as compared with their two-stage counterparts, accredited from that before kickback. If the amplitude and duration of
to the reuse of the current of the pre-amplifier by the polarity-inverted Vdiff are sufficiently large, the latch will
latch. yield an erroneous output. In the example studied here, no
A number of challenges exist in design of low-power high- erroneous output is produced by kickback. This is because
resolution dynamic comparators: (i) The input transistors of the duration of polarity-inverted Vdiff is small and the latch
these comparators need to be sufficiently large in order to is implicitly clocked. Should an explicitly clocked latch is
lower the noise and offset voltage of the comparators. This, used, the comparator will likely yield an erroneous output,
however, is at the expense of more power consumption, as as to be seen in Section V.

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FIGURE 6. Kickbacks in the dynamic comparator in Fig. 3. Vin+ = 401 mV, Vin− =
400 mV, Rinp = 1 k, and Rinn is varied from 1 k to 5 k. Circuit parameters are the
same as those in Fig. 3 with A3 · · · A1 = 000 and B3 · · · B1 = 000.

FIGURE 5. Impact of offset compensation capacitor arrays on the power

consumption of dynamic comparator in Fig. 3. Legends: Dashed line: A3 · · · A1 = 000
and B3 · · · B1 = 000. Solid line: Dashed line: A3 · · · A1 = 000 and B3 · · · B1 = 111.

these comparators is their long conversion time measured

from the time at which CLK=1 is asserted to the time
B. TIME-DOMAIN COMPARATORS at which the outputs are generated. The large number of
Time-domain comparators emerged as a viable archi- the voltage-controlled delay stages needed to yield a large
tecture to combat the challenges encountered in design gain also makes it difficult to lower area consumption. The
of low-power high-resolution voltage-domain compara- mismatch between the two voltage-controlled delay lines, the
tors. These comparators can be loosely classified into accumulation of timing errors arising from device noise and
(i) voltage-controlled delay line (VCDL) comparators [8], mismatch between the stages of the same delay line, and the
[9], [32], [33], (ii) voltage-controlled oscillator (VCO) metastability window of the arbiter set the minimum signal
comparators [34], [35], [36], and (iii) edge-pursuit com- that these comparators can detect. It is important to note
parators [37], [38]. that although a large amount of dynamic power is consumed
VCDL comparators use a pair of VCDLs, each composed at the assertion of CLK=1 and the toggling of the arbiter,
of a set of cascaded voltage-controlled delay stages, to map a the delay stages also consume a non-negligible amount of
small differential voltage whose polarity is to be determined dynamic power, as evidenced in Fig. 9.
to a large time variable whose polarity is the same as that As compared with VCDL comparators, voltage-controlled
of the differential voltage and can be determined using a ring oscillator comparators minimize area consumption and
generic arbiter. An example of such comparators is shown mismatch-induced timing errors by using a pair of identical
in Fig. 8 [8]. The resolution of these comparators is dictated voltage-controlled ring oscillators performing both voltage-
by the gain of the VCDL, which is set by the number of to-time conversion and time accumulation. An example
the voltage-controlled delay stages, the width of the current- of such comparators is shown in Fig. 10. Both DFFs
sourcing pMOS / current-sinking nMOS transistors, and the functioning as band-bang phase detectors are reset by RST (a
metastability window of the arbiter. A notable drawback of narrow pulse) initially such that EOC (End of Comparison)

244 VOLUME 6, 2025

 FIGURE 9. Voltages and power consumption the VCDL comparator in Fig. 8. Circuit
parameters: VDD = 0.6 V, Vinp = 299 mV, Vinn = 300 mV, Wn = 0.32 μm, Wp = 0.96 μm,
L = 0.13 μm.

FIGURE 10. VCO comparator [34], [43]. Static DFFs are used for bang-bang phase
FIGURE 7. Kickbacks in the dynamic comparator in Fig. 3. Vin+ = 401 mV, Vin− =
detection.
400 mV, Rinp = 1 k, and Rinn is varied from 1 k to 5 k. Circuit parameters are the
same as those in Fig. 3 with A3 · · · A1 = 000 and B3 · · · B1 = 000.

FIGURE 11. Voltages and power consumption of VCO comparator in Fig. 10. Circuit
parameters: VDD = 0.6 V, Wn = 0.32 μm, Wp = 0.96 μm, L = 0.13 μm. Case 1: Vin = 1 mV
(Vinp = 301 mV and Vinn = 300 mV). Case 2: Vin = 2 mV (Vinp = 302 mV and Vinn =
FIGURE 8. VCDL comparator [8] with a self-reset arbiter. 300 mV).

is zero, enabling the oscillation of the oscillators. RST also oscillation cycles before DFF1 can be triggered. Similarly if
resets the oscillators and the inputs of the phase detectors Vinp < Vinn , Vxp will lag Vxn . Once the time between Vxp
such that any phase difference between Vxp and Vxn after and Vxn exceeds the metastability window of DFF2, Von =1
the assertion of RST is solely due to the difference between will be asserted. Fig. 11 shows the comparison process with
Vinp and Vinn . If Vinp > Vinn , Vxp will lead Vxn . Once the two different inputs.
time between Vxp and Vxn exceeds the metastability window It is evident that VCO comparators offer a virtually
of DFF1, Vop =1 will be asserted, resulting EOC=1 and unlimited gain while the gain of VCDL comparators is
oscillation will be terminated. If the difference between Vinp finite. VCO comparators are area-efficient as compared with
and Vinn is small, the oscillators will need to complete more their VCDL counterparts especially when the resolution of

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TABLE 2. Performance comparison of recently reported low-power low-data-rate

SAR ADC (Abbreviations: dyn.: dynamic. stg.: stage).

comparators is high. The minimum input signal of a VCDL

comparator is set by the timing errors caused by the noise
and mismatch of the voltage-controlled delay stages, the
mismatch between the VCDLs, the gain of the VCDLs,
and the metastability window of the arbiter while that of a
VCO comparator is lower bound by timing errors caused by FIGURE 12. (a) Single-stage dynamic comparator (comparator 1) [27], [28], [50] and
(b/c/d) two-stage dynamic comparators (comparator 2 [24], comparator 3 [51],
the noise and mismatch of the stages of the oscillators, the comparator 4 [6], and comparator 5 [52], [53]). A pair of static buffers are employed at
mismatch of the oscillators, and the metastability window the output nodes.

of the DFFs. The conversion time of a VCDL comparator

is set by the delay of the VCDL and is fixed while that of
a VCO comparator is rather input-dependent specifically it drops along with the progress of bit conversion, the gain of
will be small if the input is large and large if the input is the VCDL also drops even though a larger gain is desired in
small. VCO comparators are more power-efficient as fewer lower-bit conversions. VCO comparators also suffer from a
oscillation cycles will be needed if the input is large. To number of drawbacks. For example, the conversion time of
further improve power efficiency and eliminate the impact of VCO comparators is input-dependent and exceedingly large
mismatch between the oscillators of VCO comparators, edge- for a small input.
pursuit comparators that only have one voltage-controlled Table 2 compares the performance of recently reported
ring oscillator and one arbiter emerged [38], [44]. low-power SAR ADCs. It is seen that the resolution
As compared with voltage-domain comparators, time- of SAR ADC with a dynamic comparator is generally
domain comparators offer a number of attractive advantages. limited to 10b. The figure-of-merit (FoM) of these ADCs is
For example, the resolution of time-domain comparators is generally low, indicating that they are particularly suitable
only lower bounded by the timing errors caused by noise for power-constrained applications. For this reason, we focus
and mismatch and the metastability of the arbiters. These on dynamic comparators in this study. In what follow
comparators are composed of simple voltage-controlled delay we investigate the comparison time, power consumption,
stages and logic gates, hence offering excellent technology kickback, offset voltage, and noise of dynamic comparators.
compatibility. Time-domain comparators are also free of
clock kickback, as to be seen in Section V. Despite of III. COMPARISON TIME
these intrinsic advantages, time-domain comparators suffer Fig. 12(a) is perhaps the most widely used single-stage
from a number of inherent drawbacks. For example, a large dynamic comparator [27], [28], [50]. In the reset phase
number of voltage-controlled delay stages are needed in where CLK=0, Vop , Von , Vop1 , and Von1 are pulled to
VCDL comparators in order to provide a sufficiently large VDD to remove the memory of the latch. The removal of
gain for detecting a small input. The transfer characteristics the current path from VDD to the ground eliminates static
of voltage-controlled delay stages are highly sensitive to power consumption of the comparator during CLK=0. In
PVT uncertainty. Mismatch between the voltage-controlled the following comparison phase where CLK=1, the input
delay lines and that between the stages of the same delay transistors are activated, allowing Vop1 and Von1 to drop
line detrimentally impact the resolution. The gain of VCDL from their initial voltage VDD at rates set by gm1,2 Vinp and
comparators is also impacted by the common-mode voltage gm1,2 Vinn , respectively where gm1,2 is the transconductance
of the input voltages. For SAR ADC with top-plate sampling, of the input transistors. Vop and Von are then set as per
since the common-mode component of the input voltages Vop1 and Von1 in a regenerative fashion. Once regeneration

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 FIGURE 14. Impact of supply voltage on the instantaneous power consumption of
comparator 4. Circuit parameters are given in the caption of Fig. 13.

is the time measured from the threshold-crossing of CLK

to that of the output of the comparator, on supply voltage
VDD and input voltage Vin . It is seen comparator 3 offers
the shortest comparison time while comparator 1 has the
longest comparison time. These observations echo our
earlier qualitative assessment of the comparison time of the
FIGURE 13. Comparison of the comparison time, average power consumption of
dynamic comparators in Fig. 12 at TT/27o C. Vinp = VDD /2 + Vin and Vinn = VDD /2.
comparators. Also observed is that comparison time rises
Top-left: Vin = 1 mV. Top-right: Vin = 100 μV. Bottom-left: Vin = 10 μV. Comparator 3 exponentially with the reduction of VDD . Further the smaller
fails at VDD = 0.7 V and Vin = 10 μV. Bottom-right: Comparator 5 with a nMOS or a MIM
dynamic biasing capacitor, Vin = 100 μV, and VDD = 0.6 V. Input transistors: Wn =10
the input, the longer the comparison time as more time
μm. All other transistors: Wn = 1 μm and Wp = 3 μm. L = 0.13 μm. is needed to discharge the internal nodes from their initial
voltage of VDD before the latch can be activated. Fig. 13
(bottom-right) compares the delay of comparator 5 with
is completed, no current path will exist from VDD to the its dynamic biasing capacitor implemented using a nMOS
ground thereby eliminating any static power consumption capacitor and a MIM capacitor. It is seen the delay of the
in post-regeneration. The comparator is power-efficient not comparator with a dynamic biasing MIM capacitor is orders
only because power is only consumed during regeneration, of magnitude smaller as compared with that with a nMOS
the same current is used by both the latch and the input capacitor. To minimize the delay, a MIM capacitor, though
transistors during regeneration. The comparator suffers from area-inefficient as compared with its nMOS counterpart,
a long comparison time because regeneration will start only should be used. Also observed is that the larger the dynamic
after Vop1 or Von1 drop to VDD − VT from their initial value biasing capacitor, the smaller the delay. It approaches 3.3
VDD and the speed of regeneration is set by the common- ns, the delay of comparator 4.
mode current of the input transistors.
Comparators 2-5 shown in Fig. 12 are four popular two- IV. POWER CONSUMPTION
stage dynamic comparators [6], [24], [26], [52]. Similar Comparators in Fig. 12 consume dynamic power at the rising
to comparator 1, these comparators only consume dynamic and falling edges of CLK. At the falling edge of CLK,
power during output regeneration and consume no static the capacitors at nodes on1 and op1 are charged to VDD ,
power upon the establishment of the latch. The latch of consuming fCLK Cint VDD2 where Cint is the capacitance at
comparator 2 is clocked implicitly by the output of the Von1 and Vop1 . The capacitor at the source of the input
pre-amplifier. It suffers from a long comparison time as in 2
transistors is also charged to VDD , consuming fCLK Css VDD
the comparison phase where CLK=1, the latch will gain its where Css is the capacitance at the source of the input
supply voltage and undergo regeneration only after Vop1 or transistors. At the rising edge of CLK, the capacitors at
Von1 drop sufficiently. Comparator 3 improves comparison nodes on1 and op1 discharge from their initial voltage VDD
time, accredited to the immediate presence of the supply and the capacitor at the source of the input transistors
voltage of the latch after the assertion of CLK=1. Comparator also discharge from its initial voltage VDD , both consuming
4 also suffers from a long comparison time as regeneration dynamic power. The latch also consumes dynamic power.
will only start once Vop1 or Von1 drop sufficiently. A common Fig. 14 shows the instantaneous power of comparator 4 at
drawback of comparators 2-4 is that capacitors at the drain of the rising and falling edges of CLK with supply voltage
the input transistors that were charged to VDD during CLK=0 swept from 0.4 V to 0.8 V. The average power consumption
discharge for the entire duration of CLK=1 even though of the comparators is shown in Fig. 15(a). It is seen that
their discharge is only needed until the start of regeneration. the higher the supply voltage, the higher the average power
Comparator 5 improves power efficiency by terminating the consumption. This echoes Fig. 14. Also observed is that
discharge process of the capacitors once the regeneration of comparator 1 consumes the least amount of the average
the latch starts. power, echoing our earlier qualitative assessment of the
Fig. 13 (top-left, top-right, bottom-left) plots the depen- power efficiency of the comparators. The power consumption
dence of the comparison time of the comparators, which of comparators 3/4/5 is rather comparable. Comparator 2

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FIGURE 15. (a) Average power consumption of dynamic comparators in Fig. 12.
(b) Impact of the capacitance of the dynamic biasing capacitor on the average power
consumption of comparator 5. The period of clock: 100 μs.

FIGURE 16. Kickbacks in a dynamic comparator.

FIGURE 17. Impact of DAC impedance asymmetry on clock kickback in comparator

1 with DAC+ and DAC- preceding the comparator represented by their Thevenin
consumes the most power due to its highest transistor count. equivalents (DAC+: Vin+ ∼ Rinp pair. DAC-: Vin− ∼ Rinn pair). Vin+ = 401 mV and Vin− =
400 mV. (a) Rinn is varied from 1 k to 5 k and Rinp = 1 k. (b) Rinp is varied from 1 k
Fig. 15(b) plots the impact of the dynamic biasing capacitor to 5 k and Rinn = 1 k. VDD = 0.6 V.
on the average power consumption of comparator 5. It is
seen the larger the dynamic biasing capacitor, the higher
the average power consumption. Also, the higher the supply large buffer. The transition of the clock is therefore sharper
voltage, the higher the average power consumption. as compared with that of the output. Clock kickback thus
contains more high-frequency components as compared with
V. KICKBACK output kickback. Since the impedance of kickback paths is
Kickback in the dynamic comparator of a SAR ADC is the low for high-frequency signals, more clock is coupled to the
transient glitch of the gate voltage of the input transistors input nodes.
caused by the coupling of either the source voltage of the Although the clock is coupled to the input nodes via two
input transistors at the start of comparison where clock is identical paths, since the amount of clock kickback depends
asserted hereafter referred to as clock kickback or the drain upon the impedance looking into the DAC from the gate of
voltage of the input transistors during output regeneration the input transistors of the comparator, clock kickback will be
henceforth referred to as output kickback, as shown Fig. 16. common-mode if the output impedance of DAC+ and that of
The amplitude of the kickback-induced transient glitch of the DAC− are the same and differential if the output impedance
input can exceed the actual input voltage of the comparator of DAC+ and that of DAC- differ. Fig. 17 plots the key
with the opposite polarity, causing the comparator to yield signals of comparator 1 with DAC+ and DAC- represented by
an incorrect output. Kickback impacts the minimum voltage their Thevenin equivalent circuits. It is seen Vinp and Vinn will
that the comparator can sense subsequently the resolution of dip by the same amount if Rinp = Rinn and different amounts
SAR ADC. if Rinp = Rinn . Also, the larger the difference between Rinp
Output kickback is differential as the outputs are differen- and Rinn , the severer the clock kickback. In Fig. 17(a), clock
tial and they couple to the input nodes via two separate but kickback has no impact on the output of the comparator as it
identical paths. Output kickback is often of a less concern does not change the polarity of the input of the comparator
as compared with clock kickback for the following reasons: whereas in Fig. 17(b), clock kickback changes the polarity
(i) The outputs of the comparator couple to the input nodes of the input. It will cause the comparator to yield an incorrect
via Cgd , as seen in Fig. 12. Clock kickback, on the other output if the amplitude and duration of clock kickback are
hand, couple to the input nodes via Cgs . Since Cgs > Cgd , sufficiently large.
clock kickback path has a smaller impedance. (ii) Output In Fig. 18(a), the length of the tail transistor of the
kickback occurs during the regeneration of the output that comparator is changed from 0.13 μm to 2 μm so that the
takes place after the assertion of the clock at which clock time constant of the common-source node of the comparator
kickback takes place. Output kickback therefore occurs after is increased. It is seen that the increased time constant of
clock kickback. (iii) Clock signal is typically provided by a the common source node suppresses clock kickback. No

248 VOLUME 6, 2025

 FIGURE 19. 8b SAR ADC with top-plate sampling.

FIGURE 18. Impact of (a) the channel length of the tail transistor and (b) the shunt
capacitor on clock kickback in comparator 1. Circuit parameters: Vin+ = 401 mV and Vin−
= 400 mV. Rinp is varied from 1 k to 5 k and Rinp = 1 k. VDD = 0.6 V.

error exists at the output of the comparator. In Fig. 18(b), a

6 pF shunt nMOS capacitor (dimensions: 20 μm ×24 μm) FIGURE 20. Resistance of DAC switches. Circuit parameters: Wn = 0.32 μm, Wn =
is added at the drain of the tail transistor. This added shunt 0.96 μm, L = 0.13 μm, and VR = 40 mV.
capacitor also suppresses clock kickback and no error is
observed at the output of the comparator. A comparison of
Fig. 17 and Fig. 18 shows these two kickback suppression are the threshold voltage of nMOS and pMOS transistors,
techniques have no impact on comparison time. Increasing respectively to ensure the switches operate in triode such that
the length of the tail transistor is preferred over adding a not only their channel resistance is small, their drain-source
shunt capacitor due to its better area / power-efficiency. voltage is also small. Fig. 21 plots the channel resistance of
To investigate the impedance asymmetry of DAC+ and M2+ and M1-. Since M2+ of DAC+ operates in triode, it
DAC-, consider the 8b SAR ADC with top-plate sampling has a small channel resistance and the resistance decreases
shown in Fig. 19 where reference voltage VR is set to the full- with a rising VDD slowly. The operation of M1- of DAC-
scale-range value of the differential input. D+ −
k and Dk , k = is VR -dependent, specifically it will operate in triode with
1, 2, . . . , 8 are initialized to 0 in the sample-and-hold (S/H) a small channel resistance if VR is small and sub-threshold
phase preceding bit conversions such that the bottom plate with a large channel resistance if VR is large. Also observed
+
of DAC capacitors is connected to VR . Input voltages Vin is that the smaller VDD , the larger the difference between
−
and Vin are sampled by the S/H with bootstrapped sampling the channel resistance of M2+ of DAC+ and that of M1- of
switches and the sampled input voltages are held by the DAC-. DAC+ and DAC- thus exhibit impedance asymmetry
capacitors of DAC+ and DAC-, respectively [54]. D+ 8 and especially when VDD is low. Fig. 20 compares the resistance
D−8 are determined directly from the sampled input voltages of the switches with VR = 40 mV and VDD = 0.6 V.
without any DAC capacitor switching whereas the remaining Kickback is most critical in LSB conversion where the
bits are determined from the down-switching of one capacitor input of the comparator is the smallest. Consider the special
per bit, specifically the bottom plate of capacitor Ck+ will case where D+ k =1 for k = 8, 7, . . . , 2 and assume VINP <
be switched from VR to the ground if Vinp > Vinn while VINN at the start of LSB conversion, as shown in Fig. 22.
keeping Ck− unchanged. Similar operations will be performed Since all switches in DAC+ are in triode while those in
on Ck− if Vinn > Vinp . Fig. 20 shows two widely used DAC- are in sub-threshold, the difference between R+ DAC and
DAC switches. SW1 should be used if VR > |VTp | while R−DAC is maximized subsequently the worst the kickback. If
SW2 should be used if VDD − VR > VTn where VTn and VTp kickback causes the polarity of the input of the comparator

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YUAN: COMPARATIVE STUDY OF DYNAMIC COMPARATORS

FIGURE 21. Channel resistance of M2 of DAC+ and that of M1 of DAC- at TT/27o C FIGURE 24. Kickback in LSB conversion of 8b SAR ADC of Fig. 22 with comparator
with Dk+ = VDD / Dk− =0. Transistor size: W1,2 = 1 μm and L = 0.13 μm. 2.

FIGURE 25. Kickback in LSB conversion of 8b SAR ADC with comparator 3.

+
FIGURE 22. Kickback in LSB with D8,7,...,2 = 1 and VINP < VINN at the start of LSB
conversion. If no kickback is present, comparator will yield COMP+ = 0 subsequently
+
D1 = 0. If kickback causes VINP > VINN and the duration of the polarity-inverted input of
the comparator is sufficiently long, comparator will yield COMP+ = 1 subsequently
D1+ =1.

FIGURE 26. Kickback in LSB conversion of 8b SAR ADC with comparator 4.

D+ + +
8 D7 , . . . D2 is 1100000, 1100000, 1110000, and 1100000,
respectively. Since the difference between RINP and RINN is
smaller at D+ + +
8 D7 , . . . D2 =111000, as compared with that at
+ + +
D8 D7 , . . . D2 =110000, comparator 3 has the least kickback
FIGURE 23. Kickback in LSB conversion of 8b SAR ADC with comparator 1. VDD = whiles comparators 1, 2, and 4 have comparable kickback.
0.8 V, VR = 400 mV, and unit capacitance of DAC: C = 26 fF (the minimum-size MIM
capacitor of TSMC 130 nm, dimensions: 4 μm × 4 μm) DAC voltages before LSB
Fig. 27 investigates kickback in the VCO comparator of
conversion : VINP =400 mV and VINN = 403.125 mV. Note  VDAC = VR/28 = 3.125 mV.D+8 Fig. 10. It is seen when the impedance asymmetry of the
D+7 . . .D+2 is varied from 1111111 to the value at which comparators yield a correct
output.
DAC preceding the comparator exists, although kickback
asymmetry will exist, it will have no impact on the output
of the comparator. This is because transient kickback has
to change its polarity and the duration of the polarity- no impact on the accumulated delay of the oscillators
inverted input is sufficiently long, the comparator will yield subsequently the output of the comparator. This is the distinct
an incorrect output. As D+ k , k = 8, 7, . . . , 2, varies with characteristic of VCO comparators that is not shared by their
the input of the ADC, the difference between RINP and voltage-mode counterparts.
RINN also varies with the input of the ADC. Kickback is
thus input-dependent. Figs. 23-26 compare the dependence VI. OFFSET VOLTAGE
of the kickback in comparators 1-4 on D+ + +
8 D7 , . . . D2 in LSB The input offset voltage of the comparator of a SAR ADC
conversion. Comparators 1-4 will yield a correct output when rises mainly from the mismatch of the input transistors

250 VOLUME 6, 2025

 FIGURE 29. Impact of the width of the input transistors of comparator 1 on its input
offset voltage.

FIGURE 27. Kickback in VCO comparator. (a) Rinn is varied from 1 k to 5 k and
Rinp = 1 k. (b) Rinp is varied from 1 k to 5 k and Rinn = 1 k. Vin+ = 301 mV and Vin−
= 300 mV.

FIGURE 30. Comparator 1 with a pair of digitally tuned capacitor arrays for offset
voltage compensation.

comparator is mismatch-free. Let the gate-source voltage of

the input transistors be VGS + Vos,W/L and VGS . Neglecting
the 2nd-order terms, one can show
W 2Vos,W/L
IDS ≈ kn (VGS − VT )2 . (2)
L VGS − VT
Equating (1) and (2) yields

IDS  W
FIGURE 28. Vos of comparator 1 is determined by varying Vos that is placed across
Vos,W/L = L
. (3)
the input nodes of the comparator while monitoring the number of the erroneous
output of the comparator in Monte Carlo simulation with 100 samples.
gm W L
Eq. (3) shows increasing W/L lowers Vos,W/L , as evidenced
in Figs. 28 and 29. Increasing W also increases power
of the comparator [50]. It must be no larger than , the consumption and worsens the loading impact of the input
quantization error of the ADC. The impact of the mismatch capacitance of the comparator on the DAC. Note the gate
of the input transistors can be represented by an input offset capacitance of the input transistors varies with the gate.
voltage Vos,W/L . Let the aspect ratio of the input transistors voltage, as shown in Fig. 31. It is low and stable in
be WL and L +  L with  L  L where  L denotes
W W W W W
sub-threshold where Vgs is small, rises in transition from
the dimension mismatch of the input transistors. Assume the sub-threshold to saturation where Vgs increases, and is large
input transistors operate in saturation with transconductance and stable in saturation. It can be shown the input offset
gm and DC channel current IDS . The difference between voltage due to threshold voltage mismatch VT of the input
the channel current of the input transistors caused by the transistors is given by Vos,VT = VT .
dimension mismatch is given by Consider comparator 1 shown in Fig. 12(a). For conve-
 
W nience, it is redrawn in Fig. 30 with offset compensation
IDS = kn  (VGS − VT )2 , (1) capacitor arrays added and capacitors at some key nodes
L
shown. Capacitors at both the internal nodes and output
where kn = 12 μn Cox , μn the mobility of free electrons, and nodes, denoted by Cint and Cout , respectively are charged to
Cox the gate capacitance per unit area. Now consider the VDD during CLK=0. Upon CLK=1, Cint starts to discharge,

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YUAN: COMPARATIVE STUDY OF DYNAMIC COMPARATORS

FIGURE 31. Dependence of the gate capacitance of a nMOS transistor on its gate
voltage. Circuit parameters: VDD = 0.6 V, L = 0.13 μm, and W is varied from 5 μm to 25
μm.

FIGURE 33. Input offset voltage Vos of dynamic comparators with

Vinp = 0.5VDD + Vos , Vinn = 0.5VDD , and VDD = 0.8 V. Vos is swept from 1 mV to 13 mV
with a step of 3 mV. Input transistors of comparators: Wn = 10μm. Monte Carlo
(mismatch and process): 100 samples.

input transistors is infinite, the input offset voltage of the

comparators due to latch mismatch is obtained from
Vlatch
Vos,latch = . (5)
gm1,2 ro1,2
With ro1,2  1/gm3,4 typically, the impact of the mismatch
FIGURE 32. Input offset voltage due to latch mismatch.
of the latch in comparators 2-5 is smaller as compared with
that in comparator 1 and therefore not of a critical concern
as well.
causing von1 and vop1 to drop. During the initial discharge
The impact of Vos is typically minimized using a pair
process of Cint , vGS3,4 < VT holds and the latch remains
of digitally tuned MOS capacitor arrays placed at the
inactive. A further discharge of Cint results in vGS3,4 ≥ VT ,
internal nodes of the comparator as shown in Fig. 30 so that
activating M3/4. M3/4 in this case operate in saturation
they do not load the DAC. The input offset voltage after
as vGS3,4 = VDD − VT and vDS3,4 = VDD − VT hence
compensation is given by
satisfying saturation condition vDS3,4 > vGS3,4 − VT . Once
M3/4 conduct, Cout will start to discharge and vop and von Vos, w/o cal.
Vos, w/ cal. = , (6)
will start to drop. Once they drop below VDD − VT (assume 2N
VTn = |VTp | = VT for simplicity), M5/6 will start to conduct where N is the number of the tuning bits of the capacitor
and regeneration is activated. Note the turn-on order of M3 arrays. Since Vos, w/ cal. <  is required, we obtain the min-
and M4 sets the direction of regeneration subsequently the imum number of the tuning bits of the offset compensation
output of the comparator. The impedance looking into the capacitor arrays
latch after the turn-on of M3/4 is 1/gm3,4 approximately and  
Vos, w/ cal.
small. Although Cint is present at the drain of M1/2, the Nmin = 1.44 ln . (7)
impedance at the drain of M1/2 is dictated by 1/gm3,4 . 
The mismatch of the latch with its impact represented by Fig. 33 plots the number of the erroneous output of the
Vlatch in Fig. 32 affects both the start and direction of the dynamic comparators with Vinp = 0.5VDD + Vos , Vinn =
regeneration of the latch. Since the gain from the inputs to
g
0.5VDD , and VDD = 0.8 V. It is seen comparators 1/2/3 have
the internal nodes is given by gm1,2 ( gm3,4
1
||ro1,2 ) ≈ gm1,2
m3,4
as comparable input offset voltages while comparator 4 has
gm3,4  ro1,2 , we obtain the input offset voltage due to latch
1 the smallest offset voltage. Fig. 34 plots the number of the
mismatch erroneous output of dynamic comparators with VDD =0.5 V
  while other parameters are the same as those in Fig. 33. It
gm3,4
Vos,latch = Vlatch . (4) is seen the input offset voltage of comparators 1/2/4 remains
gm1,2 approximately the same as that with VDD =0.8 V while that
Since the input transistors of the comparator are typically of comparator 3 deteriorates from 13 mV to 19 mV.
larger as compared with those of the latch, gm1,2  gm3,4
holds. As a result, the impact of the mismatch of the VII. NOISE
latch is greatly suppressed and typically not of a critical The minimum signal that a dynamic comparator can detect
concern [50]. For comparators 2-5 in Fig. 12, since the is set by the thermal noise and flicker noise of the transistors
impedance looking into the latch from the drain of the of the comparator. Consider comparator 1 in Fig. 30. During

252 VOLUME 6, 2025

 the approach of [50], [55], [56]. To simplify analysis, we
neglect the thermal noise deposited onto Cint by the pull-up
transistors M7-10 during CLK=0. Since
dvon1  
Cint = − IDS + gm vinp , von1 (0− ) = VDD , (9a)
dt

dvop1
Cint = −(IDC + gm vinn ), vop1 (0− ) = VDD , (9b)
dt
where IDC is the common-mode or DC current of the input
transistors and gm1,2 = gm , integrating (9a) and (9b) over
[0, t] and noting vinp and vinn remain unchanged during the
bit determination where CLK=1, we arrive at
 
FIGURE 34. Input offset voltage Vos of dynamic comparators with IDC gm t
Vinp = 0.5VDD + Vos , Vinn = 0.5VDD , VDD = 0.5 V, and other parameters the same as
von1 = VDD − t+ vinp , (10a)
those used in Fig. 33.
Cint Cint
 
CLK=1 where the comparison of the input voltages is IDC gm t
vop1 = VDD − t+ vinn . (10b)
performed, the noise of the tail transistor gated by CLK Cint Cint
enters the input transistors as a common-mode disturbance. Substrating (10a) from (10b) yields
Its impact is suppressed by the differential signaling of
the comparator. Pull-up pMOS transistors M7-10 are off gm t  
vop1 − von1 = vinp − vinn (11)
and there is no noise from these transistors during CLK=1. Cint
They, however, inject thermal noise to Cint and Cout during from which we obtain the gain of the comparator in
CLK=0. The latch is off initially with no noise from the amplification mode
transistors of the latch. It will switch on when VGS3,4 > VT
gm t
at which the nMOS transistors of the latch will operate in Av = . (12)
saturation. M3/4 exhibit both thermal noise and flicker noise Cint
whose power in frequency range f is given by i2t3,4 = The duration of the amplification mode of the comparator,
4kTγ gm3,4 f and =
i2f3,4
Kf IDS3,4
f
respectively where k = denoted by τamp , is the time from the assertion of CLK=1
f
to the time at which von1 drops from VDD to VDD − VT
1.38 × 10−23 J/K is Boltzmann’s constant, T is temperature
(assume vinp > vinn ). Evaluating (10a) at t = τamp and
in degrees Kelvin, γ is a process-dependent thermal noise
noting gm vinp  IDC especially when approaching the most-
parameter, Kf is a process-dependent flicker noise parameter,
significant-bit (MSB), we arrive at
and f is frequency. The power of the thermal noise and
flicker noise of the input transistors M1/2 are given by IDC
K I VDD − VT = VDD − τamp (13)
i2t1,2 = 4kTγ gm1,2 f and i2f1,2 = f DS1,2 f f respectively. Cint
Since gm1,2  gm3,4 as the width of the input transistors are from which we obtain
typically much larger as compared with that of the transistors
of the latch and noting IDS1,2 = IDS3,4 = IDS , we arrive at Cint
τamp = VT . (14)
i2t1,2  i2t3,4 and i2f1,2 = i2f3,4 . The power of the total thermal IDC
noise current and that of the total flicker noise current of It follows from (12) and (14)
the input transistors are given by gm
Av = VT . (15)
i2t ≈ i2t1,2 = 4kTγ gm1,2 f . (8a) IDS
2Kf IDS The output noise due to the thermal noise of the input
i2f = i2f1,2 + i2f3,4 = f . (8b) transistors, denoted by v2no,t , is obtained from
f
The impact of the noise on the output of the comparator   t 2  t 
1 2
is only of a concern in the time interval from the assertion v2no,t = it dt ×2= 2 i2t dt . (16)
Cint 0 Cint 0
of CLK=1 at which Cint starts to discharge from VDD to
the start of the regeneration of the latch at which VGS3,4 = Note constant ‘2’ accounts for the noise of both input
VDD − VT . This is because once regeneration is launched, transistors and Ito’ isometry formula was utilized in (16).
noise will have no impact on the direction of regeneration Making use of (8a), we arrive from (16)
subsequently the output of the comparator. The comparator
8kTγ gm t
in this case operates in amplification mode [50]. To find the v2no,t = 2
f . (17)
gain of the comparator in amplification mode, we follow Cint

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YUAN: COMPARATIVE STUDY OF DYNAMIC COMPARATORS

Evaluating (17) at t = τamp , we obtain the power of the

input-referred thermal noise of the comparator
  
v2no,t 4kTγ VGS − VT
v2t = 2 = f . (18)
Av Cint VT
Eq. (18) shows increasing the width of the input transistors
increases Cint subsequently lowers v2t . Also observed is that
increasing VGS worsens v2t and increases power consumption.
Let us now focus on the flicker noise of the input
transistors. Following the same approach as that for the
thermal noise, one can show that the power of the output
noise due to the flicker noise of the input transistors, denoted
by v2no,f , is given by
2 Kf IDS t
v2no,f = 2
f . (19)
Cint f FIGURE 35. [h]Impact of the width of the input transistors on the output of
comparator 1 at TT/0.6V/27o C with clock frequency fCLK = 100 kHz and only the noise
Evaluating (19) at t = τamp , we obtain the power of the of the input transistors accounted. Circuit parameters: Vinp = 450 mV + 150 μV, Vinn =
450 mV. Input transistors: Wn = 10μm. All other transistors: Wn = 0.32μm,
input-referred flicker noise Wp = 0.96μm, and L = 0.13 μm. Transient noise: fmax = 1.12 GHz, fmin = 100 kHz, and
100 iterations.
v2no,f Kf (VGS − VT )2 f
v2f = = . (20)
A2v Cint 2VT f
VIII. CONCLUSION
Eq. (20) shows increasing the width of the input transistors
A critical review and the classification of comparators in
lowers v2f . low-power low-data-rate SAR ADCs were presented. Both
The preceding analysis of the offset voltage and noise of voltage-domain and time-domain comparators were studied
the comparator shows the mismatch of the latch will impact and their pros and cons were examined. The architecture,
the input offset voltage of the comparator after the latch is comparison time, and power consumption of five widely
activated. The impedance at the drain of the input transistors used voltage-domain dynamic comparators were studied
in this case is dictated by the resistance looking into the first. It was followed with an investigation of kickback in
source of the nMOS transistors of the latch and is small. these comparators. We showed although clock kickback is
The noise of the input transistors impacts the input-referred common-mode, the impedance asymmetry of the DAC of
noise of the comparator before the latch is activated. The SAR ADCs arising from the different resistances of DAC
impedance at the drain of the input transistors in this case switches gives rise to a differential clock kickback that occurs
is dictated by Cint . earlier than output kickback with more strength and hence
To quantify the impact of the thermal noise and flicker dictates the kickback in dynamic comparators. If the strength
noise of the input transistors of comparator 1, fmin and fmax and duration of clock kickback are sufficiently large, the
are needed in transient noise simulation. Since the impact of comparator will yield an erroneous output. The dependence
the noise of the input transistors is only of a concern from of clock kickback on the input of SAR ADC in LSB
the assertion of CLK = 1 to the time at which Vop and Von conversion was also investigated. The offset voltage of the
start to depart, which is approximately 1.4 ns, as shown in dynamic comparators and its dependence on supply voltage
Fig. 35(a), we have f−3dB ≈ 1.4×10 1
−9 = 0.714 GHz form were investigated, and the minimum tuning bits of digitally
which we obtain fmax = 2 f-3dB = 1.12 GHz. Note π2 is
π
tuned offset compensation capacitor arrays were obtained.
the noise bandwidth factor. Since the lowest frequency in The noise of dynamic comparators was also investigated.
the comparator is fCLK = 100 kHz, we set fmin = fCLK . The noise of dynamic comparators can be reduced by
Simulation results show when an input-referred noise-voltage increasing the width of the input transistors at the price
that is less than 150 μV is applied, errors will exist at the of more power consumption, worsening clock kickback,
output of the comparator even with a large number of the and the increased loading impact of the comparator on the
fingers of the input transistors. Fig. 35 plots the output of DAC.
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[44] H. Zhuang, C. Tong, X. Peng, and H. Tang, “Low-power, low- FEI YUAN received the B.Eng. degree in electri-
noise edge-race comparator for SAR ADCs,” IEEE Trans. VLSI Syst., cal engineering from Shandong University, Jinan,
vol. 28, no. 12, pp. 2699–2707, Dec. 2020. China, in 1985, and the M.A.Sc. degree in
[45] M. Liu, P. Harpe, R. van Dommele, and A. van Roermund, “A 0.8V chemical engineering and the Ph.D. degree in
10b 80kS/s SAR ADC with duty-cycled reference generation,” in electrical engineering from the University of
Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2015, Waterloo, Waterloo, ON, Canada, in 1995 and
pp. 1–3. 1999, respectively.
[46] F. Yaul and A. Chandrakasan, “A 10 bit SAR ADC with From 1985 to 1989, he was a Lecturer with the
data-dependent energy reduction using LSB-first successive approxi- Department of Electrical Engineering, Changzhou
mation,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2825–2834, Institute of Technology, Jiangsu, China. He was
Dec. 2014. a Visiting Faculty with the Humber College of
[47] Z. Fu and K. Pun, “An SAR ADC switching scheme with MSB Applied Arts and Technology, Toronto, ON, Canada, and the Lambton
prediction for a wide input range and reduced reference voltage,” College of Applied Arts and Technology, Sarnia, ON, Canada, in 1989.
IEEE Trans. VLSI Syst., vol. 26, no. 12, pp. 2863–2872, Dec. 2018. From 1989 to 1994, he was with Paton Controls Ltd., Sarnia, as a
[48] C. Wulff and T. Ytterdal, “A compiled 9-bit 20-MS/s 3.5-fJ/conv.step Controls Engineer, where he designed distributed process control systems
SAR ADC in 28-nm FDSOI for Bluetooth low energy receivers,” for petrochemical processes worldwide. Since 1999, he has been with
IEEE J. Solid-State Circuits, vol. 52, no. 7, pp. 1915–1926, Jul. 2017. the Department of Electrical, Computer, and Biomedical Engineering,
[49] Y. Kim and C. Yoo, “A 100-kS/s 8.3-ENOB 1.7-μW time-domain Toronto Metropolitan University (formerly Ryerson University), Toronto,
analog-to-digital converter,” IEEE Trans. Circuits Syst. II, Exp. Briefs, where he is currently a Professor. He served as the Chair with the
vol. 61, no. 6, pp. 408–412, Jun. 2014. Department of Electrical, Computer, and Biomedical Engineering from 2010
[50] B. Razavi, “The strongARM latch,” IEEE Solid-State Circuits Mag., to 2015 and the Director of Quality Assurance, Faculty of Engineering and
vol. 7, no. 2, pp. 12–17, Jun. 2015. Architectural Science from 2015 to 2021. He is the Author of Injection-
[51] D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, Locking in Mixed-Mode Signal Processing (Springer, 2019), an Editor
“A double-tail latch-type voltage sense amplifier with 18 ps setup+hold of Low-Power Circuits for Emerging Applications in Communications,
time,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, Computing and Sensing (CRC Press, 2018), an Editor and a Lead Co-Author
2007, pp. 314–605. of CMOS Time-Mode Circuits: Principles and Applications (CRC Press,
[52] H. Bindra, C. Lokin, D. Schinkel, A. Annema, and B. Nauta, “A 2015), the Author of CMOS Circuits for Passive Wireless Microsystems
1.2-V dynamic bias latch-type comparator in 65-nm CMOS with (Springer, 2010), CMOS Active Inductors and Transformers: Principle,
0.4-mV input noise,” IEEE J. Solid-State Circuits, vol. 53, no. 7, Implementation, and Applications (Springer, 2008), and CMOS Current-
pp. 1902–1912, Jul. 2018. Mode Circuits for Data Communications (Springer, 2006), and the Lead
[53] H. Bindra, A. Annema, S. Louwsma, and B. Nauta, “A 0.2-8 MS/s Co-Author of Computer Methods for Analysis of Mixed-Mode Switching
10b flexible SAR ADC achieving 0.35-2.5 fJ/conv-step and using self- Circuits (Kluwer Academic, 2004). He is also the author/co-author of
quenched dynamic bias comparator,” in Proc. Symp. VLSI Circuits, over 250 research papers in refereed international journals and conference
Dig. Tech. Papers, 2019, pp. C74–C75. proceedings. He is the co-recipient of the Best Student Paper Award at
[54] F. Yuan, “Bootstrapping techniques for energy-efficient succes- 2021 IEEE International Symposium on Circuits and Systems. He was
sive approximation ADC,” Analog Integr. Circuits Signal Process., awarded the Dean’s Teaching Award in 2017, the Ryerson Research Chair
vol. 114, pp. 299–313, Mar. 2023. in 2005, the Dean’s Research Award in 2004, the Early Tenure in 2003,
[55] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. V. der Plas, “Noise the Doctoral Scholarship from Natural Science and Engineering Research
analysis of regenerative comparators for reconfigurable ADC archi- Council of Canada from 1997 to 1998, the Teaching Excellence Award
tectures,” IEEE Trans. Circuits Syst. I, vol. 55, no. 6, pp. 1441–1454, from the Changzhou Institute of Technology in 1988, and the Science and
Jul. 2008. Technology Innovation Award from the City of Changzhou, Jiangsu, China,
[56] S. Chiang, H. Sun, and B. Razavi, “A 10-bit 800-MHz 19-mW CMOS in 1988. He is a Fellow of the Institute of Engineering and Technology,
ADC,” IEEE J. Solid-State Circuits, vol. 49, no. 4, pp. 935–949, and a registered professional engineer in the province of Ontario,
Apr. 2014. Canada.

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