Computer Architecture

1. Computer Architecture Write short notes describing the operation of each of the following: (a)
DRAM memory cell (b) DRAM memory chip (c) DRAM memory module (d) DRAM memory module
refresh cycle (e) interleaved DRAM memory modules [4 marks each]

2.What is the PCI Local Bus and when is it used? [5 marks] What types of signals are defined in its
specification? [5 marks] Characterise operation of buses such as the PCI Local Bus in terms of basic
read, basic write, and basic arbitration operations. [10 marks]

3.Write short notes on each of the following parameters of cache design:

(a) size [4 marks]
(b) mapping function [4 marks]
(c) replacement algorithm [4 marks]
(d) write policy [4 marks]
(e) block size [4 marks]

4.Give the circuit diagram and describe the operation of the following types of memory cell:
(a) bipolar memory cell (static) [5 marks]
(b) MOS memory cell (static) [5 marks]
Give the key characteristics of each of the following types of memory: DRAM, ROM, PROM, EPROM
and EEPROM. [2 marks each]

5.Give a simplified schematic of a PC showing the main CPU, its support chips, and bus interface. [10
marks]
Describe how interrupts and bus arbitration are handled in this design. [10 marks]

6.Write short notes on the following:

(a) static memory bit [6 marks]
(b) dynamic memory bit [6 marks]
(c) memory chip organisation [4 marks]
(d) memory module organisation [4 marks]

7.(a) You have designed a simple processor together with private instruction and data caches. You are
asked to improve its performance for a particular application. You try each of the changes listed below
individually but in each case the performance does not improve significantly. Describe why this might
occur.
(i) You change the Instruction Set Architecture (ISA) and processor design to provide more registers for
the compiler to use. Each instruction is now encoded using more bits. [4 marks]
(ii) You add a custom instruction that performs a sequence of instructions in fewer clock cycles than
was previously possible. [4 marks]
(iii) You replace your current DRAM with a special low-latency DRAM. [3 marks]
(iv) You increase the associativity of the data cache from 2-way to 4-way. [3 marks]
(b) You add a second processor core on the same chip with its own private caches, but the speedup you
achieve for a new multithreaded application is only 1.2×. What different factors could explain this
limited speedup? [6 marks]

8.(a) Why might high-performance system-on-chip (SoC) designs, for example, those that power
mobile phones, typically contain many processors, and domain-specific hardware accelerators? [6
marks]
 (b) If we simply wanted to run independent programs on the different cores of a multicore processor,
would we need a cache coherency mechanism, a memory consistency model, both, or neither? [4
marks]
(c) What does the term “side-channel” refer to in the context of hardware security? Provide an example
of a side channel that could be present in a processor. [4 marks]
(d) Why do GPUs typically require high-bandwidth access to main memory? [3 marks]
(e) Why do we need to keep Translation Lookaside Buffers (TLBs) coherent in a multi-core system?

9.(a) Why might it be reasonable to estimate the performance of a high-performance processor as being
proportional to the square root of the area of the core? [4 marks]

(b) It has become increasingly difficult to boost the performance of high-performance superscalar
processors. This has raised concerns within industry that only very modest gains might be possible in
the future. (i) Should we be concerned about the stagnation of single-thread performance? Provide one
argument in favour and one against. [6 marks]
(ii) Some suggest that industry should explore radically different processor designs to boost single-
thread performance. Why have developments in Instruction Set Architectures (ISAs) and
microarchitectures historically been more incremental in nature? [3 marks]
(iii) One potential avenue for innovation involves enhancing the information shared between the
compiler and hardware. This would be achieved by modifying the Instruction Set Architecture (ISA).
What are the possible benefits of this approach, and what challenges might arise in practice? [4 marks]

(c) A chiplet is a small, modular integrated circuit that can be combined with other chiplets to create a
complex system within a single package. What are the benefits of this approach when compared to
designing and manufacturing a single die

10. (a) Conventional instruction sets specify an instruction’s operands by using register names. We
could alternatively specify an instruction’s operands by inter instruction distance, that is, indicating the
required operand by counting backwards to the instruction that generated it.
(i) Describe one possible advantage of this approach. [3 marks]
(ii) If we specified an instruction’s operands in this way we could still retain the register file. Describe a
simple way to determine the destination register for each instruction that would mean it would not be
encoded in the instruction. [3 marks]
(iii) In what cases would it be difficult to specify operands using the scheme described? [6 marks]

(b) Precisely what invariants does a cache coherence protocol guarantee? [3 marks]
(c) Imagine a multi-core system with a directory-based cache-coherence protocol.
(i) What are the benefits of a directory-based cache coherence protocol over a snooping protocol? [2
marks]
(ii) Why might an L3 cache have more tags and directory entries than cache lines, that is, be a non-
inclusive cache that maintains an inclusive directory? [3 marks]

11.Many high-performance microprocessors support multithreading in hardware.

(a) In coarse-grained multithreading, threads switch following specific events.
(i) What hardware support is required for coarse-grained multithreading? [3 marks]
(ii) What hardware can be provided to reduce the cost of thread switching in coarse-grained
multithreading and how does it help? [3 marks]
(b) In fine-grained multithreading, a new thread is selected to be fetched on each clock cycle.
(i) How can fine-grained multithreading reduce the hardware requirements of a simple in-order
processor in some circumstances? [3 marks]
(ii) What is the impact on performance of fine-grained multithreading and how can it be improved? [3
marks]
(c) In simultaneous multithreading, threads co-exist within a core.
(i) Describe a scenario where overall performance will improve, and another where it will get worse,
with simultaneous multithreading. [4 marks]
(ii) What factors need to be considered when deciding whether to duplicate, partition or share a core
resource? [4 marks]

12.(a) Describe why it is often important to try to limit off-chip memory accesses when designing a
high-performance domain-specific accelerator that is part of a System-on-a-Chip (SoC)? [4 marks]

(b) What techniques or strategies might be employed to reduce off-chip memory accesses when
designing a domain-specific accelerator? [8 marks]

(c) Imagine a domain-specific accelerator with numerous individual compute units. Each compute unit
is programmable, has specialised functional units and produces requests to access memory. The
compute units share a L1 cache.

In order to help improve the effective bandwidth to the shared L1 cache, memory requests that access
the same address may be coalesced (or merged). Experiments confirm that there is scope to coalesce
requests both from a single unit and from different units.
You are asked to design a hardware scheme for coalescing load requests only, store requests are not
coalesced. The compute units generate loads and stores in program order. For all requests from a single
compute unit, the coalescing unit must ensure that stores are not reordered with respect to loads or
other stores from the same compute unit.
The accelerator provides no guarantees about the way in which requests from different compute units
may be reordered. The design should be efficient and scalable, i.e. make good use of any on-chip
memory required and make some attempt to minimise the number of address comparisons required. It
should be possible to coalesce requests that are made from different compute units. There is no need to
discuss how data is returned from the L1 cache to the compute units.

13.What do you understand by pipelining? Explain arithmetic pipeline with an example. (Lecture 6)
11) Describe the various types of external memory.
12) Explain various data transfer scheme between I/O devices and 8085.
13) Draw and explain basic architecture of 8088

2) Describe the RISC characteristics. 3) Discuss about stack organization. 4) Explain various
representations of data in computer. 5) What do you understand by random-access memories? Explain.
6) Discuss the PCI (Peripheral Component Interconnect). 7) Explain CPU structure and functions. 8)
How micro-programmed control unit is designed? 9) Explain instruction cycle.
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