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Bece102l Cat 1 G1 2022

The document is an examination paper for a B.Tech course in Digital Systems Design, consisting of various questions related to Boolean algebra, Karnaugh maps, and circuit design. It includes tasks such as simplifying Boolean expressions, implementing functions using logic gates, identifying errors in code, and designing a full adder circuit. The exam is structured to assess students' understanding of digital systems and their ability to apply theoretical concepts in practical scenarios.

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tiwari7titan
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24 views7 pages

Bece102l Cat 1 G1 2022

The document is an examination paper for a B.Tech course in Digital Systems Design, consisting of various questions related to Boolean algebra, Karnaugh maps, and circuit design. It includes tasks such as simplifying Boolean expressions, implementing functions using logic gates, identifying errors in code, and designing a full adder circuit. The exam is structured to assess students' understanding of digital systems and their ability to apply theoretical concepts in practical scenarios.

Uploaded by

tiwari7titan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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SLOT: G1+TG1

SCHOOL OF ELECTRONICS ENGINEERING


B.Tech CAT I Fall Sem(2022-23)

Course Code : BECE102L Duration : 90 Minutes.


Course Name : Digital Systems Design Max. Marks : 50

Answer all questions

Q.No Question Max. CO BL


Marks
1
Simplify the following Boolean expression to minimum no of
literals using the laws of Boolean Algebra 10 CO1 BL 3

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
a) A = (̅̅̅̅̅̅̅̅̅
̅̅̅̅)(̅ )( )
b) ̅
Z = BC + A + ̅ ̅ ̅ ̅ ̅ + A̅C + ABC
c) Y = (A’ + B’) (A + C’) + B’(B + C) (̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅)
d) Y= (̅̅̅̅̅̅̅̅̅̅̅̅
) + ̅C ̅ + A ̅ ̅ + ̅ ̅ CD + AC ̅
2 a) Find the prime implicants for the following Boolean BL3
functions, and determine which are essential: (4 marks) CO1
( ) ( ) 10
b) Using the Karnaugh map method obtain the minimal sum
of the products and product of sums expressions for the
function (6 marks)
( ) ( )

3 Implement the following function using i) NOR logic gate and 10 CO1 BL2
ii) NAND logic gate
f( a, b, c, d) = ΠM (1,2,3,5,6,7,8,9,12,13)
4 Identify the errors in the following code and find out the CO2 BL4
logical expression. Also draw the truth table and logical
diagram from the logical expression. 10
module file(x,y,a,b,bin);
output (x,y);
reg (x,y);
input wire (a,b,bin)
always (a or b or bin)
begin
case({a,b,bin})
3’b000:{x,y}=2'b00;
3’b001:{x,y}=2’b11;
3’b010:{x,y}=2’b11;
3’b011:{x,y}=2’b01;
3’b100:{x,y}=2’b10;
3’b101:{x,y}=2'b00;
3’b110:{x,y}=2'b00;
3’b111:{x,y}=2’b11;
end case
end
end module

Answer:
Line 1: x=difference, y=borrow.
Line 2, 3 and 4: No need of open and close () brace.
Line 4: Semi colon ; missing.
Line 5: @ missing.
Line 16 and 18: Space next to the end is not required.

Logical Expression:
x = a  b  bin
y = ̅b + ((̅+ b) bin)

5 Design the full adder circuit using half adder and OR gate 10 CO2 BL2,
(Write the corresponding expression and truth table). Also, 4
write the behavioral modelling Verilog code using case
statements.
Inputs
Outputs

Cout (C S
A B Cin
arry) (Sum)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

module fulladd_be(sum,carry,a,b,c);
input wire a,b,c;
output sum,carry;
reg sum,carry;
always @(a or b or c)
begin
case({a,b,c})
3'b000:{sum,carry}=2'b00;
3'b001:{sum,carry}=2'b10;
3'b010:{sum,carry}=2'b10;
3'b011:{sum,carry}=2'b01;
3'b100:{sum,carry}=2'b10;
3'b101:{sum,carry}=2'b01;
3'b110:{sum,carry}=2'b01;
3'b111:{sum,carry}=2'b11;
endcase
end
endmodule

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