Subject Title VLSI Design and Testing LAB

Subject Code BECL606 IA Marks 50

Number of Lecture Hrs / Week 2 Hrs. Lab Exam Marks 50
Total Number of Lecture Hrs 40 Exam Hours 03

FACULTY DETAILS:
Name: Prof. S. S. KAMATE Designation: Asst. Professor Experience: T-21.Yrs, I-00Yrs
No. of times course taught: 01 Specialization: Digital Electronics

1.0 Prerequisite Subjects:

Sl. No Branch Semester Subject

01 Electronics & Communication Engineering III Digital Electronics
02 Electronics & Communication Engineering V Fundamentals of CMOS VLSI
03 Electronics & Communication Engineering VI Microelectronics Circuits

2.0 Course Objectives

This laboratory course enables students to :

 Design, model, simulate and verify digital circuits.
 Perform ASIC design flow and understand the process of synthesis, synthesis constraints and evaluating the
synthesis reports to obtain optimum gate level netlist.
 Perform RTL-GDSII flow and understand the ASIC Design flow.

3.0 Course Outcomes

At the end of the course students will be able to:
Cognitiv
Course Outcome POs
e Level
C323.1 Design and simulate combinational and sequential digital circuits using U PO1, PO2, PO3, PO5,
Verilog HDL PO8, PO10,
C323.2 Understand the Synthesis process of digital circuits using EDA tool U PSO1,PSO2
PO1, PO2, PO3, PO5,
PO8, PO10,
Perform ASIC design flow and understand the process of synthesis, U PSO1,PSO2
PO1, PO2, PO3, PO5,
C323.3
synthesis PO8, PO10,
C323.4 constraints
Design and and evaluating
simulate basic the
CMOSsynthesis reports
circuits to obtaincommon
like inverter, optimum gate U PSO1,PSO2
PO1, PO2, PO3, PO5,
source PO8, PO10,
C323.5 amplifier
Perform RTL-GDSII flow and understand the stages in ASIC design U PSO1,PSO2
PO1, PO2, PO3, PO5,
PO8, PO10,
PSO1,PSO2
Total Hours of instruction 40

4.0 Course Content

Laboratory Experiments

Sl. No. Experiments

Design a 4-Bit Adder

1. • Write a Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and generate the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
 4-Bit Shift and add Multiplier
• Write Verilog Code
2. • Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for
ALUBehavioral Modeling
3. • Write Verilog description
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
Flip-Flops ( D,SR and JK )
• Write the Verilog description
• Verify the Functionality using Test-bench
4. • Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
Power requirement and Total area required.
• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.
Four bit Synchronous MOD-N counter with Asynchronous reset
• Write Verilog Code
5. • Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist Identify Critical path
a) Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the
widths of inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology.
Carry out the following:
i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the time
6. period of 20ns and plot the input voltage and output voltage of designed inverter?
ii.From the simulation result compute tpHL, tpLH and td for all three geometrical settings of width?
iii.Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter.
Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre layout
simulations and compare the results.
Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS inverter
7. computed in experiment above. Verify the functionality of NOR gate and also find out the delay td
for all four possible combinations of input vectors. Table the results. Increase the drive strength to
2X and 4X and tabulate the results.
Construct the schematic of the Boolean Expression

8. Y= AB+CD+E using CMOS Logic. Verify the functionality of the expression find out the delay td
for some combination of input vectors. Tabulate the results.
a) Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load and
find its transient response and AC response? Measure the Unit Gain Bandwidth (UGB),
9. amplification factor by varying transistor geometries, study the impact of variation in width to
UGB.
b) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC &
LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
a) Construct the schematic of two-stage operational amplifier and measure the following:
i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase margin with and without
coupling capacitance iv. Use the op-amp in the inverting and non-inverting configuration and verify
its functionality. v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by
10. varying the stage wise transistor geometries and record the observations.
b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in
part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post
layout simulations, compare the results with pre-layout simulations and perform the
comparative analysis.
Demonstration Experiments ( For CIE )
UART
 • Write Verilog description
11. • Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path.
Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
12. • Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract
parasitic and perform post layout simulations, compare the results with pre-layout simulations.
Record the observations.

5.0 Relevance to future subjects

SL. Semester Subject Topics
No
01 VIII Project work VLSI based projects
02 Higher VLSI era Exposure to the VLSI flow and different types of design.

6.0 Relevance to Real World

SL. No Real World Mapping
01 VLSI design
02 Miniaturization of different designs to provide more flexibility for the designers

7.0 Gap Analysis and Mitigation

SL. No Delivery Type Details
02 NPTEL VLSI design methods

8.0 Books Used and Recommended to Students

Text Books
1. “Basic VLSI Design” by Douglas A. Pucknell and Kamran Eshaghian
2. “CMOS VLSI Design”- A Circuits and Systems Perspective”- Neil H.E. Weste, David Harris, Ayan Banerjee, 3rd
Edition, Pearson Education.
3. “FPGA Based System Design”-Wayne Wolf, Pearson Education, 2004, Technology and Engineering

Relevant Websites (Reputed Universities and Others) for Notes

9.0
/Animation / Videos Recommended
Website and Internet Contents References
1) https://vtu.ac.in
2) http://www.bookspar.com/engineering-vtu
3) http://www.slideshare.net/farohalolya/8086-microprocessor-lab-manual
4) https://www.youtube.com/results?search_query=microprocessor

10.0 Magazines/Journals Used and Recommended to Students

Sl.No Magazines/Journals website
1 IEEE http://ieeexplore.ieee.org/Xplore/home.jsp
2 PC World http://www.pcworld.com/article/146957/components/article.html

11.0 Examination Note

Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam (SEE)
is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20 marks). A
student shallbe deemed to have satisfied the academic requirements and earned the credits allotted
to each course. The student has to secure not less than 35% (18 Marks out of 50) in the semester-end
examination (SEE).
Continuous Internal Evaluation (CIE):
CIE marks for the practical course is 50 Marks.
The split-up of CIE marks for record/ journal and test are in the ratio 60:40.
 Each experiment to be evaluated for conduction with observation sheet and record write-up.
Rubrics for the evaluation of the journal/write-up for hardware/software experiments designed
by the faculty who is handling the laboratory session and is made known to students at the
beginning of thepractical session.
 Record should contain all the specified experiments in the syllabus and each experiment write-up
willbe evaluated for 10 marks.
 Total marks scored by the students are scaled downed to 30 marks (60% of maximum marks).
 Weightage to be given for neatness and submission of record/write-up on time.
 Department shall conduct 02 tests for 100 marks, the first test shall be conducted after the 8 th
weekof the semester and the second test shall be conducted after the 14th week of the
semester.
 In each test, test write-up, conduction of experiment, acceptable result, and
procedural knowledge will carry a weightage of 60% and the rest 40% for viva-voce.
 The suitable rubrics can be designed to evaluate each student’s performance and
learning ability. Rubrics suggested in Annexure-II of Regulation book
 The average of 02 tests is scaled down to 20 marks (40% of the maximum marks).
The Sum of scaled-down marks scored in the report write-up/journal and average marks of two tests
is the total CIE marks scored by the student.
Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute, examiners are appointed
by the University
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of the answer script to be
strictly adhered to by the examiners. OR
based on the course requirement evaluation rubrics shall be done.
 Course Plan 2024-25 Even – Semester -6th
Electronics and Communication Engineering

12.0 Course Delivery Plan

Sl. No. Experiments
Design a 4-Bit Adder
1. • Write a Verilog description
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and generate the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
4-Bit Shift and add Multiplier
• Write Verilog Code
2. • Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report generated identify Critical path, Maximum delay, Total number of cells, Power
requirement and Total area required
32-Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if statement for
ALUBehavioral Modeling
3. • Write Verilog description
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
Flip-Flops ( D,SR and JK )
• Write the Verilog description
• Verify the Functionality using Test-bench
4. • Synthesize the design by setting proper constraints and obtain the gate level netlist.
From the report gate level netlist identify Critical path, Maximum delay, Total number of cells,
Power requirement and Total area required.
• Verify the functionality using Gate level netlist and compare the results at RTL and
gate level netlist.
Four bit Synchronous MOD-N counter with Asynchronous reset
• Write Verilog Code
5. • Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist Identify Critical path
b) Construct the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out
the following:
i. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and the
6. time period of 20ns and plot the input voltage and output voltage of designed inverter?
ii. From the simulation result compute tpHL, tpLH and td for all three geometrical settings of
width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for CMOS
inverter.
Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre layout
simulations and compare the results.
Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS inverter
7. computed in experiment above. Verify the functionality of NOR gate and also find out the delay td
for all four possible combinations of input vectors. Table the results. Increase the drive strength to
2X and 4X and tabulate the results.
Construct the schematic of the Boolean Expression

8. Y= AB+CD+E using CMOS Logic. Verify the functionality of the expression find out the delay td
for some combination of input vectors. Tabulate the results.
c) Construct the schematic of Common Source Amplifier with PMOS Current Mirror Load and
find its transient response and AC response? Measure the Unit Gain Bandwidth (UGB),

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 Course Plan 2024-25 Even – Semester -6th
Electronics and Communication Engineering

9. amplification factor by varying transistor geometries, study the impact of variation in width to
UGB.
d) Draw Layout of common source amplifier, use optimum layout methods. Verify for DRC &
LVS, extract parasitic and perform post layout simulations, compare the results with pre-
layout simulations. Record the observations.
a) Construct the schematic of two-stage operational amplifier and measure the following:
i. Unity gain Bandwidth ii. dB Bandwidth iii. Gain Margin and phase margin with and without
coupling capacitance iv. Use the op-amp in the inverting and non-inverting configuration and verify
its functionality. v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by
10. varying the stage wise transistor geometries and record the observations.
b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in
part a. Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post
layout simulations, compare the results with pre-layout simulations and perform the
comparative analysis.
Demonstration Experiments ( For CIE )
UART
• Write Verilog description
11. • Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing constraints
Tabulate the Area, Power and Delay for the Synthesized netlist, Identify Critical path.
Design and characterize 6T binary SRAM cell and measure the following:
• Read Time, Write Time, SNM, Power
12. • Draw Layout of 6T SRAM, use optimum layout methods. Verify for DRC & LVS, extract
parasitic and perform post layout simulations, compare the results with pre-layout simulations.
Record the observations.

13.0 VIVA BANK

1. The minimum voltage to keep the MOS transistor in on state is known as. 'Pinch off of the channel takes place in
which region.
3. Which of 'the following equation is true for liner region?
a)Vds < Vgs -Vt b) Ids> Vgs - Vt c) Vds = Vgs - Vt d) None
4. The oxide layer used in the MOS fabrication is
5. Which of the following Well process is superior?
a) P-well b)N-well c) Both P-well and N-well d) None
6. What is the advantage of CMOS technology?
7. Transit time is given by-----------------------
8. When the VTC of the CMOS inverter shifts towards left,
9. The demarcation line has to be drawn in-------------------stick diagram.
10. If the value of lambda is 1micrometer then the minimum feature size o the transistor is ?
11. The scaling factor for the Gate capacitance Cg is given by
12. The scaling factor for power-speed product is given by
13. If the gate voltage and the input voltage of the NMOS transistor is 5V and threshold voltage
of the transistor is O. 7V, then the output voltage
14. The mobility of the electrons is-------------------- than the holes.
15. As the width of the transistor increases the number of contact cuts-----------------
16. Transmission gate is----------------
17. The CMOS schematic diagram of NAND gate consists of-------------------
18. If the size of the transistors in an inverter increases, then the input capacitance
19. The minimum value of the scaling factor in a cascaded inverter circuit to drive large capacitive load
20. In a lambda-based rules, the distance between two MI layers is
21. Match the following;
A B
a) CMOS technology i) Strong '0'
b) Bipolar technology ii) Strong' 1’
c) Transmission gate iii) High input impedance
d) PMOS transistor iv) Low input impedance
e) NMOS transistor v) Bi-directional switch
22. What is rise time & fall time of Inverter.
23. Define Symmetrical inverter.
24. What is the value of e in case of load handling by inverter.
25. What is Pass transistor?
26. Give the disadvantage of Pass transistor.
27 What is the advantage of Transmission gate over Pass transistor.

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 Course Plan 2024-25 Even – Semester -6th
Electronics and Communication Engineering

28. What is a Flip-flop?

29. What is a master slave Flip-flop?
30. What is a race-around condition?
31. What is RC extraction?
32. What is Back annotation?
33. What do you mean by DC-analysis?
34. What do you mean by AC-analysis?
35. What is the Gain of common drain amplifier?
36. How the common source amplifier is formed.
37. What is speed Vs area tradeoff?
38. What is DRC & ERC.
39. Differentiate Serial & Parallel adder.
32. Explain booth multiplier

14.0 University Result

Examination FCD FC SC % Passing
New Course

Prepared by Checked by

Prof. S S Kamate Prof. S. S Kamate HOD Principal

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