Explore more resources

Altera® Design Hub

General-Purpose I/O User Guide

Agilex™ 3 FPGAs and SoCs

Updated for Quartus® Prime Design Suite: 25.1.1

Online Version 847266

Send Feedback 2025.08.04
 Contents

Contents

1. Agilex™ 3 General-Purpose I/O Overview....................................................................... 5

1.1. Package Selection and I/O Vertical Migration Support................................................. 6
1.2. Types of I/O Banks................................................................................................ 7
2. Agilex 3 HSIO Banks....................................................................................................... 8
2.1. HSIO Bank Overview..............................................................................................8
2.1.1. HSIO Bank Structure..................................................................................9
2.1.2. HSIO Buffers and Registers......................................................................... 9
2.2. HSIO Features.....................................................................................................11
2.2.1. Supported I/O Standards for HSIO Banks.................................................... 11
2.2.2. HSIO Buffer Behavior............................................................................... 13
2.2.3. Programmable I/O Element Features for the HSIO Bank................................ 14
2.3. HSIO Implementation Guide..................................................................................16
2.3.1. I/O Assignments with the Quartus Prime Assignment Editor...........................17
2.3.2. Assigning Pin I/O Standards in the Quartus Prime Pin Planner........................ 19
2.4. HSIO Termination................................................................................................ 19
2.4.1. Single-Ended I/O Termination in Agilex 3 Devices......................................... 20
2.4.2. True Differential Signaling I/O Termination in Agilex 3 Devices....................... 31
2.5. HSIO Design Guidelines........................................................................................ 36
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os........................36
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O
Standards in the Same or Adjacent HSIO Bank............................................ 36
2.5.3. VREF Sources and Input Standards Grouping................................................ 37
2.5.4. HSIO Pin Restrictions for External Memory Interfaces....................................38
2.5.5. RZQ Pin Requirement................................................................................38
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages........................... 38
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check................... 39
2.5.8. Simultaneous Switching Noise................................................................... 39
2.5.9. HPS Shared I/O Requirements................................................................... 40
2.5.10. Clocking Requirements............................................................................40
2.5.11. Clock Restrictions for GPIO Interfaces....................................................... 40
2.5.12. SDM Shared I/O Requirements.................................................................40
2.5.13. Unused Pins.......................................................................................... 41
2.5.14. VCCIO_PIO Supply for Unused HSIO Banks................................................... 41
2.5.15. HSIO Pins During Power Sequencing......................................................... 41
2.5.16. Drive Strength Requirement for HSIO Input Pins........................................ 42
2.5.17. Maximum DC Current Restrictions ........................................................... 42
2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility.................. 43
2.5.19. Connection to True Differential Signaling Input Buffers During Device
Reconfiguration........................................................................................44
2.5.20. Implementing a Pseudo Open Drain.......................................................... 45
2.5.21. Allowed Duration for Using RT OCT........................................................... 45
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction.......................... 46
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO..............46
2.6. HSIO Simulation.................................................................................................. 46
2.6.1. IBIS Models—HSIO Support...................................................................... 47
2.6.2. IBIS-AMI Models...................................................................................... 48

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

2
Contents

2.6.3. HSPICE Models........................................................................................ 48

2.6.4. Net Length Reports.................................................................................. 48
3. Agilex 3 HVIO Banks..................................................................................................... 49
3.1. HVIO Bank Overview............................................................................................ 49
3.1.1. HVIO Bank Structure................................................................................ 49
3.1.2. HVIO Buffers and Registers....................................................................... 50
3.2. HVIO Features.....................................................................................................51
3.2.1. Supported I/O Standards for HVIO Banks.................................................... 51
3.2.2. Dedicated Features of HVIO Pins................................................................ 52
3.2.3. HVIO Buffer Behavior............................................................................... 53
3.2.4. Programmable I/O Element Features for the HVIO Bank................................ 53
3.3. HVIO Implementation Guide..................................................................................54
3.3.1. I/O Assignments with the Quartus Prime Assignment Editor...........................54
3.3.2. Assigning Pin I/O Standards in the Quartus Prime Pin Planner........................ 56
3.4. HVIO Design Guidelines........................................................................................ 57
3.4.1. HVIO Pins During Power Sequencing...........................................................57
3.4.2. Unused HVIO Pins.................................................................................... 57
3.4.3. VCCIO_HVIO Supply for Unused HVIO Banks................................................... 58
3.4.4. Maximum DC Current Restrictions ............................................................. 58
3.5. HVIO Simulation.................................................................................................. 58
3.5.1. IBIS Models—HVIO Support...................................................................... 59
3.5.2. HSPICE Models........................................................................................ 59
3.5.3. Net Length Reports.................................................................................. 60
4. Agilex 3 HPS I/O Banks................................................................................................ 61
4.1. HPS I/O Bank Overview........................................................................................ 61
4.2. HPS I/O Features................................................................................................. 61
4.2.1. Supported I/O Standards for HPS I/O Banks................................................ 62
4.2.2. Programmable I/O Element Features for the HPS I/O Bank............................ 62
4.2.3. HPS I/O Buffer Behavior........................................................................... 63
4.3. HPS I/O Implementation Guide.............................................................................. 63
4.3.1. Configuring Open Drain Feature for the HPS I/O........................................... 64
4.3.2. I/O Assignments with the Quartus Prime Assignment Editor...........................65
4.3.3. Assigning Pin I/O Standards in the Quartus Prime Pin Planner........................ 67
4.4. HPS I/O Design Guidelines.................................................................................... 67
4.4.1. HPS I/O Pins During Power Sequencing....................................................... 67
4.4.2. HPS Shared I/O Requirements................................................................... 68
4.5. HPS I/O Simulation.............................................................................................. 68
4.5.1. IBIS Models—HPS I/O Support...................................................................68
4.5.2. Net Length Reports.................................................................................. 69
5. Agilex 3 SDM I/O Banks................................................................................................70
5.1. SDM I/O Bank Overview....................................................................................... 70
5.2. SDM I/O Features................................................................................................ 70
5.2.1. Supported I/O Standards for SDM I/O Banks............................................... 71
5.2.2. SDM I/O Buffer Behavior...........................................................................71
5.2.3. I/O Standards and Features for Configuration Pins........................................72
5.3. SDM I/O Design Guidelines................................................................................... 74
5.3.1. SDM I/O Pins During Power Sequencing...................................................... 74
5.3.2. Avalon Streaming Interface Dedicated Configuration Pins.............................. 75
5.4. SDM I/O Simulation............................................................................................. 75

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

3
 Contents

5.4.1. IBIS Models—SDM I/O Support.................................................................. 75

5.4.2. Net Length Reports.................................................................................. 76
6. Agilex 3 I/O Troubleshooting Guidelines...................................................................... 77

7. GPIO FPGA IP............................................................................................................... 78

7.1. Release Information for GPIO FPGA IP.................................................................... 78
7.2. Generating the GPIO FPGA IP................................................................................ 78
7.2.1. Altera FPGA IP Generation Output.............................................................. 80
7.3. GPIO FPGA IP Parameter Settings.......................................................................... 83
7.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP..................... 84
7.4. GPIO FPGA IP Interface Signals............................................................................. 84
7.4.1. Shared Signals........................................................................................ 87
7.4.2. Data Bit-Order for Data Interface.............................................................. 87
7.4.3. Input and Output Bus High and Low Bits..................................................... 87
7.4.4. Data Interface Signals and Corresponding Clocks......................................... 88
7.5. GPIO FPGA IP Architecture.................................................................................... 88
7.5.1. GPIO FPGA IP Data Paths.......................................................................... 89
7.5.2. Register Packing...................................................................................... 91
7.6. Verifying Resource Utilization and Design Performance.............................................. 91
7.7. GPIO FPGA IP Timing........................................................................................... 91
7.7.1. Timing Components................................................................................. 91
7.7.2. Delay Elements........................................................................................93
7.7.3. Timing Analysis....................................................................................... 93
7.7.4. Timing Closure Guidelines......................................................................... 96
7.8. GPIO FPGA IP Design Examples............................................................................. 96
7.8.1. GPIO FPGA IP Synthesizable Quartus Prime Design Example.......................... 97
7.8.2. GPIO FPGA IP Simulation Design Example................................................... 97
8. Programmable I/O Features Description...................................................................... 99
8.1. Programmable Pre-Emphasis............................................................................... 100
8.2. Programmable De-Emphasis................................................................................ 101
8.3. Programmable Differential Output Voltage............................................................. 102
8.4. Continuous Time Linear Equalization.....................................................................103
9. Document Revision History for the General-Purpose I/O User Guide: Agilex 3
FPGAs and SoCs..................................................................................................... 104

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

4
 847266 | 2025.08.04

Send Feedback

1. Agilex™ 3 General-Purpose I/O Overview

The Agilex™ 3 I/O system includes four types of I/O interfaces. Each I/O interface
caters to different interfacing requirements.

Table 1. Types of I/O Interfaces

Interface Type Features

High-speed I/O (HSIO) • 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V single-ended non-voltage referenced
I/O standards.
• 1.05 V, 1.1 V and 1.2 V single-ended and differential voltage referenced I/O
standards.
• 1.3 V true differential I/O compatible with LVDS, capable to interface with
LVDS subsets such as:
— RSDS
— Mini-LVDS
— Any I/O standards using equivalent electrical specifications
• LPDDR4 external memory interfaces up to 1,067 MHz with a Hard Memory
Controller (HMC).
• LVDS serializer/deserializer (SERDES) interface up to 1.25 Gbps.
• MIPI* D-PHY* interface up to 2.5 Gbps(1) per lane

High-voltage I/O (HVIO) 1.8 V, 2.5 V, and 3.3 V single-ended non-voltage referenced JEDEC-compliant
I/O standards.

Secure Device Manager (SDM) I/O 1.8 V single-ended non-voltage referenced I/O standard.

Hard Processor System (HPS) I/O 1.8 V single-ended non-voltage referenced I/O standard.

Related Information
• Agilex 3 FPGAs and SoCs Device Data Sheet
• LVDS SERDES User Guide: Agilex 3 FPGAs and SoCs
• External Memory Interfaces (EMIF) IP User Guide: Agilex 3 FPGAs and SoCs
• General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs
Get the latest and previous versions of this user guide. If an IP or software
version is not listed, the user guide for the previous IP or software version
applies.
• MIPI D-PHY specifications, MIPI Alliance website.
Provides more information about the standard and long reference channels.

(1) Up to 2.5 Gbps for standard reference, short reference, and long reference channels. For more
information, refer to the MIPI D-PHY specifications and the Agilex 3 data sheet.

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
 1. Agilex™ 3 General-Purpose I/O Overview
847266 | 2025.08.04

1.1. Package Selection and I/O Vertical Migration Support

Figure 1. Package Options, Migrations, and I/O Pins
• The arrows indicate the package migration paths. The shades represent the devices included in each path.
• To achieve full I/O migration across devices in the same migration path, restrict I/Os and transceivers
utilization to match the device with the lowest I/O and transceiver counts.

Package
Key: HVIO / HSIO (LVDS) / HPSIO / Transceivers
Ball Pitch: 0.5 mm Ball Pitch: Variable (1)(2)
Grid Array Pattern: Standard Grid Array Pattern: Variable Pitch BGA
Series Device MBGA: Micro Fineline BGA VPBGA: Variable Pitch BGA
M12A M16A B18A B18B B23C
484-pin MBGA 896-pin MBGA 474-pin VPBGA 538-pin VPBGA 931-pin VPBGA
12 mm × 12 mm 16 mm × 16 mm 18 mm × 18 mm 23 mm × 23 mm 23 mm × 23 mm
A3C 025 160 / 72 (36) / 0 / 0 160 / 48 (24) / 0 / 0 160 / 96 (48) / 0 / 0
A3C 050 160 / 72 (36) / 0 / 0 160 / 48 (24) / 0 / 0 160 / 96 (48) / 0 / 0
C-Series A3C 065 160 / 72 (36) / 0 / 0 160 / 48 (24) / 0 / 0 160 / 96 (48) / 0 / 0
A3C 100 40 / 192 (96) / 48 / 4 160 / 48 (24) / 0 / 0 200 / 144 (72) / 48 / 4
A3C 135 40 / 192 (96) / 48 / 4 160 / 48 (24) / 0 / 0 200 / 144 (72) / 48 / 4
Notes:
(1) The Variable Pitch BGA (VPBGA) packaging is compatible with Type III PCBs that use the design rules equivalent to 0.8 mm ball pitch and standard plated through hole (PTH) vias.
(2) The VPBGA ball pitch is variable and it helps to ease signal routing. For more information, contact your local sales representative.

Related Information
Device Migration Guidelines: Agilex 3 FPGAs and SoCs E-Series
Provides more information about the device migration path.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

6
1. Agilex™ 3 General-Purpose I/O Overview
847266 | 2025.08.04

1.2. Types of I/O Banks

The Agilex 3 devices contain four types of I/O banks: HSIO, HVIO, HPS, and SDM I/O
banks.

Figure 2. Locations of Different I/O Bank Types

This figure shows the approximate locations of each I/O bank type in the Agilex 3 device. The figure shows the
view of the die as shown in the Quartus® Prime Chip Planner. In the Pin Planner, this corresponds to the
"Bottom View". Different device and package combinations have different number of I/O banks. Refer to the
device pin-out files for available I/O banks and the locations of the SDM and HPS I/O banks for each device
package.

HPS HSIO HVIO

HVIO Availability of the HPS banks, HSIO

banks, and HVIO blocks varies among
Core Fabric devices. Refer to the pinout files.
HVIO
HSIO : High-Speed I/O
HVIO SDM HSIO HVIO HVIO : High-Voltage I/O
SDM : Secure Device Manager
HPS : Hard Processor System

Refer to the related information for the features and architectural descriptions of each
I/O bank type.

Related Information
• Agilex 3 HSIO Banks on page 8
• Agilex 3 HVIO Banks on page 49
• Agilex 3 HPS I/O Banks on page 61
• Agilex 3 SDM I/O Banks on page 70
• Device Migration Guidelines: Agilex 3 FPGAs and SoCs

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

7
 847266 | 2025.08.04

Send Feedback

2. Agilex 3 HSIO Banks

The HSIO banks are available in the Agilex 3 FPGAs.

The HSIO banks provide the I/O buffer and peripheral support for the following
functions:
• General-purpose interfaces (GPIO mode)—with or without GPIO FPGA IP
• External memory interfaces (EMIF mode)—with External Memory Interfaces
(EMIF) IP
• Parallel interfaces (PHYLITE mode)—with PHY Lite for Parallel Interfaces IP
• LVDS SERDES interfaces—with LVDS SERDES FPGA IP
• MIPI D-PHY interfaces—with MIPI DPHY IP

Related Information
• LVDS SERDES User Guide: Agilex 3 FPGAs and SoCs
• Types of I/O Banks on page 7
• Device Migration Guidelines: Agilex 3 FPGAs and SoCs
• External Memory Interfaces (EMIF) IP User Guide: Agilex 3 FPGAs and SoCs

2.1. HSIO Bank Overview

Each HSIO bank contains a top index sub-bank and a bottom index sub-bank.
• Top index sub-bank—the pin index numbers are 48 to 95.
• Bottom index sub-bank—the pin index numbers are 0 to 47.

Each sub-bank contains four I/O lanes. Each I/O lane has 12 I/O pins. Consequently,
there are a total of 48 single-ended I/O pins or 24 true differential I/O pairs in each
sub-bank.

If you use SERDES, you can configure each I/O lane to support a SERDES transmitter
or receiver channel, with optional dynamic phase alignment (DPA), for:
• Up to six dedicated differential receiver input buffer pairs
• Up to six dedicated differential transmitter output buffer pairs

If you do not use SERDES, you can configure each true differential buffer as receiver
or transmitter.

Additionally, each sub-bank also contains dedicated circuitries including:

• I/O PLL
• Hard memory controller
• On-chip termination (OCT) calibration blocks

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

The total number of HSIO banks varies across different device packages. Some HSIO
banks are shared with the SDM and HPS function blocks. Refer to the device pin-out
files for available I/O banks for each device package.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

2.1.1. HSIO Bank Structure

Figure 3. Agilex 3 HSIO Bank Structure (Die Top View)
This figure shows the HSIO bank structure of the Agilex 3 device. The figure shows the view of the die as
shown in the Quartus Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View".
Different device packages have different number of HSIO banks. Refer to the device pin-out files for available
HSIO banks and the locations of the HPS shared HSIO banks for each device package.

HSIO Bank HPS I/O Bank Top Index Sub-Bank Bottom Index Sub-Bank
HPS Shared HSIO Bank SDM I/O Bank Index: #48-#95 Index: #0-47

HPS 3A
I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane I/O Lane
Top I/O Bank Row

Bottom I/O Bank Row Top Index Bottom Index

I/O PLL I/O PLL
SDM 2A
HMC Clock Fabric HMC
OCT
Wide Network PLL Slim
SERDES & DPA
I/O Center
Differential I/O Buffer Pair

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

2.1.2. HSIO Buffers and Registers

The I/O registers consist of three different paths.
• The input path for handling data from the input pin to the core
• The output path for handling data from the core to the output pin
• The output enable (OE) path for handling the OE signal to the output buffer

The I/O registers allow fast source-synchronous register-to-register transfers and

resynchronizations. To use the I/O registers to implement double data rate (DDR)
circuitry, you can use the GPIO FPGA IP.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

9
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

The input and output paths contain the following blocks:

• Input registers:
— Support full rate data transfer from the periphery to the core
— Support double or single data rate data captured from I/O buffer to the core
• Output registers:
— Support full rate data transfer from the core to the periphery
— Support double or single data rate data transfer to the output pin
• OE registers:
— Support the output enable signal from the core to the periphery
— Support double data rate or single data rate data transfer to the I/O pin

The input and output paths also support the following features:
• Clock enable
• Asynchronous or synchronous reset
• Bypass mode for input and output paths
• Delay chain on input and output paths

Figure 4. I/O Element (IOE) Structure of Agilex 3 HSIO

In this figure, "Td" is the delay block with fixed delay inserted to ensure correct timing of the DDR data
transfer.

OE from Core
OE
D Q Delay Chain
Td VCCIO_PIO
Write Data from Core [0]
Programmable
D Q Pull-Up Resistor

Output
Write Data from Core [1] OCT
Delay Chain
D Q 2 x Td
Full Rate Outclock From OCT
Calibration
To Core
Block
Input Register
Input
Read Data to Core [0] Alignment Q D Delay Chain
Registers

Read Data to Core [1]

Q D Q D

Full Rate Inclock Input Register Input Register

Related Information
GPIO FPGA IP on page 78

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

10
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.2. HSIO Features

The I/O bank within the HSIO interface supports various differential and single-ended
I/O standards to cater to different types of interfacing requirements.

• Single-ended LVCMOS for general purpose I/O interfacing.

• Single-ended and pseudo-differential voltage-referenced I/O standards for general
purpose and external memory interfacing. The differential voltage-referenced
output pins are not true differential output pins. The differential voltage-
referenced I/O standards use two single-ended output pins with one of the output
pins inverted.
• True differential I/O buffer pairs using the True Differential Signaling and
SLVS-400 I/O standards. The True Differential Signaling I/O standard is
compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL I/O standards. One true
differential buffer pair forms a true differential channel.

Power Pins for the HSIO Buffers

The VCCIO_PIO and VCCPT pins power the I/O buffers located in the I/O bank within
the HSIO interface.

HSIO Buffer Features

• Single-ended non-voltage referenced and voltage-referenced I/O standards
• Differential voltage-referenced I/O standards
• True differential transmitters and receivers
• Serializer/deserializer (SERDES)
• Programmable slew rate
• Programmable weak pull-up resistor
• Programmable differential output voltage (VOD) for true differential output buffers
• Programmable receiver equalization calibration
• On-chip series termination (RS OCT)
• On-chip parallel termination (RT OCT)
• On-chip differential termination (RD OCT)
• Dynamic on-chip parallel termination
• Internally generated VREF
• Programmable pre-emphasis for true differential output buffer
• Programmable de-emphasis

2.2.1. Supported I/O Standards for HSIO Banks

The VCCIO_PIO and VCCPT power supplies power the HSIO buffers. Each I/O sub-bank
has its own VCCIO_PIO power supply and supports only one I/O voltage.

The True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-
LVDS, and LVPECL standards at a lower signal swing.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

11
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

You can place the True Differential Signaling input buffer in a HSIO bank powered by
1.05 V, 1.1 V, 1.2 V and 1.3 V VCCIO_PIO. The maximum input voltage to the True
Differential Signaling input buffer must not exceed the value of
Maximum V ID
Maximum V ICM + :
2
• For 1.05 V, 1.1 V, and 1.2 V VCCIO_PIO, the maximum input voltage is 1.177 V
• For 1.3 V VCCIO_PIO bank, the maximum input voltage depends on the termination:
— On-chip differential termination (RD OCT) enabled—maximum input voltage is
1.602 V
— On-board differential termination with RD OCT disabled—maximum input
voltage is 1.427 V with VICM capped at 1.2 V

By default, the Quartus Prime software assigns 1.2 V to the VCCIO_PIO pin in unused
I/O sub-banks.

Table 2. HSIO Bank Supported I/O Standards

This table lists the input and output voltages of a HSIO bank.

I/O Standard VCCIO_PIO (V) VCCPT (V) JEDEC Standard

Input Output

1.3 V LVCMOS 1.3 1.3 1.8 —

1.2 V LVCMOS 1.2 1.2 1.8 JESD8-12A.01

1.1 V LVCMOS 1.1 1.1 1.8 —

1.05 V LVCMOS 1.05 1.05 1.8 —

1.0 V LVCMOS 1.0 1.0 1.8 —

SSTL-12 (2) 1.2 1.2 1.8 JESD79-4B

HSTL-12 (2) 1.2 1.2 1.8 JESD-16A

HSUL-12 (2) 1.2 1.2 1.8 JESD209-3C

POD12 (2) 1.2 1.2 1.8 JESD79-4B

POD11 (2) 1.1 1.1 1.8 JESD79-5

LVSTL11 1.1 1.1 1.8 JESD209-4C

LVSTL105 1.05 1.05 1.8 JESD209-5

Differential SSTL-12 (2) (3) 1.2 1.2 1.8 JESD79-4B

Differential HSTL-12 (2) (3) 1.2 1.2 1.8 JESD8-16A

Differential HSUL-12 (2) (3) 1.2 1.2 1.8 JESD209-3C

Differential POD-12 (2) (3) 1.2 1.2 1.8 JESD79-4B

Differential POD11 (2) (3) 1.1 1.1 1.8 JESD79-5

Differential LVSTL11 (3) 1.1 1.1 1.8 JESD209-4C

Differential LVSTL105 (3) 1.05 1.05 1.8 JESD209-5

continued...

(2) Input buffers are powered by 1.8 V VCCPT

(3) Uses two single-ended outputs with second output programmed as inverted.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

12
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

I/O Standard VCCIO_PIO (V) VCCPT (V) JEDEC Standard

Input Output

SLVS-400 (4) 1.1/1.2 1.1/1.2 1.8 JESD8-13

DPHY (4) 1.1/1.2 1.1/1.2 1.8 —

True Differential Signaling (2) 1.05/1.1/1.2/1.3 1.3 1.8 —

Related Information
• I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the electrical specifications for the supported I/O standards.
• Assigning Pin I/O Standards in the Quartus Prime Assignment Editor on page 17
• Assigning Pin I/O Standards in the Quartus Prime Pin Planner on page 19

2.2.2. HSIO Buffer Behavior

Table 3. HSIO Pins Guideline for Different Pin States
HSIO Pin State

Not turned on Powering up Fully powered up Configuration User mode Powering down
mode

Either tri-state the • Pin voltage All pins are tri- All pins are tri- Valid data • Pin voltage
pins or do not must not stated with weak stated with weak transactions can must not
drive them with exceed pull-up enabled. pull-up enabled. be initiated. exceed
any external VCCIO_PIO or VCCIO_PIO or
voltage. 1.2 V, 1.2 V,
whichever is whichever is
lower.(5) lower.(5)
• After full • When the
VCCIO_PIO VCCIO_PIO and
power up, the VCC power rails
pins are tri- are powering
stated with down, the I/O
weak pull-up pin signals
enabled. measure
between
ground and
the VCCIO_PIO
voltage levels.

Note: After the Agilex 3 device fully powers up, the voltage levels for the HSIO pins must
not exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Related Information
Agilex 3 FPGAs and SoCs Device Data Sheet

(4) Not supported in GPIO mode.

(5) VCCIO_PIO refers to the real-time onboard voltage supply.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

13
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.2.3. Programmable I/O Element Features for the HSIO Bank

Table 4. Programmable Slew Rate, De-Emphasis, Receiver Equalization Calibration,
and I/O Delay
This table lists the I/O standards that the feature supports and the available settings for each I/O standard.

I/O Standard Slew Rate De-Emphasis Receiver I/O Delay(6)

Control Equalization
Calibration

• 1.3 V LVCMOS • Fastest — Off Refer to the

• 1.2 V LVCMOS • Fast device data
sheet
• 1.1 V LVCMOS • Medium
• 1.05 V LVCMOS (Default)
• 1.0 V LVCMOS • Slow

• SSTL-12 / Differential SSTL-12 • Off (Default) • Off (Default)

• HSTL-12 / Differential HSTL-12 • Low LP • Small
• HSUL-12 / Differential HSUL-12 • Medium LP • Medium
• High LP • Large
• POD12 / Differential POD12 • Fastest
• Low CZ
• POD11 / Differential POD11 (Default)
• Medium CZ
• LVSTL11 / Differential LVSTL11 • Fast
• High CZ
• LVSTL105 / Differential LVSTL105 • Medium
• SLVS-400 • Slow
• DPHY

True Differential Signaling — —

Table 5. Programmable Weak Pull-Up Resistor

This table lists the I/O standard that the features support and the available settings.

I/O Standard Weak Pull-Up Resistor

• 1.3 V LVCMOS • Off (Default)

• 1.2 V LVCMOS • On
• 1.1 V LVCMOS
• 1.05 V LVCMOS
• 1.0 V LVCMOS

Table 6. Programmable Pre-Emphasis and Differential Output Voltage

This table lists the I/O standard that the features support and the available settings.

I/O Standard Pre-Emphasis Differential Output Voltage

True Differential Signaling • Off • Low

• On (Default) • Medium low
• Medium high (Default)
• High

Related Information
• Agilex 3 FPGAs and SoCs Device Data Sheet
• Programmable I/O Features Description on page 99

(6) Delay chain is not supported in the LVDS SERDES receiver mode.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

14
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.2.3.1. Guidelines: Programmable Output Slew Rate Control

Table 7. Slew Rate Implementation and Mode Support

Uncompensated slew rate is supported only for OCT without calibration. Compensated slew rate is supported
only for OCT with calibration.

Slew Rate Setting Implementation Slew Rate Mode Support

• Fast GPIO mode Supports only the uncompensated slew rate mode.
• Medium
• External memory interface Supports only the compensated slew rate mode. The
• Slow
• PHY Lite compensated slew rate mode achieves better slew rate control by
reducing variation of the ramp rate.
• MIPI D-PHY mode

Fastest • GPIO mode Supports only the slew rate bypass mode. The implementation
• External memory interface disables slew rate control and the buffer switches at the fastest
ramp rate.
• PHY Lite
• MIPI D-PHY mode

Related Information
Programmable I/O Features Description on page 99

2.2.3.2. Guidelines: Programmable Pull-Up Resistor

The programmable pull-up resistor feature is enabled by default on unused I/O pins in
the HSIO bank.

Related Information
Programmable I/O Features Description on page 99

2.2.3.3. Guidelines: Programmable De-Emphasis

• The de-emphasis effect reduces eye height. If you use a non-default de-emphasis
setting, perform an IBIS or HSPICE simulation to estimate the electrical
performance of the I/O buffer.
• To get the optimal setting for your design, start the simulation with the lowest de-
emphasis setting. From there, fine-tune the setting until you get the best signal
integrity.
• If you use the compensated slew rate setting, de-emphasis is supported only in
the following modes:
— External memory interface
— PHY Lite
— MIPI D-PHY

Related Information
Programmable I/O Features Description on page 99

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

15
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.3. HSIO Implementation Guide

The Quartus Prime software provides tools for you to create, configure and compile
your I/O design. Each tool provides different functions and supports different features
to implement your I/O design.

Table 8. Quartus Prime I/O Implementation Tools

Tool Functions Supported Assignment Supported I/O Standards

Assignment • View, create and edit • I/O standard • 1.3 V LVCMOS

Editor assignments. • Programmable slew rate control • 1.2 V LVCMOS
• The Quartus Prime software: • Programmable I/O delay • 1.1 V LVCMOS
— Dynamically validates your • Programmable weak pull-up • 1.05 V LVCMOS
edits. resistor • 1.0 V LVCMOS
— Notify you of errors and • Programmable pre-emphasis • SSTL-12
warnings of invalid
• Programmable de-emphasis • HSTL-12
assignments.
• Programmable VOD • HSUL-12
• OCT • POD12
• Receiver equalization • POD11
• Fast input register • LVSTL11
• Fast output enable register • LVSTL105
• Fast output register • Differential SSTL-12
• Differential HSTL-12
Pin Planner • Graphically represent pin • I/O standard
locations on the device. • Differential HSUL-12
• Programmable slew rate control
• With this tool, you can: • Differential POD-12
• Programmable weak pull-up
— Perform initial pin planning. resistor • Differential POD11
— Locate, place, and assign I/O • OCT • Differential LVSTL11
pins. • Differential LVSTL105
— Configure board trace models • SLVS-400
for pins you select for signal • DPHY
integrity evaluations.
• True Differential
Signaling

GPIO FPGA • Instantiate the IP. • SDR transfer

IP • Customize your IP instance using • DDIO transfer —
parameters options. • Output enable

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

16
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.3.1. I/O Assignments with the Quartus Prime Assignment Editor

You can assign all instance-specific settings and constraints through the Quartus Prime
Assignment Editor. You can filter assignments by node name or category.

Figure 5. Quartus Prime Assignment Editor

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

2.3.1.1. Assigning Pin I/O Standards in the Quartus Prime Assignment Editor
1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select I/O Standard (Accepts
wildcards).
4. Under the Value column, select the I/O standard that you want to assign to the
pin.
5. From the Quartus Prime menu, select File ➤ Save.

Related Information
Supported I/O Standards for HSIO Banks on page 11

2.3.1.2. Assigning Programmable IOE Features in the Quartus Prime Assignment

Editor
1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select a supported programmable IOE
feature.
4. Under the Value column, select a supported value.
5. From the Quartus Prime menu, select File ➤ Save.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

17
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Related Information
HSIO Programmable IOE Features Assignment Names and Settings on page 18
Provides a list of supported programmable IOE features for the HSIO, the
assignment names, and supported values.

2.3.1.3. HSIO Programmable IOE Features Assignment Names and Settings

Table 9. HSIO Programmable IOE Features Assignment Names and Settings

This table lists the programmable IOE features assignment names and values that you can specify in the
Quartus Prime Assignment Editor and Pin Planner tools.

Feature Assignment Name Supported Values

Slew rate control Slew Rate • 0—slow

• 1—medium
• 2—fast
• 3—fastest
For the default setting, refer to the related
information.

I/O delay • Input Delay Chain Setting Refer to the device data sheet.
• Output Delay Chain Setting
• Output Enable Delay Chain Setting

Weak pull-up resistor Weak Pull-Up Resistor • On

• Off (default)

Pre-emphasis Programmable Pre-emphasis • 0—off

• 1—on (default)

De-emphasis Programmable De-emphasis • HIGH

• HIGH CONST Z
• LOW
• LOW CONST Z
• MEDIUM
• MEDIUM CONST Z
• OFF (default)

Receiver equalization Receiver Equalization • OFF (default)

calibration • SMALL
• MEDIUM
• LARGE

Differential output voltage Programmable Differential Output • 0—low

Voltage (VOD) • 1—medium low
• 2—medium high (default)
• 3—high

Related Information
• Programmable IOE Delay, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the input and output delay chains specifications.
• Assigning Programmable IOE Features in the Quartus Prime Assignment Editor on
page 17

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

18
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.3.2. Assigning Pin I/O Standards in the Quartus Prime Pin Planner
You can use the Quartus Prime Pin Planner for I/O pin planning, assignment, and
validation.

Figure 6. Quartus Prime Pin Planner

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

2 3 4

1. From the Quartus Prime menu, select Assignments ➤ Pin Planner.

2. Under the Node Name column in the All Pins box, look for the pin that you want
to configure.
3. Under the Location column, select the specific pin location.
The I/O Bank column displays the I/O bank name where the pin resides. The
Top View - Flip Chip diagram shows the I/O banks in different colors.
4. Under the I/O Standard column, select the supported I/O standards that you
want to assign to the pin.
If you select True Differential Signaling, the Pin Planner automatically adds a
negative node with a specific pin location.

Related Information
Supported I/O Standards for HSIO Banks on page 11

2.4. HSIO Termination

Agilex 3 devices support on-chip termination for single-ended and true differential I/O
standards. The OCT maintains signal quality, saves board space, and reduces external
component costs. You can also use external termination for the single-ended I/Os and
true differential signaling I/Os.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

19
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.4.1. Single-Ended I/O Termination in Agilex 3 Devices

Agilex 3 devices support on-chip termination for single-ended I/O standards. OCT
helps to minimize reflections and improve electrical margins.

Figure 7. RS and RT OCT

This figure shows the single-ended termination schemes supported in Agilex 3 devices. RT2 is the dynamic
parallel termination that switches on only when the device is receiving. In bidirectional applications, RT2
automatically switches on when the device is receiving and switches off when the device is driving.

Driving Device Receiving Device

V CCIO

2 × R T2
RS
Z 0 = 50 Ω
V REF
2 × R T2

GND

2.4.1.1. Single-Ended I/O Standards On-Chip Termination

Serial (RS) and parallel (RT) OCT provides I/O impedance matching and termination
capabilities.

The OCT calibration circuit uses the impedance of the external resistor that is
connected to the RZQ pin as reference. During calibration, the circuit continuously
alters the impedance of the I/O buffer until the impedance reaches a predetermined
ratio to the reference resistance.

The OCT with calibration feature is not supported in GPIO mode.

Table 10. OCT Schemes Supported in Agilex 3 Devices

Direction OCT Scheme

Output RS OCT with calibration

RS OCT without calibration

Input RT OCT with calibration

RT OCT without calibration

Bidirectional Dynamic RS and RT OCT

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

20
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.4.1.1.1. RS OCT
Agilex 3 devices support RS OCT with and without calibration.

Table 11. RS OCT Schemes

OCT Scheme Description

RS without calibration • Available on output buffer only.

• Driver-impedance matching provides the I/O driver with a controlled output
impedance that closely matches the impedance of the transmission line.

RS with calibration • The RS OCT calibration circuit uses the impedance of the external resistor
connected to the RZQ pin as a reference.
• During calibration, the circuit continuously alters the impedance of the I/O
buffer until the value reaches the target impedance, which is a predetermined
ratio to the reference resistance.
• The calibration occurs at the end of the device configuration. When the
calibration circuit finds the correct impedance, the circuit stops changing the
characteristics of the drivers.
• In EMIF and MIPI D-PHY modes, you may trigger recalibration during user
mode.

Figure 8. RS OCT without Calibration

This figure shows the RS as the total impedance of the output buffer.
Driver Receiving
Series Termination Device
V CCIO

RS

Z 0 = 50 Ω

RS

GND

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

21
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 9. RS OCT with Calibration

This figure shows the RS as the total impedance of the output buffer.
Driver Receiving
Series Termination Device
V CCIO

RS

Z 0 = 50 Ω

RS

GND

Table 12. Selectable I/O Standards for RS OCT for HSIO Banks
The default values are in bold font.

I/O Standard RS OCT without Calibration(7) (Ω) RS OCT with Calibration (Ω)

1.3 V LVCMOS 34, 40 —

1.2 V LVCMOS 34, 40 —

1.1 V LVCMOS 34, 40 —

1.05 V LVCMOS 34, 40 —

1.0 V LVCMOS 34, 40 —

SSTL-12 34, 40 34, 40

HSTL-12 34, 40 34, 40

HSUL-12 34, 40 34, 40

POD12 34, 40 34, 40

POD11 34, 40 34, 40

LVSTL11 34, 40 34, 40

LVSTL105 34, 40 34, 40

Differential SSTL-12 34, 40 34, 40

Differential HSTL-12 34, 40 34, 40

Differential HSUL-12 34, 40 34, 40

Differential POD12 34, 40 34, 40

Differential POD11 34, 40 34, 40

Differential LVSTL11 34, 40 34, 40

continued...

(7) Supported only in GPIO mode.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

22
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

I/O Standard RS OCT without Calibration(7) (Ω) RS OCT with Calibration (Ω)

Differential LVSTL105 34, 40 34, 40

SLVS-400 — 45

DPHY — 45

Related Information
OCT Features Assignment Names and Settings on page 31

(7) Supported only in GPIO mode.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

23
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.4.1.1.2. RT OCT
The Agilex 3 devices support RT OCT with and without calibration. RT OCT is available
only for input and bidirectional pins. Output pins do not support RT OCT.

You must disable RT OCT for interfaces that require external termination circuitry near
the receiver of the Agilex 3 device.

Table 13. RT OCT Schemes

OCT Scheme Description

RT OCT without calibration • Available only on the input buffer.

• Receiver impedance matching provides the receiver with a controlled input impedance
that closely matches the impedance of the transmission line.

RT OCT with calibration • The RT OCT calibration circuit uses the impedance of the external resistor connected to
the RZQ pin as a reference.
• During calibration, the circuit continuously alters the impedance of the I/O buffer until
the value reaches the target impedance, which is a predetermined ratio to the
reference resistance.
• The calibration occurs at the end of the device configuration. When the calibration
circuit finds the correct impedance, the circuit stops changing the characteristics of the
drivers.
• In EMIF and MIPI D-PHY modes, you may trigger recalibration during user mode.

Figure 10. RT OCT with Calibration

Transmitter Receiving Device
V CCIO

2 × R T2

Z 0 = 50 Ω
V REF

2 × R T2

GND

Table 14. Selectable I/O Standards for RT OCT with Calibration

This table lists the output termination settings for calibrated OCT on different I/O standards. The default values
are in bold font.

I/O Standard RT OCT without Calibration(8) (Ω) RT OCT with Calibration (Ω)

1.3 V LVCMOS — —

1.2 V LVCMOS — —

1.1 V LVCMOS — —

1.05 V LVCMOS — —

1.0 V LVCMOS — —
continued...

(8) Supported only in GPIO mode.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

24
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

I/O Standard RT OCT without Calibration(8) (Ω) RT OCT with Calibration (Ω)

SSTL-12 50 50, 60

HSTL-12 50 50, 60

HSUL-12 — —

POD12 50 40, 50, 60

POD11 50 40, 50, 60

LVSTL11 50 40, 50, 60

LVSTL105 50 40, 50, 60

Differential SSTL-12 50 50, 60

Differential HSTL-12 50 50, 60

Differential HSUL-12 — —

Differential POD12 50 40, 50, 60

Differential POD11 50 40, 50, 60

Differential LVSTL11 50 40, 50, 60

Differential LVSTL105 50 40, 50, 60

Related Information
OCT Features Assignment Names and Settings on page 31

2.4.1.1.3. Dynamic OCT

Dynamic OCT is useful for terminating a high performance bidirectional path by
optimizing signal integrity depending on data direction. Dynamic OCT reduces power
usage because the termination switches on only during input operations.

Table 15. Dynamic OCT Based on Bidirectional I/O

Dynamic RT OCT or RS OCT switches on or off based on whether the bidirectional I/O acts as a receiver or
driver.

Dynamic OCT Bidirectional I/O State

Dynamic RT OCT Receiver On

Driver Off

Dynamic RS OCT Receiver Off

Driver On

(8) Supported only in GPIO mode.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

25
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 11. Dynamic RT OCT in Agilex 3 Devices

VCCIO VCCIO
Transmitter Receiver
100 Ω 2 x RT
Rs
Z0 = 50 Ω

100 Ω 2 x RT
Rs

GND GND

FPGA OCT FPGA OCT

VCCIO VCCIO
Receiver Transmitter
2 x RT 100 Ω
Rs
Z0 = 50 Ω

2 x RT 100 Ω
Rs

GND GND

FPGA OCT FPGA OCT

2.4.1.2. OCT Calibration Block

You can calibrate the OCT using the OCT calibration block available in each HSIO bank.
Only the 1.05 V, 1.1 V, and 1.2 V VCCIO_PIO banks can use the OCT calibration block.

The OCT calibration block can calibrate the I/O buffers located in the same HSIO
banks only. For example, you can use the OCT calibration block in bank 2A to calibrate
the I/O buffers in bank 2A only.

The OCT calibration process uses the RZQ pin that is available in every HSIO sub-bank
for series-calibrated and parallel-calibrated terminations.
• You can use the RZQ pin in one sub-bank to calibrate I/Os in the other sub-bank
within the same HSIO bank. For example, you can use the RZQ pin in the bottom
index sub-bank of bank 2B to calibrate the I/Os in the top index sub-bank of bank
2B. Both sub-bank must use the same VCCIO_PIO voltage value.
• The RZQ pin is a dual-purpose I/O pin and functions as a general-purpose I/O pin
if you do not use the calibration circuit.
• The RZQ pin shares the same VCCIO_PIO supply voltage with the I/O sub-bank
where the pin is located.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

26
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

The OCT calibration block has an external 240 Ω reference resistor associated with it
through the RZQ pin available in every sub-bank.
• Connect the RZQ pin to GND through an external 240 Ω resistor.
• For differential I/O standards, you must use the same RZQ resistor to calibrate
both the positive and negative legs of the differential I/O pin.
• You can use each RZQ resistor to calibrate two RS OCT settings and one RT OCT
setting for all I/O standards.

2.4.1.3. Single-Ended I/O Standards External Termination

The SSTL, HSTL, POD, and LVSTL I/O standards require a termination voltage. The
internally-generated reference voltage of the receiving device tracks the termination
voltage of the transmitting device.

Altera recommends that you use OCT with these I/O standards to save board space
and cost. OCT reduces the number of external termination resistors required.

Note: You cannot use RS and RT OCT simultaneously. For more information, refer to the
related information.

Table 16. I/O Standards Required External Termination

I/O Standard External Termination Scheme

1.3 V LVCMOS No on-board termination required

1.2 V LVCMOS No on-board termination required

1.1 V LVCMOS No on-board termination required

1.05 V LVCMOS No on-board termination required

1.0 V LVCMOS No on-board termination required

SSTL-12 Single-ended SSTL I/O standard termination

HSTL-12 Single-ended HSTL I/O standard termination

HSUL-12 No on-board termination required

POD12 Single-ended POD I/O standard termination

POD11 Single-ended POD I/O standard termination

LVSTL11 Single-ended LVSTL I/O standard termination

LVSTL105 Single-ended LVSTL I/O standard termination

Differential SSTL-12 Differential SSTL I/O standard termination

Differential HSTL-12 Differential HSTL I/O standard termination

Differential HSUL-12 No on-board termination required

Differential POD12 Differential POD I/O standard termination

Differential POD11 Differential POD I/O standard termination

Differential LVSTL11 Differential LVSTL I/O standard termination

Differential LVSTL105 Differential LVSTL I/O standard termination

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

27
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 12. SSTL and HSTL I/O Standards External Termination

VCCIO_PIO/2
RT
External
Termination in
Receiver Pins

FPGA On-Board Receiver

VCCIO_PIO

OCT Termination 2RT

in Receiver Pins
2RT

Transmitter On-Board GND FPGA

VCCIO_PIO VCCIO_PIO
Series V REF
OCT 2 RT 2 RT

OCT in
Bidirectional Pins 2 RT 2RT

GND GND Series

V REF OCT
On-Board
FPGA FPGA

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

28
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 13. POD I/O Standards External Termination

VCCIO
RT
External
Termination in
Receiver Pins

On-Board
FPGA Receiver

VCCIO

OCT Termination RT
in Receiver Pins

On-Board FPGA
Transmitter

VCCIO
VCCIO
Series
OCT RS Parallel
OCT RT
50 Ω V REF
OCT in
Bidirectional Pins
Series
V REF OCT RS
On-Board
FPGA FPGA

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

29
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 14. LVSTL I/O Standards External Termination

External
Termination in
Receiver Pins RT

FPGA On-Board GND Receiver

OCT Termination
in Receiver Pins
RT

Transmitter On-Board GND FPGA

Series
OCT RS RT
50 Ω V REF
OCT in GND
Parallel
Bidirectional Pins OCT RT
GND Series
V REF OCT RS
On-Board
FPGA FPGA

Related Information
Dynamic OCT on page 25

2.4.1.4. Single-Ended I/O Termination Implementation Guide

To implement I/O termination in your design, you can assign the termination for your
pin using the Quartus Prime Assignment Editor or through the External Memory
Interfaces (EMIF) IP and PHY Lite for Parallel Interfaces IP.

Related Information
Configuring OCT Using the Assignment Editor on page 30

2.4.1.4.1. Configuring OCT Using the Assignment Editor

1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor.
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select a supported termination feature.
4. Under the Value column, select a supported value.
5. From the Quartus Prime menu, select File ➤ Save.

Related Information
Single-Ended I/O Termination Implementation Guide on page 30

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

30
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.4.1.4.2. OCT Features Assignment Names and Settings

Table 17. Agilex 3 FPGAs OCT Assignment Names and Settings

OCT Feature Assignment Name Supported Values

RS with calibration Output Termination • Series 34 Ohm with Calibration

• Series 40 Ohm with Calibration
• Series 45 Ohm with Calibration
• Series 50 Ohm with Calibration

RS without calibration Output Termination • Series 34 Ohm without Calibration

• Series 40 Ohm without Calibration

RT with calibration Input Termination • Parallel 40 Ohm with Calibration

• Parallel 50 Ohm with Calibration
• Parallel 60 Ohm with Calibration

RT without calibration Input Termination • Parallel 50 Ohm without Calibration

• Parallel 60 Ohm without Calibration

Related Information
• RS OCT on page 21
Lists the supported RS OCT values for different I/O standards.
• RT OCT on page 24
Lists the supported RT OCT values for different I/O standards.

2.4.2. True Differential Signaling I/O Termination in Agilex 3 Devices

All HSIO banks have dedicated circuitry to support true differential I/O standards by
using the True Differential Signaling, DPHY, or SLVS-400 differential buffers without
resistor networks.

The True Differential Signaling buffer is compatible with the LVDS, RSDS, Mini-LVDS,
and LVPECL standards. The True Differential Signaling, DPHY, and SLVS-400 buffers
support 100 Ω differential on-chip termination (RD OCT). If you use an SLVS-400 or
DPHY receiver:
• The RD OCT is calibrated and always enabled.
• You must connect a 240 Ω RZQ resistor

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

31
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 15. True Differential Signaling I/O Standard Termination

Termination True Differential Signaling

Differential Outputs Differential Inputs

External
50 Ω
On-Board
100 Ω
Termination
50 Ω

Differential Outputs Differential Inputs

OCT

50 Ω
OCT Receiver 100 Ω
50 Ω

Receiver

Figure 16. SLVS-400 and DPHY I/O Standards Termination

Termination SLVS-400 / DPHY

Differential Outputs Differential Inputs

OCT

50 Ω
OCT Receiver
100 Ω
50 Ω

Receiver

Use OCT with these I/O standards to save board space and cost. OCT reduces the
number of external termination resistors usage.

Related Information
• Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the
banks shared with the HPS and SDM, the DQ groups, the pin functions, and the
pin locations.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

32
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

• AN 555: True Differential Signaling Termination and Biasing for Agilex 7 M-Series
and Agilex 5 FPGAs
Provides useful information that you can also apply to Agilex 3 devices.

2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination

All I/O pins and dedicated clock input pins located in the HSIO banks of Agilex 3
devices support on-chip differential termination (RD OCT). The Agilex 3 devices
provide a 100 Ω on-chip differential termination option on each differential receiver
channel for the True Differential Signaling, DPHY, and SLVS-400 I/O standards.

Figure 17. OCT for Differential I/O Termination

Differential Receiver
Differential with On-Chip 100 Ω
Transmitter Termination
Z 0 = 50 Ω

RD

Z 0 = 50 Ω

2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor

Table 18. Differential Input RD OCT in Quartus Prime Assignment Editor Settings
To Assignment Name Value

rx_in Input Termination Differential

1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor.

2. Under the To column, search for the input pin that you want to configure.
3. Under the Assignment Name column, select Input Termination.
4. Under the Value column, select Differential.
5. From the Quartus Prime menu, select File ➤ Save.

2.4.2.1.2. Guidelines: Differential Input RD OCT

Disable RD OCT for interfaces that require external voltage bias circuitry near the true
differential receivers of Agilex 3 devices.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

33
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 18. External Voltage Bias Circuitry with RD OCT Disabled

True Differential True Differential
Transmitter Receiver

0.1 µF
Z 0 = 50 Ω V ICM 50 Ω
0.1 µF RD
Z 0 = 50 Ω 50 Ω

Disable

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

34
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.4.2.2. True Differential Signaling I/O Standard External Termination

Analyze the electrical specification requirement of the LVDS interface and ensure the
common-mode voltage for your LVDS data rate conforms to the data sheet
specification.
• Use AC coupling and external voltage bias circuitry if the common-mode voltage of
the output buffer does not match the differential receiver input common-mode
voltage.
• Consider using a dedicated VICM voltage supply for wide LVDS interfaces that share
a common VICM reference voltage.

Note: Altera recommends that you use SPICE or IBIS models to verify your AC- or
DC-coupled termination.

Figure 19. Example of AC-Coupled External VICM Termination

True Differential True Differential
Transmitter Receiver

0.1 µF
Z 0 = 50 Ω V ICM 50 Ω
0.1 µF
Z 0 = 50 Ω 50 Ω

Figure 20. Example of AC-Coupled External Termination for 1.3 V VCCIO_PIO

1.3 V VCCIO_PIO
True Differential True Differential
Transmitter Receiver

10 KΩ 10 KΩ

0.1 µF

100 Ω
0.1 µF 10 KΩ On-Board Differential
Termination

10 KΩ

Related Information
• HSIO Differential I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device
Data Sheet
Provides the VICM specifications for the True Differential Signaling I/O standard.
• AN 555: True Differential Signaling Termination and Biasing for Agilex 7 M-Series
and Agilex 5 FPGAs
Provides useful information that you can also apply to Agilex 3 devices.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

35
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.5. HSIO Design Guidelines

Different functions of the HSIO pins have different guidelines, placement restrictions,
connection requirements, and clocking requirements.

Related Information
Pin Connection Guidelines: Agilex 3 FPGAs and SoCs
Provides descriptions of the pins available in the device and relevant connection
guidelines.

2.5.1. I/O Standard Placement Restrictions for True Differential I/Os

Adhere to these placement guidelines for the true differential I/Os.
• Do not place LVSTL, SLVS-400, or DPHY I/O standard in the same I/O lane as the
True Differential Signaling I/O standard.
• You can place True Differential Signaling I/O standard in the same I/O lane as
LVSTL I/O standard only if you use the True Differential Signaling input as a
reference clock.
• If you use the SLVS-400, DPHY, or 1.05 V, 1.1 V, or 1.2 V True Differential
Signaling I/O standard, you can place only the LVCMOS I/O standard in the same
I/O lane.

2.5.2. Placement Restrictions for True Differential and Single-Ended I/O

Standards in the Same or Adjacent HSIO Bank
If you use true differential I/O standards and single-ended I/O standards in the same
HSIO banks, adhere to the following placement guidelines.

• Do not place true differential and toggling single-ended I/O standards in the
combinations of locations listed in the following tables.
• The Quartus Prime software issues this error message:

Compilation error—violation of the same bank placement restriction.

From Quartus Prime software version 25.1.1 onwards, you can place true differential
and single-ended I/O standards in the combinations of locations listed in the following
table for the two scenarios listed below:
• The receiver equalization calibration is enabled for the affected true differential
input buffers.
• The single-ended I/O is a non-toggling pin. You must use the following .qsf in
your Quartus design to exclude the non-toggling pins in the Quartus Prime
placement rules check:
set_instance_assignment -name TOGGLE_SPEED TOGGLE_SPEED_SLOW -to <pin name>

For example:
set_instance_assignment -name TOGGLE_SPEED TOGGLE_SPEED_SLOW -to din

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

36
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Table 19. Restricted Pin Placement Combinations for True Differential and Single-Ended
I/O Standards in the Same HSIO Bank

This table lists the combinations of pins and I/O standards not allowed in the same HSIO bank. Examples:
• If you place a true differential I/O standard in pin pair 10 and 11, do not place single-ended I/O standards
in pins 8 or 19.
• If you place a single-ended I/O standard in pin 57 or 67, do not place a true differential I/O standard in
pin pair 58 and 59.

Combinations Not Allowed Combinations Not Allowed Combinations Not Allowed Combinations Not Allowed
(Pin Index Number) (Pin Index Number) (Pin Index Number) (Pin Index Number)

True Single- True Single- True Single- True Single-

Differential Ended Pin Differential Ended Pin Differential Ended Pin Differential Ended Pin
Pin Pair Pin Pair Pin Pair Pin Pair

0 and 1 3, 4 24 and 25 27, 28 48 and 49 51, 52 72 and 73 75, 76

2 and 3 0 26 and 27 16, 24 50 and 51 40, 48 74 and 75 64, 72

4 and 5 1, 15 28 and 29 25, 39 52 and 53 49, 63 76 and 77 73, 87

6 and 7 9 30 and 31 22, 32 54 and 55 46, 56 78 and 79 70, 80

8 and 9 6, 11 32 and 33 31, 34 56 and 57 55, 58 80 and 81 79, 82

10 and 11 8, 19 34 and 35 33, 43 58 and 59 57, 67 82 and 83 81, 90

12 and 13 14, 17 36 and 37 38, 41 60 and 61 62, 65 84 and 85 86, 89

14 and 15 5, 12 38 and 39 29, 36 62 and 63 53, 60 86 and 87 77, 84

16 and 17 13, 26 40 and 41 37, 50 64 and 65 61, 74 88 and 89 85

18 and 19 10, 21 42 and 43 35, 45 66 and 67 59, 69 90 and 91 83, 92

20 and 21 18, 23 44 and 45 42, 47 68 and 69 66, 71 92 and 93 91, 94

22 and 23 20, 30 46 and 47 44, 54 70 and 71 68, 78 94 and 95 93

2.5.3. VREF Sources and Input Standards Grouping

Consider these VREF sources guidelines.

Agilex 3 devices support internal VREF sources. Each I/O lane in the bank also has its
own internal VREF generator. You can configure VREF generator in the External Memory
Interfaces (EMIF) IP and PHY Lite for Parallel Interfaces IP.

In each I/O lane, adhere to the input standards grouping to ensure all input pins in
the I/O lane use the same internal VREF source. If the mix of input standards in an I/O
lane does not adhere to these groupings, Quartus Prime displays error messages
during design compilation.

Note: Although the following table lists the groups based on VREF, the final rules depend on
implementation. For example, the PHY Lite interface uses one I/O standard per I/O
lane. If you use HSTL-12 and SSTL-12 with the PHY Lite for Parallel Interfaces IP,
assign each I/O standard in a different I/O lane.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

37
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Table 20. Input Standards Groups Per I/O Lane

Group Input Standards Mix within I/O Lane

Group 1 • POD12
• 1.2 V True Differential Signaling
• 1.2 V LVCMOS
• Differential POD12

Group 2 • POD11
• 1.1 V True Differential Signaling
• 1.1 V LVCMOS
• Differential POD11

Group 3 • SSTL-12
• HSTL-12
• HSUL-12
• 1.2 V True Differential Signaling
• 1.2 V LVCMOS
• Differential SSTL-12
• Differential HSTL-12
• Differential HSUL-12

Group 4 • LVSTL11
• 1.1 V LVCMOS
• Differential LVSTL11

Group 5 • LVSTL105
• 1.05 V LVCMOS
• Differential LVSTL105

Related Information
I/O Standard Selection and I/O Bank Supply Compatibility Check on page 39

2.5.4. HSIO Pin Restrictions for External Memory Interfaces

In specific external memory interface implementations, some HSIO pins are not
usable. For details, refer to the External Memory Interfaces (EMIF) IP User Guide:
Agilex 3 FPGAs and SoCs.

2.5.5. RZQ Pin Requirement

There is one RZQ pin per I/O sub-bank. The RZQ pins are dual-purpose pins, and can
be used as GPIO if you do not use OCT calibration.

Adhere to the following guidelines if you use the RZQ pin:

• To use the RZQ pins for OCT calibration, connect a 240 Ω precision resistor with a
±1% tolerance to the pins.
• You cannot place the RZQ pin in an I/O lane with any input standard except
LVCMOS or True Differential Signaling input buffer.

2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages

The following guidelines apply to I/O standards based on the VCCIO_PIO voltages.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

38
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

1.2 V, 1.1 V, or 1.05 V VCCIO_PIO

If you use a 1.2 V, 1.1 V, or 1.05 V VCCIO_PIO, you can implement single-ended non-
voltage referenced and voltage-referenced I/O standards. The 1.2 V, 1.1 V, or 1.05 V
buffer also supports differential voltage-referenced I/O and true differential input
standards.

You can implement a mix of both voltage-referenced and non-voltage referenced I/O,
and true differential input standards within the I/O bank if all the I/O standards
support the VCCIO_PIO of the I/O bank.

1.3 V VCCIO_PIO

If you use a 1.3 V VCCIO_PIO voltage, you can implement both 1.3 V LVCMOS and True
Differential Signaling I/O standards in the same I/O lane and sub-bank. The buffer can
interface with upstream or downstream devices that are compatible with the Agilex 3
FPGAs electrical specifications.

If you use True Differential Signaling input, analyze the electrical specification
requirement to implement your true differential receiver.

Implement DC coupling if the signal swing and VICM voltage requirement are within the
Agilex 3 True Differential Signaling standard specification. Otherwise, implement AC
coupling and external bias circuitry.

Related Information
I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the electrical specifications for the supported I/O standards.

2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
• Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks
are located in rows along the top periphery and bottom periphery of the device.
Each I/O bank has two sub-banks. Each sub-bank has its own PLL, DPA and
SERDES circuitries, and individual VCCIO_PIO voltage rail.
• Ensure that the selected I/O standard is supported in the targeted I/O sub-bank.
• Place I/O pins that share the same VCCIO_PIO voltage levels in the same I/O sub-
bank.
• Verify that all output signals in each I/O sub-bank are intended to drive out at the
sub-bank's I/O voltage level.
• Verify that all voltage-referenced signals in each I/O lane are intended to use the
same VREF source by adhering to the voltage-referenced input standards grouping
per I/O lane.

Related Information
VREF Sources and Input Standards Grouping on page 37

2.5.8. Simultaneous Switching Noise

Considering simultaneous switching noise (SSN) impact on the design, use differential
I/O standards and lower voltage I/O standards for high-switching I/O pins. Place clock
signals, RZQ pins, and asynchronous control signals near ground signals and away
from large switching buses.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

39
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.5.9. HPS Shared I/O Requirements

The HPS external memory interface uses I/O pins located in the HSIO bank instead of
the HPS I/O bank. The VCCIO_PIO powers the HSIO bank instead of the 1.8 V VCCIO_HPS.
For the location of the HPS shared HSIO pins, refer to device pin-out files.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

2.5.10. Clocking Requirements

In your clocking scheme, use the dedicated clock pins for I/O PLL reference clock or as
output clock for better jitter performance.

You must use the True Differential Signaling input standard for the I/O PLL reference
clock.

2.5.11. Clock Restrictions for GPIO Interfaces

Adhere to these clock sharing guidelines when designing with multiple TX or multiple
RX registers in the same I/O lane.
• When placing multiple TX or multiple RX SDR registers in the same I/O lane, you
must use the same reference clock to drive these TX or RX registers. This rule
applies when the register packing option is enabled in your FPGA design.
• When placing multiple TX or multiple RX DDIO registers in the same I/O lane, you
must use the same reference clock to drive these registers.

2.5.12. SDM Shared I/O Requirements

The Avalon® streaming interface ×16 configuration modes use the configuration pins
located in an HSIO bank for device configuration. The VCCIO_PIO voltage rail, instead of
the VCCIO_SDM voltage rail, powers the HSIO bank.

When you use Avalon streaming interface ×16 configuration scheme, Avalon
streaming interface pins in the SDM shared IO bank are not usable as user I/Os for:
• Designs that use external partial reconfiguration, for example, designs that send
partial reconfiguration bitstream using Avalon streaming interface pins.
• Designs that use the HPS.

Related Information
Agilex 3 Configuration Pins, Device Configuration User Guide: Agilex 3 FPGAs and
SoCs
Provides more details about the I/O setting and restrictions on the pins during
device configuration.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

40
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.5.13. Unused Pins

Unused I/O pins are configured as input tri-stated with no weak pull-up. If the entire
HSIO bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or
connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside
in an active HSIO bank, you may leave these pins floating or connected to a tri-stated
upstream or downstream I/O pin.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

2.5.14. VCCIO_PIO Supply for Unused HSIO Banks

When the entire HSIO bank is unused, you may connect the VCCIO_PIO pin of the
unused HSIO bank to 0 V, 1.0 V, 1.05 V, 1.1 V, 1.2 V, or 1.3 V.

If only one of the sub-banks within the same HSIO bank is unused, you must connect
the VCCIO_PIO pin of the unused sub-bank to the same VCCIO_PIO voltage level as
the other actively utilized sub-bank. You must use following .qsf to assign the
VCCIO_PIO of the unused sub-bank to the intended voltage supply value.
set_global_assignment -name IOBANK_VCCIO <voltage supply> -section_id
<sub_bank_name>

Example:
set_global_assignment -name IOBANK_VCCIO 1.1V -section_id 3B_B

2.5.15. HSIO Pins During Power Sequencing

Agilex 3 devices do not support hot-socketing and require a specific power sequence.
Design your power supply solution to properly control the complete power sequence.

Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins
located in the HSIO banks. These guidelines apply for unpowered, power up to power-
on reset (POR), POR delay, POR delay to configuration, configuration, initialization,
user mode, and power down device states.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

41
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

• The I/O pins in the HSIO banks can be tri-stated, driven to ground, or driven to
the VCCIO_PIO level.
• While the device is powering up or down:
— The input signals of an I/O pin, at all times, must not exceed the I/O buffer
power supply rail of the bank where the I/O pin resides.
— If you use a pin in a HSIO bank with 1.3 V VCCIO_PIO, the pin voltage must not
exceed the VCCIO_PIO rail or 1.2 V, whichever is lower.
• While the device is powering up or powering down, the HSIO pins can tolerate a
maximum of 10 mA per pin and a total of 100 mA per HSIO bank.
• While the device is not turned on, tri-state the I/O pin and do not drive the pin
with any external voltage.
• After the device fully powers up, the voltage levels for the HSIO pins must not
exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Table 21. Guideline Examples

Condition Guideline

The VCCIO_PIO pin ramps up and at period X, the At period X, keep the signals driven by the device connected to
VCCIO_PIO voltage is 1.1 V. the HSIO I/O pin at a voltage of 1.1 V or lower.

The 1.3 V VCCIO_PIO pin ramps up and the voltage Keep the HSIO pin voltage at 1.2 V or lower until the device fully
continues to rise pass the 1.2 V level. powers up.

2.5.16. Drive Strength Requirement for HSIO Input Pins

Each HSIO input pin with programmable pull-up feature turned on requires 1 mA of
drive strength. The connected output buffer must provide a minimum of 1 mA to the
pin.

If an output buffer drives two input pins, the output buffer must provide 2 mA to the
input pins. Increase the drive strength current according to the number of input pins
the output buffer drives.

If you connect an output buffer to multiple input pins and one of the input pins has
programmable pull-up feature enabled, you must turn on the same programmable
feature on all of the other input pins.

2.5.17. Maximum DC Current Restrictions

While using Agilex 3 HSIO pins, adhere to the maximum allowed duration of the per
pin DC current limit.

Table 22. Maximum Allowed Duration of DC Current Limit

DC Current Limit Maximum Allowed Duration (%)

±7.5 mA 100%

±10 mA 75%

±15 mA 50%

More than ±15 mA Not allowed

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

42
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Related Information
• Absolute Maximum Ratings, Agilex 3 FPGAs and SoCs Device Data Sheet
Lists the absolute maximum ratings for DC output current.
• DC Characteristics, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides more information related to DC current specifications.

2.5.18. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility

Evaluate the electrical signal level compatibility between Agilex 3 1.05 V, 1.1 V, or
1.2 V output and the downstream device. Ensure that the VOH and VOL voltages of the
1.05 V, 1.1 V, or 1.2 V output buffer conform to the VIH and VIL specifications of the
receiving buffer of the downstream device.

Example 1. 1.2 V LVCMOS I/O Standard Voltage Swing Calculation

If you use the 1.2 V LVCMOS I/O standard, the output signal swings from 0 V to 1.2 V
on a lossless transmission line with no external pull-up or pull-down component.
Ensure that the VIH or VIL tolerance of the downstream connecting device can meet
those conditions.

Example 2. 1.2 V Voltage-Referenced I/O Standards Voltage Swing Calculation

If you use the 1.2 V voltage-referenced I/O standards, the output signal swing has a
dependency on the external board termination or the internal termination of the
receiver.

Figure 21. Termination Setup Using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up
Resistor to VCCIO_PIO/2
This figure shows an example termination setup and its equivalent circuit.
VCCIO/2
Rs OCT
40 Ω 50 Ω

FPGA On-Board Receiver

Rs OCT Termination

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

43
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Figure 22. Equivalent Circuit of the Example with Output Buffer Driving HIGH
When the output buffer is driving HIGH, the pin voltage is 0.93 V based on voltage divider rule:
1.2 V−Pin Voltage Pin Voltage−0.6 V
( = ).
40 50
1.2 V 0.6 V

40 Ω 50 Ω

Output buffer = HIGH

Figure 23. Equivalent Circuit of the Example with Output Buffer Driving LOW
When the output buffer is driving LOW, the pin voltage is 0.27 V based on the voltage divider rule:
0.6 V−Pin Voltage Pin Voltage
( = ).
50 40
0.6 V

50 Ω

40 Ω

Output buffer = LOW

2.5.19. Connection to True Differential Signaling Input Buffers During

Device Reconfiguration
You can reconfigure Agilex 3 FPGAs at any time during user mode. Follow these
guidelines for connection from an external device driving the True Differential
Signaling input buffer during reconfiguration of Agilex 3 FPGAs.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

44
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Table 23. True Differential Signaling Input Buffer Reconfiguration Guidelines

True Differential Signaling Input External Connection Guidelines
Buffer Mode After Reconfiguration

Same mode as before FPGA The external device can continue to drive the True Differential Signaling input
reconfiguration buffer during reconfiguration of the FPGA.

Different mode after FPGA • Before you start reconfiguration of the FPGA, ensure that the external device
reconfiguration tri-states the connection.
• The external device can initiate a new connection to the True Differential
Signaling input buffer after successful reconfiguration of the FPGA.

2.5.20. Implementing a Pseudo Open Drain

Apply this method to implement a pseudo open drain for Agilex 3 devices using the
LVCMOS I/O standard.

Figure 24. Pseudo Open Drain Connection

Output Data

1. Use the GPIO IP to initiate an output or bidirectional buffer with the OE turned on.
2. Connect the input port of the output buffer to the ground.
3. Connect the actual data signal to the OE port.

Note: Drive the buffer LOW before you switch the OE signal. When you switch the OE signal
to HIGH, the output pin drives LOW. When you switch the OE signal to LOW, the output
pin is tri-stated. You need an external pull-up circuitry to pull the connection to HIGH.

2.5.21. Allowed Duration for Using RT OCT

When you use RT OCT, adhere to the maximum allowed duration for enabling the RT
OCT based on pin utilization per I/O bank.

This guideline applies to the following I/O standard when operating in GPIO or PHY
Lite modes:
• SSTL-12 and Differential SSTL-12
• HSTL-12 and Differential HSTL-12
• HSUL-12 and Differential HSUL-12

Table 24. Maximum Allowed RT OCT Duration

Number of Pins In Use Per I/O Bank Maximum Allowed RT OCT Duration
(With RT OCT Turned On) (%)

32 100

38 90

48 80

58 70

96 60

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

45
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction

If you use single-ended external memory interface or PHY Lite strobe signal, such as
DQS, leave the remaining positive or negative leg of the differential pin pair as an
unused pin.

For example, if you assign a single-ended external memory interface strobe signal to
pin function DIFF2B_T_1P, ensure that the other leg of the pair, pin function
DIFF2B_T_1N, is left unused.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V

VCCIO_PIO
If you use the SLVS-400 or DPHY I/O standard, Quartus Prime sets a default 1.2 V
VCCIO_PIO to the sub-bank. To use SLVS-400 or DPHY at 1.1 V, set the sub-bank's
VCCIO_PIO to 1.1 V through the Quartus Prime settings file (.qsf).

set_global_assignment -name IOBANK_VCCIO 1.1V -section_id <sub_bank_name>

Example:
set_global_assignment -name IOBANK_VCCIO 1.1V -
section_id 3B_B

2.6. HSIO Simulation

Altera provides several types of simulation models for Agilex 3 devices.

These simulation models are:

• Synopsys* HSPICE* models
• IBIS models
• IBIS AMI models

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

46
2. Agilex 3 HSIO Banks
847266 | 2025.08.04

Table 25. Simulation Models Descriptions

Model Supported I/O Description
Type

HSPICE HSIO • Simulates actual transistor level design to obtain precise electrical simulation.
• The syntax describes I/O buffers, board components and connections, and specific
simulation parameters.
• The model contains encrypted transistor and logic cell library models, output buffer
circuit models for single-ended and differential I/Os, and sample SPICE decks for
single-ended and differential I/Os.
• The model requires a longer simulation time compared to the IBIS model.

IBIS HSIO • This is a behavioral model of the I/O buffers based on the I/V curve data derived
from the HSPICE simulation.
• The pre-emphasis feature is an example that can use the IBIS simulation model.
• This model has a shorter simulation time compared to HSPICE.
• The simulation model has less complexity compared to HSPICE models and
supported by many simulation tools.

IBIS AMI Transceiver I/O • Algorithmic Modeling Interface (IBIS AMI) is a part of IBIS 5.0 specification for
high-speed transmitter and receiver models that are supplied as executables in
tools that support IBIS simulation.
• This is an industry standard model methodology for high-speed link simulation
applied to multi gigabit serial link channels.
• This simulation model allows simulation of millions of bits in minutes, crosstalk and
jitter analysis, detect data pattern dependencies, and able to model complex blocks
such as equalization and CDR.

2.6.1. IBIS Models—HSIO Support

You can use the Agilex 3 IBIS model to perform system-level simulations for various
I/O configurations across three predefined process, voltage, and temperature settings.

The Agilex 3 IBIS model kit contains the following information:

• IBIS model file (.ibs)
• User guide that describes the model usage
• Model list sheet that lists the supported I/O feature for each model
• Package RLC report that provides the lumped package RLC values for each
supported Agilex 3 variant

You can use the Agilex 3 IBIS model to simulate all valid I/O features configurations
across all supported I/O standards:

• Slew rate
• Weak pull-up
• De-emphasis
• Pre-emphasis
• Differential output voltage

Related Information
IBIS Models for FPGA Devices

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

47
 2. Agilex 3 HSIO Banks
847266 | 2025.08.04

2.6.2. IBIS-AMI Models

You can use the Agilex 3 IBIS AMI models to perform system-level simulations for
LPDDR4 interfaces across three predefined process, voltage, and temperature
settings.

2.6.3. HSPICE Models

You can use the Agilex 3 SPICE model to perform system-level simulations for various
configurations. The SPICE kits provide models that support a wide variety of I/O
features across process, voltage, and temperature (PVT)

Each SPICE kit contains the following items:

• Encrypted transistor and logic cell library models
• Encrypted input or output buffer circuit models for single-ended and differential
I/Os
• Single-ended and differential sample SPICE decks
• User guide that describes the model usage

The HSPICE models provide options to simulate buffer behavior for the following I/O
features:
• RS OCT with and without calibration
• RT OCT with calibration

Related Information
Accessing HSPICE Simulation Kits, Quartus Prime Pro Edition User Guide: PCB Design
Tools

2.6.4. Net Length Reports

The net length information consists of the package trace delay from the die pad to the
package pin. Each pin in an FPGA package has its own net length information. This
information is important for you to perform board trace compensation to optimize the
channel-to-channel skew on your board design.

Related Information
Agilex 3 Device Package Net Length Report
Downloads the net length reports for Agilex 3 devices.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

48
 847266 | 2025.08.04

Send Feedback

3. Agilex 3 HVIO Banks

The HVIO banks are available in all Agilex 3 devices.

The HVIO banks provide single-ended I/O buffers that support 1.8 V, 2.5 V, or 3.3 V
I/O voltages. You must assign all I/Os within one HVIO bank with the same I/O
standard.

Related Information
• Types of I/O Banks on page 7
• Device Migration Guidelines: Agilex 3 FPGAs and SoCs

3.1. HVIO Bank Overview

Each HVIO block contains two banks with 20 single-ended I/O pins in each bank.

Additionally, each HVIO block also contains dedicated fabric-feeding PLL.

The total number of HVIO banks varies across different device packages. Refer to the
device pin-out files for the HVIO banks availability and locations in each device
package.

Related Information
Supported I/O Standards for HVIO Banks on page 51

3.1.1. HVIO Bank Structure

Figure 25. Agilex 3 HVIO Bank Structure (Die Top View)
This figure shows the HVIO bank structure of the Agilex 3 device. The figure shows the view of the die as
shown in the Quartus Prime Chip Planner. In the Pin Planner, this corresponds to the "Bottom View".
Different device packages have different number of HVIO banks. Refer to the device pin-out files for HVIO
banks availability and locations for each device package.

HVIO I/O Group I/O Pin 0 19 Pin ID

Block
HVIO
HVIO Bank HVIO Bank
Block 0 0
HVIO
Fabric-Feeding PLL

Block
HVIO HVIO I/O Group I/O Group
HVIO
Block Block
Availability of HVIO banks varies among 19 19
devices. Refer to pinout files.

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

3.1.2. HVIO Buffers and Registers

The I/O registers consist of three different paths.
• The input path for handling data from the input pin to the core
• The output path for handling data from the core to the output pin
• The output enable (OE) path for handling the OE signal to the output buffer

The I/O registers allow fast source-synchronous register-to-register transfers and

resynchronizations. To use the I/O registers to implement DDR circuitry, you can use
the GPIO FPGA IP.

The input and output paths contain the following blocks:

• Input registers:
— Support full rate data transfer from the periphery to the core
— Support double or single data rate data captured from I/O buffer to the core
• Output registers:
— Support full rate data transfer from the core to the periphery
— Support double or single data rate data transfer to the output pin
• OE registers:
— Support the output enable signal from the core to the periphery
— Support double data rate or single data rate data transfer to the I/O pin

The input and output paths also support the following features:
• Clock enable
• Asynchronous or synchronous reset
• Delay chain on input and output paths

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

50
3. Agilex 3 HVIO Banks
847266 | 2025.08.04

Figure 26. I/O Element (IOE) Structure of Agilex 3 HVIO

OE from Core
OE
D Q Delay Chain
Td VCCIO_HVIO
Write Data from Core [0]
Programmable
D Q Pull-Up Resistor

Output
Write Data from Core [1] Delay Chain
D Q 2 x Td
Full Rate Outclock

To Core
Programmable
Input Register Pull-Down Resistor
Input
Read Data to Core [0] Alignment Q D Delay Chain
Registers

Read Data to Core [1]

Q D Q D

Full Rate Inclock Input Register Input Register

3.2. HVIO Features

The I/O bank within the HVIO interface supports 1.8 V, 2.5 V, and 3.3 V LVCMOS and
LVTTL I/O standards.

Power Pins for the HVIO Buffers

The VCCIO_HVIO and VCCPT_HVIO pins power the I/O buffers located in the I/O bank
within the HVIO interface.

HVIO Buffer Features

• Single-ended I/O buffers—support LVCMOS and LVTTL I/O standards
• Programmable current strength
• Programmable weak pull-up and pull-down resistor
• Programmable open-drain output
• Programmable delay chain

Related Information
Supported I/O Standards for HVIO Banks on page 51

3.2.1. Supported I/O Standards for HVIO Banks

The VCCIO_HVIO, VCCPT_HVIO, and VCC power supplies power the HVIO buffers. Each
HVIO bank has its own VCCIO_HVIO power supply, but shares VCCPT_HVIO and VCC power
supplies between the HVIO banks and with other blocks.

The HVIO bank supports 1.8 V, 2.5 V, and 3.3 V VCCIO_HVIO. In the bank, you can
implement I/O standards that support the bank's VCCIO_HVIO.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

51
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

Table 26. HVIO Bank Supported I/O Standards

This table lists the input and output voltages of a HVIO bank. To use the LVTTL I/O standards on the hardware,
assign the equivalent LVCMOS I/O standards in the Quartus Prime software.

I/O Standard VCCIO_HVIO (V) VCCPT_HVIO JEDEC Standard

(V)
Input Output

1.8 V LVCMOS/LVTTL 1.8 1.8 1.8 JESD8-31

2.5 V LVCMOS/LVTTL 2.5 2.5 1.8 JESD8-12A.01

3.3 V LVCMOS/LVTTL 3.3 3.3 1.8 JESD8-B

Related Information
• I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the electrical specifications for the supported I/O standards.
• Assigning Pin I/O Standards in the Quartus Prime Assignment Editor on page 55
• Assigning Pin I/O Standards in the Quartus Prime Pin Planner on page 56

3.2.2. Dedicated Features of HVIO Pins

In the HVIO bank, each I/O pin provides dedicated features such as System PLL
reference clock, PERST, clock source for RGMII, and Fabric-Feeding I/O PLL.

For more information about the dedicated features of the HVIO pins refer to the
related information.

Related Information
• Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the
banks shared with the HPS and SDM, the DQ groups, the pin functions, and the
pin locations.
• Pin Connection Guidelines: Agilex 3 FPGAs and SoCs
Provides descriptions of the pins available in the device and relevant
connection guidelines.
• GTS Transceiver PHY User Guide: Agilex 3 FPGAs and SoCs

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

52
3. Agilex 3 HVIO Banks
847266 | 2025.08.04

3.2.3. HVIO Buffer Behavior

Table 27. HVIO Pins Guideline for Different Pin States
HVIO Pin State

Not turned on Powering up Fully powered up Configuration User mode Powering down
mode

Either tristate the • Pin voltage All pins are tri- All pins are tri- Valid data • Pin voltage
pins or do not must not stated. stated. transactions can must not
drive them with exceed be initiated. exceed
any external VCCIO_HVIO.(9) VCCIO_HVIO.(9)
voltage. • After full • When the
VCCIO_HVIO VCCIO_HVIO and
power up, the VCC power rails
pins are tri- are powering
stated. down, the I/O
pin signals
measure
between
ground and
the VCCIO_HVIO
voltage levels.

Note: After the Agilex 3 device fully powers up, the voltage levels for the HVIO pins must
not exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Related Information
Agilex 3 FPGAs and SoCs Device Data Sheet

3.2.4. Programmable I/O Element Features for the HVIO Bank

Table 28. Programmable IOE Feature Settings for Agilex 3 HVIO Bank
This table lists the I/O standards that the feature supports and the available settings for each I/O standard.

I/O Standard Programmable IOE Feature

Current Strength Weak Pull-up/Pull-down(10) Open-Drain I/O Delay

1.8 V LVCMOS • 3 mA • Disabled (Default) • Enabled Refer to

• 6 mA • Weak pull-up with 20 kΩ resistor • Disabled the device
2.5 V LVCMOS (Default) datasheet.
• 9 mA • Weak pull-down with 20 kΩ resistor
3.3 V LVCMOS • 12 mA (Default)

Related Information
• Agilex 3 FPGAs and SoCs Device Data Sheet
• Programmable I/O Features Description on page 99

3.2.4.1. Guidelines: Programmable Open-Drain Output

If you enable the open-drain output feature, follow these guidelines.

(9) VCCIO_HVIO refers to the onboard real-time voltage supply.

(10) The weak pull-up/pull-down feature is available only for the input buffer.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

53
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

• Do not pull the output voltage higher than the VI (DC) level.
• Intel recommends that you use an external pull-up resistor higher than 2 kΩ.

Related Information
Programmable I/O Features Description on page 99

3.3. HVIO Implementation Guide

The Quartus Prime software provides tools for you to create, configure and compile
your I/O design. Each tool provides different functions and supports different features
to implement your I/O design.

Table 29. Quartus Prime I/O Implementation Tools

Tool Functions Supported Assignment Supported I/O
Standards

Assignment • View, create and edit assignments. • I/O standard • 1.8 V LVCMOS
Editor • The Quartus Prime software: • Programmable current strength • 2.5 V LVCMOS
— Dynamically validates your edits. • Programmable weak pull-up and • 3.3 V LVCMOS
— Notify you of errors and warnings of pull-down resistor
invalid assignments.

Pin Planner • Graphically represent pin locations on • I/O standard

the device. • Programmable current strength
• With this tool, you can: • Programmable weak pull-up and
— Perform initial pin planning. pull-down resistor
— Locate, place, and assign I/O pins.
— Configure board trace models for
pins you select for signal integrity
evaluations.

GPIO FPGA • Instantiate the IP. Programmable open-drain output

IP • Customize your IP instance using —
parameters options.

3.3.1. I/O Assignments with the Quartus Prime Assignment Editor

You can assign all instance-specific settings and constraints through the Quartus Prime
Assignment Editor. You can filter assignments by node name or category.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

54
3. Agilex 3 HVIO Banks
847266 | 2025.08.04

Figure 27. Quartus Prime Assignment Editor

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

3.3.1.1. Assigning Pin I/O Standards in the Quartus Prime Assignment Editor
1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select I/O Standard (Accepts
wildcards).
4. Under the Value column, select the I/O standard that you want to assign to the
pin.
5. From the Quartus Prime menu, select File ➤ Save.

Related Information
Supported I/O Standards for HVIO Banks on page 51

3.3.1.2. Assigning Programmable IOE Features in the Quartus Prime Assignment

Editor
1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select a supported programmable IOE
feature.
4. Under the Value column, select a supported value.
5. From the Quartus Prime menu, select File ➤ Save.

Related Information
HVIO Programmable IOE Features Assignment Names and Settings on page 56
Provides a list of supported programmable IOE features for the HVIO, the
assignment names, and supported values.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

55
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

3.3.1.3. HVIO Programmable IOE Features Assignment Names and Settings

Table 30. HVIO Programmable IOE Features Assignment Names and Settings
This table lists the programmable IOE features assignment names and values that you can specify in the
Quartus Prime Assignment Editor and Pin Planner tools.

Feature Assignment Name Supported Values

Current strength Current Strength • 3mA

• 6mA
• 9mA
• 12mA (default)

Weak pull-up/pull-down Weak Pull Up/Down • No Pull Up or Down (Default)

resistor(11) • Pull Down 20 kOhm
• Pull Up 20 kOhm

Related Information
Assigning Programmable IOE Features in the Quartus Prime Assignment Editor on
page 55

3.3.2. Assigning Pin I/O Standards in the Quartus Prime Pin Planner
You can use the Quartus Prime Pin Planner for I/O pin planning, assignment, and
validation.

Figure 28. Quartus Prime Pin Planner

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

2 3 4

(11) The weak pull-up/pull-down feature is available only for the input buffer.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

56
3. Agilex 3 HVIO Banks
847266 | 2025.08.04

1. From the Quartus Prime menu, select Assignments ➤ Pin Planner.

2. Under the Node Name column in the All Pins box, look for the pin that you want
to configure.
3. Under the Location column, select the specific pin location.
The I/O Bank column displays the I/O bank name where the pin resides. The
Top View - Flip Chip diagram shows the I/O banks in different colors.
4. Under the I/O Standard column, select the supported I/O standards that you
want to assign to the pin.
If you select True Differential Signaling, the Pin Planner automatically adds a
negative node with a specific pin location.

Related Information
Supported I/O Standards for HVIO Banks on page 51

3.4. HVIO Design Guidelines

Different functions of the HVIO pins have different guidelines, placement restrictions,
connection requirements, and clocking requirements.

3.4.1. HVIO Pins During Power Sequencing

Agilex 3 devices do not support hot-socketing and require a specific power sequence.
Design your power supply solution to properly control the complete power sequence.

Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins
located in the HVIO banks. These guidelines apply for unpowered, power up to power-
on reset (POR), POR delay, POR delay to configuration, configuration, initialization,
user mode, and power down device states.
• The I/O pins in the HVIO banks can be tri-stated, driven to ground, or driven to
the VCCIO_HVIO level.
• While the device is powering up or down, the input signals to an HVIO pin, at all
times, must not exceed the VCCIO_HVIO rail.
• While the device is powering up, powering down, or not turned on, the HVIO pins
can tolerate a maximum of 10 mA per pin and a total of 100 mA per HVIO bank.
• After the device fully powers up, the voltage levels for the HVIO pins must not
exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.
• For more information, refer to the Agilex 3 FPGAs and SoCs Pin Connection
Guidelines document.

Table 31. Guideline Example

Condition Guideline

The VCCIO_HVIO pin ramps up and at period X, the At period X, keep the signals driven by the device connected to
VCCIO_HVIO voltage is 0.9 V. the HVIO I/O pin at a voltage of 0.9 V or lower.

3.4.2. Unused HVIO Pins

Unused HVIO pins are configured as input tri-stated. You may leave these pins
floating.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

57
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

3.4.3. VCCIO_HVIO Supply for Unused HVIO Banks

Connect the VCCIO_HVIO of the unused HVIO bank to 0 V, 1.8 V, 2.5 V, or 3.3 V.

3.4.4. Maximum DC Current Restrictions

While using Agilex 3 HVIO pins, adhere to the maximum allowed duration of the per
pin DC current limit for the specified current strength setting.

Table 32. Maximum Allowed Durations of DC Current Limits Per Current Strength
Setting
Current Strength Setting DC Current Limit Maximum Allowed Duration (%)

12 mA ±8 mA 100%

±10 mA 60%

±12 mA 40%

More than ±12 mA Not allowed

9 mA ±6 mA 100%

±7.5 mA 60%

±9 mA 40%

More than ±9 mA Not allowed

6 mA ±4 mA 100%

±5 mA 60%

±6 mA 40%

More than ±6 mA Not allowed

3 mA ±2 mA 100%

±2.5 mA 60%

±3 mA 40%

More than ±3 mA Not allowed

3.5. HVIO Simulation

Altera provides simulation models for Agilex 3 devices.

These simulation models are:

• Synopsys HSPICE models
• IBIS models

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

58
3. Agilex 3 HVIO Banks
847266 | 2025.08.04

Table 33. Simulation Models Descriptions

Model Supported I/O Description
Type

HSPICE HVIO • Simulates actual transistor level design to obtain precise electrical simulation.
• The syntax describes I/O buffers, board components and connections, and specific
simulation parameters.
• The model contains encrypted transistor and logic cell library models, output buffer
circuit models for single-ended and differential I/Os, and sample SPICE decks for
single-ended and differential I/Os.
• The model requires a longer simulation time compared to the IBIS model.

IBIS HVIO • This is a behavioral model of the I/O buffers based on the I/V curve data derived
from the HSPICE simulation.
• The pre-emphasis feature is an example that can use the IBIS simulation model.
• This model has a shorter simulation time compared to HSPICE.
• The simulation model has less complexity compared to HSPICE models and
supported by many simulation tools.

3.5.1. IBIS Models—HVIO Support

You can use the Agilex 3 IBIS model to perform system-level simulations for various
I/O configurations across three predefined process, voltage, and temperature settings.

The Agilex 3 IBIS model kit contains the following information:

• IBIS model file (.ibs)
• User guide that describes the model usage
• Model list sheet that lists the supported I/O feature for each model
• Package RLC report that provides the lumped package RLC values for each
supported Agilex 3 variant

You can use the Agilex 3 IBIS model to simulate all valid I/O features configurations
across all supported I/O standards:

• Current strength
• Weak pull-up and pull-down
• Open-drain

3.5.2. HSPICE Models

You can use the Agilex 3 SPICE model to perform system-level simulations for various
configurations. The SPICE kits provide models that support a wide variety of I/O
features across process, voltage, and temperature (PVT)

Each SPICE kit contains the following items:

• Encrypted transistor and logic cell library models
• Encrypted input or output buffer circuit models for single-ended and differential
I/Os
• Single-ended and differential sample SPICE decks
• User guide that describes the model usage

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

59
 3. Agilex 3 HVIO Banks
847266 | 2025.08.04

The HSPICE models provide options to simulate buffer behavior for the following I/O
features:
• Current strength
• Weak pull-up and pull-down
• Open-drain

3.5.3. Net Length Reports

The net length information consists of the package trace delay from the die pad to the
package pin. Each pin in an FPGA package has its own net length information. This
information is important for you to perform board trace compensation to optimize the
channel-to-channel skew on your board design.

Related Information
Agilex 3 Device Package Net Length Report
Downloads the net length reports for Agilex 3 devices.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

60
 847266 | 2025.08.04

Send Feedback

4. Agilex 3 HPS I/O Banks

The HPS bank is available in the Agilex 3 SoCs. The HPS bank provides the I/O buffer
and peripheral support to interface with the hard processor system (HPS).

Related Information
• Types of I/O Banks on page 7
• Device Migration Guidelines: Agilex 3 FPGAs and SoCs

4.1. HPS I/O Bank Overview

The HPS I/O bank contains 48 I/O pins. You can use these I/O pins to access HPS
features such as clocks, peripherals, mass storage flash, and JTAG.

4.2. HPS I/O Features

The I/O bank within the HPS interface supports single-ended IO standards.

Power Pins for the HPS I/O Buffers

The VCCIO_HPS pin powers the I/O buffers located in the HPS I/O bank within the
HPS I/O interface.

HPS I/O Buffer Features

The HPS I/O buffer supports these features:

• Programmable current strength
• Programmable weak pull-up and pull-down resistor
• Programmable open-drain output
• Programmable slew rate
• Schmitt Trigger input buffer
• Programmable delay chain
• On-die termination impedance

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
 4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

4.2.1. Supported I/O Standards for HPS I/O Banks

The VCCIO_HPS power supply powers the HPS I/O buffer.

Table 34. Agilex 3 HPS I/O Bank Supported I/O Standards

I/O Standard VCCIO_HPS (V)

Input Output

1.8 V LVCMOS 1.8 1.8

Related Information
• I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the electrical specifications for the supported I/O standards.
• Assigning Pin I/O Standards in the Quartus Prime Pin Planner on page 67

4.2.2. Programmable I/O Element Features for the HPS I/O Bank
Table 35. Programmable IOE Feature Settings for Agilex 3 HPS I/O Bank
This table lists the supported IOE features for each I/O standards in the HPS I/O banks.

I/O Programmable IOE Feature

Standard
Current Slew Rate Weak Pull-up/ Schmitt Open-Drain I/O Delay On-Die
Strength Pull-down Trigger/ Termination
TTL Input Impedance

1.8 V • 2 mA • Slow • Disabled • Schmitt • Enabled Refer to the • NMOS(12)

LVCMOS • 4 mA • Fast • Weak pull-up Trigger • Disabled device (Default)
(Default) with 20 kΩ (Default) (Default) datasheet. • PMOS(13)
• 6 mA
resistor • TTL
• 8 mA
(Default)
(Default)
• Weak pull-up
with 50 kΩ
resistor
• Weak pull-up
with 80 kΩ
resistor
• Weak pull-down
with 20 kΩ
resistor
• Weak pull-down
with 50 kΩ
resistor
• Weak pull-down
with 80 kΩ
resistor

Related Information
• Agilex 3 FPGAs and SoCs Device Data Sheet
• Programmable I/O Features Description on page 99
• HPS Programmable I/O Timing Characteristics, Agilex 3 FPGAs and SoCs Device
Data Sheet

(12) On-die pull-down termination.

(13) On-die pull-up termination.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

62
4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

• Hard Processor System Technical Reference Manual: Agilex 3 SoCs

4.2.3. HPS I/O Buffer Behavior

Table 36. HPS I/O Pins Guideline for Different Pin States
HPS I/O Pin State

Not turned on Powering up Fully powered up HPS initialization HPS boot Powering down
completed

Pin voltage must • Pin voltage All pins are All pins are Valid data • Pin voltage
not exceed must not configured as configured as transactions can must not
VCCIO_HPS. exceed Schmitt Trigger Schmitt Trigger be initiated. exceed
VCCIO_HPS.(14) input with 20 kΩ input with 20 kΩ VCCIO_HPS.(14)
• All pins are in weak pull-up weak pull-up • All pins are in
undetermined enabled. enabled. undetermined
state. state.

Note: After the Agilex 3 device fully powers up, the voltage levels for the HPS I/O pins must
not exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Related Information
Agilex 3 FPGAs and SoCs Device Data Sheet

4.3. HPS I/O Implementation Guide

The Quartus Prime software provides tools for you to create, configure and compile
your I/O design. Each tool provides different functions and supports different features
to implement your I/O design.

Table 37. Quartus Prime I/O Implementation Tools

Tool Functions Supported Assignment Supported I/O
Standards

Assignment • View, create and edit • Programmable slew rate control 1.8 V LVCMOS
Editor assignments. • Programmable current strength
• The Quartus Prime software: • Programmable weak pull-up
— Dynamically validates your select
edits. • Programmable weak pull-down
— Notify you of errors and select
warnings of invalid • Schmitt Trigger
assignments.
• On-die termination impedance

Pin Planner • Graphically represent pin • Programmable slew rate control

locations on the device. • Programmable current strength
• With this tool, you can:
— Perform initial pin planning.
— Configure board trace models
for pins you select for signal
integrity evaluations.

(14) VCCIO_HPS refers to the real-time onboard voltage supply.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

63
 4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

4.3.1. Configuring Open Drain Feature for the HPS I/O

You can turn on the open drain feature for the HPS I/Os through the Hard Processor
System FPGA IP in the Quartus Prime Platform Designer.

Figure 29. Hard Processor System FPGA IP Parameter Editor

1. From the Quartus Prime menu, select Tools ➤ Platform Designer

2. Specify the Quartus project and Platform Designer system, then click Open.
3. In Platform Designer, open the Hard Processor System FPGA IP parameter
editor.
4. Navigate to the Pin Mux and Peripherals ➤ Pin Mux GUI ➤ Advanced ➤
Advanced IP Placement tab.
5. If you make any changes, click Apply Selections, then click OK.
6. Scroll down to the HPS IO Open Drain Select section.
7. Turn on the HPS_ION_N Open Drain Enable that you want.

Figure 30. HPS IO Open Drain Select Section

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

64
4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

4.3.2. I/O Assignments with the Quartus Prime Assignment Editor

You can assign all instance-specific settings and constraints through the Quartus Prime
Assignment Editor. You can filter assignments by node name or category.

Figure 31. Quartus Prime Assignment Editor

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

4.3.2.1. Assigning Programmable IOE Features in the Quartus Prime Assignment

Editor
1. From the Quartus Prime menu, select Assignments ➤ Assignment Editor
2. Under the To column, search for the pin that you want to configure.
3. Under the Assignment Name column, select a supported programmable IOE
feature.
4. Under the Value column, select a supported value.
5. From the Quartus Prime menu, select File ➤ Save.

Related Information
HPS I/O Programmable IOE Features Assignment Names and Settings on page 66
Provides a list of supported programmable IOE features for the HPS I/O, the
assignment names, and supported values.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

65
 4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

4.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings

Table 38. HPS I/O Programmable IOE Features Assignment Names and Settings
This table lists the programmable IOE features assignment names and values that you can specify in the
Quartus Prime Assignment Editor and Pin Planner tools.

Feature Assignment Name Supported Values

Slew rate control Slew Rate • 0—slow

• 1—fast (default)

• Weak pull-up resistor Weak Pull-Up Resistor • On (default)—turns on the weak pull-up
• Weak pull-down resistor or pull-down resistor
• Off—turns off the weak pull-up or pull-
down resistor

Weak Pull Up/Down Select (15) • No Pull Up or Down

• Pull Down 20 kOhm
• Pull Down 50 kOhm
• Pull Down 80 kOhm
• Pull Up 20 kOhm (default)
• Pull Up 50 kOhm
• Pull Up 80 kOhm

Schmitt Trigger input buffer Schmitt Trigger • On (default)

• Off

Current strength Current Strength • 2 mA

• 4 mA
• 6 mA
• 8 mA (default)

On-die termination HPS IO On-Die Termination Impedance • NMOS (default)

impedance • PMOS

Related Information
Assigning Programmable IOE Features in the Quartus Prime Assignment Editor on
page 65

(15) You must use this together with the Weak Pull-Up Resistor assignment.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

66
4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

4.3.3. Assigning Pin I/O Standards in the Quartus Prime Pin Planner
You can use the Quartus Prime Pin Planner for I/O pin planning, assignment, and
validation.

Figure 32. Quartus Prime Pin Planner

This figure shows an example of the user interface and does not represent actual components, features, or
settings supported by Agilex 3 FPGAs.

2 3 4

1. From the Quartus Prime menu, select Assignments ➤ Pin Planner.

2. Under the Node Name column in the All Pins box, look for the pin that you want
to configure.
3. Under the I/O Standard column, select the supported I/O standards that you
want to assign to the pin.
If you select True Differential Signaling, the Pin Planner automatically adds a
negative node with a specific pin location.

Related Information
Supported I/O Standards for HPS I/O Banks on page 62

4.4. HPS I/O Design Guidelines

Different functions of the HPS I/O pins have different guidelines, placement
restrictions, connection requirements, and clocking requirements.

4.4.1. HPS I/O Pins During Power Sequencing

Agilex 3 devices do not support hot-socketing and require a specific power sequence.
Design your power supply solution to properly control the complete power sequence.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

67
 4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

Adhere to the these guidelines to prevent unnecessary current draw on the I/O pins
located in the HPS I/O banks. These guidelines apply for unpowered, power up to
POR, POR delay, POR delay to configuration, configuration, initialization, user mode,
and power down device states.
• The I/O pins in the HPS I/O banks can be tri-stated, driven to ground, or driven to
the VCCIO_HPS level.
• While the device is powering up or down, the input signals of an I/O pin, at all
times, must not exceed the I/O buffer power supply rail of the bank where the I/O
pin resides.
• While the device is powering up, powering down, or not turned on, the HPS I/O
pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per HPS I/O
bank.
• After the device fully powers up, the voltage levels for the HPS I/O pins must not
exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Table 39. Guideline Example

Condition Guideline

The VCCIO_HPS pin ramps up and at period X, the At period X, keep the signals driven by the device connected to
VCCIO_HPS voltage is 0.9 V. the HPS I/O pin at a voltage of 0.9 V or lower.

4.4.2. HPS Shared I/O Requirements

The HPS external memory interface uses I/O pins located in the HSIO bank instead of
the HPS I/O bank. The VCCIO_PIO powers the HSIO bank instead of the 1.8 V VCCIO_HPS.
For the location of the HPS shared HSIO pins, refer to device pin-out files.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

4.5. HPS I/O Simulation

You can use the Agilex 3 IBIS model to perform system-level simulations for various
I/O configurations across three predefined process, voltage, and temperature settings.

4.5.1. IBIS Models—HPS I/O Support

The Agilex 3 IBIS model kit contains the following information:
• IBIS model file (.ibs)
• User guide that describes the model usage
• Model list sheet that lists the supported I/O feature for each model
• Package RLC report that provides the lumped package RLC values for each
supported Agilex 3 variant

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

68
4. Agilex 3 HPS I/O Banks
847266 | 2025.08.04

You can use the Agilex 3 IBIS model to simulate all valid I/O features configurations
across all supported I/O standards:

• Slew rate
• Weak pull-up
• Current strength
• Open drain

Related Information
IBIS Models for FPGA Devices

4.5.2. Net Length Reports

The net length information consists of the package trace delay from the die pad to the
package pin. Each pin in an FPGA package has its own net length information. This
information is important for you to perform board trace compensation to optimize the
channel-to-channel skew on your board design.

Related Information
Agilex 3 Device Package Net Length Report
Downloads the net length reports for Agilex 3 devices.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

69
 847266 | 2025.08.04

Send Feedback

5. Agilex 3 SDM I/O Banks

The SDM bank is available in the Agilex 3 FPGAs. The SDM bank provides the I/O
buffer and peripheral support for device configuration and to interface with the secure
device manager (SDM).

Related Information
• Types of I/O Banks on page 7
• Device Migration Guidelines: Agilex 3 FPGAs and SoCs

5.1. SDM I/O Bank Overview

The SDM I/O bank contains 24 dedicated pins for device configuration purposes. The
SDM I/O interfaces supports 1.8 V single-ended non-voltage referenced I/O standard
for interfacing with the SDM.

The Agilex 3 pin-out files list the dedicated function of each pin in the SDM I/O bank.

Related Information
Agilex 3 Device Pin-Out Files
Each device pinout file lists the available I/O banks for each package, the banks
shared with the HPS and SDM, the DQ groups, the pin functions, and the pin
locations.

5.2. SDM I/O Features

The I/O bank within the SDM interface supports single-ended IO standards.

Power Pins for the SDM I/O Buffers

The VCCIO_SDM pin powers the I/O buffers located in the SDM I/O bank within the
SDM I/O interface.

SDM I/O Buffer Features

The SDM I/O buffer is pre-configured with these features:

• Programmable current strength
• Programmable weak pull-up and pull-down resistor
• Programmable open-drain output
• Programmable slew rate
• Schmitt Trigger input buffer

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

Related Information
Programmable I/O Features Description on page 99

5.2.1. Supported I/O Standards for SDM I/O Banks

The VCCIO_SDM power supply powers the SDM I/O buffer.

Table 40. Agilex 3 SDM I/O Bank Supported I/O Standards

I/O Standard VCCIO_SDM (V)

Input Output

1.8 V LVCMOS 1.8 1.8

Related Information
I/O Standards Specifications, Agilex 3 FPGAs and SoCs Device Data Sheet
Provides the electrical specifications for the supported I/O standards.

5.2.2. SDM I/O Buffer Behavior

Table 41. SDM I/O Pins Guideline for Different Pin States
SDM I/O Pin State

Not turned on Powering up Fully powered up Configuration mode Powering down

Pin voltage must not • Pin voltage must Refer to the related Refer to the related • Pin voltage must
exceed VCCIO_SDM. not exceed information. information. not exceed
VCCIO_SDM.(16) VCCIO_SDM.(16)
• All pins are in • All pins are in
undetermined undetermined
state, except these state, except these
pins: pins:
— VSIGP_0 — VSIGP_0
— VSIGP_1 — VSIGP_1
— VSIGN_0 — VSIGN_0
— VSIGN_1 — VSIGN_1
— RREF_SDM — RREF_SDM

Related Information
• Agilex 3 FPGAs and SoCs Device Data Sheet
• Agilex 3 Configuration Timing Diagram, Device Configuration User Guide: Agilex 3
FPGAs and SoCs
• I/O Standards and Features for Configuration Pins on page 72
Lists the pre-configured SDM I/O settings for each SDM pin across different
device configurations modes and provides guidelines for the SDM I/O pins
during configuration mode.

(16) VCCIO_SDM refers to the real-time onboard voltage supply.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

71
 5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

5.2.3. I/O Standards and Features for Configuration Pins

The SDM pins have different I/O standards and features in different configuration
schemes. You can assign the unused SDM pins for other functions in the Quartus
Prime software.

Table 42. Agilex 3 AS ×4 Configuration Scheme—Dedicated Configuration Pins

Pin SDM I/O Direction I/O Standard Schmitt Weak Drive Open Slew
Function Trigger/TTL Pull-Up/ Strength Drain Rate
Input Pull-Down

AS_DATA1 SDM_IO1 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast

AS_CLK SDM_IO2 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AS_DATA2 SDM_IO3 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast

AS_DATA0 SDM_IO4 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast

AS_nCSO0 SDM_IO5 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AS_DATA3 SDM_IO6 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast

AS_nCSO2 SDM_IO7 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AS_nCSO3 SDM_IO8 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AS_nCSO1 SDM_IO9 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AS_nRST SDM_IO15 Output 1.8 V LVCMOS — — 8 mA Disable Fast

Table 43. Agilex 3 AS ×4 Configuration Scheme—Unused Configuration Pins

For the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.

SDM I/O Direction I/O Standard Schmitt Weak Pull-Up/Pull-Down

Trigger/TTL Input

SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor

SDM_IO10 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO11 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO13 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO14 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor

Table 44. Agilex 3 Avalon Streaming Interface ×8 Configuration Scheme—Dedicated

Configuration Pins
Pin Function SDM I/O Direction I/O Standard Schmitt Weak Drive Open Slew
Trigger/TTL Pull-Up/ Strength Drain Rate
Input Pull-Down

AVSTx8_DATA2 SDM_IO1 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_DATA0 SDM_IO2 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger
continued...

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

72
5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

Pin Function SDM I/O Direction I/O Standard Schmitt Weak Drive Open Slew
Trigger/TTL Pull-Up/ Strength Drain Rate
Input Pull-Down

AVSTx8_DATA3 SDM_IO3 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_DATA1 SDM_IO4 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_DATA4 SDM_IO6 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_READY SDM_IO8 Output 1.8 V LVCMOS — — 8 mA Disable Fast

AVSTx8_DATA7 SDM_IO10 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_VALID SDM_IO11 Input 1.8 V LVCMOS Schmitt Weak — — —

Trigger pull-down
with 20 kΩ
resistor

AVSTx8_DATA5 SDM_IO13 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_CLK SDM_IO14 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

AVSTx8_DATA6 SDM_IO15 Input 1.8 V LVCMOS Schmitt Disable — — —

Trigger

Table 45. Agilex 3 Avalon Streaming Interface ×8 Configuration Scheme—Unused

Configuration Pins
For the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.

SDM I/O Direction I/O Standard Schmitt Weak Pull-Up/Pull-Down

Trigger/TTL Input

SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor

SDM_IO5 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO7 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO9 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor

SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor

Table 46. Agilex 3 Avalon Streaming Interface ×16 Configuration Scheme—Dedicated

Configuration Pins
For all pin functions in this table:
• The I/O location is the SDM shared GPIO bank.
• The weak pull-up or pull-down, and open drain options are not applicable.

Pin Function Direction I/O Standard Drive Strength Slew Rate

AVST_CLK Input 1.2 V LVCMOS — —

AVST_READY Output 1.2 V LVCMOS Series 34 Ω OCT without calibration Slow

AVST_VALID Input 1.2 V LVCMOS — —

AVST_DATA Input 1.2 V LVCMOS — —

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

73
 5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

Table 47. Agilex 3 Optional Configuration Pins

The SDM I/O for each pin function in this table is as assigned in the Quartus Prime configuration pins option.

Pin Function Direction I/O Standard Schmitt Weak Drive Open Slew
Trigger/ Pull-Up/ Strength Drain Rate
TTL Input Pull-Down

CONF_DONE Output 1.8V LVCMOS — — 8 mA Disable Fast

INIT_DONE Output 1.8V LVCMOS — — 8 mA Disable Fast

CvP_CONFDONE Output 1.8V LVCMOS — — 8 mA Disable Fast

SEU_ERROR Output 1.8V LVCMOS — — 8 mA Disable Fast

HPS_COLD_nRESET Bidirectional 1.8V LVCMOS Schmitt Weak pull-up 2 mA Enable Fast

Trigger with 20 kΩ
resistor

Direct to factory Input 1.8V LVCMOS Schmitt Weak pull- — — —

image Trigger down with
20 kΩ resistor

nCATTRIP Output 1.8V LVCMOS — — 2 mA Disable Slow

TAMPERDETECTION Output 1.8V LVCMOS — — 8 mA Disable Fast

TAMPERRESPONSESTATUS Output 1.8V LVCMOS — — 8 mA Disable Fast

Related Information
• Agilex 3 Configuration Pins, Device Configuration User Guide: Agilex 3 FPGAs and
SoCs
Provides more information about the configuration pins in Agilex 3 devices.
• SDM I/O Buffer Behavior on page 71
• IBIS Models—SDM I/O Support on page 75
• Avalon Streaming Interface Dedicated Configuration Pins on page 75

5.3. SDM I/O Design Guidelines

Different functions of the SDM I/O pins have different guidelines, placement
restrictions, connection requirements, and clocking requirements.

5.3.1. SDM I/O Pins During Power Sequencing

Agilex 3 devices do not support hot-socketing and require a specific power sequence.
Design your power supply solution to properly control the complete power sequence.

Adhere to the guidelines to prevent unnecessary current draw on the I/O pins located
in the SDM I/O banks. These guidelines apply for unpowered, power up to POR, POR
delay, POR delay to configuration, configuration, initialization, user mode, and power
down device states.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

74
5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

• The I/O pins in the SDM I/O banks can be tri-stated, driven to ground, or driven to
the VCCIO_SDM level.
• While the device is powering up or down, the input signals of an I/O pin, at all
times, must not exceed the I/O buffer power supply rail of the bank where the I/O
pin resides.
• While the device is powering up, powering down, or not turned on, the SDM I/O
pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per SDM I/O
bank.
• After the device fully powers up, the voltage levels for the SDM I/O pins must not
exceed the DC input voltage (VI) value or the AC maximum allowed overshoot
during transitions.

Table 48. Guideline Example

Condition Guideline

The VCCIO_SDM pin ramps up and at period X, the At period X, keep the signals driven by the device connected to
VCCIO_SDM voltage is 0.9 V. the SDM I/O pin at a voltage of 0.9 V or lower.

5.3.2. Avalon Streaming Interface Dedicated Configuration Pins

The Avalon streaming interface dedicated configuration pins are powered by bank 3AT.
If you use the Avalon streaming interface ×16 configuration scheme, you must power
bank 3AT with 1.2 V VCCIO_PIO.

Related Information
I/O Standards and Features for Configuration Pins on page 72

5.4. SDM I/O Simulation

You can use the Agilex 3 IBIS model to perform system-level simulations for various
I/O configurations across three predefined process, voltage, and temperature settings.

5.4.1. IBIS Models—SDM I/O Support

The Agilex 3 IBIS model kit contains the following information:
• IBIS model file (.ibs)
• User guide that describes the model usage
• Model list sheet that lists the supported I/O feature for each model
• Package RLC report that provides the lumped package RLC values for each
supported Agilex 3 variant

You can use the Agilex 3 IBIS model to simulate all valid I/O features configurations
across all supported I/O standards:

• Slew rate
• Weak pull-up
• Weak pull-down
• Current strength

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

75
 5. Agilex 3 SDM I/O Banks
847266 | 2025.08.04

Related Information
• IBIS Models for FPGA Devices
• I/O Standards and Features for Configuration Pins on page 72
Lists the pre-configured SDM I/O settings for each SDM pin across different
device configurations modes and provides guidelines for the SDM I/O pins
during configuration mode.

5.4.2. Net Length Reports

The net length information consists of the package trace delay from the die pad to the
package pin. Each pin in an FPGA package has its own net length information. This
information is important for you to perform board trace compensation to optimize the
channel-to-channel skew on your board design.

Related Information
Agilex 3 Device Package Net Length Report
Downloads the net length reports for Agilex 3 devices.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

76
 847266 | 2025.08.04

Send Feedback

6. Agilex 3 I/O Troubleshooting Guidelines

These debug guidelines are initial debug actions and do not necessarily resolve the
failures in your designs.

Table 49. GPIO Debug Guidelines

This table lists the failure symptoms and the associated debug actions that you can take to identify the failure
areas when you are designing GPIO systems with Agilex 3 devices.

Failure Symptoms Recommended Debug Actions

1.2 V LVCMOS output at the entire bank does not reach • Check the power-up and power-down sequences of each
1.2 V. voltage rail with respect to time.
Note: Not applicable to the HVIO bank. • Compare the power sequences as per recommendation
in the Power Management User Guide: Agilex 3 FPGAs
and SoCs.
• Verify the VCCIO_PIO voltage signal is 1.2 V.

Quartus Prime software shows an error message to indicate Select the I/O pins specified in the error message and check
incorrect I/O settings for VCCIO during design compilation. the I/O settings for the pins.
Error message example: Illegal constraint of I/O
bank to the location <I/O bank>

Quartus Prime software shows illegal I/O error message Select the I/O pins specified in the error message and set
during design compilation. the pins to the correct I/O function. Refer to the device pin-
Error message example: Programmable VOD option is outs file for more information about the pin functions.
set to 1 for pin <pin_name>, but setting is
not supported by <I/O standard>

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
 847266 | 2025.08.04

Send Feedback

7. GPIO FPGA IP
The GPIO FPGA IP provides features to support the device I/O blocks. You can use the
Quartus Prime parameter editor to configure the GPIO FPGA IP.

7.1. Release Information for GPIO FPGA IP

Altera® FPGA IP versions match the Quartus Prime Design Suite software versions
until v19.1. Starting in Quartus Prime Design Suite software version 19.2, the IP has a
new versioning scheme.

The IP version (X.Y.Z) number can change with each Quartus Prime software version.
A change in:

• X indicates a major revision of the IP. If you update the Quartus Prime software,
you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.

Table 50. GPIO FPGA IP Current Release Information

Item Description

IP Version 23.0.0

Quartus Prime Version 25.1.1

Release Date 2025.08.04

Related Information
GPIO FPGA IP Release Notes

7.2. Generating the GPIO FPGA IP

Using the GPIO FPGA IP parameter editor, you can customize the IP settings and
generate the IP variant files, simulation testbench, and HDL instantiation template.

Before you begin, create or open a Quartus Prime project.

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
7. GPIO FPGA IP
847266 | 2025.08.04

Figure 33. GPIO FPGA IP Parameter Editor

1. In the IP Catalog window, double-click GPIO FPGA IP.

The Parameter Editor window appears.
2. Specify a top-level name for your new IP variant and click Create.
Do not include space and special characters in the name and file path.
3. Set the values in the Parameters tab.
The System Messages tab displays errors and warning for the parameters
settings.
4. From the Parameter Editor menu, select File ➤ Save.
The parameter editor saves the IP variant settings in the <your_ip>.ip file.
5. To generate the IP variant HDL files:
a. Click Generate HDL.
The Generation window appears.
b. Specify the output file generation options and click Generate.
The parameter editor generates the synthesis and simulation files as you
specified, and automatically adds the .ip file of the variant to your project.
c. Click Close.
6. To generate a simulation testbench:

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

79
 7. GPIO FPGA IP
847266 | 2025.08.04

a. From the Parameter Editor menu, select Generate ➤ Generate Testbench

System.
b. Specify the testbench generation options and click Generate.
c. Click Close.
7. To generate an HDL instantiation template that you can copy and paste into your
text editor:
a. From the Parameter Editor menu, select Generate ➤ Show Instantiation
Template.
b. Select the HDL Language.
The code template appears in the Example HDL box.
c. Click Copy and then click Close.

After generating and instantiating your IP variant, assign appropriate pins to connect
the ports.

7.2.1. Altera FPGA IP Generation Output

The Quartus Prime software generates the following output file structure for individual
IPs that are not part of a Platform Designer system.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

80
7. GPIO FPGA IP
847266 | 2025.08.04

Figure 34. Individual IP Generation Output

<Project Directory>
<your_ip>.ip - Top-level IP variation file
<your_ip> - IP core variation files
<your_ip>.bsf - Block symbol schematic file
<your_ip>.cmp - VHDL component declaration
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists files for IP core synthesis
<your_ip>.spd - Simulation startup scripts
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file *
<your_ip>_generation.rpt - IP generation report
<your_ip>_inst.v or .vhd - Lists file for IP core synthesis
<your_ip>.qgsimc - Simulation caching file (Platform Designer)
<your_ip>.qgsynthc - Synthesis caching file (Platform Designer)
sim - IP simulation files
<your_ip>.v or vhd - Top-level simulation file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
<IP Submodule>_<version> - IP Submodule Library
sim- IP submodule 1 simulation files
<HDL files>
synth - IP submodule 1 synthesis files
<HDL files>
<your_ip>_tb - IP testbench system *
<your_testbench>_tb.qsys - testbench system file
<your_ip>_tb - IP testbench files
your_testbench> _tb.csv or .spd - testbench file
sim - IP testbench simulation files
* If supported and enabled for your IP core variation.

Table 51. Output Files of Altera FPGA IP Generation

File Name Description

<your_ip>.ip Top-level IP variation file that contains the parameterization of an IP in your

project. If the IP variation is part of a Platform Designer system, the parameter
editor also generates a .qsys file.

<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local
generic and port definitions that you use in VHDL design files.

<your_ip>_generation.rpt IP or Platform Designer generation log file. Displays a summary of the

messages during IP generation.
continued...

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

81
 7. GPIO FPGA IP
847266 | 2025.08.04

File Name Description

<your_ip>.qgsimc (Platform Designer Simulation caching file that compares the .qsys and .ip files with the current
systems only) parameterization of the Platform Designer system and IP. This comparison
determines if Platform Designer can skip regeneration of the HDL.

<your_ip>.qgsynth (Platform Synthesis caching file that compares the .qsys and .ip files with the current
Designer systems only) parameterization of the Platform Designer system and IP. This comparison
determines if Platform Designer can skip regeneration of the HDL.

<your_ip>.csv Contains information about the upgrade status of the IP component.

<your_ip>.bsf A symbol representation of the IP variation for use in Block Diagram Files
(.bdf).

<your_ip>.spd Input file that ip-make-simscript requires to generate simulation scripts.

The .spd file contains a list of files you generate for simulation, along with
information about memories that you initialize.

<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP
components you create for use with the Pin Planner.

<your_ip>_bb.v Use the Verilog blackbox (_bb.v) file as an empty module declaration for use
as a blackbox.

<your_ip>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file
into your HDL file to instantiate the IP variation.

<your_ip>.regmap If the IP contains register information, the Quartus Prime software generates
the .regmap file. The .regmap file describes the register map information of
master and slave interfaces. This file complements the .sopcinfo file by
providing more detailed register information about the system. This file enables
register display views and user customizable statistics in System Console.

<your_ip>.svd Allows HPS System Debug tools to view the register maps of peripherals that
connect to HPS within a Platform Designer system.
During synthesis, the Quartus Prime software stores the .svd files for slave
interface visible to the System Console masters in the .sof file in the debug
session. System Console reads this section, which Platform Designer queries
for register map information. For system slaves, Platform Designer accesses
the registers by name.

<your_ip>.v HDL files that instantiate each submodule or child IP for synthesis or
<your_ip>.vhd simulation.

mentor/ Contains a msim_setup.tcl script to set up and run a ModelSim* simulation.

aldec/ Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a

simulation.

/synopsys/vcs Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
/synopsys/vcsmx Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to
set up and run a VCS MX simulation.

/xcelium Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and

other setup files to set up and run a simulation.

/submodules Contains HDL files for the IP submodule.

<IP submodule>/ Platform Designer generates /synth and /sim sub-directories for each IP
submodule directory that Platform Designer generates.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

82
7. GPIO FPGA IP
847266 | 2025.08.04

7.3. GPIO FPGA IP Parameter Settings

You can set the parameter settings for the GPIO FPGA IP in the Quartus Prime
software. There are three groups of options: General, Buffer, and Registers.

Table 52. GPIO FPGA IP Parameters—General

Parameter Condition Allowed Values Description

Data Direction — • Input Specifies the data direction for the GPIO.
• Output
• Bidir

Data width — 1 to 128 Specifies the data width.

Use legacy top-level — • On Use same port names as in Stratix® V, Arria®

port names • Off V, and Cyclone® V devices.
For example, dout becomes dataout_h and
dataout_l, and din becomes datain_h
and datain_l.
Note: The behavior of these ports are
different than in the Stratix V, Arria V,
and Cyclone V devices. For the
migration guideline, refer to the
related information.

Table 53. GPIO IP Parameters—Buffer

Parameter Condition Allowed Values Description

Use differential buffer — • On If turned on, enables differential I/O buffers.

• Off

Use pseudo differential • Data Direction = • On If turned on in output mode, enables pseudo
buffer Output • Off differential output buffers.
• Use differential This option is automatically turned on for
buffer = On bidirectional mode if you turn on Use
differential buffer.

Enable output enable Data Direction = • On If turned on, enables user input to the OE
port Output • Off port. This option is automatically turned on
for bidirectional mode.

Table 54. GPIO IP Parameters—Registers

Parameter Condition Allowed Values Description

Register mode — • None Specifies the register mode for the GPIO IP:
• Simple • None—specifies a simple wire connection
register from/to the buffer.
• DDIO • Simple register—specifies that the DDIO
is used as a simple register in single data-
rate mode (SDR). The Fitter may pack this
register in the I/O.
• DDIO— specifies that the IP core uses the
DDIO.

Enable synchronous Register mode = DDIO • None Specifies how to implement synchronous
clear / preset port • Clear reset port.
• Preset • None—Disables synchronous reset port.
• Clear—Enables the SCLR port for
synchronous clears.
• Preset—Enables the SSET port for
synchronous preset.
continued...

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

83
 7. GPIO FPGA IP
847266 | 2025.08.04

Parameter Condition Allowed Values Description

Enable asynchronous Register mode = DDIO • None Specifies how to implement asynchronous
clear / preset port • Clear reset port.
• Preset • None—Disables asynchronous reset port.
• Clear—Enables the ACLR port for
asynchronous clears.
• Preset—Enables the ASET port for
asynchronous preset.
ACLR and ASET signals are active high.

Enable clock enable Register mode = DDIO • On • On—exposes the clock enable (CKE) port
ports • Off to allow you to control when data is
clocked in or out. This signal prevents
data from being passed through without
your control.
• Off—clock enable port is not exposed and
data always pass through the register
automatically.

Input DDIO With Delay • Data Direction = • On If turned on, the I/O uses the DDIO with
Bidir • Off delay.
• Register mode =
DDIO

Separate input/output • Data Direction = • On If turned on, enables separate clocks (CK_IN
Clocks Bidir • Off and CK_OUT) for the input and output paths
• Register mode = in bidirectional mode.
Simple register or
DDIO

Related Information
• Input Path on page 89
Provides a figure showing the input path waveform.
• Guideline: Swap datain_h and datain_l Ports in Migrated IP on page 84

7.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP

When you migrate your GPIO IP from previous devices to the GPIO IP, you can turn on
Use legacy top-level port names option in the GPIO IP parameter editor. However,
the behavior of these ports in the GPIO IP is different than in the IP used for the
Stratix V, Arria V, and Cyclone V devices.

The GPIO IP drives these ports to the output registers on these clock edges:
• datain_h—on the falling edge of outclock
• datain_l—on the rising edge of outclock

If you migrated your GPIO IP from Stratix V, Arria V, and Cyclone V devices, swap the
datain_h and datain_l ports when you instantiate the IP generated by the GPIO IP.

7.4. GPIO FPGA IP Interface Signals

Depending on the parameter settings you specify, different interface signals are
available for the GPIO IP.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

84
7. GPIO FPGA IP
847266 | 2025.08.04

Figure 35. GPIO IP Interfaces

Data Pad
Clock GPIO FPGA IP
Reset

Figure 36. GPIO Interface Signals

dout
Data Interface Signals oe
din
pad_in
ck_in pad_in_b
ck_out pad_out
Clock Interface Signals ck GPIO FPGA IP
cke pad_out_b
pad_io
sclr pad_io_b
Reset Interface Signals aclr
aset
sset

Table 55. Pad Interface Signals

The pad interface is the physical connection from the GPIO IP to the pad. This interface can be an input, output
or bidirectional interface, depending on the IP configuration. In this table, SIZE is the data width specified in
the IP parameter editor.

Signal Name Direction Description

pad_in[SIZE-1:0] Input Input signal from the pad.

pad_in_b[SIZE-1:0] Input Negative node of the differential input signal from the pad. This port
is available if you turn on the Use differential buffer option.

pad_out[SIZE-1:0] Output Output signal to the pad.

pad_out_b[SIZE-1:0] Output Negative node of the differential output signal to the pad. This port is
available if you turn on the Use differential buffer option.

pad_io[SIZE-1:0] Bidirectional Bidirectional signal connection with the pad.

pad_io_b[SIZE-1:0] Bidirectional Negative node of the differential bidirectional signal connection with
the pad. This port is available if you turn on the Use differential
buffer option.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

85
 7. GPIO FPGA IP
847266 | 2025.08.04

Table 56. Data Interface Signals

The data interface is an input or output interface from the GPIO IP to the FPGA core. In this table, SIZE is the
data width specified in the IP parameter editor.

Signal Name Direction Description

din[DATA_SIZE-1:0] Input Data input from the FPGA core in output or bidirectional mode.
DATA_SIZE depends on the register mode:
• Bypass or simple register—DATA_SIZE = SIZE
• DDIO—DATA_SIZE = 2 × SIZE

dout[DATA_SIZE-1:0] Output Data output to the FPGA core in input or bidirectional mode,
DATA_SIZE depends on the register mode:
• Bypass or simple register—DATA_SIZE = SIZE
• DDIO—DATA_SIZE = 2 × SIZE

oe[OE_SIZE-1:0] Input OE input from the FPGA core in output mode with Enable output
enable port turned on, or bidirectional mode. OE is active high.
When transmitting data, set this signal to 1. When receiving data,
set this signal to 0. OE_SIZE depends on the register mode:
• Bypass or simple register—DATA_SIZE = SIZE
• DDIO—DATA_SIZE = SIZE

Table 57. Clock Interface Signals

The clock interface is an input clock interface. It consists of different signals, depending on the configuration.
The GPIO IP can have zero, one, two, or four clock inputs. Clock ports appear differently in different
configurations to reflect the actual function performed by the clock signal.

Signal Name Direction Description

ck Input In input and output paths, this clock feeds a packed register or
DDIO.
In bidirectional mode, this clock is the unique clock for the input and
output paths if you turn off the Separate input/output Clocks
parameter.

ck_in Input In bidirectional mode, these clocks feed a packed register or DDIO in
the input and output paths if you turn on the Separate input/
ck_out output Clocks parameter.

cke Input Clock enable.

Table 58. Reset Interface Signals

The reset interface connects the GPIO IP core to the DDIOs.

Signal Name Direction Description

sclr Input Synchronous clear input. Not available if you select None or Preset
for the Enable synchronous clear / preset port option.

aclr Input Asynchronous clear input. Active high. Not available if you select
None or Preset for the Enable asynchronous clear / preset
port option.

aset Input Asynchronous set input. Active high. Not available if you select None
or Clear for the Enable asynchronous clear / preset port
option.

sset Input Synchronous set input. Not available if you select None or Clear for
the Enable synchronous clear / preset port option.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

86
7. GPIO FPGA IP
847266 | 2025.08.04

7.4.1. Shared Signals

• The input, output, and OE paths share the same clear and preset signals.
• The output and OE path shares the same clock signals.

7.4.2. Data Bit-Order for Data Interface

Figure 37. Data Bit-Order Convention
This figure shows the bit-order convention for the din, dout and oe data signals.

SIZE - 1 ... 0 SIZE

t1 t0

SIZE - 1 ... 0 SIZE - 1 ... 0 2 x SIZE

t3 t2 t1 t0

SIZE - 1 ... 0 SIZE - 1 ... 0 SIZE - 1 ... 0 SIZE - 1 ... 0 4 x SIZE

• If the data bus size value is SIZE, the LSB is at the right-most position.
• If the data bus size value is 2 × SIZE, the bus is made of two words of SIZE.
• If the data bus size value is 4 × SIZE, the bus is made of four words of SIZE.
• The LSB is in the right-most position of each word.
• The right-most word specifies the first word going out for output buses and the
first word coming in for input buses.

Related Information
Input Path on page 89

7.4.3. Input and Output Bus High and Low Bits

The high and low bits in the input or output signals are included in the din and dout
input and output buses.

Input Bus

For the din bus, if datain_h and datain_l are the high and low bits, with each
width being datain_width:
• datain_h = din[(2 × datain_width - 1):datain_width]
• datain_l = din[(datain_width - 1):0]

For example, for din[7:0] = 8'b11001010:

• datain_h = 4'b1100
• datain_l = 4'b1010

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

87
 7. GPIO FPGA IP
847266 | 2025.08.04

Output Bus

For the dout bus, if dataout_h and dataout_l are the high and low bits, with each
width being dataout_width:
• dataout_h = dout[(2 × dataout_width - 1):dataout_width]
• dataout_l = dout[(dataout_width - 1):0]

For example, for dout[7:0] = 8'b11001010:

• dataout_h = 4'b1100
• dataout_l = 4'b1010

7.4.4. Data Interface Signals and Corresponding Clocks

Table 59. Data Interface Signals and Corresponding Clocks
Parameter Configuration Signal Name Clock Signal Name

Separate input/output Register mode

Clocks

Off • Simple Register • din ck

• DDIO • dout
• oe
• All pad signals

DDIO • sclr
• sset

On • Simple Register din ck_in

• DDIO
• dout ck_out
• oe

All pad signals • Input path: ck_in

• Output path: ck_out

DDIO • sclr • Input path: ck_in

• sset • Output path: ck_out

7.5. GPIO FPGA IP Architecture

The GPIO IP supports the I/O components and features of the Agilex 3 devices. You
can use the Quartus Prime parameter editor to configure the GPIO IP.

Components of the GPIO IP:

• Double data rate input/output (DDIO)—doubles the data-rate of a communication
channel
• Delay chains—configure the delay chains to perform specific delay and assist in
I/O timing closure
• I/O buffers—connect the pads to the FPGA

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

88
7. GPIO FPGA IP
847266 | 2025.08.04

7.5.1. GPIO FPGA IP Data Paths

Figure 38. High-Level View of Single-Ended I/O
Core GPIO Buffer
OEIN[1:0] OE
Path

DATAIN[3:0] Output
Path

DATAOUT[3:0] Input
Path

Table 60. GPIO IP Data Path Modes

Data Path Register Mode

Bypass Simple Register DDIO

Input Data goes from the delay The DDIO operates as a simple The DDIO operates as a regular
element to the core, bypassing register. The Fitter chooses DDIO.
all double data rate I/Os whether to pack the register in
(DDIOs). the I/O or implement the
register in the core, depending
Output Data goes from the core on the area and timing trade-
straight to the delay element, offs.
bypassing all DDIOs.

Bidirectional The output buffer drives both an The DDIO operates as a simple The DDIO operates as a regular
output pin and an input buffer. register. The output buffer DDIO. The output buffer drives
drives both an output pin and both an output pin and an input
an input buffer. buffer. The input buffer drives a
set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.

7.5.1.1. Input Path

The pad sends data to the input buffer, and the input buffer feeds the delay element.
After the data goes to the output of the delay element, the programmable bypass
multiplexers select the features and paths to use.

Figure 39. Simplified View of Single-Ended HSIO Input Path

aclr / sclr
aset / sset

dout[0] Pad
DDIO Delay
IN Element
dout[1]

ck

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

89
 7. GPIO FPGA IP
847266 | 2025.08.04

Figure 40. Input Path Waveform in DDIO Mode

The actual timing relationship between different signals may vary depending on the specific design, delays, and
phases that you specify for the clock.

pad D0 D1 D2 D3 D4 D5 D6 D7
ck
dout[0] D0 D2 D4 D6
dout[1] D1 D3 D5 D7

Related Information
Data Bit-Order for Data Interface on page 87

7.5.1.2. Output and Output Enable Paths

The output delay element sends data to the pad through the output buffer.

Figure 41. Simplified View of Single-Ended HSIO Output Path

oe
From Output Enable Path
aclr / sclr
aset / sset

din[0]
DDIO Delay Pad
OUT Element
din[1]

ck

Figure 42. Output Path Waveform in DDIO Mode

din[0] 0 1 0 1 0 1 0 1 0 1 0
din[1] 0 1 0 1 0 1 0 1 0 1 0 1
ck
Pad 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Figure 43. Simplified View of Output Enable Path

aclr / sclr
aset / sset

oe Delay
FF Element

From Output
ck Data Path

The difference between the output path and output enable (OE) path is that the OE
path does not contain DDIO. To support packed-register implementations in the OE
path, a simple register operates as DDIO.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

90
7. GPIO FPGA IP
847266 | 2025.08.04

7.5.2. Register Packing

The GPIO IP allows you to pack registers into the periphery to save area and resource
utilization.

You can configure the DDIO on the input and output path as a flip flop by adding .qsf
assignments.

Table 61. Register Packing .qsf Assignments

Path .qsf Assignment

Input register set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>

packing

Output register set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>

packing

Output enable set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to

register packing register>

Note: The .qsf assignments do not guarantee register packing. However, these
assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps
the flip flop in the core.

7.6. Verifying Resource Utilization and Design Performance

You can refer to the Quartus Prime compilation reports to get details about the
resource usage and performance of your design.
1. From the Quartus Prime menu, select Processing ➤ Start Compilation to run a
full compilation.
2. Wait for the compilation to complete.
3. From the Quartus Prime menu, select Processing ➤ Compilation Report.
4. Using the Table of Contents, navigate to Fitter ➤ Resource Section.
a. To view the resource usage information, select Resource Usage Summary.
b. To view the resource utilization information, select Resource Utilization by
Entity.

7.7. GPIO FPGA IP Timing

The performance of the GPIO IP depends on the I/O constraints and clock phases. To
validate the timing for your GPIO configuration, Altera recommends that you use the
Timing Analyzer.

Related Information
Using the Quartus Prime Timing Analyzer, Quartus Prime Pro Edition User Guide:
Timing Analyzer

7.7.1. Timing Components

The GPIO IP timing components consist of two paths.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

91
 7. GPIO FPGA IP
847266 | 2025.08.04

• I/O interface paths—from the FPGA to external receiving devices and from
external transmitting devices to the FPGA.
• Core interface paths of data and clock—from the I/O to the core and from the core
to I/O.

Note: The Timing Analyzer treats the path inside the DDIO_IN and DDIO_OUT blocks as
black boxes.

Figure 44. Input Path Timing Components

ACLR_N
APRE_N

DATAOUT[0] Pad
DDIO Delay
Core Interface Data Path Element
IN
DATAOUT[1]
I/O Interface Path

CK
Core Interface Clock Path

Figure 45. Output Path Timing Components

OE
From Output Enable Path
ACLR_N
APRE_N

DATAOUT[0]
DDIO Delay Pad
Core Interface Data Path
OUT Element
DATAOUT[1]
I/O Interface Path

CK
Core Interface Clock Path

Figure 46. Output Enable Path Timing Components

ACLR_N
APRE_N
I/O Interface Path

OEIN Delay
FF Element
Core Interface Data Path
From Output
CK Data Path
Core Interface Clock Path

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

92
7. GPIO FPGA IP
847266 | 2025.08.04

7.7.2. Delay Elements

The Quartus Prime software does not automatically set delay elements to maximize
slack in the I/O timing analysis. To close the timing or maximize slack, set the delay
elements manually in the Quartus Prime settings file (.qsf).

Table 62. Delay Elements .qsf Assignments

Specify these assignments in the .qsf to access the delay elements.

Delay Element .qsf Assignment

Input Delay Element set_instance_assignment –to <PIN> -name INPUT_DELAY_CHAIN <0..63>

Output Delay Element set_instance_assignment –to <PIN> -name OUTPUT_DELAY_CHAIN <0..15>

Output Enable Delay set_instance_assignment –to <PIN> -name OE_DELAY_CHAIN <0..15>

Element

The Agilex 3 FPGAs and SoCs Device Data Sheet provides information on delay chain
specification and offset settings across fast and slow models.
• Fast model—Specifies the delay value when the maximum delay chain offset
setting is selected using the fastest process.
• Slow model—Specifies the delay value when the maximum delay chain offset
setting is selected using the slowest process within a specific speed grade.

For example, if you assign input delay chain setting to #10 using an Agilex 3 device
with -1 speed grade:
• Minimum delay value = 10 * delay specification for fast model / 63 = x ns
• Maximum delay value = 10 * delay specification for -1V slow model / 63 = y ns

The input delay ranges from x ns to y ns when you select -1 device speed grade in
your design.

Note: The IOE delay chains are not process, voltage and temperature (PVT) compensated,
which means the delay chain value changes across PVT.

7.7.3. Timing Analysis

The Quartus Prime software does not automatically generate the SDC timing
constraints for the GPIO IP. You must manually enter the timing constraints.

Follow the timing guidelines and examples to ensure that the Timing Analyzer
analyzes the I/O timing correctly.
• To perform proper timing analysis for the I/O interface paths, specify the system
level constraints of the data pins against the system clock pin in the .sdc file.
• To perform proper timing analysis for the core interface paths, define these clock
settings in the .sdc file:
— Clock to the core registers
— Clock to the I/O registers for the simple register and DDIO modes

Related Information
AN 433: Constraining and Analyzing Source-Synchronous Interfaces
Describes techniques for constraining and analyzing source-synchronous interfaces.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

93
 7. GPIO FPGA IP
847266 | 2025.08.04

7.7.3.1. Single Data Rate Input Register

Figure 47. Single Data Rate Input Register

Table 63. Single Data Rate Input Register .sdc Command Examples
Command Command Example Description

create_clock create_clock -name sdr_in_clk -period Creates clock setting for the input clock.
"100 MHz" sdr_in_clk

set_input_delay set_input_delay -clock sdr_in_clk Instructs the Timing Analyzer to analyze the
0.15 sdr_in_data timing of the input I/O with a 0.15 ns input
delay.

7.7.3.2. DDIO Input Register

You can properly constrain the system by using a virtual clock to model the off-chip
transmitter to the FPGA.

Figure 48. DDIO Input Register

Outside FPGA FPGA

Table 64. DDIO Input Register .sdc Command Examples

Command Command Example Description

create_clock create_clock -name virtual_clock Create clock setting for the virtual clock and the
-period "200 MHz" DDIO clock.
continued...

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

94
7. GPIO FPGA IP
847266 | 2025.08.04

Command Command Example Description

create_clock -name ddio_in_clk

-period "200 MHz" ddio_in_clk

set_input_delay set_input_delay -clock virtual_clock Instruct the Timing Analyzer to analyze the
0.25 ddio_in_data positive clock edge and the negative clock edge
of the transfer. Note the -add_delay in the
set_input_delay -add_delay
second set_input_delay command.
-clock_fall -clock virtual_clock 0.25
ddio_in_data

set_false_path set_false_path -fall_from Instruct the Timing Analyzer to ignore the

virtual_clock -rise_to ddio_in_clk positive clock edge to the negative edge
triggered register, and the negative clock edge to
set_false_path -rise_from
the positive edge triggered register.
virtual_clock -fall_to ddio_in_clk

7.7.3.3. Single Data Rate Output Register

Figure 49. Single Data Rate Output Register

Table 65. Single Data Rate Output Register .sdc Command Examples
Command Command Example Description

create_clock and create_clock -name sdr_out_clk Generate the source clock and the output clock
create_generated_ -period "100 MHz" sdr_out_clk to transmit.
clock create_generated_clock -source
sdr_out_clk -name sdr_out_outclk
sdr_out_outclk

set_output_delay set_output_delay -clock Instructs the Timing Analyzer to analyze the

sdr_out_outclk 0.45 sdr_out_data output data to transmit against the output
clock to transmit.

7.7.3.4. DDIO Output Register

Table 66. DDIO Output Register .sdc Command Examples

Command Command Example Description

create_clock and create_clock -name ddio_out_clk Generate the clocks to the DDIO and the clock
create_generated_ -period "200 MHz" ddio_out_clk to transmit.
clock
continued...

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

95
 7. GPIO FPGA IP
847266 | 2025.08.04

Command Command Example Description

create_generated_clock -source
ddio_out_clk -name ddio_out_outclk
ddio_out_outclk

set_output_delay set_output_delay -clock Instruct the Timing Analyzer to analyze the

ddio_out_outclk 0.55 ddio_out_data positive and negative data against the output
clock.
set_output_delay -add_delay
-clock_fall -clock ddio_out_outclk
0.55 ddio_out_data

set_false_path set_false_path -rise_from Instruct the Timing Analyzer to ignore the

ddio_out_clk -fall_to rising edge of the source clock against the
ddio_out_outclk falling edge of the output clock, and the falling
edge of source clock against rising edge of
set_false_path -fall_from output clock
ddio_out_clk -rise_to
ddio_out_outclk

7.7.4. Timing Closure Guidelines

For the GPIO input registers, the input I/O transfer is likely to fail the hold time if you
do not set the input delay chain. This failure is caused by the clock delay being larger
than the data delay.

However, if the I/O PLL drives the clocks of the GPIO input registers (simple register
or DDIO mode), you can set the compensation mode to source synchronous mode.
The Fitter automatically configures the I/O PLL to improve the setup and hold slack for
the input I/O timing analysis.

For the GPIO output and output enable registers, you can add delay to the output data
and clock using the output and output enable delay chains.
• If you observe setup time violation, you can increase the output clock delay chain
setting.
• If you observe hold time violation, you can increase the output data delay chain
setting.

7.8. GPIO FPGA IP Design Examples

The GPIO IP can generate design examples that match your IP configuration in the
parameter editor. You can use these design examples as references for instantiating
the IP and reviewing the expected behavior in simulations.

You can generate the design examples from the GPIO IP parameter editor. After you
set the parameters that you want, click Generate Example Design. The IP
parameter editor generates the design example source files in the directory you
specify.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

96
7. GPIO FPGA IP
847266 | 2025.08.04

Figure 50. Source Files in the Generated Design Example Directory

Design Example Folder

ed_sim.qsys
ed_synth.qsys
make_qii_design.tcl
make_sim_design.tcl
params.tcl
readme.txt

Note: The .qsys files are for internal use during design example generation only. You
cannot edit these .qsys files.

7.8.1. GPIO FPGA IP Synthesizable Quartus Prime Design Example

The synthesizable design example is a compilation-ready Platform Designer system
that you can include in an Quartus Prime project.

Generating and Using the Design Example

To generate the synthesizable Quartus Prime design example from the source files,
run the following command in the design example directory:
quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following command:

quartus_sh -t make_qii_design.tcl [device_name]

The TCL script creates a qii directory that contains the ed_synth.qpf project file.
You can open and compile this project in the Quartus Prime software.

7.8.2. GPIO FPGA IP Simulation Design Example

The simulation design example uses your GPIO IP parameter settings to build the IP
instance connected to a simulation driver. The driver generates random traffic and
internally checks the legality of the out going data.

Using the design example, you can run a simulation using a single command,
depending on the simulator that you use. The simulation demonstrates how you can
use the GPIO IP.

Generating and Using the Design Example

To generate the simulation design example from the source files for a Verilog
simulator, run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

97
 7. GPIO FPGA IP
847266 | 2025.08.04

To generate the simulation design example from the source files for a VHDL simulator,
run the following command in the design example directory:
quartus_sh -t make_sim_design.tcl VHDL

The TCL script creates a sim directory that contains subdirectories—one for each
supported simulation tool. You can find the scripts for each simulation tool in the
corresponding directories.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

98
 847266 | 2025.08.04

Send Feedback

8. Programmable I/O Features Description

Table 67. I/O Features and Description
I/O Features Description

Programmable Each I/O pin contains a slew rate control, allowing you to specify the slew rate on a pin-by-pin basis.
Output Slew Rate The slew rate control affects both the rising and falling edges of the signal.
Control A faster slew rate provides high-speed transitions for high-performance systems while a slower slew
rate reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

Programmable You can activate the programmable IOE delays to ensure zero hold time, minimize setup time, or
IOE Delay increase the clock-to-output time. This feature helps read and write timing margins because it
minimizes the uncertainties between signals on the bus.
Each pin can have a different input delay from the pin-to-input register or a delay from output
register-to-output pin values. This is to ensure that the signals within a bus have the same delay
going into or out of the device.

Programmable You can assign current strength setting to the single-ended output buffer.
Current Strength For a list of I/O standards that support programmable current strength, refer to the related
information.
The current strength setting is not supported for:
• HSIO banks
• Input-only pins
• Pins with I/O standards that use true differential output buffers
• Dedicated programming pins such as TDO

Programmable The programmable open-drain output provides a high-impedance state on output when logic to the
Open-Drain output buffer is high. If logic to the output buffer is low, the output is low.
Output You can attach several open-drain outputs to a wire. This connection type is like a logical OR function
and is commonly called an active-low wired-OR circuit. If at least one of the outputs is in logic 0 state
(active), the circuit sinks the current and brings the line to low voltage.
You can use open-drain output if you are connecting multiple devices to a bus. For example, you can
use the open-drain output for system-level control signals that can be asserted by any device or as an
interrupt.

Programmable Each I/O pin on supported banks provides an optional programmable pull-up resistor during user
Pull-Up Resistor mode. The pull-up resistor weakly holds the I/O to the I/O bank power supply level.

Programmable Each I/O pin on supported banks provides an optional programmable pull-down resistor during user
Pull-Down mode. The pull-down resistor weakly holds the I/O to the ground level.
Resistor

Programmable Pre-emphasis momentarily boosts the high-frequency component of the output signal during
Pre-Emphasis switching to increase the output slew rate. The amount of pre-emphasis required depends on the
attenuation of the high-frequency component along the transmission line.
For more information, refer to Programmable Pre-Emphasis on page 100.

Programmable De-emphasis attenuates the I/O signal height when the symbol is longer than the specified duration.
De-Emphasis You can use de-emphasis to alter the signal amplitude to compensate for signal degradation over long
transmission path.
For more information, refer to Programmable De-Emphasis on page 101.

Receiver The FPGAs support Continuous Time Linear Equalization (CTLE) on all HSIO input buffers except for
Equalization 1.0 V, 1.05 V, 1.1 V, 1.2 V, and 1.3 V LVCMOS I/O standards. You can turn on CTLE for external
Calibration memory interface implementation.
For more information, refer to Continuous Time Linear Equalization on page 103.
continued...

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.
 8. Programmable I/O Features Description
847266 | 2025.08.04

I/O Features Description

Programmable The programmable VOD settings allow you to adjust the output eye-opening to optimize the trace
Differential Output length and power consumption. A higher VOD swing improves voltage margins at the receiver end, and
Voltage a smaller VOD swing reduces power consumption.
For more information, refer to Programmable Differential Output Voltage on page 102.

Schmitt Trigger The Schmitt Trigger allows input buffers to respond to slow input edge rates with a fast output edge
rate. Most importantly, Schmitt Triggers provide hysteresis on the input buffer, preventing slow-rising
noisy input signals from ringing or oscillating on the input signal driven into the logic array.
This feature provides system noise tolerance on the device inputs but adds a small, nominal input
delay.

On-Die The HPS and SDM input pins support on-die pull-up and pull-down termination. The on-die
Termination termination provides impedance matching and termination capabilities. You can enable this feature on
Impedance input operations to minimize reflections and improve electrical margins.

Related Information
• Programmable I/O Element Features for the HVIO Bank on page 53
• Programmable I/O Element Features for the HPS I/O Bank on page 62

8.1. Programmable Pre-Emphasis

The VOD setting and the output impedance of the driver set the output current limit of
a high-speed transmission signal. At a high frequency, the slew rate may not be fast
enough to reach the full VOD level before the next edge, producing pattern-dependent
jitter. With pre-emphasis, the output current is boosted momentarily during switching
to increase the output slew rate.

Pre-emphasis increases the amplitude of the high-frequency component of the output

signal and thus helps to compensate for the frequency-dependent attenuation along
the transmission line. The overshoot introduced by the extra current happens only
during a change of state switching to increase the output slew rate and does not ring,
unlike the overshoot caused by signal reflection. The amount of pre-emphasis required
depends on the attenuation of the high-frequency component along the transmission
line.

Figure 51. Programmable Pre-emphasis

This figure shows the true differential output with pre-emphasis.

Voltage boost
from pre-emphasis
VP
OUT

VOD

OUT
VP
Differential output
voltage (peak–peak)

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

100
8. Programmable I/O Features Description
847266 | 2025.08.04

8.2. Programmable De-Emphasis

To compensate for signal degradation over long transmission path, you can alter the
signal amplitude through the programmable de-emphasis feature.

Table 68. Programmable De-Emphasis Feature Description

Item Description

Availability Available for the following I/O standards:

• SSTL-12 and Differential SSTL-12
• HSTL-12 and Differential HSTL-12
• HSUL-12 and Differential HSUL-12
• POD 11 and Differential POD11
• POD12 and Differential POD12
• LVSTL11 and Differential LVSTL11
• LVSTL105 and Differential LVSTL105
• SLVS-400
• DPHY

Implementation Two-tap de-emphasis implementation:

• A main tap
• A delayed post tap at 1 UI

Behavior If turned on, the feature attenuates the I/O signal height, when the symbol is longer than 1 UI.

Types • Constant impedance de-emphasis:

— Provides double the effective equalization level of the low power de-emphasis.
— Three equalization settings: low, medium, and high.
• Low power de-emphasis:
— Three equalization settings: low, medium, and high.

Recommendations • The de-emphasis effect reduces eye height. If you use a non-default de-emphasis setting,
perform an IBIS or HSPICE simulation to estimate the I/O buffer's electrical performance.
• To get the optimal setting for your design, start the simulation with the lowest de-emphasis
setting. Then, fine-tune the setting until you get the best signal integrity condition.

Figure 52. De-Emphasis Off: Signal Attenuation for Supported I/O Standards
1 UI

1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 VTT (†)

(†) Offset voltage has dependency on the board termination setup and voltages.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

101
 8. Programmable I/O Features Description
847266 | 2025.08.04

Figure 53. Constant Impedance De-Emphasis: Signal Attenuation for Supported I/O
Standards
1 UI

LOW

HIGH
1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 VTT (†)
HIGH

LOW
(†) Offset voltage has dependency on the board termination setup and voltages.

Figure 54. Low Power De-Emphasis: Signal Attenuation for Supported I/O Standards
1 UI
LOW

HIGH

1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 VTT (†)

HIGH

LOW
(†) Offset voltage has dependency on the board termination setup and voltages.

8.3. Programmable Differential Output Voltage

The programmable VOD settings allow you to adjust the output eye-opening to
optimize the trace length and power consumption. A higher VOD swing improves
voltage margins at the receiver end, and a smaller VOD swing reduces power
consumption. You can statically adjust the VOD of the differential signal by changing
the VOD settings in the Quartus Prime software Assignment Editor.

General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs Send Feedback

102
8. Programmable I/O Features Description
847266 | 2025.08.04

Figure 55. Differential VOD

This figure shows the VOD of the true differential output.

Single-Ended Waveform

Positive Channel (p)

VOD
Negative Channel (n)
VCM
Ground

Differential Waveform VOD (diff peak - peak) = 2 x VOD (single-ended)

VOD
p-n=0V
VOD

8.4. Continuous Time Linear Equalization

Each supported receiver uses a programmable equalization circuit that boosts the
high-frequency gain of the incoming signal to compensate for the low-pass
characteristics of the physical medium.

You can set this feature to automatically tune the receiver equalization settings based
on the frequency content of the incoming signals. Through the automatic tuning, you
can obtain the optimal CTLE settings.

The Agilex 3 FPGAs support a one-time receiver CTLE calibration. If you enable this
feature, the calibration finds a stable receiver equalizer setting. Once found, the
feature locks the equalizer value to the stable setting.

Send Feedback General-Purpose I/O User Guide: Agilex 3 FPGAs and SoCs

103
847266 | 2025.08.04

Send Feedback

9. Document Revision History for the General-Purpose

I/O User Guide: Agilex 3 FPGAs and SoCs
Document Version Quartus Prime Changes
Version

2025.08.04 25.1.1 • Added new topic—Clock Restrictions for GPIO Interfaces.

• Updated Placement Restrictions for True Differential and Single-Ended
I/O Standards in the Same or Adjacent HSIO Bank.
• Updated the note about VREF Sources and Input Standards Grouping.
• Updated Unused Pins.
• Updated the following IP names:
— "Hard Processor System Agilex 3 FPGA IP" to "Hard Processor
System FPGA IP"
— "GPIO Intel® FPGA IP" to "GPIO FPGA IP".
• Updated Table: GPIO FPGA IP Current Release Information.

2025.04.07 25.1 Initial release.

© Altera Corporation. Altera, the Altera logo, the ‘a’ logo, and other Altera marks are trademarks of Altera
Corporation. Altera reserves the right to make changes to any products and services at any time without notice.
Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing
orders for products or services.
*Other names and brands may be claimed as the property of others.