A Highly Scalable, Time-Based Capless Low-Dropout

Regulator Using Master-Slave Domino Control

Abirmoya Santra1,2, Angelo De Carmine1, Guttha Venkata Sesha Rao1, Qadeer A. Khan1
[ee16d040, ee14b072, ee17s012]@smail.iitm.ac.in, [email protected], [email protected]
1 2
Department of Electrical Engineering Sankalp Analog Solutions,
Indian Institute of Technology Madras Sankalp Semiconductor Pvt. Ltd.,
Chennai, INDIA Hubli, INDIA

Abstract—An ultra-low quiescent current capacitor-less low- to improve transients and PSR will lead to a higher quiescent
drop out (LDO) regulator is proposed in this paper. The LDO is power in LDO [2].
designed using domino control which automatically increases or
decrease the drive strength based on load current. Quiescent Dominant pole to be at VGATE Large size MP forces
current of the proposed LDO also varies with load current hence slow down the loop or requires dominant pole to be at VGATE
current consumption is minimized under light load condition. large current in error amplifier
The proposed LDO architecture is fully scalable and can be VDD
easily scaled up for higher load currents with almost no design VREF
efforts. Implemented in TSMC-65nm, it uses only 1pF of on-chip VGATE
compensation capacitor and consumes a quiescent current of AEA MP
11.5µA. For an input of 1.2 V and output of 0.9V to 1.1V, settling CGATE
VO
time of <200ns with undershoot/overshoot of 62mV/40mV for 0- Error
5mA in 100ns load step is achieved 1pF output capacitor. Amplifier RFB1
VFB CO
Keywords— Power management, voltage regulator, low drop- RLOAD
out regulator (LDO), error-amplifier, voltage controlled oscillator RFB2
(VCO), time-based control, flipped source follower, capless LDO,
Digital LDO, domino control.
Fig. 1 A conventional analog LDO.
I. INTRODUCTION Recently, the digital LDO (D-LDO) gained a large
As technology is paving its way into the Internet-of-Things popularity due to its low-voltage operation capability, process
(IoT), demand for highly efficient power management is portability and low quiescent power [4-6]. However, the
growing up exponentially. Since battery life of sensors, baseline D-LDO faces the fundamental tradeoffs among
wearables and other battery powered devices is critical, transient response, output resolution, output voltage ripple and
especially when these devices are not large enough to house a poor supply noise rejection. Fig. 2 shows the architecture of a
large battery, efficient power delivery to these modules conventional D-LDO based on single bit A/D converter and
becomes essential without compromising the performance. digital accumulator. Since accumulator acts as digital
These battery powered devices are mostly powered-up by a integrator, the update rate (clock speed) should be much less
sophisticated power management IC (PMIC) which contains than time constant at VO which therefore limits the transient
multiple switching and low dropout regulators (LDO) on a response. Accuracy of the output in D-LDO is determined by
single chip [1]. Even though LDOs cater to smaller portion of the step size of LSB hence may often require more than 10-bit
power need, they may still outnumber switching regulators. resolution to achieve accuracy as good as analog. Increasing
This is mainly due to large number of low power analog the resolution of D/A converter not only complicates the design
modules such as sensors, A/D-D/A converters, amplifiers, but further slows down the loop.
filters, clock generators, etc. Due to limited board space Comparator Digital Accumulator Pass Elements
available on a mobile device, integrating such a large number (A/D Converter) (Up/Down Counter) (D/A Converter)
VREF
of LDOs on a single chip requires smaller on-chip and off-chip DERROR
VDD VDD VDD
area. Moreover, depending upon the nature of the load, these (0 or 1)
DCTRL[n-1:0]

LDOs should be capable of operating with wide range of load MP0 MP1 MPn-1
currents and output capacitors. Z-1
Actual VO

Fig.1 shows the circuit diagram of a conventional analog Accumulator slows Error
down the loop VO
LDO where large size pass element MP, forces dominant pole CLK Desired VO
RFB1
to be at VGATE which slows down the transient response as well VFB CO
LSB
as degrades PSR. Transient response can be improved by RFB2
RLOAD
increasing the slew rate of the error amplifier (EA) and the
loop response. Whereas for improving PSR; a high gain and a Fig. 2 A conventional digital LDO.
wide bandwidth of the loop is required. Both these techniques

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 Some implementations [4-5] use a large decap at the output LDOs are only activated one by one when load current rises.
to improve transients and PSR while others [6] use complex During low load current (<1mA) only master LDO is kept
course-fine multi-loop architectures. enabled hence reducing the overall IQ significantly without
In this paper, a highly scalable time-based LDO using compromising the performance. The phenomenon of domino
master slave domino control has been proposed to reap the control is illustrated in Fig. 3 which shows how slaves LDOs
benefits of both analog and digital LDOs and systematically are turned ON and OFF based on increasing and decreasing
compensate their demerits. The proposed LDO is a true capless load current.
LDO, doesn’t suffer from limit cycle oscillations and has
excellent PSR and transient response. In achieving these, the
quiescent power has not been compromised.
Section II elaborates on the details of the proposed 4 Each slave LDO is designed to

No. of Slave LDOs Enabed

architecture including time-based master and Gm based slave handle load current of up to 1mA
LDOs. Simulation results are presented in Section III followed
by conclusion in Section IV. Hysteresis
3 Increasing
II. PROPOSED LDO WITH DOMINO CONTROL Load Current
Conceptual architecture of the proposed LDO is shown in
Fig. 3. It consists of a master LDO with high gain error 2 Decreasing Fine load regulation is
amplifier (EA) which generates the control voltage V CM for Load Current controlled by the master LDO
pass transistor MPM. Multiple slave LDOs with
transconductor, Gm followed by proportional resistor RP with Master LDO can handle load
1 transient of 5mA/100ns
dc bias at VCM, are used to generate the corresponding control
voltages, VCTRL_S to drive slave pass transistors, MPS. Only Master LDO is Enabled
for Load Current <1mA

nth SLAVE LDO 0

(Enabled by (n-1)th LDO) 0mA 1mA 2mA 3mA 4mA 5mA
Max. Load VDD
VREF Load Current
VCTRL_Sn
Gm MPS
RP Fig. 4 No. of slave LDOs vs. load current.
VFB VCM

EN
Increasing Load Current

Design details of LDOs and generation of enable signals are

Enable from
(n-1)th Slave LDO
discussed in the following sub-sections.
Enable to 3rd
Slave LDO
nd
2 SLAVE LDO
(Enabled 1st Slave LDO)
VDD A. Master LDO
VREF
VCTRL_S2
Gm MPS
RP Master LDO, shown in Fig. 5, is designed using time-
VFB VCM based error amplifier which offer smaller area and low
1st SLAVE LDO
(Enabled by Master LDO)
EN quiescent current compared to conventional error amplifier
VREF
VDD [7]. Time based error amplifier generates control voltage
VCTRL_S1
Gm MPS VCTRL for flipped voltage follower based pass element which
RP regulates the output voltage VO to a desired value.
VFB VCM
Min. Load Time-Based Error Amplifier Pass Element Hysteretic Current Comparator
VDD
VCM VDD EN
VCO
MP
VDD VDD
VREF VFB VREF

VREF ɸREF UP 1µA

Gmz
1000x

MP_SF
MPC
1/2x
EN
EN
EA MPM VCTRL
EN (To first
VO PFD DN EN
slave LDO)
VFB ɸFB 1µA 80k
VGATE
0.4µA 0.1µA
VFB RFB2 1pF
VCM 2µA

RL VCO
RFB1 CL
Master LDO
VFB
(Always ON) VO
RL CL
RFB2
RFB1

Fig. 3 Architecture of the proposed LDO based on master-slave domino

control. Fig. 5 Circuit diagram of the time-based master LDO.

While master LDO is always kept enabled, each slave A hysteretic current comparator is used to detect the load
LDO is enabled by previous LDO i.e. 1st slave LDO is enabled current above 1mA and generate enable signal EN which
by the master LDO, 2nd slave LDO enabled by the 1st slave activates 1st slave LDO to support additional load currents.
LDO and so on, creating a domino effect. Therefore, slave

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 Total current consumed by the master LDO was 11.5µA with III. RESULTS AND DISCUSSION
time-based error amplifier taking 9µA and pass element and Stability of the proposed LDO was verified across load
current comparator taking 2µA and 0.5µA, respectively. current 5µA-5mA and output capacitance of 1pF-100pF. It can
B. Slave LDO be observed from Fig. 7 that UGB remains between 2.45-
3.8MHz and phase margin is above 59° degrees for all the
The slave LDO, as shown in Fig. 6, uses pass element and
cases.
current comparator similar to master LDO. In order to avoid
conflict between master and slave LDO, the control voltage,
VCTRL_S for the pass element is generated from a feed-forward
transconductor (Gm) whose DC value is set by the DC control
voltage, VCM, generated by the error amplifier in master LDO.
In steady state, control voltage of slave LDO remains same as
control voltage of master LDO. However, feed-forward
transconductor can instantaneously change VCTRL_S to correct
for any fast changes in the output voltage due to load transient.
Proportional resistor RP helps in isolating the gate of source
follower transistor MP_SF of the slave LDO from that of master
LDO thus preventing any additional capacitive loading at the
output of time-based error amplifier.

Pass Element Hysteretic Current Comparator

Feed-Froward
Transconductor VDD VDD
MP
1000x MPC
1/2x
VREF
VCTRL_S MP_SF
EN
EN Fig.7 Stability response of the proposed LDO.
Gm EN EN (To next
RP VGATE slave LDO)
VFB VCM 0.4µA 0.1µA
2µA
(From Master
LDO)
DC load regulation along with enable signals of 4 slave LDOs
is shown in Fig. 8. Slave LDOs start activating one by one as
VO load current goes above 1mA and all four slave LDOs are
Fig. 6 Circuit diagram of the slave LDO.
turned on for the load current above 4mA. The effectiveness of
slave LDOs can be observed by the output voltage, VO which is
regulated at 1V throughout the entire load range of 0 to 5mA.
Slave LDO is designed to handle approximately 1mA
current so total number of slave LDOs can be chosen based on
the maximum required load current. Hysteretic current
comparator detects load current above 1mA and generate
VO(V)

enable signal EN to activate the next slave LDO to support

additional load currents.

The proposed LDO was designed to handle maximum load

current of 5mA so total of 4 slave LDOs were used with 1mA
supplied by the master LDO.
Volt

Enable 1st Enable 2nd Enable 3rd Enable 4th

Slave LDO Slave LDO Slave LDO Slave LDO

The proposed domino control based on master-slave LDOs

is fully scalable in nature and significantly reduces the design
time. For instance, in order to design an LDO for load current
ILOAD (mA)
of 100mA, the same 5mA LDO architecture can be re-used
and scaled-up by simply stacking 95 more slave LDOs. Even Fig.8 Load regulation and activation of slave LDOs w.r.t. load current.
though each slave LDO consumes 3.5µA, none of these LDOs
are enabled for load current less than 1mA. Therefore,
quiescent current of the proposed LDO is determined only by Load transient response at different output voltages was
the master LDO (which is always ON). Unlike conventional simulated by applying a load step of 100µA↔5mA with
LDOs, which require high quiescent current to support fast rise/fall=100ns as shown in Fig. 9. The LDO achieves settling
transient with wider range of load currents, the proposed time of less than 200ns with undershoot/overshoot of <
domino based architecture guarantees much lower quiescent 62mV/40mV for a minimum output capacitance (1pF).
current.

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 TABLE I. PERFORMANCE TABLE AND COMPARISON
40mV
This ISCAS’17 JSCC’1 ISCAS’18
62mV Metrics [3]
JSCC’18[6]
[7]
VO (mA)

25mV
Work 7[4]

60mV
25mV
Technology 65nm 180nm 28nm 65nm 65nm
60mV
0.5-
1.2/ 1.2/
Vin/Vout 1.84/1.8 1.1/0.9 1/0.45-
0.8-1.1 0.8-1.1
0.95
ILOAD (mA)

Overshoot/
<62/40 50/40 120 105 <160/70
Undershoot(mV)
5mA
Settling Time (µs) <0.2 4.6 1.2 <1 0.2

100ns Current, IQ (µA) 11.5 7 110 3.2 27.5

fUGB (MHz) 2.45 0.1 - - 3

IL.max (mA) 5 50 25 10 10
Fig. 9. Load transient response of the proposed LDO for VO=0.9V,
1.0V and 1.1V. CLOAD=1pF, ILOAD = 100µA-5mA/5mA-100µA with Comp./Load(pF)
10/100 1.2/100
1/100 23500 100
rise/fall=100ns. Cap (CC/CL,max)

FOM1 (ps) 0.285 3.89 704 35 1.76

1
Lower value indicates better performance.
Power supply rejection (PSR) performance shown in Fig.
10 was obtained by adding 100mV pk-to-pk, 1MHz signal IV. CONCLUSION
ripple in VDD and measuring VO. Approx. 33x attenuation in An output capacitor-less time-based LDO using master-
the ripple at LDO output was observed showing high PSR up slave domino control is proposed. The proposed offers highly
to 1MHz. scalable architecture and significantly reduces the design time.
Time-based master LDO offers smaller area with lower current
consumption and can be easily migrated to different process
technologies. Designed in 65nm CMOS process with total on-
chip compensation capacitance of 1pF, proposed LDO
VO (V)

consumes quiescent current of only 11.5µA. Operated at input

voltage of 1.2V, it can regulate output from 0.9V to 1.1V with
load current of 0-5mA and load capacitance of 0-100pF and
offers excellent figure-of-merit compared to state-of-the art
LDOs.
VDD (V)

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