THVD8000

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THVD8000 RS-485 Transceiver with OOK Modulation for Power Line Communication

1 Features 3 Description
• 3-V – 5.5-V supply voltage THVD8000 is an RS-485 transceiver with on-off
• Half-duplex communication keying (OOK) modulation and demodulation built in
– Up to 500 kbps data rate with f0 / bps = 10 for power line communication. Modulating data onto
– Higher data rates are possible with f0 / bps < 10 existing power lines allows power delivery and data
communication to share a common pair of wires,
• RS-485 electrical signaling with on-off keying
resulting in a significant reduction of the system cost.
(OOK) modulation
• Pin selectable carrier frequency: 125 kHz – 5 MHz A pin programmable interface simplifies the system
• Spread spectrum clocking for excellent EMI design. The carrier frequency can be adjusted by
performance changing an external resistor on the F_SET pin. A
• Polarity free broad range of carrier frequencies gives the system
designer the flexibility to choose the external inductors
• TX timeout to avoid stuck bus conditions
and capacitors. In addition, OOK modulation operates
• Operational common-mode range: –7 V to 12 V with immunity to data polarity for ease of system
• Bus I/O protection installations.
– ± 18-V DC fault protection
Device Information
– ± 16 kV HBM ESD
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
– ± 8 kV IEC 61000-4-2 contact discharge
THVD8000 SOT-23 (8) 2.90 mm × 1.60 mm
– ± 15 kV IEC 61000-4-2 air gap discharge
– ± 4 kV IEC 61000-4-4 fast transient burst (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Extended temperature range: -40°C to 125°C
• 8-Pin SOT-23 package for space constrained
applications
2 Applications
• HVAC systems
• Building automation
• Factory automation & control
• Appliances
• Lighting
• Grid infrastructure
• Power delivery
AC/DC
supply
Load

Vcc L1 L2 L3 L4 Vcc
C1 C3
R R
MCU MODE THVD8000
THVD8000 MODE MCU
D D
C2 C4
GND GND

Simplified Schematic

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Table of Contents
1 Features............................................................................1 8.2 Functional Block Diagrams....................................... 14
2 Applications..................................................................... 1 8.3 Feature Description...................................................14
3 Description.......................................................................1 8.4 Device Functional Modes..........................................16
4 Revision History.............................................................. 2 9 Application Information Disclaimer............................. 17
5 Pin Configuration and Functions...................................3 9.1 Application information..............................................17
6 Specifications.................................................................. 4 9.2 Typical application (OOK mode)............................... 17
6.1 Absolute Maximum Ratings ....................................... 4 10 Power supply recommendations............................... 19
6.2 ESD Ratings .............................................................. 4 11 Layout........................................................................... 20
6.3 ESD Ratings - IEC Specifications .............................. 4 11.1 Layout guidelines.................................................... 20
6.4 Recommended Operating Conditions ........................4 11.2 Layout Example...................................................... 20
6.5 Thermal Information ...................................................5 12 Device and Documentation Support..........................21
6.6 Electrical Characteristics ............................................5 12.1 Device Support....................................................... 21
6.7 Power Dissipation Characteristics ............................. 7 12.2 Receiving Notification of Documentation Updates..21
6.8 Switching Characteristics ...........................................7 12.3 Support Resources................................................. 21
6.9 Typical Characteristics................................................ 8 12.4 Trademarks............................................................. 21
7 Parameter Measurement Information............................ 9 12.5 Electrostatic Discharge Caution..............................21
8 Detailed Description......................................................14 12.6 Glossary..................................................................21
8.1 Overview................................................................... 14

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (May 2020) to Revision A (March 2021) Page

• Changed the data sheet status From: Advanced Information To: Production data............................................ 1

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5 Pin Configuration and Functions

R 1 8 V
CC

MODE 2 7 B

F_SET 3 6 A

D 4 5 GND

Not to scale

Figure 5-1. DRL Package, 8-Pin SOT-23, Top View

Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
R 1 Digital output Receive data output
Transmit/receive mode selection. Low = receive mode; High = transmit mode. 2-MΩ
MODE 2 Digital input
pull-down to GND
F_SET 3 Analog input Carrier frequency selection. Use a resistor to GND to select a frequency.
D 4 Digital input Driver data input, 2-MΩ pull-up to VCC
GND 5 Ground Device ground
A 6 Bus input/output Bus I/O port A (complementary to B)
B 7 Bus input/output Bus I/O port B (complementary to A)
VCC 8 Power 3.3-V to 5-V device supply

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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VL Input voltage at any logic pin (D, MODE or F_SET) –0.3 5.7 V
VA, VB Voltage at A or B inputs (differential or with respect to GND) –18 18 V
IO Receiver output current –24 24 mA
TJ Junction temperature 170 °C
TSTG Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
A and B pins to GND ±16,000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
All pins ±4,000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-
All pins ±1,500
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings - IEC Specifications

VALUE UNIT
IEC 61000-4-2 ESD contact discharge, A and B pins to GND ±8,000
V(ESD) Electrostatic discharge IEC 61000-4-2 ESD air gap discharge, A and B pins to GND ±15,000 V
IEC 61000-4-4 electrical fast transient, A and B pins to GND ±4,000

6.4 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage 3 5.5 V
VID Input differential voltage (A and B pins) –7 12 V
VCM Operational common mode voltage (A and B pins) –7 12 V
VIH High-level input voltage (D and MODE pins) 2 VCC V
VIL Low-level input voltage (D and MODE pins) 0 0.8 V
Driver –60 60
IO Output current mA
Receiver –4 4
RF_SET Carrier frequency selection resistor 1.5 80 kΩ
ΔRF_SET Carrier frequency selection resistor tolerance –2 2 %
1/tUI Data rate Modulation mode(1) f0 / 10 bps
CF_SET Recommended load capacitance on F_SET pin 100 pF
TA Operating ambient temperature –40 125 °C

(1) f0 is the carrier frequency (in Hz) set by the external resistor between F_SET and GND pins.

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6.5 Thermal Information

THVD8000
THERMAL METRIC(1) DDF (SOT-23) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 106.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 38.4 °C/W
RθJB Junction-to-board thermal resistance 29.9 °C/W
ψJT Junction-to-top characterization parameter 29.5 °C/W
ψJB Junction-to-top characterization parameter 29.5 °C/W

(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted). All typical values are measured at 25°C and supply
voltage of VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
RL = 60 Ω, –7 V ≤ Vtest ≤ 12 V,
See Figure 7-1 1.5 3.5
Measured at 2nd pulse
Driver differential output voltage RL = 100 Ω, CL = 50 pF, Measured
|VOD| See Figure 7-1 2 4 V
magnitude at 2nd pulse
RL = 54 Ω, CL = 50 pF, Measured
See Figure 7-1 1.5 3.5
at 2nd pulse
Steady state common-mode
VOC RL = 60 Ω, CL = 50 pF See Figure 7-2 1 VCC / 2 3 V
output voltage
Change in differential driver
ΔVOC RL = 60 Ω, CL = 50 pF See Figure 7-2 -160 160 mV
common-mode output voltage
Peak-to-peak driver common- RL = 60 Ω, CL = 50 pF, VCC = 3.3
VOC(PP) See Figure 7-2 425 mV
mode output voltage V and VCC = 5V
IOS Driver short-circuit output current MODE = VCC, –7 V ≤ [VA or VB] ≤ 12 V –250 250 mA
Minimum carrier frequency(1) RF_SET = 77 kΩ 125 kHz
f0 See Figure 7-3
Maximum carrier frequency(1) RF_SET = 1.5 kΩ 5 MHz
Carrier frequency duty cycle
DCDf0 Measured over the full range of f0 –2 2 %
distortion
Δf0 Carrier frequency tolerance Measured with a ±2% tolerant RF_SET –25 25 %
Variation of the carrier frequency
ΔfSSC ±5 %
for spread spectrum clocking Measured across the full carrier frequency range
fSSC Spread spectrum clock rate 30 kHz

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Over operating free-air temperature range (unless otherwise noted). All typical values are measured at 25°C and supply
voltage of VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Receiver

Bus input current in receive VI = 12 V 75 125

II MODE = GND, VCC = 0 V or 5.5 V µA
mode VI = –7 V –97 –70
125 kHz 225
OOK signal differential swing
VMAG_ZERO (magnitude) to detect a zero at 1 MHz 150 mV
the R output
5 MHz 115
125 kHz 20
OOK signal differential swing
MODE = GND, over full common
VMAG_ONE (magnitude) to detect a one at 1 MHz 10 mV
mode range
the R output
5 MHz 10
125 kHz 40
Receiver differential input
VMAG_HYS 1 MHz 20 mV
voltage threshold hysteresis
5 MHz 20
Logic / Control Pins
IIN Input current (D, MODE) VO = 0 V or VCC –5 5 µA
IIN Input current (F_SET) VO = VCC 55 µA
IO = 0 mA 1.4 V
VO Output voltage (F_SET)
1.5 kΩ ≤ RPD ≤ 78 kΩ 785 mV
Receiver high-level output
VOH IOH = –4 mA VCC – 0.4 VCC – 0.2 V
voltage
VOL Receiver low-level output voltage IOL = 4 mA 0.2 0.4 V
Receiver high-impedance output
IOZ VO = 0 V or VCC, MODE = 0 –1 1 µA
current
Device
D = VCC, MODE
= VCC, resistor
Transmit mode 3.1 5
between F_SET
and GND, no load
ICC Supply current (quiescent) mA
D = VCC, MODE
= GND, resistor
Receive mode 4 6
between F_SET
and GND, no load
TSD Thermal shutdown temperature 160 170 185 ℃
THYS Thermal shutdown hysteresis 11 15 ℃

(1) See OOK modulation section for the complete carrier frequency range

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6.7 Power Dissipation Characteristics

Over operating free-air temperature range (unless otherwise noted). All typical values are measured at 25°C and supply
voltage of VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f0 = 125 kHz, 12.5 kHz
(25 kbps) clock pattern 60 80 mW
MODE = VCC, RL = as data
PDOOK Chip power dissipation 60 Ω, no CL, see
Figure 2 f0 = 5 MHz, 500 kHz
(1Mbps) clock pattern as 90 125 mW
data

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted). All typical values are measured at 25°C and supply
voltage of VCC = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr, tf Driver differential output rise and fall times 10 30 ns
RL = 60 Ω, CL = 50 pF,
tPHL, tPLH Driver propagation delay 1.2 2.5 Clocks
See Figure 7-4
tSK(P) Driver pulse skew, |tPHL – tPLH| 0.3 2.5 Clocks
Receiver
tr, tf Receiver output rise and fall times 1.5 16 ns
CL = 15 pF, See Figure
tPHL, tPLH Receiver propagation delay time 4 6.5
7-5 Clocks
tSK(P) Receiver pulse skew, |tPHL – tPLH| 1.1 3
Device
Worst case of tTX-
Transmit to receive mode change delay, RX_OOK_ZERO and tTX-
tTX-RX_OOK For all RFSET 14 clocks
OOK mode RX_OOK_ONE. See Figure
7-6 and Figure 7-7
Receive to transmit mode change delay,
tRX-TX_OOK For all RFSET See Figure 7-8 12 clocks
OOK mode
tTX_TIMEOUT Transmit timeout delay 60 110 s

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6.9 Typical Characteristics

65
-40C (3.3V) -40C (5.5V)
27C (3.3V) 27C (5.5V)
60 125C (3.3V) 125C (5.5V)

55

50

ICC (mA)
45

40

35

30
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
OOK Frequency (MHz)

RL = 60Ω Data rate = ƒ0/10 TX Enabled

Figure 6-1. ICC vs OOK Frequency

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7 Parameter Measurement Information

375

A
D

VOD
RL
GND
+
B ±
Vtest
375

OOK mode

A
VOD
B

Figure 7-1. Measurement of Driver Differential Output Voltage With Common-Mode Load

RL / 2
A
VCC or D
VOD

GND
B RL / 2 CL

VOC
OOK mode
D

VOD = VA - VB

ûVOC
VOC
VOC(PP)

Figure 7-2. Measurement of Driver Differential and Common-Mode Outputs

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tUI

A
B

1 / f0

Figure 7-3. Measurement of Carrier Frequency

A
Clock D RL CL
pattern
B

OOK mode
D tPLH
tPHL

50%

A
B

90%
VA - VB 60% VOD

10%
tr
tf

Figure 7-4. Measurement of Driver Switching Characteristics

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THVD8000 as
DUT
the generator
A
Clock D R
60 50 pF
pattern
CL
B

OOK mode
D

A
B

90%
VA - VB 60% VOD

R tPLH
tPHL
90%
50%
10%

tf tr

Figure 7-5. Measurement of Receiver Characteristics

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VCC
DUT 1k
A
R

B
15 pF
MODE

OOK mode
MODE
F0 = 5 MHz
50%

A 750 mV

Hi-Z -750 mV
B
R

50%

100 ns
tTX-RX_OOK_ZERO

Figure 7-6. Transmit to Receive Mode Change with Low Output

DUT
A
R

B 15 pF 1k
MODE

OOK mode
MODE

50%

A
Hi-Z 0V
B

R 50%

100 ns
tTX-RX_OOK_ONE

Figure 7-7. Transmit to Receive Mode Change with High Output

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A
D
60 50 pF

B
MODE

OOK mode

50%
MODE
A

90%
A-B VOD

tRX-TX_OOK

Figure 7-8. Receive to Transmit Mode Change

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8 Detailed Description
8.1 Overview
THVD8000 enables power line communication using RS-485 physical layer signaling. An integrated OOK
modulator enables RS-485 data to be directly coupled onto existing power cables via series capacitors without
any updates to the MCU or the controller. The THVD8000 receiver extracts the data from the power cables
through series capacitors by using a precise bandpass filter and a demodulator.
8.2 Functional Block Diagrams

VCC

D A
B

F_SET
Logic &
MODE Control

R
Demodulation

GND

8.3 Feature Description

8.3.1 OOK Modulation with F_SET pin
Data at the D input is modulated with the carrier frequency (f0) via the F_SET pin. Figure 8-1 illustrates the
modulation scheme. A high level at the D input is driven to the mid-level with zero differential voltage (VOD). A
low level at the D input is modulated at the carrier frequency. It is recommended to use a carrier frequency that
is 10x higher than the data rate. Higher data rates are possible at the expense of increased pulse width distortion
with the use of lower ratios.

Data input: D

Bus at driver
pins: A / B

Figure 8-1. OOK Modulation Scheme

f0 is programmable by changing the external resistor (RF_SET) value connected to ground. Table 8-1 shows the
carrier frequency for the each recommended resistor value.
Table 8-1. OOK f0 versus RF_SET
RF_SET (kΩ) OOK f0 (kHz)
77 125
50 187.5
19 500

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Table 8-1. OOK f0 versus RF_SET (continued)

RF_SET (kΩ) OOK f0 (kHz)
12.5 750
9.3 1000
4.4 2000
1.5 5000

The oscillator used to generate the carrier frequency features spread spectrum clocking to reduce emissions.
8.3.2 OOK Demodulation
The OOK signal received at the A and B inputs go through a bandpass filter and a peak detector to regenerate
the original data stream. Figure 8-2 shows the OOK input and the R output waveforms. The bandpass filter
characteristics will adapt to optimal settings automatically based on the carrier frequency, set via RF_SET.
Bus at receiver
pins: A / B

Data output: R

Figure 8-2. OOK Demodulation

8.3.3 Transmitter Timeout

The driver path incorporates a timeout feature to prevent a faulty node from occupying the bus indefinitely in a
multi-drop application.
The driver stops transmitting and the outputs will go high impedance if the D input doesn't detect an edge
(either rising or falling) for longer than tTX_TIMEOUT. One of the following events brings the device back to normal
operation.
• Any edge at D input
• Toggle MODE pin
The transmit path resumes operation within tMODE.
8.3.4 Polarity Free Operation
THVD8000 is immune to A and B polarity at the receiver input in OOK mode. The receiver data comparator
only checks for the receive input signal magnitude, ignoring the polarity, to determine its logic level. Note that
reversing the polarity does result in degraded pulse width distortion.
8.3.5 Glitch Free Mode Change
The device incorporates a delay of up to tMODE when changing the state of the MODE pin. This feature ensures
that there are no glitches at the A, B and R outputs when transitioning between transmit and receive modes.
8.3.6 Integrated IEC ESD and EFT Protection
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±8 kV contact and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to
±4 kV. This integrated protection eliminates the need of external components reducing the system BOM.

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8.4 Device Functional Modes

Table 8-2. THVD8000 Functional Modes
F_SET Configuration Device Functional Mode
RF_SET between F_SET and GND OOK mode, f0 set by the RF_SET value
F_SET at high impedance
F_SET at VCC Invalid, not recommended for normal operation
F_SET short to GND

8.4.1 OOK Mode

Data at the D input is modulated with the carrier frequency set by the RF_SET value when the device is
transmitting (MODE = VCC). See Section 8.3.1 section for more details. In receiving (MODE = GND), the device
expects an OOK modulated signal at the A and B inputs. The data is demodulated and sent out via R pin. See
Section 8.3.2 section for more details.
Table 8-3. Driver function table for OOK mode
INPUTS OUTPUTS FUNCTION
F_SET MODE D A B
RF_SET (See Table 8-1) H H or Z Bias to VCM Bias to VCM Driver is actively biased to
VCM on the bus
H L Oscillating Oscillating Bus actively driven at
carrier frequency
L or Z X Z Z Driver disabled, device in
receive mode

Table 8-4. Receiver function table for OOK mode

INPUTS OUTPUT FUNCTION
F_SET MODE Input R
RF_SET (See Table 8-1) L or Z Oscillating at F_SET and VID > L Receive valid bus low
VMAG_ZERO
L or Z Oscillating at F_SET and ? Receive invalid bus, output
VMAG_ONE < VID < VMAG_ZERO indeterminate
L or Z Oscillating at F_SET and VID < H Receive valid bus high
VMAG_ONE
L or Z Z / not oscillating H Receive valid bus high
L or Z OPEN, SHORT, IDLE (VID = 0 V) H Failsafe high output
H X Z Receiver disabled, device in
transmit mode

8.4.2 Thermal shutdown (TSD)

The THVD8000 has a protection feature called thermal shutdown. When the junction temperature reaches TSD,
the device enters thermal shutdown protection mode. This mode disables the driver and receiver outputs, which
will halt all communication through the device. Normal operation resume once the junction temperature drops out
of thermal shutdown, which is typically TSD - THYS.

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9 Application Information Disclaimer

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application information

The THVD8000 is able to transmit data over an AC coupled power line pair using On-Off Keying (OOK).
9.2 Typical application (OOK mode)
In order to combine data and power over a single pair of wires, capacitors and inductors are used in a bias-tee
configuration. High-frequency differential data is AC-coupled onto the bus lines via series capacitances while
power is DC-coupled via series inductances. The values of these components will depend on the carrier
frequency, number of nodes on the bus, and the power delivery requirements (i.e., voltage and total current
sourced or consumed by a given node).
The transmitted differential communication signal is AC-coupled onto the power bus as shown below. This
configuration provides the advantage that the power transmitted on the bus has little impact on the differential
data, allowing for a wide range of voltage and current scenarios. Typical applications are realized with the
THVD8000 transmitting over a power bus of 24VDC or 24VAC with currents from 100mA to 1A, but due to the
AC-coupling the THVD8000 does not directly see these voltages. For more information, please refer for the
THVD8000 design guide.
In Figure 9-1, there is an optional rectifier network pictured on the bus lines. This network of diodes can ensure
that the node is receives power correctly from the bus wires, even if the lines get swapped.
A termination resistance, RT, is not required for device functionality but can be useful in improving signal integrity
in some applications by reducing reflections that can occur at cable ends.
Sing le Nod e

VIN
VOUT
LDO
GND

Sup ply
VCC

Ln Ln L1
R R C
A
MODE B RT Single Node

C
D D L1

F_SET
RFSET GND GND

Figure 9-1. Typical power line network with 2 nodes

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9.2.1 Design requirements

The main requirements are the values of the bus capacitors and the power inductors. Both of these values are
dependant upon the carrier frequency selected.
9.2.1.1 Carrier frequency
This device uses on-off-keying to transmit binary data on the bus. Please read Section 8.3.1 for detailed
information. The modulation and demodulation of the data can result in pulse width distortion due to
asymmetries in low-to-high and high-to-low transition times. These asymmetries are due to factors like
synchronization of the data to the internal carrier oscillator in the transmit path and the response time of
the band-pass filter in the receive path. The impact of these factors can be minimized by choosing a carrier
frequency much higher than the data rate required. A frequency ratio of at least 10:1 is recommended.
9.2.2 Detailed design procedure
9.2.2.1 Inductor value selection
It is important to note that the inductor selected must also take power consumption into consideration. The
inductor should be sized to handle the maximum anticipated current in addition to the inductance value.
The parallel aggregate impedance should be selected so that the total equivalent impedance at the carrier
frequency is Z ≥ 375 Ω. This assumes RS-485 loading with 60 Ω termination. If no termination is used in the
application, then the total equivalent impedance at the carrier frequency could be reduced to Z ≥ 60 Ω. These
examples assume that termination is used. Equation 1 shows the parallel aggregate impedance equation for
inductors L1 to Ln. Since the inductance value for each node should be the same, it's simple to determine that
each node's impedance should be n times the total equivalent impedance. For example, if there are 4 nodes
connected to the bus and the equivalent impedance is 375 Ω, then each node impedance should be 1,500 Ω.

< = <1 ||<2 || . . || <J (1)

To determine the suggested inductance value, Equation 2 can be rearranged to determine Ln, as shown in
Equation 3.

<J = 2èB0 .J (2)

<J
.J =
2èB0 (3)

ƒ0 is the carrier frequency (OOK frequency) used. If the previous 1.5 kΩ impedance per node is assumed with a
carrier frequency of 1 MHz, the resulting inductance limit is ~240 µH per node. Be aware that this is the minimum
suggested value per node. Refer to Figure 9-2 as a quick reference on the minimum inductance value to achieve
375 Ω of total aggregate impedance. This value can be multiplied by the number of nodes on the bus to get the
minimum inductance per node. Referring to the previous example, if there are 4 nodes and a carrier frequency of
1 MHz, then the minimum aggregate inductance is about 60 µH, which is 240 µH when multiplied by 4.
9.2.2.2 Capacitor value selection
Capacitor selection is easier than inductor selection, primarily because capacitance impedance is important to
allow higher frequency signals through. However, the capacitor ratings for voltage must be carefully selected
to meet the application requirements. Special considerations for hot plug nodes should be made to ensure that
voltage transients during hot plugging do not exceed the absolute maximum values. See Section 6.1.
The number of nodes on the bus does not play into the capacitance calculation. The impedance of a capacitor is
shown in Equation 4.

1
<=
2èB0 % (4)

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Maintaining Z ≤ 5 Ω keeps the impedance low enough at the carrier frequency to allow data to pass through. If
the equation is rearranged to calculate C, the result is shown in Equation 5.

1
%=
2èB0 < (5)

If the previous example of a 1 MHz carrier frequency is used, then a minimum capacitance value of about 32 nF.
For a quick reference, refer to Figure 9-3.
9.2.3 Application Curves

400 350

350
300

300
250

250

Capacitance (nF)
200
L (µH)

200
150
150

100
100

50 50

0 0
100 200 300 500 700 1000 2000 3000 5000 100 200 300 500 700 1000 2000 3000 5000
Carrier Frequency f0 (kHz) Carrier Frequency f0 (kHz)
Figure 9-2. Inductor selection (select values above Figure 9-3. Capacitor selection (select values
the line) above the line)

10 Power supply recommendations

To ensure reliable operation at all data rates and supply voltages, the supply should be decoupled with a 100 nF
to 220 nF ceramic capacitor and a 1 µF capacitor (for ESD sensitive designs) located as close to the supply pins
as possible. This helps to reduce supply voltage ripple present on the outputs of switched-mode power supplies
and also helps to compensate for the resistance and inductance of the PCB power planes.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: THVD8000
THVD8000
SLLSFD6A – MAY 2020 – REVISED MARCH 2021 www.ti.com

11 Layout
11.1 Layout guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order
to protect against surge transients that may occur in industrial environments. Since these transients have a
wide frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Place F_SET components near the pin to keep capacitance load below recommended value
4. Use a pull up or down resistor on mode to set a default state
5. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
6. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
7. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
8. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
9. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example

R
2
Via to GND
C 1 Via to VCC

R THVD8000 VCC
R 4
C
MODE B
JMP

MCU R
R F_SET A
C
3
D GND
2

Figure 11-1. Layout Example (OOK)

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12 Device and Documentation Support

12.1 Device Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: THVD8000
 PACKAGE OPTION ADDENDUM

www.ti.com 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

THVD8000DDFR Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 8000
THVD8000DDFR.A Active Production SOT-23-THIN (DDF) | 8 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 8000

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD8000DDFR SOT- DDF 8 3000 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
23-THIN

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Mar-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
THVD8000DDFR SOT-23-THIN DDF 8 3000 184.0 184.0 19.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DDF0008A SCALE 4.000
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

C
2.95 SEATING PLANE
TYP
2.65

A PIN 1 ID 0.1 C
AREA

6X 0.65
8
1

2.95
2.85 2X
NOTE 3 1.95

4 4X 0 -15
5
0.38
8X
0.22
1.65 0.1 C A B
B 1.1
1.55
MAX

4X 4 -15

0.20
TYP
0.08

SEE DETAIL A

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.3
DETAIL A
TYPICAL

4222047/E 07/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05)
SYMM
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(R0.05)
TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX EXPOSED EXPOSED

METAL 0.05 MIN
ALL AROUND ALL AROUND METAL

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4222047/E 07/2024
NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDF0008A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

8X (1.05) SYMM
(R0.05) TYP
1
8

8X (0.45)
SYMM

6X (0.65)
5
4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4222047/E 07/2024
NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
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