SPC564Bxx

SPC56ECxx
32-bit MCU family built on the Power Architecture® for automotive
body electronics applications
Datasheet - production data

– Up to 6 FlexCAN with 64 buffers each

– Up to 10 LINFlex/UART channels
– Up to 8 buffered DSPI channels
LBGA256 LQFP208 LQFP176 – I2C interface
(17 x 17 x 1.7 mm) (28 x 28 x 1.4 mm) (24 x 24 x 1.4 mm)
– One FleyRay (dual-ch.) with 128 buffers
– Fast Ethernet Controller
Features  Cryptographic Services Engine (CSE)
 e200z4d, 32-bit Power Architecture® – AES-128 en/decryption, CMAC auth.
– Up to 120 MHz and 200 MIPs operation – Secured device boot mode
 e200z0h, 32-bit Power Architecture  32-ch. eDMA with multiple request sources
– Up to 80 MHz and 75 MIPs operation  Clock generation
 Memory – 4 to 40 MHz main oscillator
– Up to 3 MByte on-chip Flash with ECC – 16 MHz internal RC oscillator
– Up to 256 KByte on-chip SRAM with ECC – Software-controlled FMPLL
– 64KByte on-chip Data Flash with ECC – 128 kHz internal RC oscillator
– 16-entry memory protection unit (MPU) – 32 kHz auxiliary oscillator
– User selectable Memory BIST – Clock Monitoring Unit (CMU)
 Interrupts  Low power capabilities
– 255 interrupt sources with 16 priority levels – Ultra low power STANDBY
– Up to 54 ext. IRQ including 30 wake-up – CAN Sampler to store CAN ID in STBY
– Fast wake-up and exectute from RAM
 GPIOs: from 147 (LQFP176) to 199
(LBGA256)  Exhaustive debugging capability
 System timer units – Nexus 3+ interface on LBGA256 only
– 8-ch. 32-bit periodic interrupt timer (PIT) – Nexus 1 on all devices
– 4-channel 32-bit system timer (STM)  Voltage supply
– Safety System Watchdog Timer (SWT) – Single 5 V or 3.3 V supply
– Real-time clock timer (RTC/API) – On-chip Vreg with external ballast transitor
 eMIOS, 16-bit counter timed I/O units  Operating temperature range -40 to 125 °C
– Up to 64 channels with PWM/MC/IC/OC
 Two ADC (10-bit and 12-bit)
– Up to 62 channels extendable to 90 ch.
– Multiple Analog Watchdog
 Dedicated diagnostic features for lighting
– Advanced shiffted PWM generation
– ADC conversion synchronized on PWM
 Communication interfaces

March 2016 DocID17478 Rev 9 1/123

This is information on a product in full production. www.st.com
 SPC564Bxx-SPC56ECxx

Table 1. Device summary

Part number
Package
1.5 MByte 2 MByte 3 MByte

SPC564B64L7 SPC564B70L7 SPC564B74L7

LQFP176
SPC56EC64L7 SPC56EC70L7 SPC56EC74L7
SPC564B64L8 SPC564B70L8 SPC564B74L8
LQFP208
SPC56EC64L8 SPC56EC70L8 SPC56EC74L8
LBGA256 SPC56EC64B3 SPC56EC70B3 SPC56EC74B3

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SPC564Bxx-SPC56ECxx Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Document Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.1 NVUSRO [PAD3V5V(0)] field description . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.2 NVUSRO [PAD3V5V(1)] field description . . . . . . . . . . . . . . . . . . . . . . . 52
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5.1 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.5.2 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.6.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 67
3.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 67
3.8.2 VDD_BV options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.8.3 Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69
3.9 Low voltage domain power consumption . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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Contents SPC564Bxx-SPC56ECxx

3.10.1 Program/Erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.10.2 Flash memory power supply DC characteristics . . . . . . . . . . . . . . . . . . 74
3.10.3 Flash memory start-up/switch-off timings . . . . . . . . . . . . . . . . . . . . . . . 75
3.11 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 75
3.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 75
3.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 76
3.12 Fast external crystal oscillator (4–40 MHz) electrical characteristics . . . . 77
3.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 80
3.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 83
3.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 85
3.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.18 Fast Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) . 96
3.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) . . . . 97
3.18.3 MII Async Inputs Signal Timing (CRS and COL) . . . . . . . . . . . . . . . . . . 97
3.18.4 MII Serial Management Channel Timing (MDIO and MDC) . . . . . . . . . . 98
3.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.19.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.19.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.19.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
3.19.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
4.2.1 LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 110
4.2.2 LQFP208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 112
4.2.3 LBGA256 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . 114

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

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SPC564Bxx-SPC56ECxx Contents

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

DocID17478 Rev 9 5/123

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List of tables SPC564Bxx-SPC56ECxx

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 2. SPC564Bxx and SPC56ECxx family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. SPC564Bxx and SPC56ECxx series block summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 7. PAD3V5V(0) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 8. PAD3V5V(1) field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 12. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 13. LBGA256 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 15. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 16. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 17. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 61
Table 18. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 20. I/O supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 21. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 22. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 23. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 24. Low voltage monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. Low voltage power domain electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 26. Code flash memory—Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 27. Data flash memory—Program and erase specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 28. Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 29. Flash memory read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 30. Flash memory power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 31. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 32. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 33. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 34. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 35. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 79
Table 37. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 38. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82
Table 39. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 83
Table 41. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 85
Table 42. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 43. ADC conversion characteristics (10-bit ADC_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 44. Conversion characteristics (12-bit ADC_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 45. MII Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 46. MII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 47. MII Async Inputs Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 48. MII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

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SPC564Bxx-SPC56ECxx List of tables

Table 49. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 50. DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 51. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 52. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 53. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 54. LQFP208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 55. LBGA256 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 56. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 57. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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List of figures SPC564Bxx-SPC56ECxx

List of figures

Figure 1. SPC564Bxx and SPC56ECxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. 176-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3. 208-pin LQFP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. 256-pin BGA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 6. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 7. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 8. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 9. Low voltage monitor vs. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 10. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics. . . . . . . . . . . . . . . . 79
Figure 12. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 13. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 82
Figure 15. ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 16. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 17. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 18. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 19. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 20. ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 21. MII receive signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 22. MII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 23. MII async inputs timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 24. MII serial management channel timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 25. DSPI classic SPI timing–master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 26. DSPI classic SPI timing–master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 27. DSPI classic SPI timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 28. DSPI classic SPI timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 29. DSPI modified transfer format timing–master, CPHA = 0. . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 30. DSPI modified transfer format timing–master, CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 31. DSPI modified transfer format timing–slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 32. DSPI modified transfer format timing–slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 33. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 34. Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 36. Timing diagram - JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 37. LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 38. LQFP208 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 39. LBGA256 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 40. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

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SPC564Bxx-SPC56ECxx Introduction

1 Introduction

1.1 Document Overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the SPC564Bxx
and SPC56ECxx device. To ensure a complete understanding of the device functionality,
refer also to the SPC564Bxx and SPC56ECxx Reference Manual.

1.2 Description
The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built
on the Power Architecture embedded category. This document describes the features of the
family and options available within the family members, and highlights important electrical
and physical characteristics of the device.
The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B
microcontroller family. It provides the scalability needed to implement platform approaches
and delivers the performance required by increasingly sophisticated software architectures.
The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx
automotive controller family complies with the Power Architecture embedded category,
which is 100 percent user-mode compatible with the original Power Architecture user
instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high
performance processing optimized for low power consumption. It also capitalizes on the
available development infrastructure of current Power Architecture devices and is supported
with software drivers, operating systems and configuration code to assist with users
implementations.

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122
10/123

Introduction
Table 2. SPC564Bxx and SPC56ECxx family comparison(1)
Feature SPC564B64 SPC56EC64 SPC564B70 SPC56EC70 SPC564B74 SPC56EC74

LQFP LQFP LQFP LQFP LBGA LQFP LQFP LQFP LQFP LBGA LQFP LQFP LQFP LQFP LBGA
Package
176 208 176 208 256 176 208 176 208 256 176 208 176 208 256

CPU e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h
Up to 120 MHz Up to 120 MHz Up to 120 MHz
Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d) Up to 120 MHz (e200z4d)
Execution speed(2)
(e200z4d) Up to 80 MHz (e200z4d) Up to 80 MHz (e200z4d) Up to 80 MHz
(e200z0h)(3) (e200z0h)(3) (e200z0h)(3)
Code flash memory 1.5 MB 2 MB 3 MB
Data flash memory 4 x16 KB
SRAM 128 KB 192 KB 160 KB 256 KB 192 KB 256 KB
DocID17478 Rev 9

MPU 16-entry
eDMA(4) 32 ch
10-bit ADC
dedicated(5),
(6) 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch

shared with
12-bit ADC(7) 19 ch
12-bit ADC

dedicated(8) 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch 5 ch 10 ch

SPC564Bxx-SPC56ECxx
shared with
10-bit ADC(7) 19 ch
CTU 64 ch
Total timer I/O(9) eMIOS 64 ch, 16-bit
SCI (LINFlexD) 10
SPI (DSPI) 8
CAN (FlexCAN)(10) 6
 Table 2. SPC564Bxx and SPC56ECxx family comparison(1) (continued)

SPC564Bxx-SPC56ECxx
Feature SPC564B64 SPC56EC64 SPC564B70 SPC56EC70 SPC564B74 SPC56EC74

LQFP LQFP LQFP LQFP LBGA LQFP LQFP LQFP LQFP LBGA LQFP LQFP LQFP LQFP LBGA
Package
176 208 176 208 256 176 208 176 208 256 176 208 176 208 256

FlexRay Yes
STCU(11) Yes
Ethernet No Yes No Yes No Yes
2C
I 1
32 kHz oscillator (SXOSC) Yes
GPIO(12) 147 177 147 177 199 147 177 147 177 199 147 177 147 177 199
Nexus Nexus Nexus
Debug JTAG JTAG JTAG
3+ 3+ 3+
DocID17478 Rev 9

Cryptographic Services
Optional
Engine (CSE)
1. Feature set dependent on selected peripheral multiplexing; table shows example.
2. Based on 125 C ambient operating temperature and subject to full device characterization.
3. The e200z0h can run at speeds up to 80 MHz. However, if system frequency is >80 MHz (e.g., e200z4d running at 120 MHz) the e200z0h needs to run at 1/2 system
frequency. There is a configurable e200z0 system clock divider for this purpose.
4. DMAMUX also included that allows for software selection of 32 out of a possible 57 sources.
5. Not shared with 12-bit ADC, but possibly shared with other alternate functions.
6. There are 23 dedicated ANS plus 4 dedicated ANX channels on LQPF176. For higher pin count packages, there are 29 dedicated ANS plus 4 dedicated ANX channels.
7. 16x precision channels (ANP) and 3x standard (ANS).
8. Not shared with 10-bit ADC, but possibly shared with other alternate functions.
9. As a minimum, all timer channels can function as PWM or Input Capture and Output Control. Refer to the eMIOS section of the device reference manual for information on
the channel configuration and functions.
10. CAN Sampler also included that allows ID of CAN message to be captured when in low power mode.
11. STCU controls MBIST activation and reporting.
12. Estimated I/O count for proposed packages based on multiplexing with peripherals.

Introduction
11/123
Introduction SPC564Bxx-SPC56ECxx

1.3 Block diagram

Figure 1 shows the detailed block diagram of the SPC564Bxx and
SPC56ECxx.

Figure 1. SPC564Bxx and SPC56ECxx block diagram

FEC
JTAGC
JTAG Port CSE SRAM Code Flash Data Flash

64-bit 8 x 5 crossbar switch

2  128 KB 2  1.5 MB 64 KB
Nexus Port Nexus 3+ FlexRay
Nexus
Instructions
e200z0h (Master)
NMI0 Data 2  SRAM Flash memory

MPU
(Master) controller controller
Voltage Instructions
NMI1 e200z4d (Master)
regulator Data
(Master) (Slave)
Nexus 3+
NMI0
(Slave)
Interrupt requests (Slave)
NMI1 from peripheral
blocks DMAMUX
MPU
INTC registers
Clocks eDMA
CMU CAN
( Master) Sampler STCU
FMPLL

8
16 x
RTC/API 4  STM SWT ECSM PIT RTI MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM WKP
Semaphores

Peripheral Bridge

SIUL 10 ch(1) 27 ch or 33 ch(2) 2  32 ch 10  8 6

Reset Control 1  12-bit 1  10-bit CTU LINFlexD DSPI I2C FlexCAN
eMIOS
Interrupt ADC ADC
Request External
Interrupt
Request
IMUX
GPIO &
Pad Control

(3) (3)
I/O
Legend: ADC Analog-to-Digital Converter JTAGC JTAG controller
BAM Boot Assist Module LINFlexD Local Interconnect Network Flexible with DMA sup
CSE Cryptographic Services Engine MC_ME Mode Entry Module
CAN Controller Area Network (FlexCAN) MC_CGM Clock Generation Module
CMU Clock Monitor Unit MC_PCU Power Control Unit
CTU Cross Triggering Unit MC_RGM Reset Generation Module
DMAMUX DMA Channel Multiplexer MPU Memory Protection Unit
DSPI Deserial Serial Peripheral Interface Nexus Nexus Development Interface
eDMA enhanced Direct Memory Access NMI Non-Maskable Interrupt
FlexCAN Controller Area Network controller modules PIT_RTI Periodic Interrupt Timer with Real-Time Interrupt
FEC Fast Ethernet Controller RTC/API Real-Time Clock/ Autonomous Periodic Interrupt
eMIOS Enhanced Modular Input Output System SIUL System Integration Unit Lite
ECSM Error Correction Status Module SRAM Static Random-Access Memory
FMPLL Frequency-Modulated Phase-Locked Loop SSCM System Status Configuration Module
FlexRay FlexRay Communication Controller STM System Timer Module
I2C Inter-integrated Circuit Bus SWT Software Watchdog Timer
IMUX Internal Multiplexer STCU Self Test Control Unit
INTC Interrupt Controller WKPU Wakeup Unit
Notes: 1) 10 dedicated channels plus up to 19 shared channels. See the device-comparison table.
2) Package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. See the device-comparison table.
3) 16 x precision channels (ANP) are mapped on input only I/O cells.

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SPC564Bxx-SPC56ECxx Introduction

Table 3 summarizes the functions of the blocks present on the SPC564Bxx and
SPC56ECxx.

Table 3. SPC564Bxx and SPC56ECxx series block summary

Block Function

Analog-to-digital converter (ADC) Converts analog voltages to digital values

A block of read-only memory containing VLE code which is executed according
Boot assist module (BAM)
to the boot mode of the device
Clock monitor unit (CMU) Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the
Cross triggering unit (CTU)
eMIOS or from the PIT
Cryptographic Security Engine
Supports the encoding and decoding of any kind of data
(CSE)
Supports simultaneous connections between two master ports and three slave
Crossbar (XBAR) switch ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
DMA Channel Multiplexer
Allows to route DMA sources (called slots) to DMA channels
(DMAMUX)
Deserial serial peripheral Provides a synchronous serial interface for communication with external
interface (DSPI) devices
Provides a myriad of miscellaneous control functions for the device including
Error Correction Status Module program-visible information about configuration and revision levels, a reset
(ECSM) status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA) processor via “n” programmable channels.
Enhanced modular input output
Provides the functionality to generate or measure events
system (eMIOS)
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
Supports the standard CAN communications protocol
network)
FMPLL (frequency-modulated Generates high-speed system clocks and supports programmable frequency
phase-locked loop) modulation
FlexRay (FlexRay communication
Provides high-speed distributed control for advanced automotive applications
controller)
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Fast Ethernet Controller (FEC)
Mbps Ethernet/IEEE 802.3 networks
Internal multiplexer (IMUX) SIUL Allows flexible mapping of peripheral interface on the different pins of the
subblock device
A two wire bidirectional serial bus that provides a simple and efficient method of
Inter-integrated circuit (I2C™) bus
data exchange between devices
Provides priority-based preemptive scheduling of interrupt requests for both
Interrupt controller (INTC)
e200z0h and e200z4d cores
Provides the means to test chip functionality and connectivity while remaining
JTAG controller
transparent to system logic when not in test mode

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122
Introduction SPC564Bxx-SPC56ECxx

Table 3. SPC564Bxx and SPC56ECxx series block summary (continued)

Block Function

LinFlexD (Local Interconnect

Manages a high number of LIN (Local Interconnect Network protocol)
Network Flexible with DMA
messages efficiently with a minimum of CPU load
support)
Provides hardware access control for all memory references generated in a
Memory protection unit (MPU)
device
Clock generation module Provides logic and control required for the generation of system and peripheral
(MC_CGM) clocks
Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU) from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module Centralizes reset sources and manages the device reset sequence of the
(MC_RGM) device
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
Mode entry module (MC_ME)
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Handles external events that must produce an immediate response, such as
Non-Maskable Interrupt (NMI)
power down detection
Nexus Development Interface Provides real-time development capabilities for e200z0h and e200z4d core
(NDI) processor
Periodic interrupt timer/ Real
Produces periodic interrupts and triggers
Time Interrupt Timer (PIT_RTI)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
Real-time counter (RTC/API) mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Static random-access memory
Provides storage for program code, constants, and variables
(SRAM)
Provides control over all the electrical pad controls and up 32 ports with 16 bits
System integration unit lite (SIUL) of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and
System status and configuration
status, device mode and security status), device identification data, debug
module (SSCM)
status port enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AutoSAR and operating
System timer module (STM)
system tasks
Provides the hardware support needed in multi-core systems for sharing
Semaphores resources and provides a simple mechanism to achieve lock/unlock operations
via a single write access.
Supports external sources that can generate interrupts or wakeup events, of
Wake Unit (WKPU)
which can cause non-maskable interrupt requests or wakeup events.

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

2 Package pinouts and signal descriptions

The available LQFP pinouts and the LBGA ballmaps are provided in the following figures.
For functional port pin description, see Table 6.

Figure 2. 176-pin LQFP configuration

VDD_HV_A
VSS_HV
VDD_LV
VSS_LV

PG[10]

PG[15]
PG[14]
PC[13]
PC[12]

PH[10]

PH[12]

PG[11]

PE[15]
PE[14]

PE[12]
PH[11]
PC[8]

PH[8]
PH[7]
PH[6]
PH[5]
PH[4]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]

PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
PI[0]
PI[1]
PI[2]
PI[3]

PI[4]
PI[5]
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[3] 1 132 PA[11]
PC[9] 2 131 PA[10]
PC[14] 3 130 PA[9]
PC[15] 4 129 PA[8]
PJ[4] 5 128 PA[7]
VDD_HV_A 6 127 PE[13]
VSS_HV 7 126 PF[14]
PH[15] 8 125 PF[15]
PH[13] 9 124 VDD_HV_B
PH[14] 10 123 VSS_HV
PI[6] 11 122 PG[0]
PI[7] 12 121 PG[1]
PG[5] 13 120 PH[3]
PG[4] 14 119 PH[2]
PG[3] 15 118 PH[1]
PG[2] 16 117 PH[0]
PA[2] 17 116 PG[12]
PE[0] 18 115 PG[13]
PA[1] 19 114 PA[3]
PE[1] 20 113 PI[13]
PE[8] 21 112 PI[12]
PE[9] 22 LQFP176 111 PI[11]
PE[10] 23 110 VDD_LV
PA[0]
PE[11]
24 Top view 109 VSS_LV
PI[8]
25 108
VSS_HV 26 107 PB[15]
VDD_HV_A 27 106 PD[15]
VSS_HV 28 105 PB[14]
RESET 29 104 PD[14]
VSS_LV 30 103 PB[13]
VDD_LV 31 102 PD[13]
VRC_CTRL 32 101 PB[12]
PG[9] 33 100 PD[12]
PG[8] 34 99 VDD_HV_ADC1
PC[11] 35 98 VSS_HV_ADC1
PC[10] 36 97 PB[11]
PG[7] 37 96 PD[11]
PG[6] 38 95 PD[10]
PB[0] 39 94 PD[9]
PB[1] 40 93 PB[7]
PF[9] 41 92 PB[6]
PF[8] 42 91 PB[5]
PF[12] 43 90 VDD_HV_ADC0
PC[6] 44 89 VSS_HV_ADC0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VDD_LV
VSS_LV

VSS_HV

VDD_HV_A

VDD_HV_A
VSS_HV
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]

XTAL

EXTAL

PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]

PD[8]
PB[4]

NOTE
1) VDD_HV_B supplies the IO voltage domain for the
pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7],
PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2],
PH[1], PH[0], PG[12], PG[13], and PA[3].
2)Availability of port pin alternate functions depends
on product selection.

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122
Package pinouts and signal descriptions SPC564Bxx-SPC56ECxx

Figure 3. 208-pin LQFP configuration

VDD_HV_A
VSS_HV
VDD_LV
VSS_LV

PG[10]

PG[15]
PG[14]
PC[13]
PC[12]

PH[10]

PH[12]

PG[11]
PK[15]
PK[14]
PK[13]
PK[12]

PK[10]

PE[15]
PE[14]

PE[12]
PH[11]
PK[11]
PC[8]

PH[8]
PH[7]
PH[6]
PH[5]
PH[4]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PK[9]

PE[7]
PE[6]

PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
PL[0]

PI[0]
PI[1]
PI[2]
PI[3]

PI[4]
PI[5]
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PB[3] 1
PC[9] 2 156 PA[11]
PC[14] 3 155 PA[10]
PC[15] 4 154 PA[9]
PJ[4] 5 153 PA[8]
VDD_HV_A 6 152 PA[7]
VSS_HV 7 151 PE[13]
PH[15] 8 150 PF[14]
PH[13] 9 149 PF[15]
PH[14] 10 148 VDD_HV_B
P[I6] 11 147 VSS_HV
P[I7] 12 146 PG[0]
PG[5] 13 145 PG[1]
PG[4] 14 144 PH[3]
PG[3] 15 143 PH[2]
PG[2] 16 142 PH[1]
PA[2] 17 141 PH[0]
PE[0] 18 140 PG[12]
PA[1] 19 139 PG[13]
PE[1] 20 138 PA[3]
137 PI[13]
PE[8] 21 PI[12]
PE[9] 22 136
135 PI[11]
PE[10]
PA[0]
23
24
LQFP208 134 PI[10]
133 VDD_LV
PE[11] 25 Top view VSS_LV
VSS_HV 26 132
131 PI[9]
VDD_HV_A 27 PI[8]
VSS_HV 28 130
129 PB[15]
RESET 29 PD[15]
VSS_LV 30 128
127 PB[14]
VDD_LV 31 PD[14]
VRC_CTRL 32 126
125 PB[13]
PG[9] 33 PD[13]
PG[8] 34 124
123 PB[12]
PC[11] 35 VDD_HV_A
PC[10] 36 122
121 VSS_HV
PG[7] 37 PD[12]
PG[6] 38 120
119 VDD_HV_ADC1
PB[0] 39 VSS_HV_ADC1
PB[1] 40 118
117 PB[11]
PK[1] 41 PD[11]
PK[2] 42 116
115 PD[10]
PK[3] 43 PD[9]
PK[4] 44 114
113 PJ[5]
PK[5] 45 PJ[6]
PK[6] 46 112
111 PJ[7]
PK[7] 47 PJ[8]
PK[8] 48 110
109 PB[7]
PF[9] 49 PB[6]
PF[8] 50 108
107 PB[5]
PF[12] 51 VDD_HV_ADC0
PC[6] 52 100 106
101
102
103
104
105 VSS_HV_ADC0
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PJ[12]
PJ[11]
PA[4]
PK[0]
PJ[15]
PJ[14]
PJ[13]
PA[13]
PJ[10]
PJ[9]
PA[12]

PB[9]
PB[8]
PB[10]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]

PD[8]
PB[4]
VDD_LV
VSS_LV

VSS_HV

VDD_HV_A

VDD_HV_A
VSS_HV
XTAL

EXTAL

NOTE
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9],
PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12],
PG[13], and PA[3].
2) Availability of port pin alternate functions depends on product selection.

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PC[15] PB[2] PC[13] PI[1] PE[7] PH[8] PE[2] PE[4] PC[4] PE[3] PH[9] PI[4] PH[11] PE[14] PA[10] PG[11]
A A

PH[13] PC[14] PC[8] PC[12] PI[3] PE[6] PH[5] PE[5] PC[5] PC[0] PC[2] PH[12] PG[10] PA[11] PA[9] PA[8]
B B

PH[14] VDD_HV PC[9] PL[0] PI[0] PH[7] PH[6] VSS_LV VDD_HV PA[5] PC[3] PE[15] PG[14] PE[12] PA[7] PE[13]
C _A _A C

PG[5] PI[6] PJ[4] PB[3] PK[15] PI[2] PH[4] VDD_LV PC[1] PH[10] PA[6] PI[5] PG[15] PF[14] PF[15] PH[2]
D D

PG[3] PI[7] PH[15] PG[2] VDD_LV VSS_LV PK[10] PK[9] PM[1] PM[0] PL[15] PL[14] PG[0] PG[1] PH[0] VDD_HV
E _A E

PA[2] PG[4] PA[1] PE[1] PL[2] PM[6] PL[1] PK[11] PM[5] PL[13] PL[12] PM[2] PH[1] PH[3] PG[12] PG[13]
F F

PE[8] PE[0] PE[10] PA[0] PL[3] VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV VSS_HV PK[12] VDD_HV PI[13] PI[12] PA[3]
G _B G

PE[9] VDD_HV PE[11] PK[1] PL[4] VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV VSS_HV PK[13] VDD_HV VDD_LV VSS_LV PI[11]
H _A _A H

VSS_HV VRC_CT VDD_LV PG[9] PL[5] VSS_LV VSS_LV VSS_LV VSS_HV VSS_HV VSS_HV PK[14] PD[15] PI[8] PI[9] PI[10]
J RL J

RESET VSS_LV PG[8] PC[11] PL[6] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[3] PD[14] PD[13] PB[14] PB[15]
K K

PC[10] PG[7] PB[0] PK[2] PL[7] VSS_LV VSS_LV VSS_LV VSS_LV VDD_LV VDD_LV PM[4] PD[12] PB[12] PB[13] VDD_HV
L _ADC1 L

PG[6] PB[1] PK[4] PF[9] PK[5] PK[6] PK[7] PK[8] PL[8] PL[9] PL[10] PL[11] PB[11] PD[10] PD[11] VSS_HV
M _ADC1 M

PK[3] PF[8] PC[6] PC[7] PJ[13] VDD_HV PB[10] PF[6] VDD_HV PJ[1] PD[2] PJ[5] PB[5] PB[6] PJ[6] PD[9]
N _A _A N

PF[12] PF[10] PF[13] PA[14] PJ[9] PA[12] PF[0] PF[5] PF[7] PJ[3] PI[15] PD[4] PD[7] PD[8] PJ[8] PJ[7]
P P

PF[11] PA[15] PJ[11] PJ[15] PA[13] PF[2] PF[3] PF[4] VDD_LV PJ[2] PJ[0] PD[0] PD[3] PD[6] VDD_HV PB[7]
R _ADC0 R

PJ[12] PA[4] PK[0] PJ[14] PJ[10] PF[1] XTAL EXTAL VSS_LV PB[9] PB[8] PI[14] PD[1] PD[5] VSS_HV PB[4]
T _ADC0 T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Notes:
1) VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15], PG[0], PG[1],
PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], PA[3], PM[3], and PM[4].
2)Availability of port pin alternate functions depends on product selection.

Figure 4. 256-pin BGA configuration

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2.1 Pad types

In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(a)
M = Medium(a),(b)
F = Fast(a),(b)
I = Input only with analog feature(a)
A = Analog

2.2 System pins

The system pins are listed in Table 4.

Table 4. System pin descriptions

Pin number

LBGA 256
LQFP 176

LQFP 208
I/O Pad RESET
Port pin Function
direction type config.

Input, weak
Bidirectional reset with Schmitt-Trigger pull-up only
RESET I/O M 29 29 K1
characteristics and noise filter. after
PHASE2
Analog input of the oscillator amplifier
EXTAL circuit. Needs to be grounded if oscillator I A(1) — 58 74 T8
bypass mode is used.
Analog output of the oscillator amplifier
circuit, when the oscillator is not in bypass
XTAL mode.  I/O A(1) — 56 72 T7
Analog input for the clock generator when
the oscillator is in bypass mode.
1. For analog pads, it is not recommended to enable IBE if APC is enabled to avoid extra current in middle range voltage.

a. See the I/O pad electrical characteristics in the device datasheet for details.
b. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.
For example, Fast/Medium pad will be Medium by default at reset. Similarly, Slow/Medium pad will be Slow by
default. Only exception is PC[1] which is in medium configuration by default (refer to PCR.SRC in the reference
manual, Pad Configuration Registers (PCR0—PCR198)).

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

2.3 Functional ports

The functional port pins are listed in Table 5.

Table 5. Functional port pin descriptions

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[0] SIUL I/O

AF1 E0UC[0] eMIOS_0 I/O
AF2 CLKOUT MC_CGM O
PA[0] PCR[0] M/S Tristate 24 24 G4
AF3 E0UC[13] eMIOS_0 I/O
— WKPU[19] WKPU I
— CAN1RX FlexCAN_1 I
AF0 GPIO[1] SIUL I/O
AF1 E0UC[1] eMIOS_0 I/O
AF2 — — —
PA[1] PCR[1] AF3 — — — S Tristate 19 19 F3
— WKPU[2] WKPU I
— CAN3RX FlexCAN_3 I
— NMI[0](3) WKPU I
AF0 GPIO[2] SIUL I/O
AF1 E0UC[2] eMIOS_0 I/O
AF2 — — —
PA[2] PCR[2] S Tristate 17 17 F1
AF3 MA[2] ADC_0 O
— WKPU[3] WKPU I
— NMI[1](3) WKPU I
AF0 GPIO[3] SIUL I/O
AF1 E0UC[3] eMIOS_0 I/O
AF2 LIN5TX LINFlexD_5 O
PA[3] PCR[3] AF3 CS4_1 DSPI_1 O M/S Tristate 114 138 G16
— RX_ER_CLK FEC I
— EIRQ[0] SIUL I
— ADC1_S[0] ADC_1 I
AF0 GPIO[4] SIUL I/O
AF1 E0UC[4] eMIOS_0 I/O
AF2 — — —
PA[4] PCR[4] S Tristate 51 61 T2
AF3 CS0_1 DSPI_1 I/O
— LIN5RX LINFlexD_5 I
— WKPU[9] WKPU I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[5] SIUL I/O

PA[5] PCR[5] AF1 E0UC[5] eMIOS_0 I/O M/S Tristate 146 170 C10
AF2 LIN4TX LINFlexD_4 O
AF0 GPIO[6] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O
AF2 — — —
PA[6] PCR[6] S Tristate 147 171 D11
AF3 CS1_1 DSPI_1 O
— LIN4RX LINFlexD_4 I
— EIRQ[1] SIUL I
AF0 GPIO[7] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
AF2 LIN3TX LINFlexD_3 O
PA[7] PCR[7] AF3 — — — M/S Tristate 128 152 C15
— RXD[2] FEC I
— EIRQ[2] SIUL I
— ADC1_S[1] ADC_1 I
AF0 GPIO[8] SIUL I/O
AF1 E0UC[8] eMIOS_0 I/O
AF2 E0UC[14] eMIOS_0 I/O
AF3 — — — Input,
PA[8] PCR[8] M/S weak 129 153 B16
— RXD[1] FEC I
pull-up
— EIRQ[3] SIUL I
— ABS[0] MC_RGM I
— LIN3RX LINFlexD_3 I
AF0 GPIO[9] SIUL I/O
AF1 E0UC[9] eMIOS_0 I/O
AF2 — — — Pull-
PA[9] PCR[9] M/S 130 154 B15
AF3 CS2_1 DSPI1 O down
— RXD[0] FEC I
— FAB MC_RGM I

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[10] SIUL I/O

AF1 E0UC[10] eMIOS_0 I/O
AF2 SDA I2C I/O
PA[10] PCR[10] AF3 LIN2TX LINFlexD_2 O M/S Tristate 131 155 A15
— COL FEC I
— ADC1_S[2] ADC_1 I
— SIN_1 DSPI_1 I
AF0 GPIO[11] SIUL I/O
AF1 E0UC[11] eMIOS_0 I/O
AF2 SCL I2C I/O
AF3 — — —
PA[11] PCR[11] M/S Tristate 132 156 B14
— RX_ER FEC I
— EIRQ[16] SIUL I
— LIN2RX LINFlexD_2 I
— ADC1_S[3] ADC_1 I
AF0 GPIO[12] SIUL I/O
AF1 — — —
AF2 E0UC[28] eMIOS_0 I/O
PA[12] PCR[12] S Tristate 53 69 P6
AF3 CS3_1 DSPI1 O
— EIRQ[17] SIUL I
— SIN_0 DSPI_0 I
AF0 GPIO[13] SIUL I/O
AF1 SOUT_0 DSPI_0 O
PA[13] PCR[13] M/S Tristate 52 66 R5
AF2 E0UC[29] eMIOS_0 I/O
AF3 — — —
AF0 GPIO[14] SIUL I/O
AF1 SCK_0 DSPI_0 I/O
PA[14] PCR[14] AF2 CS0_0 DSPI_0 I/O M/S Tristate 50 58 P4
AF3 E0UC[0] eMIOS_0 I/O
— EIRQ[4] SIUL I
AF0 GPIO[15] SIUL I/O
AF1 CS0_0 DSPI_0 I/O
PA[15] PCR[15] AF2 SCK_0 DSPI_0 I/O M/S Tristate 48 56 R2
AF3 E0UC[1] eMIOS_0 I/O
— WKPU[10] WKPU I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[16] SIUL I/O

AF1 CAN0TX FlexCAN_0 O
PB[0] PCR[16] M/S Tristate 39 39 L3
AF2 E0UC[30] eMIOS_0 I/O
AF3 LIN0TX LINFlexD_0 I
AF0 GPIO[17] SIUL I/O
AF1 — — —
AF2 E0UC[31] eMIOS_0 I/O
PB[1] PCR[17] S Tristate 40 40 M2
— LIN0RX LINFlexD_0 I
— WKPU[4] WKPU I
— CAN0RX FlexCAN_0 I
AF0 GPIO[18] SIUL I/O
AF1 LIN0TX LINFlexD_0 O
PB[2] PCR[18] M/S Tristate 176 208 A2
AF2 SDA I2C I/O
AF3 E0UC[30] eMIOS_0 I/O
AF0 GPIO[19] SIUL I/O
AF1 E0UC[31] eMIOS_0 I/O
AF2 SCL I2C I/O
PB[3] PCR[19] S Tristate 1 1 D4
AF3 — — —
— WKPU[11] WKPU I
— LIN0RX LINFlexD_0 I
AF0 GPI[20] SIUL I
AF1 — — —
AF2 — — —
PB[4] PCR[20] I Tristate 88 104 T16
AF3 — — —
— ADC0_P[0] ADC_0 I
— ADC1_P[0] ADC_1 I
AF0 GPI[21] SIUL I
AF1 — — —
AF2 — — —
PB[5] PCR[21] I Tristate 91 107 N13
AF3 — — —
— ADC0_P[1] ADC_0 I
— ADC1_P[1] ADC_1 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPI[22] SIUL I

AF1 — — —
AF2 — — —
PB[6] PCR[22] I Tristate 92 108 N14
AF3 — — —
— ADC0_P[2] ADC_0 I
— ADC1_P[2] ADC_1 I
AF0 GPI[23] SIUL I
AF1 — — —
AF2 — — —
PB[7] PCR[23] I Tristate 93 109 R16
AF3 — — —
— ADC0_P[3] ADC_0 I
— ADC1_P[3] ADC_1 I
AF0 GPI[24] SIUL I
AF1 — — —
AF2 — — —
AF3 — — —
PB[8] PCR[24] I — 61 77 T11
— ADC0_S[0] ADC_0 I
— ADC1_S[4] ADC_1 I
— WKPU[25] WKPU I
— OSC32k_XTAL(4) SXOSC I
GPI[25]
AF0 SIUL I
—
AF1 — —
—
AF2 — —
—
AF3 — —
PB[9](5) PCR[25] ADC0_S[1] I — 60 76 T10
— ADC_0 I
ADC1_S[5]
— ADC_1 I
WKPU[26]
— WKPU I
OSC32k_EXTAL(
— 4) SXOSC I

AF0 GPIO[26] SIUL I/O

AF1 SOUT_1 DSPI_1 O
AF2 CAN3TX FlexCAN_3 —
PB[10] PCR[26] AF3 — — — S Tristate 62 78 N7
— ADC0_S[2] ADC_0 I
— ADC1_S[6] ADC_1 I
— WKPU[8] WKPU I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[27] SIUL I/O

AF1 E0UC[3] eMIOS_0 I/O
PB[11] PCR[27] AF2 — — — S Tristate 97 117 M13
AF3 CS0_0 DSPI_0 I/O
— ADC0_S[3] ADC_0 I
AF0 GPIO[28] SIUL I/O
AF1 E0UC[4] eMIOS_0 I/O
PB[12] PCR[28] AF2 — — — S Tristate 101 123 L14
AF3 CS1_0 DSPI_0 O
— ADC0_X[0] ADC_0 I
AF0 GPIO[29] SIUL I/O
AF1 E0UC[5] eMIOS_0 I/O
PB[13] PCR[29] AF2 — — — S Tristate 103 125 L15
AF3 CS2_0 DSPI_0 O
— ADC0_X[1] ADC_0 I
AF0 GPIO[30] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O
PB[14] PCR[30] AF2 — — — S Tristate 105 127 K15
AF3 CS3_0 DSPI_0 O
— ADC0_X[2] ADC_0 I
AF0 GPIO[31] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
PB[15] PCR[31] AF2 — — — S Tristate 107 129 K16
AF3 CS4_0 DSPI_0 O
— ADC0_X[3] ADC_0 I
AF0 GPIO[32] SIUL I/O
AF1 — — Input,
—
PC[0](6) PCR[32] M/S weak 154 178 B10
AF2 TDI JTAGC I pull-up
AF3 — — —
AF0 GPIO[33] SIUL I/O
AF1 — — —
PC[1](6) PCR[33] F/M Tristate 149 173 D9
AF2 TDO JTAGC O
AF3 — — —

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[34] SIUL I/O

AF1 SCK_1 DSPI_1 I/O
PC[2] PCR[34] AF2 CAN4TX FlexCAN_4 O M/S Tristate 145 169 B11
AF3 — — —
— EIRQ[5] SIUL I
AF0 GPIO[35] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
AF2 MA[0] ADC_0 O
PC[3] PCR[35] AF3 — — S Tristate 144 168 C11
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I
— EIRQ[6] SIUL I
AF0 GPIO[36] SIUL I/O
AF1 E1UC[31] eMIOS_1 I/O
AF2 — — —
AF3
PC[4] PCR[36] M/S Tristate 159 183 A9
ALT4 FR_B_TX_EN Flexray O
— SIN_1 DSPI_1 I
— CAN3RX FlexCAN_3 I
— EIRQ[18] SIUL I
AF0 GPIO[37] SIUL I/O
AF1 SOUT_1 DSPI_1 O
AF2 CAN3TX FlexCAN_3 O
PC[5] PCR[37] M/S Tristate 158 182 B9
AF3 — — —
ALT4 FR_A_TX Flexray O
— EIRQ[7] SIUL I
AF0 GPIO[38] SIUL I/O
AF1 LIN1TX LINFlexD_1 O
PC[6] PCR[38] S Tristate 44 52 N3
AF2 E1UC[28] eMIOS_1 I/O
AF3 — — —
AF0 GPIO[39] SIUL I/O
AF1 — — —
AF2 E1UC[29] eMIOS_1 I/O
PC[7] PCR[39] S Tristate 45 53 N4
AF3 — — —
— LIN1RX LINFlexD_1 I
— WKPU[12] WKPU I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[40] SIUL I/O

AF1 LIN2TX LINFlexD_2 O
PC[8] PCR[40] S Tristate 175 207 B3
AF2 E0UC[3] eMIOS_0 I/O
AF3 — — —
AF0 GPIO[41] SIUL I/O
AF1 — — —
AF2 E0UC[7] eMIOS_0 I/O
PC[9] PCR[41] S Tristate 2 2 C3
AF3 — — —
— LIN2RX LINFlexD_2 I
— WKPU[13] WKPU I
AF0 GPIO[42] SIUL I/O
AF1 CAN1TX FlexCAN_1 O
PC[10] PCR[42] M/S Tristate 36 36 L1
AF2 CAN4TX FlexCAN_4 O
AF3 MA[1] ADC_0 O
AF0 GPIO[43] SIUL I/O
AF1 — — —
AF2 — — —
PC[11] PCR[43] AF3 MA[2] ADC_0 O S Tristate 35 35 K4
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I
— WKPU[5] WKPU I
AF0 GPIO[44] SIUL I/O
AF1 E0UC[12] eMIOS_0 I/O
AF2 — — —
PC[12] PCR[44] AF3 — — — M/S Tristate 173 205 B4
ALT4 FR_DBG[0] Flexray O
— SIN_2 DSPI_2 I
— EIRQ[19] SIUL I
AF0 GPIO[45] SIUL I/O
AF1 E0UC[13] eMIOS_0 I/O
PC[13] PCR[45] AF2 SOUT_2 DSPI_2 O M/S Tristate 174 206 A3
AF3 — — —
ALT4 FR_DBG[1] Flexray O

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[46] SIUL I/O

AF1 E0UC[14] eMIOS_0 I/O
AF2 SCK_2 DSPI_2 I/O
PC[14] PCR[46] M/S Tristate 3 3 B2
AF3 — — —
ALT4 FR_DBG[2] Flexray O
— EIRQ[8] SIUL I
GPIO[47] SIUL I/O
AF0
E0UC[15] eMIOS_0 I/O
AF1
CS0_2 DSPI_2 I/O
PC[15] PCR[47] AF2 M/S Tristate 4 4 A1
— — —
AF3
FR_DBG[3] Flexray O
ALT4
EIRQ[20] SIUL I
AF0 GPI[48] SIUL I
AF1 — — —
AF2 — — —
PD[0] PCR[48] AF3 — — — I Tristate 77 93 R12
— ADC0_P[4] ADC_0 I
— ADC1_P[4] ADC_1 I
— WKPU[27] WKPU I
AF0 GPI[49] SIUL I
AF1 — — —
AF2 — — —
PD[1] PCR[49] AF3 — — — I Tristate 78 94 T13
— ADC0_P[5] ADC_0 I
— ADC1_P[5] ADC_1 I
— WKPU[28] WKPU I
AF0 GPI[50] SIUL I
AF1 — — —
AF2 — — —
PD[2] PCR[50] I Tristate 79 95 N11
AF3 — — —
— ADC0_P[6] ADC_0 I
— ADC1_P[6] ADC_1 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPI[51] SIUL I

AF1 — — —
AF2 — — —
PD[3] PCR[51] I Tristate 80 96 R13
AF3 — — —
— ADC0_P[7] ADC_0 I
— ADC1_P[7] ADC_1 I
AF0 GPI[52] SIUL I
AF1 — — —
AF2 — — —
PD[4] PCR[52] I Tristate 81 97 P12
AF3 — — —
— ADC0_P[8] ADC_0 I
— ADC1_P[8] ADC_1 I
AF0 GPI[53] SIUL I
AF1 — — —
AF2 — — —
PD[5] PCR[53] I Tristate 82 98 T14
AF3 — — —
— ADC0_P[9] ADC_0 I
— ADC1_P[9] ADC_1 I
AF0 GPI[54] SIUL I
AF1 — — —
AF2 — — —
PD[6] PCR[54] I Tristate 83 99 R14
AF3 — — —
— ADC0_P[10] ADC_0 I
— ADC1_P[10] ADC_1 I
AF0 GPI[55] SIUL I
AF1 — — —
AF2 — — —
PD[7] PCR[55] I Tristate 84 100 P13
AF3 — — —
— ADC0_P[11] ADC_0 I
— ADC1_P[11] ADC_1 I
AF0 GPI[56] SIUL I
AF1 — — —
AF2 — — —
PD[8] PCR[56] I Tristate 87 103 P14
AF3 — — —
— ADC0_P[12] ADC_0 I
— ADC1_P[12] ADC_1 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPI[57] SIUL I

AF1 — — —
AF2 — — —
PD[9] PCR[57] I Tristate 94 114 N16
AF3 — — —
— ADC0_P[13] ADC_0 I
— ADC1_P[13] ADC_1 I
AF0 GPI[58] SIUL I
AF1 — — —
AF2 — — —
PD[10] PCR[58] I Tristate 95 115 M14
AF3 — — —
— ADC0_P[14] ADC_0 I
— ADC1_P[14] ADC_1 I
AF0 GPI[59] SIUL I
AF1 — — —
AF2 — — —
PD[11] PCR[59] I Tristate 96 116 M15
AF3 — — —
— ADC0_P[15] ADC_0 I
— ADC1_P[15] ADC_1 I
AF0 GPIO[60] SIUL I/O
AF1 CS5_0 DSPI_0 O
PD[12] PCR[60] AF2 E0UC[24] eMIOS_0 I/O S Tristate 100 120 L13
AF3 — — —
— ADC0_S[4] ADC_0 I
AF0 GPIO[61] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
PD[13] PCR[61] AF2 E0UC[25] eMIOS_0 I/O S Tristate 102 124 K14
AF3 — — —
— ADC0_S[5] ADC_0 I
AF0 GPIO[62] SIUL I/O
AF1 CS1_1 DSPI_1 O
AF2 E0UC[26] eMIOS_0 I/O
PD[14] PCR[62] S Tristate 104 126 K13
AF3 — — —
ALT4 FR_DBG[0] Flexray O
— ADC0_S[6] ADC_0 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[63] SIUL I/O

AF1 CS2_1 DSPI_1 O
AF2 E0UC[27] eMIOS_0 I/O
PD[15] PCR[63] S Tristate 106 128 J13
AF3 — — —
ALT4 FR_DBG[1] Flexray O
— ADC0_S[7] ADC_0 I
AF0 GPIO[64] SIUL I/O
AF1 E0UC[16] eMIOS_0 I/O
AF2 — — —
PE[0] PCR[64] S Tristate 18 18 G2
AF3 — — —
— CAN5RX FlexCAN_5 I
— WKPU[6] WKPU I
AF0 GPIO[65] SIUL I/O
AF1 E0UC[17] eMIOS_0 I/O
PE[1] PCR[65] M/S Tristate 20 20 F4
AF2 CAN5TX FlexCAN_5 O
AF3 — — —
AF0 GPIO[66] SIUL I/O
AF1 E0UC[18] eMIOS_0 I/O
AF2 — — —
PE[2] PCR[66] AF3 — — — M/S Tristate 156 180 A7
ALT4 FR_A_TX_EN Flexray O
— SIN_1 DSPI_1 I
— EIRQ[21] SIUL I
AF0 GPIO[67] SIUL I/O
AF1 E0UC[19] eMIOS_0 I/O
AF2 SOUT_1 DSPI_1 O
PE[3] PCR[67] M/S Tristate 157 181 A10
AF3 — — —
— FR_A_RX Flexray I
— WKPU[29] WKPU I
AF0 GPIO[68] SIUL I/O
AF1 E0UC[20] eMIOS_0 I/O
AF2 SCK_1 DSPI_1 I/O
PE[4] PCR[68] M/S Tristate 160 184 A8
AF3 — — —
ALT4 FR_B_TX Flexray O
— EIRQ[9] SIUL I

30/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[69] SIUL I/O

AF1 E0UC[21] eMIOS_0 I/O
AF2 CS0_1 DSPI_1 I/O
PE[5] PCR[69] M/S Tristate 161 185 B8
AF3 MA[2] ADC_0 O
— FR_B_RX Flexray I
— WKPU[30] WKPU I
AF0 GPIO[70] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PE[6] PCR[70] AF2 CS3_0 DSPI_0 O M/S Tristate 167 191 B6
AF3 MA[1] ADC_0 O
— EIRQ[22] SIUL I
AF0 GPIO[71] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PE[7] PCR[71] AF2 CS2_0 DSPI_0 O M/S Tristate 168 192 A5
AF3 MA[0] ADC_0 O
— EIRQ[23] SIUL I
AF0 GPIO[72] SIUL I/O
AF1 CAN2TX FlexCAN_2 O
PE[8] PCR[72] M/S Tristate 21 21 G1
AF2 E0UC[22] eMIOS_0 I/O
AF3 CAN3TX FlexCAN_3 O
AF0 GPIO[73] SIUL I/O
AF1 — — —
AF2 E0UC[23] eMIOS_0 I/O
PE[9] PCR[73] AF3 — — — S Tristate 22 22 H1
— WKPU[7] WKPU I
— CAN2RX FlexCAN_2 I
— CAN3RX FlexCAN_3 I
AF0 GPIO[74] SIUL I/O
AF1 LIN3TX LINFlexD_3 O
PE[10] PCR[74] AF2 CS3_1 DSPI_1 O S Tristate 23 23 G3
AF3 E1UC[30] eMIOS_1 I/O
— EIRQ[10] SIUL I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[75] SIUL I/O

AF1 E0UC[24] eMIOS_0 I/O
AF2 CS4_1 DSPI_1 O
PE[11] PCR[75] S Tristate 25 25 H3
AF3 — — —
— LIN3RX LINFlexD_3 I
— WKPU[14] WKPU I
AF0 GPIO[76] SIUL I/O
AF1 — — —
AF2 E1UC[19] eMIOS_1 I/O
AF3 — — —
PE[12] PCR[76] M/S Tristate 133 157 C14
— CRS FEC I
— SIN_2 DSPI_2 I
— EIRQ[11] SIUL I
— ADC1_S[7] ADC_1 I
AF0 GPIO[77] SIUL I/O
AF1 SOUT_2 DSPI_2 O
PE[13] PCR[77] AF2 E1UC[20] eMIOS_1 I/O M/S Tristate 127 151 C16
AF3 — — —
— RXD[3] FEC I
AF0 GPIO[78] SIUL I/O
AF1 SCK_2 DSPI_2 I/O
PE[14] PCR[78] AF2 E1UC[21] eMIOS_1 I/O M/S Tristate 136 160 A14
AF3 — — —
— EIRQ[12] SIUL I
AF0 GPIO[79] SIUL I/O
AF1 CS0_2 DSPI_2 I/O
PE[15] PCR[79] M/S Tristate 137 161 C12
AF2 E1UC[22] eMIOS_1 I/O
AF3 SCK_6 DSPI_6 I/O
AF0 GPIO[80] SIUL I/O
AF1 E0UC[10] eMIOS_0 I/O
PF[0] PCR[80] AF2 CS3_1 DSPI_1 O S Tristate 63 79 P7
AF3 — — —
— ADC0_S[8] ADC_0 I

32/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[81] SIUL I/O

AF1 E0UC[11] eMIOS_0 I/O
PF[1] PCR[81] AF2 CS4_1 DSPI_1 O S Tristate 64 80 T6
AF3 — — —
— ADC0_S[9] ADC_0 I
AF0 GPIO[82] SIUL I/O
AF1 E0UC[12] eMIOS_0 I/O
PF[2] PCR[82] AF2 CS0_2 DSPI_2 I/O S Tristate 65 81 R6
AF3 — — —
— ADC0_S[10] ADC_0 I
AF0 GPIO[83] SIUL I/O
AF1 E0UC[13] eMIOS_0 I/O
PF[3] PCR[83] AF2 CS1_2 DSPI_2 O S Tristate 66 82 R7
AF3 — — —
— ADC0_S[11] ADC_0 I
AF0 GPIO[84] SIUL I/O
AF1 E0UC[14] eMIOS_0 I/O
PF[4] PCR[84] AF2 CS2_2 DSPI_2 O S Tristate 67 83 R8
AF3 — — —
— ADC0_S[12] ADC_0 I
AF0 GPIO[85] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PF[5] PCR[85] AF2 CS3_2 DSPI_2 O S Tristate 68 84 P8
AF3 — — —
— ADC0_S[13] ADC_0 I
AF0 GPIO[86] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PF[6] PCR[86] AF2 CS1_1 DSPI_1 O S Tristate 69 85 N8
AF3 — — —
— ADC0_S[14] ADC_0 I
AF0 GPIO[87] SIUL I/O
AF1 — — —
PF[7] PCR[87] AF2 CS2_1 DSPI_1 O S Tristate 70 86 P9
AF3 — — —
— ADC0_S[15] ADC_0 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[88] SIUL I/O

AF1 CAN3TX FlexCAN_3 O
PF[8] PCR[88] M/S Tristate 42 50 N2
AF2 CS4_0 DSPI_0 O
AF3 CAN2TX FlexCAN_2 O
AF0 GPIO[89] SIUL I/O
AF1 E1UC[1] eMIOS_1 I/O
AF2 CS5_0 DSPI_0 O
PF[9] PCR[89] AF3 — — — S Tristate 41 49 M4
— CAN2RX FlexCAN_2 I
— CAN3RX FlexCAN_3 I
— WKPU[22] WKPU I
AF0 GPIO[90] SIUL I/O
AF1 CS1_0 DSPI_0 O
PF[10] PCR[90] M/S Tristate 46 54 P2
AF2 LIN4TX LINFlexD_4 O
AF3 E1UC[2] eMIOS_1 I/O
AF0 GPIO[91] SIUL I/O
AF1 CS2_0 DSPI_0 O
AF2 E1UC[3] eMIOS_1 I/O
PF[11] PCR[91] S Tristate 47 55 R1
AF3 — — —
— LIN4RX LINFlexD_4 I
— WKPU[15] WKPU I
AF0 GPIO[92] SIUL I/O
AF1 E1UC[25] eMIOS_1 I/O
PF[12] PCR[92] M/S Tristate 43 51 P1
AF2 LIN5TX LINFlexD_5 O
AF3 — — —
AF0 GPIO[93] SIUL I/O
AF1 E1UC[26] eMIOS_1 I/O
AF2 — — —
PF[13] PCR[93] S Tristate 49 57 P3
AF3 — — —
— LIN5RX LINFlexD_5 I
— WKPU[16] WKPU I

34/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[94] SIUL I/O

AF1 CAN4TX FlexCAN_4 O
PF[14] PCR[94] AF2 E1UC[27] eMIOS_1 I/O M/S Tristate 126 150 D14
AF3 CAN1TX FlexCAN_1 O
ALT4 MDIO FEC I/O
AF0 GPIO[95] SIUL I/O
AF1 E1UC[4] eMIOS_1 I/O
AF2 — — —
AF3 — — —
PF[15] PCR[95] M/S Tristate 125 149 D15
— RX_DV FEC I
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I
— EIRQ[13] SIUL I
AF0 GPIO[96] SIUL I/O
AF1 CAN5TX FlexCAN_5 O
PG[0] PCR[96] AF2 E1UC[23] eMIOS_1 I/O F Tristate 122 146 E13
AF3 — — —
ALT4 MDC FEC O
AF0 GPIO[97] SIUL I/O
AF1 — — —
AF2 E1UC[24] eMIOS_1 I/O
PG[1] PCR[97] AF3 — — — M Tristate 121 145 E14
— TX_CLK FEC I
— CAN5RX FlexCAN_5 I
— EIRQ[14] SIUL I
AF0 GPIO[98] SIUL I/O
AF1 E1UC[11] eMIOS_1 I/O
PG[2] PCR[98] M/S Tristate 16 16 E4
AF2 SOUT_3 DSPI_3 O
AF3 — — —
AF0 GPIO[99] SIUL I/O
AF1 E1UC[12] eMIOS_1 I/O
PG[3] PCR[99] AF2 CS0_3 DSPI_3 I/O S Tristate 15 15 E1
AF3 — — —
— WKPU[17] WKPU I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[100] SIUL I/O

AF1 E1UC[13] eMIOS_1 I/O
PG[4] PCR[100] M/S Tristate 14 14 F2
AF2 SCK_3 DSPI_3 I/O
AF3 — — —
AF0 GPIO[101] SIUL I/O
AF1 E1UC[14] eMIOS_1 I/O
AF2 — — —
PG[5] PCR[101] S Tristate 13 13 D1
AF3 — — —
— WKPU[18] WKPU I
— SIN_3 DSPI_3 I
AF0 GPIO[102] SIUL I/O
AF1 E1UC[15] eMIOS_1 I/O
PG[6] PCR[102] M/S Tristate 38 38 M1
AF2 LIN6TX LINFlexD_6 O
AF3 — — —
AF0 GPIO[103] SIUL I/O
AF1 E1UC[16] eMIOS_1 I/O
AF2 E1UC[30] eMIOS_1 I/O
PG[7] PCR[103] S Tristate 37 37 L2
AF3 — — —
— LIN6RX LINFlexD_6 I
— WKPU[20] WKPU I
AF0 GPIO[104] SIUL I/O
AF1 E1UC[17] eMIOS_1 I/O
PG[8] PCR[104] AF2 LIN7TX LINFlexD_7 O S Tristate 34 34 K3
AF3 CS0_2 DSPI_2 I/O
— EIRQ[15] SIUL I
AF0 GPIO[105] SIUL I/O
AF1 E1UC[18] eMIOS_1 I/O
AF2 — — —
PG[9] PCR[105] S Tristate 33 33 J4
AF3 SCK_2 DSPI_2 I/O
— LIN7RX LINFlexD_7 I
— WKPU[21] WKPU I

36/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[106] SIUL I/O

AF1 E0UC[24] eMIOS_0 I/O
PG[10] PCR[106] AF2 E1UC[31] eMIOS_1 I/O S Tristate 138 162 B13
AF3 — — —
— SIN_4 DSPI_4 I
AF0 GPIO[107] SIUL I/O
AF1 E0UC[25] eMIOS_0 I/O
PG[11] PCR[107] M/S Tristate 139 163 A16
AF2 CS0_4 DSPI_4 I/O
AF3 CS0_6 DSPI_6 I/O
AF0 GPIO[108] SIUL I/O
AF1 E0UC[26] eMIOS_0 I/O
PG[12] PCR[108] AF2 SOUT_4 DSPI_4 O M/S Tristate 116 140 F15
AF3 — — —
ALT4 TXD[2] FEC O
AF0 GPIO[109] SIUL I/O
AF1 E0UC[27] eMIOS_0 I/O
PG[13] PCR[109] AF2 SCK_4 DSPI_4 I/O M/S Tristate 115 139 F16
AF3 — — —
ALT4 TXD[3] FEC O
AF0 GPIO[110] SIUL I/O
AF1 E1UC[0] eMIOS_1 I/O
PG[14] PCR[110] AF2 LIN8TX LINFlexD_8 O S Tristate 134 158 C13
AF3 — — —
— SIN_6 DSPI_6 I
AF0 GPIO[111] SIUL I/O
AF1 E1UC[1] eMIOS_1 I/O
PG[15] PCR[111] AF2 SOUT_6 DSPI_6 O M/S Tristate 135 159 D13
AF3 — — —
— LIN8RX LINFlexD_8 I
AF0 GPIO[112] SIUL I/O
AF1 E1UC[2] eMIOS_1 I/O
AF2 — — —
PH[0] PCR[112] M/S Tristate 117 141 E15
AF3 — — —
ALT4 TXD[1] FEC O
— SIN_1 DSPI_1 I

DocID17478 Rev 9 37/123

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[113] SIUL I/O

AF1 E1UC[3] eMIOS_1 I/O
PH[1] PCR[113] AF2 SOUT_1 DSPI_1 O M/S Tristate 118 142 F13
AF3 — — —
ALT4 TXD[0] FEC O
AF0 GPIO[114] SIUL I/O
AF1 E1UC[4] eMIOS_1 I/O
PH[2] PCR[114] AF2 SCK_1 DSPI_1 I/O M/S Tristate 119 143 D16
AF3 — — —
ALT4 TX_EN FEC O
AF0 GPIO[115] SIUL I/O
AF1 E1UC[5] eMIOS_1 I/O
PH[3] PCR[115] AF2 CS0_1 DSPI_1 I/O M/S Tristate 120 144 F14
AF3 — — —
ALT4 TX_ER FEC O
AF0 GPIO[116] SIUL I/O
AF1 E1UC[6] eMIOS_1 I/O
PH[4] PCR[116] M/S Tristate 162 186 D7
AF2 SOUT_7 DSPI_7 O
AF3 — — —
AF0 GPIO[117] SIUL I/O
AF1 E1UC[7] eMIOS_1 I/O
PH[5] PCR[117] AF2 — — — S Tristate 163 187 B7
AF3 — — —
— SIN_7 DSPI_7 I
AF0 GPIO[118] SIUL I/O
AF1 E1UC[8] eMIOS_1 I/O
PH[6] PCR[118] M/S Tristate 164 188 C7
AF2 SCK_7 DSPI_7 I/O
AF3 MA[2] ADC_0 O
AF0 GPIO[119] SIUL I/O
AF1 E1UC[9] eMIOS_1 I/O
PH[7] PCR[119] AF2 CS3_2 DSPI_2 O M/S Tristate 165 189 C6
AF3 MA[1] ADC_0 O
ALT4 CS0_7 DSPI_7 I/O

38/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[120] SIUL I/O

AF1 E1UC[10] eMIOS_1 I/O
PH[8] PCR[120] M/S Tristate 166 190 A6
AF2 CS2_2 DSPI_2 O
AF3 MA[0] ADC_0 O
AF0 GPIO[121] SIUL I/O
AF1 — — — Input,
PH[9](6) PCR[121] AF2 — — — S weak 155 179 A11
AF3 — — — pull-up
— TCK JTAGC I
AF0 GPIO[122] SIUL I/O
AF1 — — — Input,
PH[10](6) PCR[122] AF2 — — — M/S weak 148 172 D10
AF3 — — — pull-up
— TMS JTAGC I
AF0 GPIO[123] SIUL I/O
AF1 SOUT_3 DSPI_3 O
PH[11] PCR[123] M/S Tristate 140 164 A13
AF2 CS0_4 DSPI_4 I/O
AF3 E1UC[5] eMIOS_1 I/O
AF0 GPIO[124] SIUL I/O
AF1 SCK_3 DSPI_3 I/O
PH[12] PCR[124] M/S Tristate 141 165 B12
AF2 CS1_4 DSPI_4 O
AF3 E1UC[25] eMIOS_1 I/O
AF0 GPIO[125] SIUL I/O
AF1 SOUT_4 DSPI_4 O
PH[13] PCR[125] M/S Tristate 9 9 B1
AF2 CS0_3 DSPI_3 I/O
AF3 E1UC[26] eMIOS_1 I/O
AF0 GPIO[126] SIUL I/O
AF1 SCK_4 DSPI_4 I/O
PH[14] PCR[126] M/S Tristate 10 10 C1
AF2 CS1_3 DSPI_3 O
AF3 E1UC[27] eMIOS_1 I/O
AF0 GPIO[127] SIUL I/O
AF1 SOUT_5 DSPI_5 O
PH[15] PCR[127] M/S Tristate 8 8 E3
AF2 — — —
AF3 E1UC[17] eMIOS_1 I/O

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[128] SIUL I/O

AF1 E0UC[28] eMIOS_0 I/O
PI[0] PCR[128] S Tristate 172 196 C5
AF2 LIN8TX LINFlexD_8 O
AF3 — — —
AF0 GPIO[129] SIUL I/O
AF1 E0UC[29] eMIOS_0 I/O
AF2 — — —
PI[1] PCR[129] S Tristate 171 195 A4
AF3 — — —
— WKPU[24] WKPU I
— LIN8RX LINFlexD_8 I
AF0 GPIO[130] SIUL I/O
AF1 E0UC[30] eMIOS_0 I/O
PI[2] PCR[130] S Tristate 170 194 D6
AF2 LIN9TX LINFlexD_9 O
AF3 — — —
AF0 GPIO[131] SIUL I/O
AF1 E0UC[31] eMIOS_0 I/O
AF2 — — —
PI[3] PCR[131] S Tristate 169 193 B5
AF3 — — —
— WKPU[23] WKPU I
— LIN9RX LINFlexD_9 I
AF0 GPIO[132] SIUL I/O
AF1 E1UC[28] eMIOS_1 I/O
PI[4] PCR[132] M/S Tristate 143 167 A12
AF2 SOUT_4 DSPI_4 O
AF3 — — —
AF0 GPIO[133] SIUL I/O
AF1 E1UC[29] eMIOS_1 I/O
PI[5] PCR[133] AF2 SCK_4 DSPI_4 I/O M/S Tristate 142 166 D12
AF3 CS2_5 DSPI_5 O
ALT4 CS2_6 DSPI_6 O
AF0 GPIO[134] SIUL I/O
AF1 E1UC[30] eMIOS_1 I/O
PI[6] PCR[134] AF2 CS0_4 DSPI_4 I/O S Tristate 11 11 D2
AF3 CS0_5 DSPI_5 I/O
ALT4 CS0_6 DSPI_6 I/O

40/123 DocID17478 Rev 9

SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[135] SIUL I/O

AF1 E1UC[31] eMIOS_1 I/O
PI[7] PCR[135] AF2 CS1_4 DSPI_4 O S Tristate 12 12 E2
AF3 CS1_5 DSPI_5 O
ALT4 CS1_6 DSPI_6 O
AF0 GPIO[136] SIUL I/O
AF1 — — —
PI[8] PCR[136] AF2 — — — S Tristate 108 130 J14
AF3 — — —
— ADC0_S[16] ADC_0 I
AF0 GPIO[137] SIUL I/O
AF1 — — —
PI[9] PCR[137] AF2 — — — S Tristate — 131 J15
AF3 — — —
— ADC0_S[17] ADC_0 I
AF0 GPIO[138] SIUL I/O
AF1 — — —
PI[10] PCR[138] AF2 — — — S Tristate — 134 J16
AF3 — — —
— ADC0_S[18] ADC_0 I
AF0 GPIO[139] SIUL I/O
AF1 — — —
AF2 — — —
PI[11] PCR[139] S Tristate 111 135 H16
AF3 — — —
— ADC0_S[19] ADC_0 I
— SIN_3 DSPI_3 I
AF0 GPIO[140] SIUL I/O
AF1 CS0_3 DSPI_3 I/O
PI[12] PCR[140] AF2 CS0_2 DSPI_2 I/O S Tristate 112 136 G15
AF3 — — —
— ADC0_S[20] ADC_0 I

DocID17478 Rev 9 41/123

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[141] SIUL I/O

AF1 CS1_3 DSPI_3 O
PI[13] PCR[141] AF2 CS1_2 DSPI_2 O S Tristate 113 137 G14
AF3 — — —
— ADC0_S[21] ADC_0 I
AF0 GPIO[142] SIUL I/O
AF1 — — —
AF2 — — —
PI[14] PCR[142] S Tristate 76 92 T12
AF3 — — —
— ADC0_S[22] ADC_0 I
— SIN_4 DSPI_4 I
AF0 GPIO[143] SIUL I/O
AF1 CS0_4 DSPI_4 I/O
PI[15] PCR[143] AF2 CS2_2 DSPI_2 O S Tristate 75 91 P11
AF3 — — —
— ADC0_S[23] ADC_0 I
AF0 GPIO[144] SIUL I/O
AF1 CS1_4 DSPI_4 O
PJ[0] PCR[144] AF2 CS3_2 DSPI_2 O S Tristate 74 90 R11
AF3 — — —
— ADC0_S[24] ADC_0 I
AF0 GPIO[145] SIUL I/O
AF1 — — —
AF2 — — —
PJ[1] PCR[145] S Tristate 73 89 N10
AF3 — —— —
— ADC0_S[25] ADC_0 I
— SIN_5 DSPI_5 I
AF0 GPIO[146] SIUL I/O
AF1 CS0_5 DSPI_5 I/O
PJ[2] PCR[146] AF2 CS0_6 DSPI_6 I/O S Tristate 72 88 R10
AF3 CS0_7 DSPI_7 I/O
— ADC0_S[26] ADC_0 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[147] SIUL I/O

AF1 CS1_5 DSPI_5 O
PJ[3] PCR[147] AF2 CS1_6 DSPI_6 O S Tristate 71 87 P10
AF3 CS1_7 DSPI_7 O
— ADC0_S[27] ADC_0 I
AF0 GPIO[148] SIUL I/O
AF1 SCK_5 DSPI_5 I/O
PJ[4] PCR[148] M/S Tristate 5 5 D3
AF2 E1UC[18] eMIOS_1 I/O
AF3 — — —
AF0 GPIO[149] SIUL I/O
AF1 — — —
PJ[5] PCR[149] AF2 — — — S Tristate — 113 N12
AF3 — — —
— ADC0_S[28] ADC_0 I
AF0 GPIO[150] SIUL I/O
AF1 — — —
PJ[6] PCR[150] AF2 — — — S Tristate — 112 N15
AF3 — — —
— ADC0_S[29] ADC_0 I
AF0 GPIO[151] SIUL I/O
AF1 — — —
PJ[7] PCR[151] AF2 — — — S Tristate — 111 P16
AF3 — — —
— ADC0_S[30] ADC_0 I
AF0 GPIO[152] SIUL I/O
AF1 — — —
PJ[8] PCR[152] AF2 — — — S Tristate — 110 P15
AF3 — — —
— ADC0_S[31] ADC_0 I
AF0 GPIO[153] SIUL I/O
AF1 — — —
PJ[9] PCR[153] AF2 — — — S Tristate — 68 P5
AF3 — — —
— ADC1_S[8] ADC_1 I

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[154] SIUL I/O

AF1 — — —
PJ[10] PCR[154] AF2 — — — S Tristate — 67 T5
AF3 — — —
— ADC1_S[9] ADC_1 I
AF0 GPIO[155] SIUL I/O
AF1 — — —
PJ[11] PCR[155] AF2 — — — S Tristate — 60 R3
AF3 — — —
— ADC1_S[10] ADC_1 I
AF0 GPIO[156] SIUL I/O
AF1 — — —
PJ[12] PCR[156] AF2 — — — S Tristate — 59 T1
AF3 — — —
— ADC1_S[11] ADC_1 I
AF0 GPIO[157] SIUL I/O
AF1 — — —
AF2 CS1_7 DSPI_7 O
AF3 — — —
PJ[13] PCR[157] S Tristate — 65 N5
— CAN4RX FlexCAN_4 I
— ADC1_S[12] ADC_1 I
— CAN1RX FlexCAN_1 I
— WKPU[31] WKPU I
AF0 GPIO[158] SIUL I/O
AF1 CAN1TX FlexCAN_1 O
PJ[14] PCR[158] M/S Tristate — 64 T4
AF2 CAN4TX FlexCAN_4 O
AF3 CS2_7 DSPI_7 O
AF0 GPIO[159] SIUL I/O
AF1 — — —
PJ[15] PCR[159] AF2 CS1_6 DSPI_6 O M/S Tristate — 63 R4
AF3 — — —
— CAN1RX FlexCAN_1 I

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[160] SIUL I/O

AF1 CAN1TX FlexCAN_1 O
PK[0] PCR[160] M/S Tristate — 62 T3
AF2 CS2_6 DSPI_6 O
AF3 — — —
AF0 GPIO[161] SIUL I/O
AF1 CS3_6 DSPI_6 O
PK[1] PCR[161] AF2 — — — M/S Tristate — 41 H4
AF3 — — —
— CAN4RX FlexCAN_4 I
AF0 GPIO[162] SIUL I/O
AF1 CAN4TX FlexCAN_4 O
PK[2] PCR[162] M/S Tristate — 42 L4
AF2 — — —
AF3 — — —
AF0 GPIO[163] SIUL I/O
AF1 E1UC[0] eMIOS_1 I/O
AF2 — — —
PK[3] PCR[163] M/S Tristate — 43 N1
AF3 — — —
— CAN5RX FlexCAN_5 I
— LIN8RX LINFlexD_8 I
AF0 GPIO[164] SIUL I/O
AF1 LIN8TX LINFlexD_8 O
PK[4] PCR[164] M/S Tristate — 44 M3
AF2 CAN5TX FlexCAN_5 O
AF3 E1UC[1] eMIOS_1 I/O
AF0 GPIO[165] SIUL I/O
AF1 — — —
AF2 — — —
PK[5] PCR[165] M/S Tristate — 45 M5
AF3 — — —
— CAN2RX FlexCAN_2 I
— LIN2RX LINFlexD_2 I
AF0 GPIO[166] SIUL I/O
AF1 CAN2TX FlexCAN_2 O
PK[6] PCR[166] M/S Tristate — 46 M6
AF2 LIN2TX LINFlexD_2 O
AF3 — — —

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[167] SIUL I/O

AF1 — — —
AF2 — — —
PK[7] PCR[167] M/S Tristate — 47 M7
AF3 — — —
— CAN3RX FlexCAN_3 I
— LIN3RX LINFlexD_3 I
AF0 GPIO[168] SIUL I/O
AF1 CAN3TX FlexCAN_3 O
PK[8] PCR[168] M/S Tristate — 48 M8
AF2 LIN3TX LINFlexD_3 O
AF3 — — —
AF0 GPIO[169] SIUL I/O
AF1 — — —
PK[9] PCR[169] AF2 — — — M/S Tristate — 197 E8
AF3 — — —
— SIN_4 DSPI_4 I
AF0 GPIO[170] SIUL I/O
AF1 SOUT_4 DSPI_4 O
PK[10] PCR[170] M/S Tristate — 198 E7
AF2 — — —
AF3 — — —
AF0 GPIO[171] SIUL I/O
AF1 SCK_4 DSPI_4 I/O
PK[11] PCR[171] M/S Tristate — 199 F8
AF2 — — —
AF3 — — —
AF0 GPIO[172] SIUL I/O
AF1 CS0_4 DSPI_4 I/O
PK[12] PCR[172] M/S Tristate — 200 G12
AF2 — — —
AF3 — — —
AF0 GPIO[173] SIUL I/O
AF1 CS3_6 DSPI_6 O
PK[13] PCR[173] AF2 CS2_7 DSPI_7 O M/S Tristate — 201 H12
AF3 SCK_1 DSPI_1 I/O
— CAN3RX FlexCAN_3 I

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[174] SIUL I/O

AF1 CAN3TX FlexCAN_3 O
PK[14] PCR[174] M/S Tristate — 202 J12
AF2 CS3_7 DSPI_7 O
AF3 CS0_1 DSPI_1 I/O
AF0 GPIO[175] SIUL I/O
AF1 — — —
AF2 — — —
PK[15] PCR[175] M/S Tristate — 203 D5
AF3 — — —
— SIN_1 DSPI_1 I
— SIN_7 DSPI_7 I
AF0 GPIO[176] SIUL I/O
AF1 SOUT_1 DSPI_1 O
PL[0] PCR[176] M/S Tristate — 204 C4
AF2 SOUT_7 DSPI_7 O
AF3 — — —
AF0 GPIO[177] SIUL I/O
AF1 — — —
PL[1] PCR[177] M/S Tristate — — F7
AF2 — — —
AF3 — — —
AF0 GPIO[178] SIUL I/O
PCR[178] AF1 — — —
PL[2] (7) M/S Tristate — — F5
AF2 MDO0(8) Nexus O
AF3 — — —
AF0 GPIO[179] SIUL I/O
AF1 — — —
PL[3] PCR[179] M/S Tristate — — G5
AF2 MDO1 Nexus O
AF3 — — —
AF0 GPIO[180] SIUL I/O
AF1 — — —
PL[4] PCR[180] M/S Tristate — — H5
AF2 MDO2 Nexus O
AF3 — — —
AF0 GPIO[181] SIUL I/O
AF1 — — —
PL[5] PCR[181] M/S Tristate — — J5
AF2 MDO3 Nexus O
AF3 — — —

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[182] SIUL I/O

AF1 — — —
PL[6] PCR[182] M/S Tristate — — K5
AF2 MDO4 Nexus O
AF3 — — —
AF0 GPIO[183] SIUL I/O
AF1 — — —
PL[7] PCR[183] M/S Tristate — — L5
AF2 MDO5 Nexus O
AF3 — — —
AF0 GPIO[184] SIUL I/O
AF1 — — —
PL[8] PCR[184] AF2 — — — S Pull-up — — M9
AF3 — — —
— EVTI Nexus I
AF0 GPIO[185] SIUL I/O
AF1 — — —
PL[9] PCR[185] M/S Tristate — — M10
AF2 MSEO Nexus O
AF3 — — —
AF0 GPIO[186] SIUL I/O
AF1 — — —
PL[10] PCR[186] F/S Tristate — — M11
AF2 MCKO Nexus O
AF3 — — —
AF0 GPIO[187] SIUL I/O
AF1 — — —
PL[11] PCR[187] M/S Tristate — — M12
AF2 — — —
AF3 — — —
AF0 GPIO[188] SIUL I/O
AF1 — — —
PL[12] PCR[188] M/S Tristate — — F11
AF2 EVTO Nexus O
AF3 — — —
AF0 GPIO[189] SIUL I/O
AF1 — — —
PL[13] PCR[189] M/S Tristate — — F10
AF2 MDO6 Nexus O
AF3 — — —

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SPC564Bxx-SPC56ECxx Package pinouts and signal descriptions

Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[190] SIUL I/O

AF1 — — —
PL[14] PCR[190] M/S Tristate — — E12
AF2 MDO7 Nexus O
AF3 — — —
AF0 GPIO[191] SIUL I/O
AF1 — — —
PL[15] PCR[191] M/S Tristate — — E11
AF2 MDO8 Nexus O
AF3 — — —
AF0 GPIO[192] SIUL I/O
AF1 — — —
PM[0] PCR[192] M/S Tristate — — E10
AF2 MDO9 Nexus O
AF3 — — —
AF0 GPIO[193] SIUL I/O
AF1 — — —
PM[1] PCR[193] M/S Tristate — — E9
AF2 MDO10 Nexus O
AF3 — — —
AF0 GPIO[194] SIUL I/O
AF1 — — —
PM[2] PCR[194] M/S Tristate — — F12
AF2 MDO11 Nexus O
AF3 — — —
AF0 GPIO[195] SIUL I/O
AF1 — — —
PM[3] PCR[195] M/S Tristate — — K12
AF2 — — —
AF3 — — —
AF0 GPIO[196] SIUL I/O
AF1 — — —
PM[4] PCR[196] M/S Tristate — — L12
AF2 — — —
AF3 — — —

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Table 5. Functional port pin descriptions (continued)

Pin number

direction(2)
function(1)

Peripheral
Alternate

Pad type

RESET
config.

LQFP 176

LQFP 208

LBGA256
Port

I/O
PCR Function
pin

AF0 GPIO[197] SIUL I/O

AF1 — — —
PM[5] PCR[197] M/S Tristate — — F9
AF2 — — —
AF3 — — —
AF0 GPIO[198] SIUL I/O
AF1 — — —
PM[6] PCR[198] M/S Tristate — — F6
AF2 — — —
AF3 — — —
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA =
000  AF0; PCR.PA = 001 AF1; PCR.PA = 010 AF2; PCR.PA = 011  AF3; PCR.PA = 100  ALT4. This is
intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless
of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported
as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the
values of the PSMIO.PADSELx bitfields inside the SIUL module.
3. NMI[0] and NMI[1] have a higher priority than alternate functions. When NMI is selected, the PCR.PA field is ignored.
4. SXOSC’s OSC32k_XTAL and OSC32k_EXTAL pins are shared with GPIO functionality. When used as crystal pins, other
functionality of the pin cannot be used and it should be ensured that application never programs OBE and PUE bit of the
corresponding PCR to "1".
5. If you want to use OSC32K functionality through PB[8] and PB[9], you must ensure that PB[10] is static in nature as PB[10]
can induce coupling on PB[9] and disturb oscillator frequency.
6. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
7. When MBIST is enabled to run (STCU Enable = 1), the application must not drive or tie PAD[178) (MDO[0]) to 0 V before
the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate MBIST operation. When
MBIST is not enabled (STCU Enable = 0), there are no restriction as the device does not internally drive the pad.
8. These pins can be configured as Nexus pins during reset by the debugger writing to the Nexus Development Interface
"Port Control Register" rather than the SIUL. Specifically, the debugger can enable the MDO[7:0], MSEO, and MCKO ports
by programming NDI (PCR[MCKO_EN] or PCR[PSTAT_EN]). MDO[8:11] ports can be enabled by programming NDI
((PCR[MCKO_EN] and PCR[FPM]) or PCR[PSTAT_EN]).

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SPC564Bxx-SPC56ECxx Electrical Characteristics

3 Electrical Characteristics

This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS_HV). This could be done by the internal pull-up and pull-down, which is provided by
the product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.

3.1 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 6 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 6. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
C
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

3.2 NVUSRO register

Portions of the device configuration, such as high voltage supply is controlled via bit values
in the Non-Volatile User Options Register (NVUSRO). For a detailed description of the
NVUSRO register, see SPC564Bxx and SPC56ECxx Reference Manual.

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3.2.1 NVUSRO [PAD3V5V(0)] field description

Table 7 shows how NVUSRO [PAD3V5V(0)] controls the device configuration for VDD_HV_A
domain.

Table 7. PAD3V5V(0) field description

(1)
Value Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.

The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.

3.2.2 NVUSRO [PAD3V5V(1)] field description

Table 8 shows how NVUSRO [PAD3V5V(1)] controls the device configuration the device
configuration for VDD_HV_B domain.

Table 8. PAD3V5V(1) field description

Value(1) Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V
1. '1' is delivery value. It is part of shadow flash memory, thus programmable by customer.

The DC electrical characteristics are dependent on the PAD3V5V(0,1) bit value.

3.3 Absolute maximum ratings

Table 9. Absolute maximum ratings
Value
Symbol Parameter Conditions Unit
Min Max

S Digital ground on VSS_HV

VSS_HV — 0 0 V
R pins
Voltage on VDD_HV_A pins
S
VDD_HV_A with respect to ground — –0.3 6.0 V
R
(VSS_HV)
Voltage on VDD_HV_B pins
S
VDD_HV_B(1) with respect to common — –0.3 6.0 V
R
ground (VSS_HV)
Voltage on VSS_LV (low
S voltage digital supply) pins
VSS_LV — VSS_HV 0.1 VSS_HV 0.1 V
R with respect to ground
(VSS_HV)

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Table 9. Absolute maximum ratings (continued)

Value
Symbol Parameter Conditions Unit
Min Max

Base control voltage for

VRC_CTRL(2) Relative to VDD_LV 0 VDD_LV + 1 V
external BCP68 NPN device
Voltage on VSS_HV_ADC0,
S VSS_HV_ADC1 (ADC
VSS_ADC — VSS_HV 0.1 VSS_HV + 0.1 V
R reference) pin with respect to
ground (VSS_HV)

Voltage on VDD_HV_ADC0 — –0.3 6.0

S
VDD_HV_ADC0 with respect to ground Relative to V
R VDD_HV_A 0.3 VDD_HV_A+0.3
(VSS_HV) VDD_HV_A(3)

Voltage on VDD_HV_ADC1 — –0.3 6.0

VDD_HV_ADC1 S
(4) with respect to ground Relative to V
R VDD_HV_A0.3 VDD_HV_A+0.3
(VSS_HV) VDD_HV_A2
Voltage on any GPIO pin
S Relative to VDD_HV_A/HV_B VDD_HV_A/HV_B+
VIN with respect to ground V
R VDD_HV_A/HV_B 0.3 0.3
(VSS_HV)
S Injected input current on any
IINJPAD — –10 10
R pin during overload condition
Absolute sum of all injected mA
S
IINJSUM input currents during — –50 50
R
overload condition

Sum of all the static I/O VDD = 5.0 V ± 10%,

70
S current within a supply PAD3V5V = 0
(5)
IAVGSEG mA
R segment VDD = 3.3 V ± 10%,
(VDD_HV_A or VDD_HV_B) 64
PAD3V5V = 1
S
TSTORAGE Storage temperature — –55(6) 150 °C
R
1. VDD_HV_B can be independently controlled from VDD_HV_A. These can ramp up or ramp down in any order. Design is robust
against any supply order.
2. This voltage is internally generated by the device and no external voltage should be supplied.
3. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
4. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±300 mV of VDD_HV_B when these channels are used for ADC_1.
5. Any temperature beyond 125 °C should limit the current to 50 mA (max).
6. This is the storage temperature for the flash memory.

Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD_HV_A/HV_B or
VIN < VSS_HV), the voltage on pins with respect to ground (VSS_HV) must not exceed the
recommended values.

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3.4 Recommended operating conditions

Table 10. Recommended operating conditions (3.3 V)
Value
Symbol Parameter Conditions Unit
Min Max

Digital ground on
VSS_HV SR — 0 0 V
VSS_HV pins
Voltage on VDD_HV_A pins
VDD_HV_A(1) SR with respect to ground — 3.0 3.6 V
(VSS_HV)
Voltage on VDD_HV_B pins
VDD_HV_B(1) SR with respect to ground — 3.0 3.6 V
(VSS_HV)
Voltage on VSS_LV (low
voltage digital supply)
VSS_LV(2) SR — VSS_HV 0.1 VSS_HV + 0.1 V
pins with respect to
ground (VSS_HV)
Base control voltage for
Relative to
VRC_CTRL(3) external BCP68 NPN 0 VDD_LV + 1 V
VDD_LV
device
Voltage on
VSS_HV_ADC0,
VSS_HV_ADC1 (ADC
VSS_ADC SR — VSS_HV 0.1 VSS_HV + 0.1 V
reference) pin with
respect to ground
(VSS_HV)
Voltage on — 3.0(5) 3.6
VDD_HV_ADC0 VDD_HV_ADC0 with
(4) SR Relative to V
respect to ground VDD_HV_A 0.1 VDD_HV_A + 0.1
(VSS_HV) VDD_HV_A(6)

Voltage on — 3.0 3.6

VDD_HV_ADC1 VDD_HV_ADC1 with
(7) SR Relative to V
respect to ground VDD_HV_A 0.1 VDD_HV_A + 0.1
(VSS_HV) VDD_HV_A(6)

Voltage on any GPIO pin — VSS_HV 0.1 —

VIN SR with respect to ground Relative to V
(VSS_HV) — VDD_HV_A/HV_B + 0.1
VDD_HV_A/HV_B
Injected input current on
IINJPAD SR any pin during overload — 5 5
condition
mA
Absolute sum of all
IINJSUM SR injected input currents — 50 50
during overload condition

VDD_HV_A slope to ensure — — 0.5 V/µs

TVDD SR
correct power up(8) — 0.5 — V/min

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Table 10. Recommended operating conditions (3.3 V) (continued)

Value
Symbol Parameter Conditions Unit
Min Max

Ambient temperature fCPU up to

TA SR –40 125
under bias 120 MHz  2%
°C
Junction temperature
TJ SR — 40 150
under bias
1. 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair.
2. 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance needs
to be provided as CREG on each VDD_LV pin. For details refer to the Power Management chapter of the MPC5646C
Reference Manual.
3. This voltage is internally generated by the device and no external voltage should be supplied.
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
8. Guaranteed by the device validation.

Table 11. Recommended operating conditions (5.0 V)

Value
Symbol Parameter Conditions Unit
Min Max

S
VSS_HV Digital ground on VSS_HV pins — 0 0 V
R

S Voltage on VDD_HV_A pins with — 4.5 5.5

VDD_HV_A(1) V
R respect to ground (VSS_HV) Voltage drop(2) 3.0 5.5
Generic GPIO functionality — 3.0 5.5 V
Ethernet/3.3 V functionality
S (See the notes in all figures in
VDD_HV_B
R Section 2: Package pinouts and — 3.0 3.6 V
signal descriptions for the list of
channels operating in VDD_HV_B
domain)
Voltage on VSS_LV (Low voltage
S
VSS_LV(3) digital supply) pins with respect to — VSS_HV – 0.1 VSS_HV + 0.1 V
R
ground (VSS_HV)
Base control voltage for external Relative to
VRC_CTRL(4) 0 VDD_LV + 1 V
BCP68 NPN device VDD_LV
Voltage on VSS_HV_ADC0,
S VSS_HV_ADC1 (ADC reference)
VSS_ADC — VSS_HV – 0.1 VSS_HV + 0.1 V
R pin with respect to ground
(VSS_HV)

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Table 11. Recommended operating conditions (5.0 V) (continued)

Value
Symbol Parameter Conditions Unit
Min Max

— 4.5 5.5
(2)
VDD_HV_ADC0 S Voltage on VDD_HV_ADC0 with Voltage drop 3.0 5.5
(5) V
R respect to ground (VSS_HV)
Relative to
VDD_HV_A – 0.1 VDD_HV_A + 0.1
VDD_HV_A(6)
— 4.5 5.5
VDD_HV_ADC1 S Voltage on VDD_HV_ADC1 with Voltage drop(2) 3.0 5.5
(7) V
R respect to ground (VSS_HV)
Relative to
VDD_HV_A 0.1 VDD_HV_A + 0.1
VDD_HV_A(6)
— VSS_HV –0.1 —
S Voltage on any GPIO pin with
VIN Relative to VDD_HV_A/HV_B V
R respect to ground (VSS_HV) —
VDD_HV_A/HV_B + 0.1
S Injected input current on any pin
IINJPAD — –5 5
R during overload condition
Absolute sum of all injected input mA
S
IINJSUM currents during overload — –50 50
R
condition

S VDD_HV_A slope to ensure correct — — 0.5 V/µs

TVDD
R power up(8) — 0.5 — V/min
S
TA C-Grade Part Ambient temperature under bias — 40 85
R
S
TJ C-Grade Part Junction temperature under bias — 40 110
R
S
TA V-Grade Part Ambient temperature under bias — 40 105
R
°C
S
TJ V-Grade Part Junction temperature under bias — 40 130
R
S
TA M-Grade Part Ambient temperature under bias — 40 125
R
S
TJ M-Grade Part Junction temperature under bias — 40 150
R
1. 100 nF EMI capacitance need to be provided between each VDD/VSS_HV pair.
2. Full device operation is guaranteed by design from 3.0 V–5.5 V. OSC functionality is guaranteed from the entire range
3.0V–5.5 V, the parametrics measured are at 3.0V and 5.5V (extreme voltage ranges to cover the range of operation). The
parametrics might have some variation in the intermediate voltage range, but there is no impact to functionality.
3. 100 nF EMI capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 10 µF bulk capacitance needs
to be provided as CREG on each VDD_LV pin.
4. This voltage is internally generated by the device and no external voltage should be supplied.
5. 100 nF capacitance needs to be provided between VDD_HV_(ADC0/ADC1)/VSS_HV_(ADC0/ADC1) pair.
6. Both the relative and the fixed conditions must be met. For instance: If VDD_HV_A is 5.9 V, VDD_HV_ADC0 maximum value is
6.0 V then, despite the relative condition, the max value is VDD_HV_A + 0.3 = 6.2 V.
7. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.

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8. Guaranteed by device validation.

Note: SRAM retention guaranteed to LVD levels.

3.5 Thermal characteristics

3.5.1 Package thermal characteristics

Table 12. LQFP thermal characteristics(1)

Value(3)
(2) Pin
Symbol C Parameter Conditions Unit
count
Min Typ Max

Thermal resistance, 176 — — 44.4(4) °C/W

Single-layer
RJA CC D junction-to-ambient
board—1s 208 — — 43 °C/W
natural convection
Thermal resistance, 176 — — 36.1 °C/W
Four-layer
RJA CC D junction-to-ambient
board—2s2p(5) 208 — — 33.9 °C/W
natural convection
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.
2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C.
3. All values need to be confirmed during device validation.
4. 1s board as per standard JEDEC (JESD51-7) in natural convection.
5. 2s2p board as per standard JEDEC (JESD51-7) in natural convection.

Table 13. LBGA256 thermal characteristics(1)

Symbol C Parameter Conditions Value Unit

Thermal resistance, junction-to-ambient Single-layer board—1s 44.3

RJA CC — °C/W
natural convection Four-layer board—2s2p 31
1. Thermal characteristics are targets based on simulation that are subject to change per device characterization.

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3.5.2 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation 1:

Equation 1 TJ = TA + (PD  RJA)

Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

Equation 2 PD = K / (TJ + 273 °C)

Therefore, solving equations Equation 1 and Equation 2:

Equation 3 K = PD  (TA + 273 °C) + RJA  PD2

Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations Equation 1 and Equation 2
iteratively for any value of TA.

3.6 I/O pad electrical characteristics

3.6.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate
functions:
 Slow pads—These pads are the most common pads, providing a good compromise
between transition time and low electromagnetic emission.
 Medium pads—These pads provide transition fast enough for the serial communication
channels with controlled current to reduce electromagnetic emission.
 Fast pads—These pads provide maximum speed. These are used for improved Nexus
debugging capability.
 Input only pads—These pads are associated to ADC channels and 32 kHz low power
external crystal oscillator providing low input leakage.
 Low power pads—These pads are active in standby mode for wakeup source.
Also, medium/slow and fast/medium pads are available in design which can be configured
to behave like a slow/medium and medium/fast pads depending upon the slew-rate control.

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Medium and fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.

3.6.2 I/O input DC characteristics

Table 14 provides input DC electrical characteristics as described in Figure 5.

Figure 5. I/O input DC electrical characteristics definition

VIN
VDD

VIH

VHYS

VIL

PDIx = ‘1
(GPDI register of SIUL)

PDIx = ‘0’

Table 14. I/O input DC electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input high level CMOS (Schmitt

VIH SR P — 0.65 VDD — VDD + 0.4
Trigger)
Input low level CMOS (Schmitt
VIL SR P — 0.3 — 0.35VDD V
Trigger)
Input hysteresis CMOS (Schmitt
VHYS CC C — 0.1VDD — —
Trigger)
P TA = 40 °C — 2 —
P No injection T = 25 °C — 2 —
A
ILKG CC Digital input leakage on adjacent nA
D pin TA = 105 °C — 12 500
P TA = 125 °C — 70 1000
Width of input pulse rejected by
WFI SR P — — — 40(4) ns
analog filter(3)
Width of input pulse accepted by
WNFI SR P — 1000(4) — — ns
analog filter(3)
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. Analog filters are available on all wakeup lines.

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4. The width of input pulse in between 40 ns to 1000 ns is indeterminate. It may pass the noise or may not depending on
silicon sample to sample variation.

3.6.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:
 Table 15 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
 Table 16 provides output driver characteristics for I/O pads when in SLOW
configuration.
 Table 17 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
 Table 18 provides output driver characteristics for I/O pads when in FAST
configuration.

Table 15. I/O pull-up/pull-down DC electrical characteristics

Value
Symbol C Parameter Conditions(1),(2) Unit
Min Typ Max

P VIN = VIL, VDD = PAD3V5V = 0 10 — 150

Weak pull-up 5.0 V ± 10%
C PAD3V5V = 1(3) 10 — 250
|IWPU| CC current µA
absolute value VIN = VIL, VDD =
P PAD3V5V = 1 10 — 150
3.3 V ± 10%
P VIN = VIH, VDD = PAD3V5V = 0 10 — 150
Weak pull-down 5.0 V ± 10%
C PAD3V5V = 1 10 — 250
|IWPD| CC current µA
absolute value VIN = VIH, VDD =
P PAD3V5V = 1 10 — 150
3.3 V ± 10%
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 16. SLOW configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1),(2) Unit
Min Typ Max

IOH = 3 mA,
P 0.8VDD — —
VDD = 5.0 V ± 10%, PAD3V5V = 0
Output high level
Push IOH = 3 mA,
VOH CC C SLOW 0.8VDD — — V
Pull VDD = 5.0 V ± 10%, PAD3V5V = 1(3)
configuration
IOH = 1.5 mA,
P VDD 0.8 — —
VDD = 3.3 V ± 10%, PAD3V5V = 1

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Table 16. SLOW configuration output buffer electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1),(2) Unit
Min Typ Max

IOL = 3 mA,
P — — 0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
Output low level
Push IOL = 3 mA,
VOL CC C SLOW — — 0.1VDD V
Pull VDD = 5.0 V ± 10%, PAD3V5V = 1(3)
configuration
IOL = 1.5 mA,
P — — 0.5
VDD = 3.3 V ± 10%, PAD3V5V = 1
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 17. MEDIUM configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1),(2) Unit
Min Typ Max

IOH = 3 mA,
C VDD = 5.0 V ± 10%, 0.8VDD — —
PAD3V5V = 0
Output high level IOH = 1.5 mA,
VOH CC C MEDIUM Push Pull VDD = 5.0 V ± 10%, 0.8VDD — — V
configuration PAD3V5V = 1(3)
IOH = 2 mA,
C VDD = 3.3 V ± 10%, VDD 0.8 — —
PAD3V5V = 1
IOL = 3 mA,
C VDD = 5.0 V ± 10%, — — 0.2VDD
PAD3V5V = 0
Output low level IOL = 1.5 mA,
VOL CC C MEDIUM Push Pull VDD = 5.0 V ± 10%, — — 0.1VDD V
configuration PAD3V5V = 1(3)
IOL = 2 mA,
C VDD = 3.3 V ± 10%, — — 0.5
PAD3V5V = 1
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

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Table 18. FAST configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1),(2) Unit
Min Typ Max

IOH = 14 mA,

P VDD = 5.0 V ± 10%, 0.8VDD — —
PAD3V5V = 0
Output high
IOH = 7 mA,
level
VOH CC C Push Pull VDD = 5.0 V ± 10%, 0.8VDD — — V
FAST
PAD3V5V = 1(3)
configuration
IOH = 11 mA,
C VDD = 3.3 V ± 10%, VDD 0.8 — —
PAD3V5V = 1
IOL = 14 mA,
P VDD = 5.0 V ± 10%, — — 0.1VDD
PAD3V5V = 0
Output low level IOL = 7 mA,
VOL CC C FAST Push Pull VDD = 5.0 V ± 10%, — — 0.1VDD V
configuration PAD3V5V = 1(3)
IOL = 11 mA,
C VDD = 3.3 V ± 10%, — — 0.5
PAD3V5V = 1
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus outputs (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

3.6.4 Output pin transition times

Table 19. Output pin transition times

Value(3)
(1),(2)
Symbol C Parameter Conditions Unit
Min Typ Max

D CL = 25 pF — — 50
VDD = 5.0 V ± 10 %,
T CL = 50 pF — — 100
PAD3V5V = 0
D Output transition CL = 100 pF — — 125
Ttr CC time output pin(4) ns
D SLOW configuration CL = 25 pF — — 40
VDD = 3.3 V ± 10 %,
T CL = 50 pF — — 50
PAD3V5V = 1
D CL = 100 pF — — 75
D CL = 25 pF VDD = 5.0 V ± 10 %, — — 10
T CL = 50 pF PAD3V5V = 0 — — 20
Output transition
SIUL.PCRx.SRC = 1
D time output pin(4) CL = 100 pF — — 40
Ttr CC ns
D MEDIUM CL = 25 pF — — 12
VDD = 3.3 V ± 10 %,
configuration
T CL = 50 pF PAD3V5V = 1 — — 25
D CL = 100 pF SIUL.PCRx.SRC = 1 — — 40

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Table 19. Output pin transition times (continued)

Value(3)
(1),(2)
Symbol C Parameter Conditions Unit
Min Typ Max
CL = 25 pF — — 4
VDD = 5.0 V ± 10%,
CL = 50 pF — — 6
PAD3V5V = 0
Output transition CL = 100 pF — — 12
Ttr CC D time output pin(4) ns
FAST configuration CL = 25 pF — — 4
VDD = 3.3 V ± 10%,
CL = 50 pF — — 7
PAD3V5V = 1
CL = 100 pF — — 12
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. All values need to be confirmed during device validation.
4. CL includes device and package capacitances (CPKG < 5 pF).

3.6.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply is associated
to a VDD/VSS_HV supply pair as described in Table 20.
Table 21 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static current of the I/O
on a single segment should remain below the IDYNSEG maximum value.

Table 20. I/O supplies

Package I/O Supplies

LBGA256(1) Equivalent to 208-pin LQFP segment pad distribution + G6, G11, H11, J11

pin6 pin73 pin101 pin132 pin147 pin174

pin27 (VSS_HV)
(VDD_HV_A) (VDD_HV_A) (VSS_HV) (VSS_HV) (VSS_HV)
LQFP208 (VDD_HV_A)pi —
pin7 pin75 pin102 pin133 pin148 pin175
n28 (VSS_HV)
(VSS_HV) (VDD_HV_A) (VSS_HV) (VDD_HV_A) (VDD_HV_B) (VDD_HV_A)
pin6 pin27 pin57 pin85 pin123 pin150
(VDD_HV_A) (VDD_HV_A)pi (VSS_HV) (VDD_HV_A) (VSS_HV) (VSS_HV)
LQFP176 — —
pin7 n28 pin59 pin86 pin124 pin151
(VSS_HV) (VSS_HV) (VDD_HV_A) (VSS_HV) (VDD_HV_B) (VDD_HV_A)
1. VDD_HV_B supplies the IO voltage domain for the pins PE[12], PA[11], PA[10], PA[9], PA[8], PA[7], PE[13], PF[14], PF[15],
PG[0], PG[1], PH[3], PH[2], PH[1], PH[0], PG[12], PG[13], and PA[3].

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Table 21. I/O consumption

Value(3)
(1),(2)
Symbol C Parameter Conditions Unit
Min Typ Max

VDD = 5.0 V ± 10%,

— — 19.9
C Peak I/O current for PAD3V5V = 0
ISWTSLW(4) D CL = 25 pF mA
C SLOW configuration VDD = 3.3 V ± 10%,
— — 15.5
PAD3V5V = 1
VDD = 5.0 V ± 10%,
Peak I/O current for — — 28.8
C PAD3V5V = 0
(4)
ISWTMED D MEDIUM CL = 25 pF mA
C VDD = 3.3 V ± 10%,
configuration — — 16.3
PAD3V5V = 1
VDD = 5.0 V ± 10%,
— — 113.5
C Peak I/O current for PAD3V5V = 0
ISWTFST(4) D CL = 25 pF mA
C FAST configuration VDD = 3.3 V ± 10%,
— — 52.1
PAD3V5V = 1
CL = 25 pF, 2 MHz — — 2.22
VDD = 5.0 V ± 10%,
CL = 25 pF, 4 MHz — — 3.13
PAD3V5V = 0
Root mean square CL = 100 pF, 2 MHz — — 6.54
C
IRMSSLW D I/O current for mA
C
SLOW configuration CL = 25 pF, 2 MHz — — 1.51
VDD = 3.3 V ± 10%,
CL = 25 pF, 4 MHz — — 2.14
PAD3V5V = 1
CL = 100 pF, 2 MHz — — 4.33
CL = 25 pF, 13 MHz — — 6.5
VDD = 5.0 V ± 10%,
CL = 25 pF, 40 MHz — — 13.32
Root mean square PAD3V5V = 0
C I/O current for CL = 100 pF, 13 MHz — — 18.26
IRMSMED D mA
C MEDIUM CL = 25 pF, 13 MHz — — 4.91
configuration VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz — — 8.47
PAD3V5V = 1
CL = 100 pF, 13 MHz — — 10.94
CL = 25 pF, 40 MHz — — 21.05
VDD = 5.0 V ± 10%,
CL = 25 pF, 64 MHz — — 33
PAD3V5V = 0
Root mean square CL = 100 pF, 40 MHz — — 55.77
C
IRMSFST D I/O current for FAST mA
C CL = 25 pF, 40 MHz — — 14
configuration
VDD = 3.3 V ± 10%,
CL = 25 pF, 64 MHz — — 20
PAD3V5V = 1
CL = 100 pF, 40 MHz — — 34.89
Sum of all the static VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70
S
IAVGSEG D I/O current within a mA
R VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65(4)
supply segment
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B.
3. All values need to be confirmed during device validation.
4. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

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3.7 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

Figure 6. Start-up reset requirements

VDD_HV_A

VDDMIN

RESET

VIH

VIL

device reset forced by RESET device start-up phase

Figure 7. Noise filtering on reset signal

VRESET

hw_rst
VDD
‘1’

VIH

VIL

‘0’
filtered by filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

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Table 22. Reset electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

S Input High Level CMOS

VIH P — 0.65VDD — VDD + 0.4 V
R (Schmitt Trigger)
S Input low Level CMOS
VIL P — 0.3 — 0.35VDD V
R (Schmitt Trigger)
C Input hysteresis CMOS
VHYS C — 0.1VDD — — V
C (Schmitt Trigger)
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10 %, PAD3V5V = 0 — — 0.1VDD
(recommended)
C Push Pull, IOL = 1 mA,
VOL P Output low level — — 0.1VDD V
C VDD = 5.0 V ± 10%, PAD3V5V = 1(3)
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
CL = 25 pF,
— — 10
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 50 pF,
— — 20
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100 pF,
Output transition time — — 40
C VDD = 5.0 V ± 10%, PAD3V5V = 0
Ttr D output pin(4) ns
C CL = 25 pF,
MEDIUM configuration — — 12
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50 pF,
— — 25
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100 pF,
— — 40
VDD = 3.3 V ± 10%, PAD3V5V = 1
S Reset input filtered
WFRST P — — — 40 ns
R pulse
WNFRS S Reset input not filtered
P — 1000 — — ns
T R pulse
VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150
C Weak pull-up current
|IWPU| P VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150 µA
C absolute value
VDD = 5.0 V ± 10%, PAD3V5V = 1(5) 10 — 250
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. VDD as mentioned in the table is VDD_HV_A/VDD_HV_B. All values need to be confirmed during device validation.
3. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to the RGM module section of the
device Reference Manual).
4. CL includes device and package capacitance (CPKG < 5 pF).
5. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

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3.8 Power management electrical characteristics

3.8.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage supply VDD_HV_A. The following supplies are involved:
 HV: High voltage external power supply for voltage regulator module. This must be
provided externally through VDD_HV_A power pin.
 LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
generated by the on-chip VREG with an external ballast (BCP68 NPN device). It is
further split into four main domains to ensure noise isolation between critical LV
modules within the device:
– LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
– LV_CFLA0/CFLA1: Low voltage supply for the two code Flash modules. It is
shorted with LV_COR through double bonding.
– LV_DFLA: Low voltage supply for data Flash module. It is shorted with LV_COR
through double bonding.
– LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.

Figure 8. Voltage regulator capacitance connection

100 nf 100 nf 100 nf

VDD_LV VSS_LV VDD_LV VSS_LV VDD_LV VSS_LV

40 f PD0 (always on domain)

(4  10 f)
PD1 Switchable Domain
(FMPLL, Flash) 32 KB 56 KB 8 KB
PD0 Logic

(CREGn) Split Split Split

CTRL CTRL CTRL

VDD_LV
HPVDD
VSS_LV
Off chip
VRC_CTRL sw1 (<0.1)
BCP68 HPREG
NPN driver
LPVDD

10 f
LPREG

Chip Boundary
(CDEC2)

VDD_BV VDD_HV_A VSS_HV

HPVDD
100 nf
LPVDD

1) All VSS_LV pins must be grounded, as shown for VSS_HV pin.

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The internal voltage regulator requires external bulk capacitance (CREGn) to be connected
to the device to provide a stable low voltage digital supply to the device. Also required for
stability is the CDEC2 capacitor at ballast collector. This is needed to minimize sharp injection
current when ballast is turning ON. Apart from the bulk capacitance, user should connect
EMI/decoupling cap (CREGP) at each VDD_LV/VSS_LV pin pair.

3.8.1.1 Recommendations
 The external NPN driver must be BCP68 type.
 VDD_LV should be implemented as a power plane from the emitter of the ballast
transistor.
 10 F capacitors should be connected to the 4 pins closest to the outside of the
package and should be evenly distributed around the package. For BGA packages, the
balls should be used are D8, H14, R9, J3–one cap on each side of package.
– There should be a track direct from the capacitor to this pin (pin also connects to
VDD_LV plane). The tracks ESR should be less than 100 m.
– The remaining VDD_LV pins (exact number will vary with package) should be
decoupled with 0.1 F caps, connected to the pin as per 10 F.
(see Section 3.4: Recommended operating conditions).

3.8.2 VDD_BV options

 Option 1: VDD_BV shared with VDD_HV_A
VDD_BV must be star routed from VDD_HV_A from the common source. This is to
eliminate ballast noise injection on the MCU.
 Option 2: VDD_BV independent of the MCU supply
VDD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence
the external component must meet the 2.6 V criteria through external monitoring if
required.

Table 23. Voltage regulator electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S External ballast stability

CREGn — — 40 — 60 F
R capacitance
S Stability capacitor equivalent
RREG — — — — 0.2 W
R serial resistance
VDD_HV_A/HV_B/VSS_HV
S Decoupling capacitance (Close to pair 100 — nF
CREGP —
R the pin)
VDD_LV/VSS_LV pair 100 — nF
Stability capacitance regulator
S
CDEC2 — supply (Close to the ballast VDD_BV/VSS_HV 10 — 40 F
R
collector)

C After trimming
VMREG P Main regulator output voltage 1.20 1.28 1.32 V
C TA = 25 °C

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Table 23. Voltage regulator electrical characteristics (continued)

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S Main regulator current provided to

IMREG — — — — 350 mA
R VDD_LV domain

C Main regulator module current IMREG = 200 mA — — 2

IMREGINT D mA
C consumption IMREG = 0 mA — — 1

C Low power regulator output After trimming

VLPREG P 1.17 1.27 1.32 V
C voltage TA = 25 °C
S Low power regulator current
ILPREG — — — — 50 mA
R provided to VDD_LV domain
ILPREG = 15 mA;
D — — 600
C Low power regulator module TA = 55 °C
ILPREGINT A
C current consumption ILPREG = 0 mA;
— — 20 —
TA = 55 °C
Main LVDs and reference current
C
IVREGREF D consumption (low power and main TA = 55 °C — 2 — A
C
regulator switched off)
C Main LVD current consumption
IVREDLVD12 D TA = 55 °C — 1 — A
C (switch-off during standby)
C In-rush current on VDD_BV during 600
IDD_HV_A D — — — (3) mA
C power-up
1. VDD_HV_A = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Inrush current is seen more like steps of 600 mA peak. The startup of the regulator happens in steps of 50 mV in ~25 steps
to reach ~1.2 V VDD_LV. Each step peak current is within 600 mA

3.8.3 Voltage monitor electrical characteristics

The device implements a Power-on Reset module to ensure correct power-up initialization,
as well as four low voltage detectors to monitor the VDD_HV_A and the VDD_LV voltage while
device is supplied:
 POR monitors VDD_HV_A during the power-up phase to ensure device is maintained in
a safe reset state
 LVDHV3 monitors VDD_HV_A to ensure device is reset below minimum functional
supply
 LVDHV5 monitors VDD_HV_A when application uses device in the 5.0 V±10 % range
 LVDLVCOR monitors power domain No. 1 (PD1)
 LVDLVBKP monitors power domain No. 0 (PD0). VDD_LV is same as PD0 supply.
Note: When enabled, PD2 (RAM retention) is monitored through LVD_DIGBKP.

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Figure 9. Low voltage monitor vs. Reset

VDDHV/LV

VLVDHVxH/LVxH
VLVDHVxL/LVxL

RESET

Table 24. Low voltage monitor electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S
VPORUP P Supply for functional POR module — 1.0 — 5.5
R
C
VPORH P Power-on reset threshold — 1.5 — 2.6
C
C
VLVDHV3H T LVDHV3 low voltage detector high threshold — 2.7 — 2.85
C
C
VLVDHV3L T LVDHV3 low voltage detector low threshold — 2.6 — 2.74
C
V
C
VLVDHV5H T LVDHV5 low voltage detector high threshold — 4.3 — 4.5
C
C
VLVDHV5L T LVDHV5 low voltage detector low threshold — 4.2 — 4.4
C
C
VLVDLVCORL P LVDLVCOR low voltage detector low threshold 1.08 — 1.17
C TA = 25 °C,
C after trimming
VLVDLVBKPL P LVDLVBKP low voltage detector low threshold 1.08 — 1.17
C
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.

3.9 Low voltage domain power consumption

Table 25 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.

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Table 25. Low voltage power domain electrical characteristics(1)

Value
Symbol C Parameter Conditions(2) Unit
Min Typ(3) Max(4)

C RUN mode maximum 300(6),

IDDMAX(5) D — — 210 (7) mA
C average current
P at 120 MHz TA = 25 °C — 150 208(9) mA
C RUN mode typical (8) (10)
IDDRUN D at 80 MHz TA = 25 °C — 110 150 mA
C average current(8)
C at 120 MHz TA = 125 °C — 180 280 mA

C P at 120 MHz TA = 25 °C — 20 27 mA
IDDHALT HALT mode current(11)
C C at 120 MHz TA = 125 °C — 35 100 mA

C P TA = 25 °C — 0.4 5 mA
IDDSTOP STOP mode current(12) No clocks active
C C TA = 125 °C — 16 72 mA
IDDSTDBY3 P TA = 25 °C — 50 96 µA
(96 KB C STANDBY3 mode
No clocks active
RAM C C current(13) TA = 125 °C — 630 2400 µA
retained)
IDDSTDBY2 C TA = 25 °C — 40 92 µA
(64 KB C STANDBY2 mode
No clocks active
RAM C C current(14) TA = 125 °C — 500 2000 µA
retained)
IDDSTDBY1 C TA = 25 °C — 25 85 µA
C STANDBY1 mode
(8 KB RAM No clocks active
C C current(15) TA = 125 °C — 230 1100 µA
retained)
32 KHz OSC — TA = 25 °C — — 5 µA

Adders in C 4–40 MHz OSC — TA = 25 °C — — 3 mA

T
LP mode C 16 MHz IRC — TA = 25 °C — — 500 µA
128 KHz IRC — TA = 25 °C — — 5 µA
1. Except for IDDMAX, all the current values are total current drawn from VDD_HV_A.
2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified All temperatures are based on an
ambient temperature.
3. Target typical current consumption for the following typical operating conditions and configuration. Process = typical,
Voltage = 1.2 V.
4. Target maximum current consumption for mode observed under typical operating conditions. Process = Fast, Voltage =
1.32 V.
5. Running consumption is given on voltage regulator supply (VDDREG). It does not include consumption linked to I/Os
toggling. This value is highly dependent on the application. The given value is thought to be a worst case value with all
cores and peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be
noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce
peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when possible.
6. Higher current may sunk by device during power-up and standby exit. Please refer to in rush current in Table 23.
7. Maximum “allowed” current is package dependent.
8. Only for the “P” classification: Code fetched from RAM: Serial IPs CAN and LIN in loop back mode, DSPI as Master, PLL as
system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at max frequency, periodic SW/WDG timer
reset enabled. RUN current measured with typical application with accesses on both code flash and RAM.

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9. Subject to change, Configuration: 1 e200z4d + 4 kbit/s Cache, 1 e200z0h (1/2 system frequency), CSE, 1 eDMA
(10 ch.), 6 FlexCAN (4 500 kbit/s, 2 125 kbit/s), 4 LINFlexD (20 kbit/s), 6 DSPI (2 2 Mbit/s, 3 4 Mbit/s,
1 10 Mbit/s), 16 Timed I/O, 16 ADC Input, 1 FlexRay (2 ch., 10 Mbit/s), 1 FEC (100 Mbit/s), 1 RTC, 4PIT
channels, 1 SWT, 1 STM. For lower pin count packages reduce the amount of timed I/O’s and ADC channels. RUN
current measured with typical application with accesses on both code flash and RAM.
10. This value is obtained from limited sample set.
11. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz ON. 16 MHz XTAL clock. FlexCAN:
instances: 0, 1, 2 ON (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1, 2
ON (clocked but no reception or transmission), instance: 3-9 clocks gated. eMIOS: instance: 0 ON (16 channels on PA[0]-
PA[11] and PC[12]-PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no communication,
instance: 1-7 clocks gated). RTC/API ON. PIT ON. STM ON. ADC ON but no conversion except 2 analog watchdogs.
12. Only for the “P” classification: No clock, FIRC 16 MHz OFF, SIRC128 kHz ON, PLL OFF, HPvreg OFF, LPVreg ON. All
possible peripherals off and clock gated. Flash in power down mode.
13. Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device configured for minimum consumption, all
possible modules switched-off. Measurement condition assumes Tj = Ta.
14. LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured for minimum consumption, all possible modules switched-off.
Measurement condition assumes Tj = Ta.
15. LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for minimum consumption, all possible modules switched OFF.
Measurement condition assumes Tj = Ta.

3.10 Flash memory electrical characteristics

3.10.1 Program/Erase characteristics

Table 26 shows the code flash memory program and erase characteristics.

Table 26. Code flash memory—Program and erase specifications

Value
Symbol C Parameter Unit
Initial
Min Typ(1) Max(3)
max(2)

Tdwprogram Double word (64 bits) program time(4) — 18 50 500 µs

T16Kpperase 16 KB block pre-program and erase time — 200 500 5000 ms
C
T32Kpperase 32 KB block pre-program and erase time — 300 600 5000 ms
T128Kpperase C 128 KB block pre-program and erase time — 600 1300 5000 ms
Teslat C D Erase Suspend Latency — — 30 30 µs
tESRT(5) C Erase Suspend Request Rate 20 — — — ms
tPABT D Program Abort Latency — — 10 10 µs
tEAPT D Erase Abort Latency — — 30 30 µs
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. It is Time between erase suspend resume and the next erase suspend request.

Table 27 shows the data flash memory program and erase characteristics.

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Table 27. Data flash memory—Program and erase specifications

Value
Symbol C Parameter Unit
Initial
Min Typ(1) Max(3)
max(2)

Twprogram Word (32 bits) program time(4) — 30 70 500 µs

T16Kpperase C 16 KB block pre-program and erase time — 700 800 5000 ms
Teslat C D Erase Suspend Latency — — 30 30 µs
tESRT(5) C C Erase Suspend Request Rate 10 — — — ms
tPABT D Program Abort Latency — — 12 12 µs
tEAPT D Erase Abort Latency — — 30 30 µs
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. It is time between erase suspend resume and next erase suspend.

Table 28. Flash memory module life

Value
Symbol C Parameter Conditions Unit
Min Typ

Number of program/erase cycles

per block for 16 Kbyte blocks over
— 100000 100000 cycles
the operating temperature range
(TJ)
Number of program/erase cycles
per block for 32 Kbyte blocks over
P/E CC C — 10000 100000 cycles
the operating temperature range
(TJ)
Number of program/erase cycles
per block for 128 Kbyte blocks over
— 1000 100000 cycles
the operating temperature range
(TJ)
Blocks with 0–1000 P/E
20 — years
cycles
Minimum data retention at 85 °C Blocks with 10000 P/E
Retention CC C 10 — years
average ambient temperature(1) cycles
Blocks with 100000 P/E
5 — years
cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.

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ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.

Table 29. Flash memory read access timing(1)

Conditions(2)
Frequency
Symbol C Parameter Unit
Code flash Data flash range
memory memory

P 5 wait states 13 wait states 120 —100

C 4 wait states 11 wait states 100—80
D Maximum frequency for Flash 3 wait states 9 wait states 80—64
fREAD CC MHz
C reading 2 wait states 7 wait states 64—40
C 1 wait states 4 wait states 40—20
C 0 wait states 2 wait states 20—0
1. Max speed is the maximum speed allowed including PLL frequency modulation (FM).
2. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.

3.10.2 Flash memory power supply DC characteristics

Table 30 shows the flash memory power supply DC characteristics on external supply.

Table 30. Flash memory power supply DC electrical characteristics

Value(2)
Symbol Parameter Conditions(1) Unit
Min Typ Max

Code flash
ICFREAD(3) Flash memory module 33
C Sum of the current consumption memory
read mA
C on VDD_HV_A on read access
IDFREAD (3) fCPU = 120 MHz  2%(4) Data flash
13
memory

Program/Erase on-going Code flash

ICFMOD(3) 52
C Sum of the current consumption while reading flash memory
mA
C on VDD_HV_A (program/erase) memory registers Data flash
IDFMOD(3) fCPU = 120 MHz  2% (4) 13
memory
Sum of the current consumption
C Code flash
ICFLPW(3) on VDD_HV_A during flash 1.1 mA
C memory
memory low power mode
Code flash
ICFPWD(3) Sum of the current consumption 150
C memory
on VDD_HV_A during flash µA
C Data flash
IDFPWD(3) memory power down mode 150
memory
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = –40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Data based on characterization results, not tested in production.
4. fCPU 120 MHz  2 % can be achieved over full temperature 125 °C ambient, 150 °C junction temperature.

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3.10.3 Flash memory start-up/switch-off timings

Table 31. Start-up time/Switch-off time

Value
Conditions
Symbol C Parameter (1) Unit
Min Typ Max

Code
flash — —
C Delay for flash memory module to exit memory
TFLARSTEXIT D — 125
C reset mode
Data flash
— —
memory
Code
C Delay for flash memory module to exit
TFLALPEXIT T flash — — — 0.5
C low-power mode
memory
µs
Code
flash — —
C Delay for flash memory module to exit memory
TFLAPDEXIT T — 30
C power-down mode
Data flash
— —
memory
Code
TFLALPENTR C Delay for flash memory module to
T flash — — — 0.5
Y C enter low-power mode
memory
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.

3.11 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

3.11.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user apply EMC software optimization and pre-
qualification tests in relation with the EMC level requested for the application.
 Software recommendations The software flowchart must include the management of
runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical data corruption (control registers)
 Pre-qualification trials Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).

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3.11.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI
measurements.

Table 32. EMI radiated emission measurement(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

S
— — Scan range — 0.150 1000 MHz
R
S Operating
fCPU — — — 120 — MHz
R frequency
S LV operating
VDD_LV — — — 1.28 — V
R voltages

VDD = 5 V, TA = 25 °C, No PLL

LQFP176 package frequency — — 18 dBµV
C Test conforming to IEC modulation
SEMI T Peak level
C 61967-2, ± 2% PLL
fOSC = 40 MHz/fCPU = 120 frequency — — 14(3) dBµV
MHz modulation
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.
3. All values need to be confirmed during device validation.

3.11.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.

3.11.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts (n+1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).

Table 33. ESD absolute maximum ratings(1)(2)

Symbol Ratings Conditions Class Max value(3) Unit

Electrostatic discharge voltage TA = 25 °C

VESD(HBM) H1C 2000
(Human Body Model) conforming to AEC-Q100-002
Electrostatic discharge voltage TA = 25 °C
VESD(MM) M2 200
(Machine Model) conforming to AEC-Q100-003 V
500
Electrostatic discharge voltage TA = 25 °C
VESD(CDM) C3A 750
(Charged Device Model) conforming to AEC-Q100-011
(corners)

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1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.

3.11.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up
performance:
 A supply over-voltage is applied to each power supply pin.
 A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 34. Latch-up results

Symbol Parameter Conditions Class

TA = 125 °C
LU Static latch-up class II level A
conforming to JESD 78

3.12 Fast external crystal oscillator (4–40 MHz) electrical

characteristics
The device provides an oscillator/resonator driver. Figure 10 describes a simple model of
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 35 provides the parameter description of 4 MHz to 40 MHz crystals used for the
design simulations.

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Figure 10. Crystal oscillator and resonator connection scheme

EXTAL
C1

XTAL

Crystal
XTAL
RD
C2
DEVICE
VDD
I

EXTAL
EXTAL
DEVICE

Resonator
XTAL

DEVICE

Note: XTAL/EXTAL must not be directly used to drive external circuits.

Table 35. Crystal description

Shunt
Crystal
Crystal Crystal Load on capacitance
Nominal equivalent
NDK crystal motional motional xtalin/xtalout between
frequency series
reference capacitance inductance C1 = C2 xtalout
(MHz) resistance
(Cm) fF (Lm) mH (pF)(1) and xtalin
ESR 
C0(2) (pF)

4 NX8045GB 300 2.68 591.0 21 2.93

8 300 2.46 160.7 17 3.01
10 150 2.93 86.6 15 2.91
12 NX5032GA 120 3.11 56.5 15 2.93
16 120 3.90 25.3 10 3.00
40 NX5032GA 50 6.18 2.56 8 3.49
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).

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Figure 11. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics

S_MTRANS bit (ME_GS register)

VXTAL
1/fMXOSC

VFXOSC
90%

VFXOSCOP

10%

TMXOSCSU valid internal clock

Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Fast external
fFXOSC SR — crystal oscillator — 4.0 — 40.0 MHz
frequency
Fast external VDD = 3.3 V ± 10% 4(3) — 20(3)
gmFXOSC CC C crystal oscillator mA/V
transconductance VDD = 5.0 V ± 10% 6.5(3) — 25(3)

Oscillation fOSC = 40 MHz

VFXOSC CC T amplitude at For both VDD = 3.3 V ± — 0.95 — V
EXTAL 10%, VDD = 5.0 V ± 10%
Oscillation
VFXOSCOP CC P — — 1.8 V
operating point
VDD = 3.3 V ± 10%,
— 2 2.2
fOSC = 40 MHz
VDD = 5.0 V ± 10%,
Fast external — 2.3 2.5
fOSC = 40 MHz
IFXOSC(4) CC T crystal oscillator mA
consumption VDD = 3.3 V ± 10%,
— 1.3 1.5
fOSC = 16 MHz
VDD = 5.0 V ± 10%,
— 1.6 1.8
fOSC = 16 MHz
Fast external fOSC = 40 MHz
TFXOSCSU CC T crystal oscillator For both VDD = 3.3 V ± — — 5 ms
start-up time 10%, VDD = 5.0 V ± 10%

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Table 36. Fast external crystal oscillator (4 to 40 MHz) electrical characteristics (continued)
Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input high level

0.65VDD_
VIH SR P CMOS Oscillator bypass mode — VDD_HV_A + 0.4 V
(Schmitt Trigger) HV_A

Input low level

VIL SR P CMOS Oscillator bypass mode 0.3 — 0.35VDD_HV_A V
(Schmitt Trigger)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Based on ATE Cz
4. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals).

3.13 Slow external crystal oscillator (32 kHz) electrical

characteristics
The device provides a low power oscillator/resonator driver.

Figure 12. Crystal oscillator and resonator connection scheme

OSC32K_EXTAL OSC32K_EXTAL

C1
Resonator
Crystal

RP

OSC32K_XTAL OSC32K_XTAL

DEVICE C2 DEVICE

Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.

l

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Figure 13. Equivalent circuit of a quartz crystal

C0

Crystal Cm Rm Lm
C1 C2
C1 C2

Table 37. Crystal motional characteristics(1)

Value
Symbol Parameter Conditions Unit
Min Typ Max

Lm Motional inductance — — 11.796 — KH

Cm Motional capacitance — — 2 — fF
Load capacitance at OSC32K_XTAL
C1/C2 and OSC32K_EXTAL with respect to — 18 — 28 pF
ground(2)
AC coupled @ C0 = 2.85 pF(4) — — 65
AC coupled @ C0 = 4.9 pF(4) — — 50
Rm(3) Motional resistance kW
AC coupled @ C0 = 7.0 pF(4) — — 35
AC coupled @ C0 = 9.0 pF(4) — — 30
1. The crystal used is Epson Toyocom MC306.
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (Rm) of the crystal is 50 k
4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.

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Figure 14. Slow external crystal oscillator (32 kHz) electrical characteristics

OSCON bit (OSC_CTL register)

VOSC32K_XTAL 1/fLPXOSC32K

VLPXOSC32K
90%

10%

TLPXOSC32KSU valid internal clock

Table 38. Slow external crystal oscillator (32 kHz) electrical characteristics
Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S Slow external crystal oscillator 32.76

fSXOSC — — 32 40 kHz
R frequency 8

C Slow external crystal oscillator VDD = 3.3 V ± 10%, 13(3) — 33(3)

gmSXOSC — µA/V
C transconductance VDD = 5.0 V ± 10% 15(3) — 35(3)
C
VSXOSC T Oscillation amplitude — 1.2 1.4 1.7 V
C
C
ISXOSCBIAS T Oscillation bias current — 1.2 — 4.4 µA
C
C Slow external crystal oscillator
ISXOSC T — — — 7 µA
C consumption
C Slow external crystal oscillator
TSXOSCSU T — — — 2(4) s
C start-up time
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. Based on ATE CZ
4. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

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3.14 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.

Table 39. FMPLL electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

S
fPLLIN — FMPLL reference clock(3) — 4 — 64 MHz
R
S FMPLL reference clock
PLLIN — — 40 — 60 %
R duty cycle(3)
C FMPLL output clock
fPLLOUT P — 16 — 120 MHz
C frequency
S
fCPU — System clock frequency — — — 120 + 2%(4) MHz
R
C
fFREE P Free-running frequency — 20 — 150 MHz
C
C
tLOCK P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 µs
C
C fPLLIN = 40 MHz (resonator), 6
tLTJIT — FMPLL long term jitter — — ns
C fPLLCLK @ 120 MHz, 4000 cycles (for < 1ppm)
C
IPLL C FMPLL consumption TA = 25 °C — — 3 mA
C
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. PLLIN clock retrieved directly from 4-40 MHz XOSC or 16 MIRC. Input characteristics are granted when oscillator is used
in functional mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
4. fCPU 120 + 2% MHz can be achieved at 125 °C.

3.15 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz main internal RC oscillator. This is used as the default clock
at the power-up of the device and can also be used as input to PLL.

Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

C
P TA = 25 °C, trimmed — 16 —
C Fast internal RC oscillator high
fFIRC MHz
S frequency
— — 12 20
R

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Table 40. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Fast internal RC oscillator high

C
IFIRCRUN(3) T frequency current in running TA = 25 °C, trimmed — — 200 µA
C
mode
D TA = 25 °C — — 100 nA
Fast internal RC oscillator high
C
IFIRCPWD D frequency current in power TA = 55 °C — — 200 nA
C
down mode
D TA = 125 °C — — 1 µA
sysclk = off — 500 —
sysclk = 2 MHz — 600 —
Fast internal RC oscillator high
C
IFIRCSTOP T frequency and system clock TA = 25 °C sysclk = 4 MHz — 700 — µA
C
current in stop mode
sysclk = 8 MHz — 900 —
sysclk = 16 MHz — 1250 —
VDD = 5.0 V ±
C — — 2.0
10%
TA = 55 °C
VDD = 3.3 V ±
— — — 5
C Fast internal RC oscillator 10%
TFIRCSU µs
C start-up time VDD = 5.0 V ±
— — — 2.0
TA = 10%
125 °C VDD = 3.3 V ±
— — — 5
10%
Fast internal RC oscillator
C
FIRCPRE C precision after software TA = 25 °C 1 — +1 %
C
trimming of fFIRC
C Fast internal RC oscillator
FIRCTRIM C TA = 25 °C — 1.6 %
C trimming step
Fast internal RC oscillator
variation over temperature and
C
FIRCVAR C supply with respect to fFIRC at — 5 — +5 %
C
TA = 25 °C in high-frequency
configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

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3.16 Slow internal RC oscillator (128 kHz) electrical

characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the
reference clock for the RTC module.

Table 41. Slow internal RC oscillator (128 kHz) electrical characteristics

Value(2)
(1)
Symbol C Parameter Conditions Unit
Min Typ Max

C
P TA = 25 °C, trimmed — 128 —
C Slow internal RC oscillator low
fSIRC kHz
S frequency untrimmed, across
— 84 — 205
R temperatures
C Slow internal RC oscillator low
ISIRC(3) C TA = 25 °C, trimmed — — 5 µA
C frequency current
C Slow internal RC oscillator start-
TSIRCSU P TA = 25 °C, VDD = 5.0 V ± 10% — 8 12 µs
C up time
Slow internal RC oscillator
C
SIRCPRE C precision after software trimming TA = 25 °C 2 — +2
C
of fSIRC %
C Slow internal RC oscillator
SIRCTRIM C — — 2.7 —
C trimming step
Variation in fSIRC across
C
SIRCVAR C temperature and fluctuation in — 10 — +10 %
C
supply voltage, post trimming
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. All values need to be confirmed during device validation.
3. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

3.17 ADC electrical characteristics

3.17.1 Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital
converters (10-bit and 12-bit).
Note: Due to ADC limitations, the two ADCs cannot sample a shared channel at the same time
i.e., their sampling windows cannot overlap if a shared channel is selected. If this is done,
neither of the ADCs can guarantee their conversion accuracies.

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Figure 15. ADC_0 characteristic and error definitions

Offset Error OSE Gain Error GE

1023

1022

1021

1020

1019
1 LSB ideal = VDD_ADC / 1024
1018

(2)

code out
7
(1)
6

(1) Example of an actual transfer curve

5
(5) (2) The ideal transfer curve
4 (3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)
Offset Error OSE

3.17.1.1 Input impedance and ADC accuracy

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device, can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source. A real filter, can typically be obtained by using a series resistance
with a capacitor on the input pin (simple RC Filter). The RC filtering may be limited
according to the value of source impedance of the transducer or circuit supplying the analog
signal to be measured. The filter at the input pins must be designed taking into account the
dynamic characteristics of the input signal (bandwidth) and the equivalent input impedance
of the ADC itself.

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In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a
frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to
ground. For instance, assuming a conversion rate of 1MHz, with CS+Cp2 equal to 3pF, a
resistance of 330K is obtained (Reqiv = 1 / (fc*(CS+Cp2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF,
the external circuit must be designed to respect the following relation

Equation 4
RS + RF
1
V A  ---------------------  --- LSB
R EQ 2

The formula above provides a constraint for external network design, in particular on
resistive path.

Figure 16. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection
Source Filter Current Limiter

RS RF RL RSW RAD

VA CF CP1 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance

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Figure 17. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel Extended
Sampling
Selection Switch
Source Filter Current Limiter

RS RF RL RSW1 RSW2 RAD

VA CF CP1 CP3 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
RADSampling Switch Impedance
CP Pin Capacitance (three contributions, CP1, CP2 and CP3)
CS Sampling Capacitance

A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 16): when the sampling phase is started (A/D switch
close), a charge sharing phenomena is installed.

Figure 18. Transient behavior during sampling phase

VCS Voltage Transient on CS

VA
VA2 V <0.5 LSB
1 2
1 < (RSW + RAD) CS << TS

VA1 2 = RL (CS + CP1 + CP2)

TS t

In particular two different transient periods can be distinguished:

 A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is

Equation 5
CP  CS
 1 =  R SW + R AD   ---------------------
CP + CS

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This relation can again be simplified considering CS as an additional worst condition. In

reality, transient is faster, but the A/D converter circuitry has been designed to be robust
also in very worst case: the sampling time Ts is always much longer than the internal time
constant.

Equation 6
 1   R SW + R AD   C S « T S

The charge of CP1 and CP2 is redistributed on CS,determining a new value of the voltage
VA1 on the capacitance according to the following equation

Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 

A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2 and
CS were in parallel to CP1 (since the time constant in reality would be faster), the time
constant is:

Equation 8
 2  R L   C S + C P1 + C P2 

In this case, the time constant depends on the external circuit: in particular imposing that the
transient is completed well before the end of sampling time TS, a constraints on RL sizing is
obtained:

Equation 9
8.5  
2 = 8.5  R L   C S + C P1 + C P2   TS
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF definitively
bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer
transient) will be much higher than VA1. The following equation must be respected (charge
balance assuming now CS already charged at VA1):

Equation 10
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 

The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing

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Figure 19. Spectral representation of input signal

Analog Source Bandwidth (VA)

TC 2 RFCF (Conversion Rate vs. Filter Pole)

Noise fF  f0 (Anti-aliasing Filtering Condition)

2 f0 fC (Nyquist)

f0 f
Anti-Aliasing Filter (fF = RC Filter pole) Sampled Signal Spectrum (fC = conversion Rate)

fF f f0 fC f

Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be
at least 2f0; it means that the constant time of the filter is greater than or at least equal to
twice the conversion period (TC). Again the conversion period TC is longer than the
sampling time TS, which is just a portion of it, even when fixed channel continuous
conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it
is evident that the time constant of the filter RFCF is definitively much higher than the
sampling time TS, so the charge level on CS cannot be modified by the analog signal source
during the time in which the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:

Equation 11
V A2 C P1 + C P2 + C F
------------ = --------------------------------------------------------
VA C P1 + C P2 + C F + C S

From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:

Equation 12 ADC_0 (10-bit)

C F  2048  C S

Equation 13 ADC_1 (12-bit)

C F  8192  C S

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3.17.1.2 ADC electrical characteristics

Table 42. ADC input leakage current

Value
Symbol C Parameter Conditions Unit
Min Typ Max

C TA = 40 °C — 1 —
C TA = 25 °C — 1 —
ILKG CC Input leakage current No current injection on adjacent pin nA
C TA = 105 °C — 8 200
P TA = 125 °C — 45 400

Table 43. ADC conversion characteristics (10-bit ADC_0)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Voltage on
VSS_HV_ADC0
S
VSS_ADC0 — (ADC_0 reference) — 0.1 — 0.1 V
R
pin with respect to
ground (VSS_HV)(2)
Voltage on
VDD_HV_ADC0 pin
S
VDD_ADC0 — (ADC_0 reference) — VDD_HV_A 0.1 — VDD_HV_A + 0.1 V
R
with respect to
ground (VSS_HV)
S Analog input
VAINx — — VSS_ADC0 0.1 — VDD_ADC0 + 0.1 V
R voltage(3)
S ADC_0 analog
fADC0 — — 6 — 32 + 2% MHz
R frequency
S ADC_0 power up
tADC0_PU — — — — 1.5 µs
R delay
C
tADC0_S T Sample time(4) fADC = 32 MHz 500 — ns
C

C fADC = 32 MHz 0.625 —

tADC0_C P Conversion time(5),(6) µs
C fADC = 30 MHz 0.700 —
C ADC_0 input
CS D — — — 3 pF
C sampling capacitance
C ADC_0 input pin
CP1 D — — — 3 pF
C capacitance 1
C ADC_0 input pin
CP2 D — — — 1 pF
C capacitance 2
C ADC_0 input pin
CP3 D — — — 1 pF
C capacitance 3
C Internal resistance of
RSW1 D — — — 3 k
C analog source

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Table 43. ADC conversion characteristics (10-bit ADC_0) (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

C Internal resistance of
RSW2 D — — — 2 k
C analog source
C Internal resistance of
RAD D — — — 2 k
C analog source
Current VDD = 
5 — 5
injectio 3.3 V ± 10%
n on
one
ADC_0
S
IINJ(7) — Input current Injection input, mA
R VDD = 
differen 5 — 5
t from 5.0 V ± 10%
the
convert
ed one
C Absolute value for
| INL | T No overload — 0.5 1.5 LSB
C integral non-linearity
C Absolute differential
| DNL | T No overload — 0.5 1.0 LSB
C non-linearity
C
| OFS | T Absolute offset error — — 0.5 — LSB
C
C
| GNE | T Absolute gain error — — 0.6 — LSB
C
Total unadjusted Without current
P 2 0.6 2
C error(8) for precise injection
TUEP LSB
C channels, input only
T pins With current injection 3 3

Without current
C T Total unadjusted 3 1 3
TUEX error(8) for extended injection LSB
C
T channel With current injection 4 4
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of
the sample time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC0_S depend on programming.
5. This parameter does not include the sample time tADC0_S, but only the time for determining the digital result and the time to
load the result's register with the conversion result.
6. Refer to ADC conversion table for detailed calculations.
7. PB10 should not have any current injected. It can disturb accuracy on other ADC_0 pins.
8. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.

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Figure 20. ADC_1 characteristic and error definitions

Offset Error OSE Gain Error GE

4095

4094

4093

4092

4091
1 LSB ideal = AVDD / 4096
4090

(2)

code out
7
(1)
6

(1) Example of an actual transfer curve

5
(5) (2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
4
(4) Integral non-linearity error (INL)
(4)
(5) Center of a step of the actual transfer curve
3

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
Offset Error OSE

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Table 44. Conversion characteristics (12-bit ADC_1)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Voltage on
VSS_HV_ADC1
(ADC_1
VSS_ADC1 SR — reference) pin — 0.1 0.1 V
with respect to
ground
(VSS_HV)(2)
Voltage on
VDD_HV_ADC1
VDD_ADC1 pin (ADC_1 VDD_HV_A 
SR — — VDD_HV_A + 0.1 V
3
reference) with 0.1
respect to
ground (VSS_HV)
VAINx(3), Analog input VSS_ADC1 
SR — — VDD_ADC1 + 0.1 V
(4)
voltage(5) 0.1
ADC_1 analog
fADC1 SR — — 8 + 2% 32 + 2% MHz
frequency
ADC_1 power up
tADC1_PU SR — — 1.5 µs
delay
Sample time(6)
— 440
VDD=5.0 V
tADC1_S CC T ns
Sample time(6)
— 530
VDD=3.3 V
Conversion
time(7), (8) fADC1 = 32 MHz 2
VDD=5.0 V
Conversion
time(7), (6) fADC 1= 30 MHz 2.1
VDD =5.0 V
tADC1_C CC P µs
Conversion
time(7), (6) fADC 1= 20 MHz 3
VDD=3.3 V
Conversion
time(7), (6) fADC1 = 15 MHz 3.01
VDD =3.3 V
ADC_1 input
CS CC D sampling — 5 pF
capacitance
ADC_1 input pin
CP1 CC D — 3 pF
capacitance 1
ADC_1 input pin
CP2 CC D — 1 pF
capacitance 2

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Table 44. Conversion characteristics (12-bit ADC_1) (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

ADC_1 input pin

CP3 CC D — 1.5 pF
capacitance 3
Internal
RSW1 CC D resistance of — 1 k
analog source
Internal
RSW2 CC D resistance of — 2 k
analog source
Internal
RAD CC D resistance of — 0.3 k
analog source
Current VDD =
injection 3.3 V ± 5 — 5
on one 10%
ADC_1
Input current
IINJ SR — input, mA
Injection VDD =
different
from the 5.0 V ± 5 — 5
converte 10%
d one
Absolute Integral
INLP CC T non-linearity- No overload 1 3 LSB
Precise channels
Absolute Integral
non-linearity-
INLS CC T No overload 1.5 5 LSB
Standard
channels
Absolute
DNL CC T Differential non- No overload 0.5 1 LSB
linearity
Absolute Offset
OFS CC T — 2 LSB
error
Absolute Gain
GNE CC T — 2 LSB
error
Without current
P Total Unadjusted 6 6 LSB
Error for precise injection
(9)
TUEP CC
channels, input With current
T only pins 8 8 LSB
injection
Without current
T Total Unadjusted injection 10 10 LSB
TUES(9) CC Error for
T standard channel With current 12 12 LSB
injection
1. VDD = 3.3 V ± 10 % / 5.0 V ± 10 %, TA = 40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS_HV must be common (to be tied together externally).

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3. PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be
within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
4. VDD_HV_ADC1 can operate at 5V condition while VDD_HV_B can operate at 3.3V provided that ADC_1 channels coming
from VDD_HV_B domain are limited in max swing as VDD_HV_B.
5. VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
6. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of
the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sample clock tADC1_S depend on programming.
7. Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
8. Refer to ADC conversion table for detailed calculations.
9. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.

3.18 Fast Ethernet Controller

MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are
not TTL compatible. They follow the CMOS electrical characteristics.

3.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the system clock frequency must
exceed four times the RX_CLK frequency in 2:1 mode and two times the RX_CLK
frequency in 1:1 mode.

Table 45. MII Receive Signal Timing

Spec Characteristic Min Max Unit

RXD[3:0], RX_DV,
M1 RX_ER to RX_CLK 5 — ns
setup
RX_CLK to RXD[3:0],
M2 5 — ns
RX_DV, RX_ER hold
RX_CLK pulse width
M3 35% 65% RX_CLK period
high
M4 RX_CLK pulse width low 35% 65% RX_CLK period

Figure 21. MII receive signal timing diagram

M3

RX_CLK (input)

M4
RXD[3:0] (inputs)
RX_DV
RX_ER
M1 M2

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3.18.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. In addition, the system clock frequency must
exceed four times the TX_CLK frequency in 2:1 mode and two times the TX_CLK frequency
in 1:1 mode.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Fast Ethernet Controller (FEC) chapter of the SPC564B74 and SPC56EC74
Reference Manual for details of this option and how to enable it.

Table 46. MII transmit signal timing(1)

Spec Characteristic Min Max Unit

TX_CLK to TXD[3:0],
M5 5 — ns
TX_EN, TX_ER invalid
TX_CLK to TXD[3:0],
M6 — 25 ns
TX_EN, TX_ER valid
M7 TX_CLK pulse width high 35% 65% TX_CLK period
M8 TX_CLK pulse width low 35% 65% TX_CLK period
1. Output pads configured with SRE = 0b11.

Figure 22. MII transmit signal timing diagram

M7

TX_CLK (input)
M5

M8
TXD[3:0] (outputs)
TX_EN
TX_ER

M6

3.18.3 MII Async Inputs Signal Timing (CRS and COL)

Table 47. MII Async Inputs Signal Timing(1)

Spec Characteristic Min Max Unit

M9 CRS, COL minimum pulse width 1.5 — TX_CLK period

1. Output pads configured with SRE = 0b11.

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Figure 23. MII async inputs timing diagram

CRS, COL

M9

3.18.4 MII Serial Management Channel Timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 48. MII serial management channel timing(1)

Spec Characteristic Min Max Unit

MDC falling edge to MDIO output invalid

M10 0 — ns
(minimum propagation delay)
MDC falling edge to MDIO output valid (max
M11 — 25 ns
prop delay)
M12 MDIO (input) to MDC rising edge setup 28 — ns
M13 MDIO (input) to MDC rising edge hold 0 — ns
M14 MDC pulse width high 40% 60% MDC period
M15 MDC pulse width low 40% 60% MDC period
1. Output pads configured with SRE = 0b11.

Figure 24. MII serial management channel timing diagram

M14 M15

MDC (output)

M10

MDIO (output)

M11

MDIO (input)

M12
M13

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3.19 On-chip peripherals

3.19.1 Current consumption

Table 49. On-chip peripherals current consumption(1)

Value(2)
Symbol C Parameter Conditions Unit
Typ

500 Kbps Total (static + 7.652  fperiph + 84.73

dynamic)
consumption:
FlexCAN in
CAN loop-back
(FlexCAN) mode
IDD_HV_A(CAN) CC D supply XTAL@8 MHz
current on 125 Kbps used as CAN 8.0743  fperiph + 26.757
VDD_HV_A engine clock
source
Message
sending period
is 580 µs
Static consumption:
eMIOS eMIOS channel OFF 28.7  fperiph
supply Global prescaler enabled µA
IDD_HV_A(eMIOS) CC D
current on Dynamic consumption:
VDD_HV_A
It does not change varying the 3
frequency (0.003 mA)

SCI (LINFlex) Total (static + dynamic)

supply consumption:
IDD_HV_A(SCI) CC D 4.7804  fperiph + 30.946
current on LIN mode
VDD_HV_A Baudrate: 20 Kbps
Ballast static consumption (only
1
clocked)
SPI (DSPI)
Ballast dynamic consumption
supply
IDD_HV_A(SPI) CC D (continuous communication):
current on
VDD_HV_A Baudrate: 2 Mbit 16.3  fperiph
Transmission every 8 µs
Frame: 16 bits
Ballast static
VDD = 5.5 V consumption 0.0409  fperiph
ADC supply (no conversion)
IDD_HV_A(ADC) CC D current on Ballast dynamic mA
VDD_HV_A consumption
VDD = 5.5 V 0.0049  fperiph
(continuous
conversion)

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Table 49. On-chip peripherals current consumption(1)

Value(2)
Symbol C Parameter Conditions Unit
Typ

Analog static
consumption 200 µA
ADC_0 (no conversion)
supply Analog
IDD_HV_ADC0 CC D VDD = 5.5 V
current on dynamic
VDD_HV_ADC0 consumption 4 mA
(continuous
conversion)
Analog static
VDD = 5.5 V consumption 300 µA
ADC_1 (no conversion)
supply Analog
IDD_HV_ADC1 CC D
current on dynamic
VDD_HV_ADC1 V = 5.5 V consumption 6 mA
DD
(continuous
conversion)
CFlash +
DFlash
IDD_HV(FLASH) CC D supply VDD = 5.5 V — 13.25
current on
VDD_HV_ADC mA

PLL supply
IDD_HV(PLL) CC D current on VDD = 5.5 V — 0.0031  fperiph
VDD_HV
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 120 MHz.
2. fperiph is in absolute value.

3.19.2 DSPI characteristics

Table 50. DSPI timing

Value
Spec Characteristic Symbol Unit
Min Max

Refer
1 DSPI Cycle Time tSCK — ns
note(1)

—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->0
tCSC — 115 ns

—
Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->1
tASC 15 — ns

2 CS to SCK Delay(2) tCSC 7 — ns

(3)
3 After SCK Delay tASC 15 — ns
4 SCK Duty Cycle tSDC 0.4  tSCK 0.6  tSCK ns

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Table 50. DSPI timing (continued)

Value
Spec Characteristic Symbol Unit
Min Max

Slave Setup Time

— tSUSS 5 — ns
(SS active to SCK setup time)
Slave Hold Time
— tHSS 10 — ns
(SS active to SCK hold time)
Slave Access Time
5 tA — 42 ns
(SS active to SOUT valid)(4)
Slave SOUT Disable Time
6 tDIS — 25 ns
(SS inactive to SOUT High-Z or invalid)
7 CSx to PCSS time tPCSC 0 — ns
8 PCSS to PCSx time tPASC 0 — ns
Data Setup Time for Inputs
Master (MTFE = 0) 36 — ns
9 Slave tSUI 5 — ns
Master (MTFE = 1, CPHA = 0)(5) 36 — ns
Master (MTFE = 1, CPHA = 1) 36 — ns
Data Hold Time for Inputs
Master (MTFE = 0) 0 — ns
10 Slave tHI 4 — ns
Master (MTFE = 1, CPHA = 0)(5) 0 — ns
Master (MTFE = 1, CPHA = 1) 0 — ns
Data Valid (after SCK edge)
Master (MTFE = 0) — 12 ns
11 Slave tSUO — 37 ns
Master (MTFE = 1, CPHA = 0) — 12 ns
Master (MTFE = 1, CPHA = 1) — 12 ns
Data Hold Time for Outputs
Master (MTFE = 0) 0(6) — ns
12 Slave tHO 9.5 — ns
Master (MTFE = 1, CPHA = 0) 0(7) — ns
Master (MTFE = 1, CPHA = 1) 0(8) — ns
1. This value of this parameter is dependent upon the external device delays and the other parameters mentioned in this
table.
2. The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For SPC564B74 and
SPC56EC74, the spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > tCSC.
3. The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For SPC564B74 and
SPC56EC74, the spec value of tASC will be attained only if TDSPI x PASC x ASC > tASC.
4. The parameter value is obtained from tSUSS and tSUO for slave.
5. This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is 2 ns.
7. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is 2 n.
8. For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is 2 ns.

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Figure 25. DSPI classic SPI timing–master, CPHA = 0

2 3

CSx

4 1

SCK Output
(CPOL = 0)
4

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 50.

Figure 26. DSPI classic SPI timing–master, CPHA = 1

CSx

SCK Output
(CPOL = 0)
10

SCK Output
(CPOL = 1)

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 50.

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Figure 27. DSPI classic SPI timing–slave, CPHA = 0

3
2
SS

1
SCK Input 4
(CPOL = 0)

4
SCK Input
(CPOL = 1)

5 11
12 6

SOUT First Data Data Last Data

9
10

SIN First Data Data Last Data

Note: Numbers shown reference Table 50.

Figure 28. DSPI classic SPI timing–slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 50.

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Figure 29. DSPI modified transfer format timing–master, CPHA = 0

3
CSx

4 1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 50.

Figure 30. DSPI modified transfer format timing–master, CPHA = 1

CSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 50.

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Figure 31. DSPI modified transfer format timing–slave, CPHA = 0

3
2
SS

SCK Input
(CPOL = 0)
4 4

SCK Input
(CPOL = 1)
11 12 6
5

SOUT First Data Data Last Data

9 10

SIN First Data Data Last Data

Note: Numbers shown reference Table 50.

Figure 32. DSPI modified transfer format timing–slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 50.

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Figure 33. DSPI PCS strobe (PCSS) timing

7 8

PCSS

CSx

Note: Numbers shown reference Table 50.

3.19.3 Nexus characteristics

Table 51. Nexus debug port timing(1)

Spec Characteristic Symbol Min Max Unit

1 MCKO Cycle Time(2) tMCYC 16.3 — ns

2 MCKO Duty Cycle tMDC 40 60 %
MCKO Low to MDO, MSEO,
3 tMDOV –0.1 0.25 tMCYC
EVTO Data Valid(3)
4 EVTI Pulse Width tEVTIPW 4.0 — tTCYC
5 EVTO Pulse Width tEVTOPW 1 tMCYC
6 TCK Cycle Time(4) tTCYC 40 — ns
7 TCK Duty Cycle tTDC 40 60 %
tNTDIS,
8 TDI, TMS Data Setup Time 8 — ns
tNTMSS
tNTDIH,
9 TDI, TMS Data Hold Time 5 — ns
tNTMSH
10 TCK Low to TDO Data Valid tJOV 0 25 ns
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDDE = 4.0 – 5.5 V, TA = TL to TH, and
CL = 30 pF with SRC = 0b11.
2. MCKO can run up to 1/2 of full system frequency. It can also run at system frequency when it is <60 MHz.
3. MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
4. The system clock frequency needs to be three times faster than the TCK frequency.

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Figure 34. Nexus output timing

MCKO

3
MDO
MSEO Output Data Valid
EVTO

4
EVTI

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Figure 35. Nexus TDI, TMS, TDO timing

TCK

TMS, TDI

10

TDO

3.19.4 JTAG characteristics

Table 52. JTAG characteristics

Value
No. Symbol C Parameter Unit
Min Typ Max

1 tJCYC CC D TCK cycle time 64 — — ns

2 tTDIS CC D TDI setup time 10 — — ns
3 tTDIH CC D TDI hold time 5 — — ns
4 tTMSS CC D TMS setup time 10 — — ns
5 tTMSH CC D TMS hold time 5 — — ns
6 tTDOV CC D TCK low to TDO valid — — 33 ns

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Table 52. JTAG characteristics (continued)

Value
No. Symbol C Parameter Unit
Min Typ Max

7 tTDOI CC D TCK low to TDO invalid 6 — — ns

— tTDC CC D TCK Duty Cycle 40 — 60 %
— tTCKRISE CC D TCK Rise and Fall Times — — 3 ns

Figure 36. Timing diagram - JTAG boundary scan

TCK

2/4 3/5

DATA INPUTS INPUT DATA VALID

DATA OUTPUTS OUTPUT DATA VALID

DATA OUTPUTS

Note: Numbers shown reference Table 52.

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Package characteristics SPC564Bxx-SPC56ECxx

4 Package characteristics

4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

4.2 Package mechanical data

4.2.1 LQFP176 package mechanical drawing

Figure 37. LQFP176 package mechanical drawing

C Seating plane
0.25 mm
A A2 gauge plane

k
A1 c
ccc C
A1
HD L

D
L1

ZD
ZE

132 89

133 88

E HE

176
45

Pin 1 1 44
identification
e 1T_ME

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Table 53. LQFP176 mechanical data(1)

mm inches(2)
Symbol
Min Typ Max Min Typ Max

A 1.400 1.600 0.063

A1 0.050 0.150 0.002
A2 1.350 1.450 0.053 0.057
b 0.170 0.270 0.007 0.011
C 0.090 0.200 0.004 0.008
D 23.900 24.100 0.941 0.949
E 23.900 24.100 0.941 0.949
e 0.500 0.020
HD 25.900 26.100 1.020 1.028
HE 25.900 26.100 1.020 1.028
L(3) 0.450 0.750 0.018 0.030
L1 1.000 0.039
ZD 1.250 0.049
ZE 1.250 0.049
q 0° 7° 0° 7°
Tolerance mm inches
ccc 0.080 0.0031
1. Controlling dimension: millimeter.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. L dimension is measured at gauge plane at 0.25 mm above the seating plane.

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4.2.2 LQFP208 package mechanical drawing

Figure 38. LQFP208 mechanical drawing

Note: Exact shape of each corner is optional.

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Table 54. LQFP208 mechanical data

mm mm
Ref
Min Typ Max Min Typ Max

A 1.6 1.6
A1 0.05 0.15 0.05 0.1 0.15
A2 1.3 1.35 1.45 1.3 1.35 1.45
B 0.17 0.27 0.17 0.22 0.27
c 0.09 0.2 0.11 0.15 0.19
D 30 29.8 30 30.2
D1 28 27.8 28 28.2
D3 25.5 25.5
e 0.5 0.5
E 30 29.8 30 30.2
E1 28 27.8 28 28.2
E3 25.5 25.5
L 0.45 0.6 0.75 0.4 0.5 0.6
L1 1 1
K 0° 3.5 ° 7.0 ° 1° 3° 5°

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4.2.3 LBGA256 package mechanical drawing

Figure 39. LBGA256 mechanical drawing

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Table 55. LBGA256 mechanical data

mm
Ref
Min Typ Max

A 1.210 1.700
A1 0.300
A2 0.300
A4 0.800
b 0.400 0.500 0.600
D 16.800 17.000 17.200
D1 15.000
E 16.800 17.000 17.200
E1 15.000
e 0.900 1.000 1.100
Z 0.750 1.000 1.250
ddd 0.200

Note: The package is designed according to the JEDEC standard No 95-1 Section 14 dedicated to
Ball Grid Array Package Design Guide.

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Ordering information SPC564Bxx-SPC56ECxx

5 Ordering information

Figure 40. Ordering information scheme

Example code:
SPC56 4 C 74 L7 C 8 E 0 Y
Product identifier Core Family Memory Package Temperature CPU Frequency EEPROM Options Conditioning

Y = Tray
X = Tape and Reel


0 = No option
E = Ethernet
C = CSE + Ethernet



0 = NO EEPROM
E = EEPROM



8 = 80 MHz
9 = 120 MHz



B = –40 to 105 °C
C = –40 to 125 °C

L7 = LQFP176
L8 = LQFP208
B3 = LBGA256

74 = 3 MB
70 = 2 MB
64 = 1.5 MB

B = Body
C = Gateway

4 = e200z4d
E = e200z4d + e200
z0h

SPC56 = Power
Architecture in
90 nm

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Appendix A Abbreviations

Table 56 lists abbreviations used but not defined elsewhere in this document.

Table 56. Abbreviations

Abbreviation Meaning

CS Chip select
EVTO Event out
MCKO Message clock out
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format enable
SCK Serial communications clock
SOUT Serial data out
TBD To be defined
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select

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Revision history SPC564Bxx-SPC56ECxx

Revision history

Table 57 summarizes revisions to this document.

Table 57. Revision history

Date Revision Changes

01-Jun-2010 1 Initial Release

– Editing and formatting updates throughout the document.
– Updated Voltage regulator capacitance connection figure.
– Added a new sub-section “VDD_BV Options”
– Program and erase specifications:
Updated Tdwprogram TYP to 22 us
Updated T128Kpperase Max to 5000 ms
Added tESUS parameter
– Added recommendation in the Voltage regulator electrical characteristics
section.
– Added Crystal description table in Fast external crystal oscillator (4 to 140 MHz)
electrical characteristics section and corrected the cross-reference to the same.
– Added new sections - Pad types, System pins and functional ports
– Updated TYP numbers in the Flash program and erase specifications table
– Added a new table: Program and erase specifications (Data Flash)
– Flash read access timing table: Added Data flash memory numbers
– Flash power supply DC electrical characteristics table: Updated IDFREAD and
IDFMOD values for Data flash, Removed IDFLPW parameter
– Updated feature list.
– SPC564Bxx and SPC56ECxx family comparison table: Updated ADC channels
17-Dec-2010 2 and added ADC footnotes.
– SPC564Bxx and SPC56ECxx block diagram: Updated ADC channels and added
legends.
– SPC564Bxx and SPC56ECxx series block summary: Added new blocks.
– Functional Port Pin Descriptions table: Added OSC32k_XTAL and
OSC32k_EXTAL function at PB8 and PB9 port pins.
– Electrical Characteristics: Replaced VSS with VSS_HV throughout the section.
– Absolute maximum ratings, Recommended operating conditions (3.3 V) and
Recommended operating conditions (5.0 V) tables: VRC_CTRL min is updated
to "0".
– Recommended operating conditions (3.3 V) and Recommended operating
conditions (5.0 V) tables: Clarified VIN parameter, clarified footnote 2 in both
tables.
– LQFP thermal characteristics section: Added numbers for LQFP packages.
– Low voltage power domain electrical characteristics table: Clarified footnotes
based upon review comments.
– Code flash memory—Program and erase specifications: Updated tESRT to
20 ms.
– ADC electrical characteristics section: Replace ADC0 with ADC_0 and ADC1
with ADC_1 throughout the document.
DSPI characteristics section: Replaced PCSx with CSx in all figures and tables.

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Table 57. Revision history (continued)

Date Revision Changes

– Replaced VIL min from –0.4 V to –0.3 V in the following tables: 

- I/O input DC electrical characteristics
- Reset electrical characteristics
- Fast external crystal oscillator (4 to 40 MHz) electrical characteristics
– Updated Crystal oscillator and resonator connection scheme figure
– Specified NPN transistor as the recommended BCP68 transistor throughout the
document
– Code and Data flash memory—Program and erase specifications tables:
Renamed the parameter tESUS to Teslat
– Revised the footnotes in the “Functional port pin descriptions” table.
– In the “System pin descriptions” table, added a footnote to the A pads regarding
not using IBE.
For ports PB[12–15], changed ANX to ADC0_X.
– Revised the presentation of the ADC functions on the following ports:
PB[4–7]
PD[0–11]
– ADC conversion characteristics (10-bit ADC_0) table and Conversion
characteristics (12-bit ADC_1) table- Updated footnote 5 and 7 respectively for
the definition of the conversion time.
– Data flash memory—Program and erase specifications: Updated Twprogram to
500 µs and T16Kpperase to 500 µs. Corrected Teslat classsification from “C” to
“D”.
– Code flash memory—Program and erase specifications: Corrected Teslat
classification from “C” to “D”.
28-Apr-2011 3
– Flash Start-up time/Switch-off time: Changed TFLARSTEXIT classification from “C”
to “D”.
– Functional port pin description: Added a footnote at the PB [9] port pin.
– Absolute maximum ratings table: Added footnote 1.
– Low voltage power domain electrical characteristics table: Updated IDDHALT,
IDDSTOP, IDDSTBY3, IDDSTDBY2, IDDSTDBY1.
– Updated commercial product code structure.
– Slow external crystal oscillator (32 kHz) electrical characteristics table: Updated
gmSXOSC, VSXOSC, ISXOSCBIAS and ISXOSC.
– FMPLL electrical characteristics table: Updated tLTJIT.
– Fast internal RC oscillator (16 MHz) electrical characteristics table: Updated
TFIRCSU and IFIRCPWD.
– MII serial management channel timing table: Updated M12
– JTAG characteristics table: Updated tTDOV.
– Low voltage monitor electrical characteristics table: Updated VLVDHV3H,
VLVDHV3L, VLVDHV5H, VLVDHV5L.
– DSPI electricals table: Updated spec 1, 5, 6. Updated footnote 2 and 3. Added
tCSC, tASC, tSUSS, tHSS.
– IO consumption table: Updated all parameter values.
– DSPI electricals: Updated tCSC max to 115 ns.
– Low voltage power domain electrical characteristics table: Added footnote 9.
– ADC electrical characteristics: Added 2 notes above 10-bit and 12-bit conversion
tables.

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Table 57. Revision history (continued)

Date Revision Changes

– Interchanged the denominator with numerator in Equation 11 of Input impedance

and ADC accuracy section
– Removed the note (All ADC conversion characteristics described in the table
below are applicable only for the precision channels. The data for semi-precision
and extended channels is awaited and same will be subsequently updated in
later revs.) in the ADC electrical characteristics section.
01-Dec-2011 4
– Table 49 (On-chip peripherals current consumption). Replaced IDD_HV_ADC
with IDD_HV_ADC0 and IDD_HV_ADC1 values as per ADC specs
– In Table 43, the minimum sample time of ADC0 changed to 500 at 32 MHz
– In Table 43, removed the entry for sample time at 30 MHz
– In Table 44, changed TUEX to TUES and INLX to INLS (Extended channels are
not supported by the device. So, changed to standard channel.)
– Updated the pins 23 and 24 of Figure 2: 176-pin LQFP configuration.
– Updated unit of measure in Table 44: Conversion characteristics (12-bit ADC_1)
– Modified the value to typical value in Table 49: On-chip peripherals current
consumption
– Added footnote to tESRT parameter in Table 26: Code flash memory—Program
and erase specifications
– Added footnote to tESRT parameter in Table 27: Data flash memory—Program
and erase specifications
– Updated Table 29: Flash memory read access timing.
– Updated Notes 2 and Notes 3 of Table 10: Recommended operating conditions
(3.3 V) and Table 11: Recommended operating conditions (5.0 V) respectively.
– Updated the footnote1 of Table 10: Recommended operating conditions (3.3 V)
and Table 11: Recommended operating conditions (5.0 V)
– Updated VDD_HV_A to VDD_BV for CDEC2 and IDD_HV_A in Table 23: Voltage
regulator electrical characteristics and deleted footnote3
– Updated the dedicated number of channels for 12-bit ADC in family comparison
tables
– Updated the values of fSIRC, parameters and conditions of SIRCVAR in Table 41:
04-Mar-2013 5
Slow internal RC oscillator (128 kHz) electrical characteristics
– Updated second footnote in Table 11: Recommended operating conditions
(5.0 V),
– Updated the value of tADC0_PU in Table 43: ADC conversion characteristics (10-
bit ADC_0)
– Updated the IDD values in Table 25: Low voltage power domain electrical
characteristics
– Added footnote to Table 25: Low voltage power domain electrical characteristics
related to current drawn from VDD_HV_A and VDD_HV_B
– Updated entire Section 3.17.1.1: Input impedance and ADC accuracy
– Updated the values of VLPREG in Table 23: Voltage regulator electrical
characteristics.
– Updated the values of VLPREG in Table 23: Voltage regulator electrical
characteristics.
– Added TA = 25 °C, min and max values of VMREG in Table 23: Voltage regulator
electrical characteristics
– Added TA = 25 °C, min and max values of VLPREG in Table 23: Voltage regulator
electrical characteristics

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Table 57. Revision history (continued)

Date Revision Changes

– Updated the min, max and typical values of VLVDLVCORL and VLVDLVBKPL in
Table 24: Low voltage monitor electrical characteristics
– Updated values of gmFXOSC in Table 36: Fast external crystal oscillator (4 to 40
MHz) electrical characteristics
5 – Updated values of gmSXOSC in Table 38: Slow external crystal oscillator (32
04-Mar-2013
(cont.) kHz) electrical characteristics
– Updated the footnote 5 for TADC0_C in Table 43: ADC conversion characteristics
(10-bit ADC_0)
– Updated the footnotes of Table 25: Low voltage power domain electrical
characteristics
17-Sep-2013 6 – Updated Disclaimer
– Removed occurrences of 208BGA from Table 2: SPC564Bxx and SPC56ECxx
family comparison.
– Added PM[3] and PM[4] in the figure note 1 of Figure 4: 256-pin BGA
configuration.
– Added a table note inTable 20: I/O supplies.
– Updated Figure 8: Voltage regulator capacitance connection and added a note in
this figure.
– Removed before trimming value for VMREG, updated after trimming min value of
VMREG from 1.24 V to 1.20 V, updated after trimming min value of VLPREG from
1.225 V to 1.17 V, updated after trimming typical value of VLPREG from 1.25 V to
1.27 V and updated after trimming max value of VLPREG from 1.275 V to 1.32 V
in Table 23: Voltage regulator electrical characteristics.
– Changed min value of VLVDLVCORL and VLVDLVBKPL from 1.12 V to 1.08 V, and
removed typical value of VLVDLVCORL and VLVDLVBKPL in Table 24: Low voltage
monitor electrical characteristics
– Updated max values at 120 MHz for IDDRUN from 200 mA to 208 mA and from
270 mA to 280 mA; updated max value at TA = 125 °C for IDDHALT from 80 mA to
100 mA; updated max value at TA = 25 °C for IDDSTOP from 1.2 mA to 5 mA and
28-Nov-2014 7 at TA = 125 °C from 60 mA to 72 mA; updated max value at TA = 25 °C for
IDDSTDBY3 from 75 µA to 96 µA and at TA = 125 °C from 1200 µA to 2400 µA;
updated max value at TA = 25 °C for IDDSTDBY2 from 70 µA to 92 µA and at
TA = 125 °C from 1100 µA to 2000 µA; updated max value at TA = 25 °C for
IDDSTDBY1 from 65 µA to 85 µA and at TA = 125 °C from 650 µA to 1100 µA;
updated 1st footnote in Table 25: Low voltage power domain electrical
characteristics.
– Added a footnote below Table 29: Flash memory read access timing.
– Updated the formula in Eq. 11 in Section 3.17.1.1: Input impedance and ADC
accuracy.
– Updated legend in Figure 16: Input equivalent circuit (precise channels)
– Updated min and max values for gmFXOSC at VDD = 5.0 V ± 10% from 4 mA/V to
6.5 mA/V and from 20 mA/V to 25 mA/V in Table 36: Fast external crystal
oscillator (4 to 40 MHz) electrical characteristics
– Added Figure 17: Input equivalent circuit (extended channels).
– Updated tADC0_PU value to 1.5 as max and added footnote for IINJ in Table 43:
ADC conversion characteristics (10-bit ADC_0).

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Table 57. Revision history (continued)

Date Revision Changes

– Added Category column in Table 44: Conversion characteristics (12-bit ADC_1).

7
28-Nov-2014 – Added the IDD_HV_ADC0 values in Table 49: On-chip peripherals current
(cont.)
consumption.
Updated Figure 37: LQFP176 package mechanical drawing and Figure 40:
16-Jun-2015 8
Ordering information scheme.
– Added package silhouette on the cover page
– Removed Figure 4: LBGA208 configuration
– Removed LBGA208 column in Table 4: System pin descriptions and in Table 5:
Functional port pin descriptions
– Table 12: LQFP thermal characteristics: for “RJA” row, changed Max value
relating to conditions “Single-layer board—1s” and “Four-layer board—2s2p”
from “TBD” to “43” and “33.9”, respectively
– Removed Table 13: LBGA208 thermal characteristics
– Table 13: LBGA256 thermal characteristics: for “RJA” row, changed Max value
11-Mar-2016 9 relating to conditions “Single-layer board—1s” and “Four-layer board—2s2p”
from “TBD” to “44.3” and “31”, respectively
– Removed LBGA208 row in Table 20: I/O supplies
– Removed Section 4.2.3: LBGA208 package mechanical drawing
– In Table 25: Low voltage power domain electrical characteristics, updated notes
“Only for the “P” classification: LPreg ON, HPVreg OFF, 96 KB RAM ON, device
configured for...”, “LPreg ON, HPVreg OFF, 64 KB RAM ON, device configured
for...”, and “LPreg ON, HPVreg OFF, 8 KB RAM ON, device configured for...”
– In Table 49: On-chip peripherals current consumption, changed IDD_HV_ADC1
value from “300 × fperiph“ to “300”

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