This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2957451, IEEE
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A Novel Interleaved Nonisolated Bidirectional

DC-DC Converter With High Voltage-Gain and
Full-Range ZVS
Zhixing Yan, Jun Zeng, Member, IEEE, Weijie Lin and Junfeng Liu

Abstract- A nonisolated soft-switching bidirectional dc-dc SC-BDC: switched-capacitor BDC

converter (BDC) with interleaved technique and built-in CI-BDC: coupled-inductor BDC
transformer (BT) is proposed for the interface between the energy BT-BDC: built-in transformer BDC
storage system and DC microgrid bus in this paper. A T-type MB: magnetic-based
neutral-point-clamped circuit is integrated into an interleaved
MB-BDC: magnetic-based BDC
conventional buck-boost BDC to obtain high voltage-gain ratio
(VGR) and decrease voltage stresses of power switches effectively. ZVS: zero voltage switching
Compared with couple-inductor (CI), BT allows for small RMS: root-mean-square
magnetic core size owing to its inherent saturation avoidance. The VL: the LVS voltage
interleaved structure is employed to reduce the current ripple in VH: the HVS voltage
the low-voltage side (LVS) and helps to achieve voltage matching φ: phase-shift angle
on both sides of the BT under PWM control. Thus, the circulating D: the duty cycle
current can be lowered to improve efficiency. Phase-shift control uab: the voltage of the primary side
is adopted to regulate the power flows of the proposed BT-BDC. ucd: the voltage of the secondary side
Moreover, the optimal design is given for component parameters
uLr: the leakage inductance voltage
to accomplish zero-voltage switching (ZVS) in a wide voltage
range, which can reduce the switching losses. The operational iLr: the leakage inductance current
principles and characteristics of the proposed BT-BDC are iLm: the magnetizing current
presented in detail. The analysis and performance have been fully Pbase: the power base
validated experimentally on a 40–60 V/400 V 1-kW prototype. The IL: the LVS current
accordance between the analysis and experimental results further I H: the HVS current
testifies the advantages. Pref: the power reference
iLm max: the maximum magnetizing current
Index Terms—Bidirectional dc-dc converter (BDC), built-in Ts : the periodic time
transformer, interleaved technique, high voltage-gain, zero
Tdz: the dead time
voltage switching (ZVS).
Coss: the parasitic capacitance
ABBREVIATION LIST
I. INTRODUCTION
BDC: bidirectional dc-dc converter
VGR: voltage-gain ratio Recently, energy storage systems have been widely used in
LVS: low-voltage side electric vehicles, uninterrupted power supplies, renewable
HVS: high-voltage side energy systems, and microgrids to compensate the power
SC: switched-capacitor imbalance between the power generations and the power
CI: coupled-inductor consumptions[1]–[4]. As an interactive interface between
BT: built-in transformer energy storage elements and the high voltage dc bus,
bidirectional dc-dc converters (BDCs), which have
Manuscript received; revised; accepted. Date of publication; date of current
version. This work was supported in part by the National Natural Science bidirectional power conversion capabilities, are indispensable
Foundation of China under Grants 61573155&51877085, in part by Guangdong for the applications of energy conversion. The voltage ratings
Natural Science Foundation No.2018A030313066, and in part by the of energy storage elements are generally low. Thus, the series
Fundamental Research Funds for the Central University of SCUT (No. connection of storage cells has been used commonly to increase
2018ZD50). (Corresponding author: Junfeng Liu).
Z. Yan is with the School of Electric Power, South China University of
the voltage ratings with the reducing reliability. Meanwhile,
Technology, Guangzhou 510640, China (e-mail: [email protected]). those of the high voltage dc buses are up to 400 V[5]. Therefore,
J. Zeng is with the New Energy Research Center, South China University of a BDC with the high voltage-gain ratio (VGR) is required to
Technology, Guangzhou 510640, China (e-mail: junzeng@scut. edu.cn). connect the low-voltage side (LVS) with the high-voltage side
W. Lin is with the School of Electric Power, South China University of
Technology, Guangzhou 510640, China (e-mail: [email protected]). (HVS) for energy storage systems. BDCs with high VGR are
J. Liu is with the School of Automation Science and Engineering, South mainly divided into isolated and nonisolated categories. Among
China University of Technology, Guangzhou 510640, China (e-mail: jf.liu@ isolated topologies, the shortcomings of large current ripple and
connect.polyu.hk).

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insufficient voltage regulation exist in the voltage-fed type[6]. on both sides of the BT are always matched, thus simple control
Meanwhile, the coupling of regulation variables leads to a and high efficiency.
complex control in the current-fed type[7], [8]. This paper is further organized as follows. An introduction is
Compared with isolated BDCs, nonisolated BDCs have the given in Section I. The operation mode and performance
advantages of high efficiency, low cost, and simple control[9]. analysis are described in Section II, including topology
The conventional buck-boost BDC is the simplest bidirectional principles, modulation scheme, operating modes and
topology. But it suffers from the reverse-recovery problem, calculation of transferred power. The soft-switching condition
which limits its VGR[10]. For nonisolated topologies, and parameter design are examined in Section III. The stress
switched-capacitor (SC), coupled-inductor (CI) and built-in analysis and design guidelines are presented in Section IV. The
transformer (BT) are widely used in BDCs with high VGR[11]– comparative study against other interleaved MB-BDCs is
[15]. Because capacitors replace inductors as the main energy shown in Section V. The extension of the proposed topology is
storage elements, SC-BDCs have the advantages of lightweight, given in Section VI, including magnetic components and
high power density, low voltage stress, and high VGR. generalized topologies. The waveforms of the experimental
Nevertheless, SC-BDCs are merely suitable for low power prototype and the corresponding descriptions are presented in
applications because of the current overshoot in the LVS and Section VII. Finally, the conclusions have been drawn in
large size components[13]. Meanwhile, CI-BDCs store energy Section VIII.
in inductors in one cycle and power the load in the other
iH
cycles[16]. High VGR can be achieved in CI-BDCs by the S1
Cu
proper windings design[14]. Compared with CI type, the S3 S4
advantage of BT type is that the balanced magnetic flux exists
in the magnetic core, which allowing a small core owing to its Lm
inherent saturation avoidance[17]. Therefore, magnetic-based c iLm
d
(MB) BDCs (CI-BDCs and BT-BDCs) with high VGR have S2
N2
been extensively studied recently[17]–[22]. Cd
On the other side, the current in the LVS is much higher than
the current in the HVS among BDCs with high VGR. The high Q1u Q2u VH
current ripple in MB-BDCs with high VGR affects the lifetime N1
iL1 a iLr
of energy storage in the LVS[23], [24]. Consequently, the
L1 Lr
multiphase interleaving structure is recommended in MB- iL2 b Cc Vc
BDCs to decrease the current ripples[13], [22], [25]–[29]. iL
L2
Simultaneously, the size of the LVS filter can be reduced along VL Q1d Q2d
with the decline of ripple current. A novel CI-BDC is proposed
with a good performance by adopting interleaved CIs in the
LVS, as well as SCs in series with an inductor as charge Fig. 1. Circuit diagram of the proposed converter.
pumps[13]. The CIs design is complicated because the coupling
coefficient is 0.3. Moreover, an interleaved BT-BDC, Q1d Q1u Q1d
containing the interleaved buck-boost BDC and the half-bridge Q2u Q2d Q2u Q2d
converter, is proposed to simplify the design of CIs[22]. S3 S1 S3
Although this topology has inherent zero voltage switching S2 S4 S2
(ZVS), low LVS current ripple, and high VGR, it has poor 
voltage regulation ability. When the LVS voltage changes, the
uab 2πD
ZVS feature is failed and the efficiency is decreased due to the
increase of the circulating current. A hybrid CI-BDC is ucd 2πD
proposed to improve efficiency[27]. However, the power flow
control becomes complex. Therefore, a nonisolated BDC with uLr
low LVS ripple, high VGR, wide LVS voltage range ZVS and
simple control is significant for the applications of bidirectional iLm
power conversions.
Based on the aforementioned analysis, a novel interleaved iLr
nonisolated BT-BDC is proposed with high VGR and full-range  01 234567 8
ZVS. Due to the canceling effect by using interleaving
technology, the current ripple in the LVS can be reduced Fig. 2. Steady-state waveforms when 0 < φ < 2π(D-0.5).
extremely. The drawbacks of the conventional buck-boost BDC
and isolated BDCs are overcomed. Meanwhile, the advantages II. OPERATION MODES AND PERFORMANCE ANALYSIS
of these BDCs are guaranteed by the combination of the
The circuit diagram of the proposed interleaved nonisolated
interleaved conventional buck-boost BDC and the T-type
BDC is demonstrated in Fig. 1. The converter contains the
neutral-point-clamped circuit. Due to the series connection of
interleaved buck-boost BDC and the T-type neutral-point-
the two outputs, the high VGR can be achieved and the voltage
clamped circuit. Since both circuits are in series to increase the
stresses across the main switches can be reduced. The voltages
VGR, the high-voltage VH is divided into two parts and shared

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by them. Thus, the voltage stresses on the active switches are inductor of high-frequency transformer. Lm is the magnetizing
less than VH. The primary side of the transformer is located inductance of secondary-side. Cu and Cd are the clamp
between two phases of the interleaved buck-boost BDC, while capacitors. Both primary voltage uab and secondary voltage ucd
the secondary side is located inside the T-type neutral-point- have the waveform of three-level. Due to the capability of
clamped circuit by turns ratio n = N1/N2. L1 and L2 are the same bidirectional power flow, the boost mode is defined as the
DC inductors, and Cc is the clamp capacitor. The AC inductor power flowing from LVS to HVS. The reversed power flow is
Lr represents the sum of the external inductor and the leakage defined as the buck mode.
Cs1 Cs1 Cs1
S1 S1 S1
Cu Cu Cu
Ds1 S3 S4 Ds1 S3 S4 Ds1 S3 S4

Ds3 Ds4 Ds3 Ds4 Ds3 Ds4

Cs3 Cs4 Cs3 Cs4 Cs3 Cs4
Lm Lm Lm
c iLm c iLm c iLm
d d d
Cs2 Cs2 Cs2
S2 Cd S2 Cd S2 Cd
Ds2 Ds2 Ds2
C1u C2u C1u C2u C1u C2u
Q1u Q2u VH Q1u Q2u VH Q1u Q2u VH

a i D1u
Lr
D2u
a i D1u
Lr
D2u
a i D1u
Lr
D2u
uLr
iL1 L1 Lr iL1 L1 uL r
iL1 L1 uL r
Vc Lr Vc Lr Vc
b Cc b Cc b Cc
iL2 L2 C1d C2d iL2 L2 C1d C2d iL2 L2 C1d C2d
VL Q1d Q2d VL Q1d Q2d VL Q1d Q2d
D1d D2d D1d D2d D1d D2d

Before θ0 θ0-θ1 θ1-θ2

Cs1 Cs1 Cs1

S1 S1 S1
Cu Cu Cu
Ds1 S3 S4 Ds1 S3 S4 Ds1 S3 S4

Ds3 Ds4 Ds3 Ds4 Ds3 Ds4

Cs3 Cs4 Cs3 Cs4 Cs3 Cs4
Lm Lm Lm
c iLm c iLm c iLm
d d d
S2 C s2
S2 C s2
S2 C s2
Cd Cd Cd
Ds2 Ds2 Ds2
C1u C2u C1u C2u C1u C2u
Q1u Q2u VH Q1u Q2u VH Q1u Q2u VH
D1u D2u D1u D2u D1u D2u
a iLr a iLr a iLr
uL r
iL1 L1 uLr
iL1 L1 Lr iL1 L1 uLr
Lr Vc Vc Lr Vc
b Cc b Cc b Cc
iL2 L2 C1d C2d iL2 L2 C1d C2d iL2 L2 C1d C2d
VL Q1d Q2d VL Q1d Q2d VL Q1d Q2d
D1d D2d D1d D2d D1d D2d

θ2-θ3 θ3-θ4 θ4-θ5

Cs1 Cs1 Cs1

S1 S1 S1
Cu Cu Cu
Ds1 S3 S4 Ds1 S3 S4 Ds1 S3 S4
Ds3 Ds4 Ds3 Ds4 Ds3 Ds4
Cs3 Cs4 Cs3 Cs4 Cs3 Cs4
Lm Lm Lm
c iLm c iLm c iLm
d d d
S2 C s2
S2 C s2
S2 C s2
Cd Cd Cd
Ds2 Ds2 Ds2
C1u C2u C1u C2u C1u C2u
Q1u Q2u VH Q1u Q2u VH Q1u Q2u VH
D1u D2u D1u D2u D1u D2u
a iLr a iLr a iLr
uL r uL r uL r
iL1 L1 Lr iL1 L1 Lr iL1 L1 Lr
b Cc Vc b Cc Vc b Cc Vc
iL2 L2 C1d C2d iL2 L2 C1d C2d iL2 L2 C1d C2d
VL Q1d Q2d VL Q1d Q2d VL Q1d Q2d
D1d D2d D1d D2d D1d D2d

θ5-θ6 θ6-θ7 θ7-θ8

Fig. 3. The operation modes of a half cycle when 0 < φ < 2π(D-0.5).

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A. Operational Principle drain-source voltage of S1 falls to zero, and S1 is waiting for the
D denotes the duty cycle of the switch Q1d (or Q2d). The drive driving signal.
signal of Q1d lags behind the drive signal of Q2d by 180˚. Stage 9(θ7-θ8): S1 turns ON with ZVS. The current iQ1u flows
Meanwhile, the drive signals of Q1d and Q2d are complementary from source to drain firstly. Then it begins to flows from drain
with those of Q1u and Q2u. S3 (or S4) and Q1d (or Q2d) share the to source when iL1=iLr. uab is equal to VC and ucd is equal to (VH-
same duty cycle D. The drive signal of S3 also lags behind the VC)/2. Therefore, uLr is equal to 0, and the current iLr is given as
drive signal of S4 by 180˚. Meanwhile, the drive signals of S3 iLr ( )  iLr (6 )   (6 ,8 ]. (4)
and S4 are complementary with those of S1 and S2. The phase-
The slew rate of iLr maintains zero, thus voltage-matching is
shift angle φ is the angle difference between the voltages of the
achieved. The steady-state waveforms and the operation modes
primary side and the secondary side of the transformer.
in buck mode are similar to those in the boost mode.
Despite the variation of VL, the adjustment of D can ensure
voltage-matching of VC = n(VH-VC)/2, which means the
circulating current is minimized, thus the highest efficiency[30]. B. Voltage Gain Ratio and Transferred Power Expressions
The transferred power P changes along with the variations of Since the analysis is similar for different modes, the analysis
the duty cycle D or the phase-shift angle φ. The steady-state is done under the condition of 0< φ < 2π(D-0.5). Due to the
waveforms in boost mode during one period are shown in Fig. interleaved buck-boost BDC, the primary side of the
2. It should be noted that the waveforms in the case of 0 < φ < transformer voltage uab can be calculated by
2π(D-0.5) during one cycle are chosen as an example. The V
uab  Vc  L . (5)
voltage of the primary side uab, the voltage of the secondary side 1 D
ucd, the leakage inductance voltage uLr, the leakage inductance Due to the T-type neutral-point-clamped circuit, the ucd can
current iLr and the magnetizing current iLm are demonstrated for be derived by
analysis. V  VC
The corresponding operation modes of a half cycle are shown ucd  H . (6)
2
in Fig. 3. The detailed analysis is described as follows: According to (5) and (6), the VGR can be derived as
Stage 1(Before θ0): Q1d, Q2u, S2, and S3 are in conducting state,
and the others are not. The power flows from LVS to HVS. The
V n2
G H  . (7)
slew rate of iLr maintains zero, thus voltage-matching is VL n(1  D)
achieved. Thus, the duty cycle D can be selected as follows
Stage 2(θ0-θ1): Q2u turns OFF. The sum of iL2 and iLr (n  2)VL
discharges C2d and charges C2u until D2d begins to conduct. The D 1 (8)
nVH
drain-source voltage of Q2d falls to zero, and Q2d is waiting for
the driving signal. According to Fig. 2, phase angle θ0, θ2, θ4, θ6, θ8 can be
expressed by D as
Stage 3(θ1-θ2): Q2d turns ON with ZVS. uab is equal to 0 and
ucd is equal to -(VH-VC)/2. Therefore, uLr is equal to n(VH-VC)/2, 0  0

 2  
and the current iLr is given as
1 
n(VH  VC )  4  2 D   (9)
Ts 2   2 D    
iLr ( )  iLr (0 )   (   0 )   [ 0 , 2 ].
2 Lr  6
(1) 8   .
Stage 4(θ2-θ3): S2 turns OFF. The difference between iLm and The primary voltage of transformer uab is
niLr discharges Cs4 and charges Cs2 until Ds4 begins to conduct. 0,   [0, 2 D   ]
The drain-source voltage of S4 falls to zero, and S4 is waiting for  V

the driving signal. uab ( )   L ,   (2 D   ,  ] (10)
Stage 5(θ3-θ4): S4 turns ON with ZVS. uab is equal to 0 and 1  D
ucd is equal to 0. Therefore, uLr is 0, and the current iLr is  uab (   ),   ( , 2 ].
iLr ( )  0   (2 ,4 ]. (2) Therefore, according to (1), (2), (3), (4), (9), (10) and the
symmetry of one cycle, the transferred power expression can be
Stage 6(θ4-θ5): Q1d turns OFF. The difference between iL1 and
expressed as follows:
iLr discharges C1d and charges C1u until D1u begins to conduct.
The drain-source voltage of Q1u falls to zero, and Q1u is waiting P  Pbase [  2  4 (1  D ) ] (11)
for the driving signal. where Pbase is the power base
Stage 7(θ5-θ6): Q1u turns ON with ZVS. uab is equal to VC and n2VH 2Ts
ucd is equal to 0. Therefore, uLr is equal to VC, and the current iLr Pbase  . (12)
is given as 8(n  2) 2 Lr
T V Likewise, the transferred power expressions can be
iLr ( )  iLr ( 4 )  s  C (   4 )   ( 4 , 6 ]. (3) summarized as follows:
2 Lr
Stage 8(θ6-θ7): S3 turns OFF. The sum of iLm and niLr
discharges Cs1 and charges Cs3 until Ds1 begins to conduct. The

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 Pbase [2 2  2  4 2 ( D 2  D)   2 ],

 III. DISCUSSION OF THE SOFT-SWITCHING PERFORMANCE
   [0.5 , 2 (0.5  D)]
 P [ 2  4 (1  D) ], If junction capacitances of power switches are neglected, a
 base switch can turn ON with ZVS when there is a current flowing
   (2 (0.5  D), 0]
P (13) from source to drain of the switch before the arriving of the
 Pbase [  4 (1  D) ],
2
driving signal. From the mode analysis shown in Section II, the
   (0, 2 ( D  0.5)] junction capacitances of Q1u&Q1d (or Q2u&Q2d) are discharged
 and charged by the difference between iLr and iL1 (or iL2), while
 Pbase [2 2  2  4 2 ( D 2  D )   2 ], niLr and iLm on the secondary side help to achieve ZVS of S1-S4.

   (2 ( D  0.5), 0.5 ]. The ZVS conditions for switches can be summarized as shown
in Table I.
As indicated by (13), the transferred power versus the duty
TABLE I ZVS Conditions for Switches
cycle D and the phase-shift angle φ is shown in Fig. 4. It shows
that the transferred power P only increases monotonously along Switches Current
with the increasing of phase-shift angle φ when D is fixed to
Q1u&Q2u iL1(θ4)-iLr(θ4)>0
achieve voltage-matching. The control block diagram is
demonstrated in Fig. 5. It is composed of voltage-matching Q1d&Q2d -iL2(θ0)-iLr(θ0)>0
control and power flow control. VL and VH are the LVS voltage S1&S2 niLr(θ6)+iLm(θ6)>0
and the HVS voltage, respectively. IH is the HVS current, and S3&S4 niLr(θ2)+iLm(θ2)>0
Pref is the power reference. Since D is determined by VL and VH
based on (8) to achieve voltage-matching, the transferred power
The soft-switching performances in the boost mode and buck
P is regulated only by φ using PI regulator. Meanwhile, the
mode are similar. Therefore, the conditions can be analyzed
direction of the power flow is only determined by the sign of φ,
together. For the interleaved conventional buck-boost BDC,
which means the direction of the power flow is not sensitive to
there are many references for detailed analysis of its full-range
D. Therefore, the voltage-matching is achieved by D while the
ZVS condition[22]. In this section, the soft-switching condition
transferred power flow is controlled by φ. It can be found that
of S1-S4 is analyzed in detail.
the control block is very simple and easy to implement.
The waveforms of S1-S4 are shown in Fig. 6. S1 and S2 are
Based on (7) and the battery voltage VL range, the turns ratio
taken as an example to analyze ZVS performance. According
n and the range of D can be selected reasonably. According to
to the detailed analysis in Fig. 3, the sum of iLm and niLr charges
(12) and (13), the maximum transferred power, proportional to
the junction capacitance of the switch that has been turned off
the Pbase and inversely proportional to Lr, can be obtained by Lr
and discharges the junction capacitance of the switch that is
reasonably. Thus, Pref and the range of φ can be selected by the
about to be turned on within the dead time to achieve complete
maximum transferred power.
ZVS[31]. Therefore, the ZVS condition for S1-S4 in boost and
buck mode can be calculated as follows:
Tdz VC
0 niLr  iLm dt  2Coss n (14)

where Tdz is the dead time of S1-S4, Coss is the parasitic

capacitance of S1-S4.
As seen in Fig. 6(a), before S1 turns ON, iLm is the maximum
with the value of iLm max = VLTs/(2nLm), and iLr begins to decrease.
According to (14), the ZVS condition for S1 and S2 in boost
mode can be expressed as follows:
 VLTs nVC  2CossVC 
 2nL  2 L ( 2 Ts  Tdz )  nT ,
2 
Ts  Tdz
 m r dz
(15)

 VLTs  nVC (  T ) 2  2CossVC ,  T  T .
Fig. 4. The surface of power P versus duty cycle D and phase-shift angle φ.
 2nLm 2 Lr Tdz 2 s nTdz 2
s dz

Power flow control The equation (15) can be deduced as follows:

Pref VLTs n 2VC  4C V 
  ( Ts  Tdz )  oss C , T  Tdz
iH
P
-+
φ  m L L 2 T 2  s
PI 
r dz
(16)
VLTs  n VC (  T ) 2  4CossVC ,  T  T .
2
PWM Driving
……

D modulation Signals  L Lr Tdz 2

s
Tdz 2
s dz
VH (Eq.8)  m

VL
Voltage-match control
Fig. 5 Control block diagram.

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of Lm increases along with the ascend of dead time Tdz. However,

S3 S1 S3 S3 S1 S3 the longer dead time causes more conduction time for switches
S2 S4 S2 S2 S4 S2 body diode when iLr is large enough at heavy loads. Therefore,
ILm max ILm max Lm is designed to be 800 μH and dead time Tdz = 600 ns.
iLm iLm
ILr max ILr max IV. STRESS ANALYSIS AND DESIGN GUIDELINES
iLr iLr
A 1-kW prototype with VL = 40-60V and VH = 400V
（ a） （ b） operating at 50-kHz switching frequency is adopted as an
Fig. 6. Key waveforms of S1-S4. (a) Boost mode. (b) buck mode. example to illustrate the design considerations.

It can be seen from (16) that the ZVS condition of S1 and S2 A. Stress Analysis
becomes more difficult with the decrease of phase-shifted angle 1) Duty Cycle Range: The duty cycle D ought to be closed
φ. And ZVS is easy to fail when there is no power transmission to 0.5 when the battery voltage is maximum. In this case,
(φ=0). Therefore, Lm to achieve ZVS can be derived as follows: according to (5), VC is set as 120V. Therefore, D is in the range
V TT of 1/3-0.5.
Lm  L s dz 2) Turns Ratio of the Built-in Transformer: Because of VH =
4CossVC 400V and VC = 120V, according to (5) and (7), turns ratio n is
(1  D )VC TsTdz derived to be 6/7.
 (17) 3) Voltage Stress: The voltage stress of the interleaved
4CossVC
conventional buck-boost BDC can be obtained as
(1  D )TsTdz VQ1u  VQ1d  VQ 2u  VQ 2d  VC  120V.
 . (19)
4Coss Due to the T-type neutral-point-clamped circuit, The voltage
It can be proved that Lm in (17) is independent of the output stress in the HVS can be derived as
power. In the same way, the ZVS condition for S3 and S4 in buck VS 1  VS 2  VH  VC  280V (20)
mode is the same as (17). Similarly, the ZVS condition for S1
and S2 in buck mode and the ZVS condition for S3 and S4 in VH  VC
VS 3  VS 4   140V. (21)
boost mode can be derived as: 2
(1  D)Ts  Tdz 4) Current Stress: The current ripples of two DC inductors
Lm  Tdz . (18) are neglected for analysis simplification. The currents of L1 and
4Coss
L2 are expressed as
P
iL1  iL 2  . (22)
2VL
The peak current of the magnetizing inductance Lm can be
obtained as
VT
iLm max  L S . (23)
2nLm
The current stress of the interleaved conventional buck-boost
BDC can be obtained as
IQ1u  I Q 2u  i1 (24)
IQ1d  IQ 2d  i1  iLr max . (25)
The current stress in the HVS can be derived as
I S 1  I S 2  I S 3  I S 4  niLr max  iLm max . (26)
Fig. 7. The surface of the maximum magnetizing inductance Lm versus the LVS B. Design Guidelines
voltage VL and the dead time Tdz. 1) AC Inductor Lr: Base on (12) and (13), the maximum
power point, proportional with Pbase and inversely proportional
From (17) and (18), it is obvious that the ZVS condition for with Lr, can be changed by Lr reasonably. Therefore, the value
S1-S4 in boost and buck mode can be guaranteed when Lm of 18.1 µH is adopted. And the transferred power versus the
satisfies (18). Based on (18), the maximum Lm curve versus the duty cycle D and the phase-shift angle φ is shown in Fig. 4.
LVS voltage VL and the dead time Tdz of S1-S4 is shown in Fig. 2) DC Inductor L1 and L2: The DC inductors are used to
7. Fig. 7 indicates that ZVS can be achieved when Lm is less reduce the current ripple in the LVS. By using interleaving
than the value of the boundary. technology, the current ripple Δi can be expressed as
To minimize the magnetizing loss, Lm should be designed as V
large as possible. The large inductance of Lm reduces the ( L  2VL ) DTs
magnetizing loss, but increases the copper loss. Therefore, the i  D . (27)
magnetizing loss and copper loss of transformer need to be 2 L1
comprehensively debated[32]. As seen in Fig. 7, the inductance

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It is obvious that Δi is equal to 0 when D = 0.5. And Δi proposed converter has the advantages of flexible VGR, low
increases with the decrease of VL. In order to limit the ripple current ripple and simple control.
rate within 10%, L1 = L2 = 79 µH are implemented. Similarly, it can be observed that the proposed converter with
3) Capacitors: The ripple voltages of capacitors are designed voltage matching has the better performance than other MB-
to be 1% of the average voltages. According to the operation BDCs due to the less current ripple in the LVS, full soft-
principles, the desired value of capacitors under 1-kW condition switching range, LVS voltage regulation capability, and the
is calculated reasonably[22]. The values CC = 50 µF, Cu = Cd = bidirectional symmetrical power flow capability. Moreover, Fig.
30 µF are implemented. 8 compares the theoretical VGR versus duty cycle. It can be
4) Power Switches Selection: According to (19), (20) and seen that the VGR of the proposed can be adjusted flexibly
(21), the voltage stress on Q1u, Q1d, Q2u, and Q2d is 120 V; the through the turns ratio. And the proposed BT-BDC can achieve
voltage stress on S1 and S2 is 280 V; the voltage stress on S3 andhigh VGR without a high turns ratio. Furthermore, it can be
S4 is 140 V. According to (24), (25) and (26), the current stress found that the proposed converter and [22] possess the highest
on Q1u and Q2u is 12 A; the current stress on Q1d and Q2d is 19 VGR. The proposed and [22] both contain the interleaved buck-
A; the current stress on S1, S2, S3 and S4 is 8.2 A. Consequently,boost BDC in the LVS, which can reduce current ripple
IRFP4668 and IRFP360 are selected. extremely. The two circuits included in the proposed and [22]
are in series to increase the VGR, and VH is shared by them.
V. COMPARATIVE ANALYSIS Thus, the voltage stresses on the active switches are less than
VH. Meanwhile, the difference between them is that the T-type
In order to evaluate the performance, the comparisons can be neutral-point-clamped circuit is in the proposed while half-
conducted among the proposed, conventional BDCs and the bridge circuit is in [22]. Topology in [22] theoretically can bring
other similar MB-BDCs. As seen in Table II, the BDCs less conduction loss due to fewer switches, but it is difficult to
presented in[2], [6], [7], [13], [14], [22], [26] and [27] are realize a wide range of voltage regulation while maintaining
compared with the proposed converter. The conventional buck- high efficiency. The only optimal operation condition in [22] is
boost BDC is the simplest bidirectional topology, which is matching the voltages on the two sides of the converter, whose
attractive for low-voltage applications due to simple control and duty cycle D is fixed to 0.5. Therefore, once the voltages on the
low cost. But it is not suitable for high VGR applications due to two sides of the converter are not matched, a high circulating
hard-switching, the extreme duty cycle and severe reverse- current and losing of soft switching will decrease the
recovery problem. High-frequency isolated BDCs are conversion efficiency dramatically. However, the proposed has
recommended as its VGR can be adjusted easily through the the LVS voltage regulation capability, whose duty cycle D can
turns ratio of the transformer. Among isolated BDCs, the change along with the variations of the LVS voltage. Moreover,
shortcomings of large current ripple and insufficient voltage the voltages on both sides are always matched. When D is not
regulation exist in the voltage-fed isolated BDC. Meanwhile, equal to 0.5, the proposed has higher conversion efficiency than
the coupling of regulation variables leads to a complex control [22]. Therefore, the proposed is more suitable than [22] for
in the current-fed isolated BDC. Comparatively speaking, the energy storage applications.
TABLE II Comparison Between the Proposed Converter and Other Similar Converters
[2] [6] [7]
Proposed
Items Conventional Voltage-fed Current-fed [13] [14] [22] [26] [27]
converter
buck-boost BDC isolated BDC isolated BDC
Number of
semiconductor 8 2 8 8 8 4 6 8 6
devices
Number of
phases in the 2 1 2 2 4 1 2 2 2
LVS
Theoretical n2 1 1 2 4 n 1 n2 2 2n  D nD(1  D)
voltage gain n(1  D) 1 D n n(1  D) 1 D n(1  D) n(1  D) 1 D n(1  D) 2(1  D)2  n

LVS voltage
regulation Yes Yes No Yes Yes Yes No Yes Yes
capability
Theoretical
Full-range Not Limited Full-range Not Limited Full-range Limited Limited
ZVS range
Current ripple
Low High High Low Low High Low Low Moderate
in the LVS

Fig. 9, Two windings are wound on the outer legs with adding
VI. EXTENSION OF THE PROPOSED TOPOLOGY polarity to allow flux ripple cancellation in the center leg[33].
Furthermore, the magnetic-integrated inductor is used to
A. Magnetic Components eliminate the magnetic flux ripples, which can reduce the
1) Magnetic-integrated DC inductors: Since L1 and L2 are magnetic loss so as to improve the efficiency.
designed with the same inductance and are subjected to the
same operation conditions, they can be constructed with ferrite 2) The AC inductor: The AC inductor Lr can be partly or
EI core with air gap to improve the power density. As seen in fully implemented with the leakage inductance of the built-in

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transformer. Therefore, the power density can be improved [13], [14], [22], [26], [27] and the proposed converter. (a) n = 1/2. (b) n = 1/4.
effectively by the utilization of parasitic parameters. In addition,
iL1
it can be found from (12) and (13) that the maximum power is
proportional to the Pbase and inversely proportional to Lr,
therefore, the power range can be designed by the regulation of VL
the leakage inductance Lr reasonably.
iL2

Fig. 9. The physical structure of the magnetic-integrated DC inductors using EI

core.
Voltage Gain Ratio

B. Generalized Three-Level Topologies

The idea, achieving interleaving technology and high VGR
by employing two three-level structures on both sides of the
built-in transformer, is also valid for other three-level circuits.
Therefore, a family of three-level BT-BDCs with interleaving
technology can be derived in Fig. 10. Similarly, the primary
side of the built-in transformer is located between two phases
of the interleaved conventional buck-boost BDC; while the
secondary side is located in different three-level circuits.
The topology in Fig. 10(a) is the full-bridge type, which can
Duty Cycle
achieve three-level on the secondary side of the built-in
（a）
transformer by phase-shift control. Similarly, low LVS ripple,
high VGR, wide LVS voltage range ZVS and simple control
can be achieved. Moreover, diode-clamped circuit and flying
capacitor circuit in Fig. 10(b) and (c) can reduce voltage
stresses of switches by half.
Voltage Gain Ratio

Duty Cycle
（b）

Fig. 8. Comparison of VGR versus duty cycle between converters presented in

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（ a） （b） （ c）
Fig. 10. Generalized three-level BT-BDCs topologies: (a) full-bridge type, (b) diode-clamped type, (c) flying-capacitor type

The experimental waveforms of buck and boost modes are

VII. EXPERIMENTAL RESULTS shown in Fig. 12(a)-(f) at the rated power of P = 1-kW. The
waveforms in Fig. 12(a)–(c) are tested in boost mode; and Fig.
A 1-kW experimental prototype has been built with 50-kHz 12(d)–(f) are tested in buck mode. uab and ucd are the voltages
switching frequency to verify the effectiveness of the proposed of the built-in transformer primary and secondary side,
BT-BDC. It is illustrated in Fig. 11 with its parameters shown respectively. iLr is the current of leakage inductor Lr. The
in Table III. voltage matching waveforms can be clearly observed from Fig.
For the performance evaluation at the different voltage 12(a)-(f) as the slew rate of iLr maintains zero when uab = ucd.
conversion ratios, the LVS voltage VL is 40-60 V and the HVS Thus, the voltages on both sides of BT are matched to reduce
voltage VH is clamped to 400V. L1 and L2 are 79 μH[22], Q1u, the circulating current losses and ensure ZVS for all power
Q1d, Q2u, Q2d can achieve ZVS. From the above analysis, tdz is switches. In addition, the duty cycle D is only determined by VL.
selected around 600 ns that is achieved by the dead-zone circuit. It can be found that the conversion power can be controlled
The control is implemented with a TM320F28335 digital independently by the adjustment of the phase-shift angle φ
controller. when the voltage matching is achieved by D. The experimental
results agree well with the theoretical analysis.

Fig. 11. Photo of the prototype.

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uab(200V/div) uab(200V/div) uab(200V/div)

ucd(200V/div) ucd(200V/div) ucd(200V/div)

iLr(10A/div) t(5μs/div) iLr(10A/div) t(5μs/div) iLr(10A/div) t(5μs/div)

(a) (b) (c)

uab(200V/div) uab(200V/div) uab(200V/div)

ucd(200V/div) ucd(200V/div) ucd(200V/div)

iLr(10A/div) t(5μs/div) iLr(10A/div) t(5μs/div) iLr(10A/div) t(5μs/div)

(d) (e) (f)
Fig. 12. Experimental waveforms for buck and boost modes at rated power: (a) VL=40V in the boost mode, (b) VL=50V in the boost mode, (c) VL=60V in the boost
mode, (d) VL=40V in the buck mode, (e) VL=50V in the buck mode, (f) VL=60V in the buck mode.

TABLE III Main Parameters of the Prototype Fig. 19. Under the condition of interleaving control, the
amplitude of current ripple in the LVS is greatly reduced and
Symbol Parameter Symbol Parameter the frequency is doubled, which can reduce the size of the filter
VL 40-60 V Lr 18.1 μH and prolong the lifetime of the energy storage device.
VH 400 V Lm 800 μH
P 1-kW CC 50 μF ugsQ1u(10V/div) ugsQ1d(10V/div)
fs 50-kHz Cu, Cd 30 μF udsQ1u(200V/div) udsQ1d(200V/div)
n 6/7 tdz 600 ns
iLr(10A/div)
L1, L2 79 μH iLr(10A/div)
Q1u, Q1d, Q2u, t(500ns/div) t(500ns/div)
IRFP4668 S1, S2 IRFP360 (a) (b)
Q2d, S3, S4
P 0.00005 I 500 ugsS3(10V/div)
ugsS1(10V/div)

The waveforms of soft switching are shown in Fig. 13-Fig. udsS1(200V/div) udsS3(200V/div)
18. The waveforms in Fig. 13-Fig. 15 are tested in boost mode iLr(10A/div)
in VL = 40, 50, 60V, respectively. The waveforms in Fig. 16- iLr(10A/div)
Fig. 18 are tested in buck mode in VL = 40, 50, 60V, respectively. t(500ns/div) t(500ns/div)
Fig. 14 and Fig. 17 are taken as an example to analyze ZVS (c) (d)
performance. Because of the symmetry of the topology, the Fig. 13. Experimental waveforms of soft switching for boost mode at the rated
waveforms of half power switches are shown. Fig. 14(a)–(d) are power with VL=40V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of
the waveforms of soft switching in boost mode in Q1u, Q1d, S1, S3.
and S3, respectively. Fig. 17(a)–(d) are the waveforms of soft
switching in buck mode in Q1u, Q1d, S1, and S3, respectively. The
gate voltage, the drain-to-source voltage, and the leakage
inductor current are captured. As illustrated in Fig. 14 and Fig.
17, ZVS can be achieved for all the power switches. Meanwhile,
it can be seen from Fig. 14 and Fig. 17 that the voltage stresses
on Q1u and Q1d are 120 V, while the voltage stress on S1 and S3
is 140 V and 280 V, respectively. The waveforms indicate that
the 400 V high voltage is divided into two parts and shared by
the two circuits. Thus, the voltage stresses on power switches
are reduced.
The experimental waveforms of high-frequency current
ripple in the LVS at rated power with VL = 50V are shown in

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ugsQ1u(10V/div) ugsQ1d(10V/div) ugsQ1u(10V/div) ugsQ1d(10V/div)

udsQ1u(200V/div) udsQ1d(200V/div) udsQ1u(200V/div) udsQ1d(200V/div)

iLr(10A/div) iLr(10A/div)
iLr(10A/div)
t(500ns/div) t(500ns/div) iLr(10A/div) t(500ns/div) t(500ns/div)
(a) (b) (a) (b)

ugsS1(10V/div) ugsS3(10V/div) ugsS1(10V/div) ugsS3(10V/div)

udsS1(200V/div) udsS3(200V/div) udsS1(200V/div) udsS3(200V/div)

iLr(10A/div)
iLr(10A/div) iLr(10A/div)
t(500ns/div) t(500ns/div) iLr(10A/div)
t(500ns/div) t(500ns/div)
(c) (d) (c) (d)
Fig. 14. Experimental waveforms of soft switching for boost mode at the rated Fig. 17. Experimental waveforms of soft switching for buck mode at the rated
power with VL=50V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of power with VL=50V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of
S3. S3.
ugsQ1u(10V/div) ugsQ1d(10V/div) ugsQ1u(10V/div) ugsQ1d(10V/div)
udsQ1u(200V/div) udsQ1d(200V/div) udsQ1u(200V/div) udsQ1d(200V/div)

iLr(10A/div) iLr(10A/div) iLr(10A/div)

iLr(10A/div)
t(500ns/div) t(500ns/div) t(500ns/div) t(500ns/div)
(a) (b) (a) (b)

ugsS1(10V/div) ugsS3(10V/div) ugsS1(10V/div) ugsS3(10V/div)

udsS1(200V/div) udsS1(200V/div)
udsS3(200V/div) udsS3(200V/div)
iLr(10A/div) iLr(10A/div)
iLr(10A/div) iLr(10A/div)
t(500ns/div) t(500ns/div) t(500ns/div) t(500ns/div)
(c) (d) (c) (d)
Fig. 15. Experimental waveforms of soft switching for boost mode at the rated Fig. 18. Experimental waveforms of soft switching for buck mode at the rated
power with VL=60V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of power with VL=60V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of
S3. S3.

ugsQ1u(10V/div) ugsQ1d(10V/div)
udsQ1u(200V/div) udsQ1d(200V/div) iL(4A/div)
iL1(4A/div)
iLr(10A/div)
iLr(10A/div)
iL2(4A/div) t(5μs/div)
(a) (b)
Fig. 19. Experiment waveform of high-frequency current ripple in the LVS at
ugsS1(10V/div) the rated power with VL=50V.
ugsS3(10V/div)

The pie chart of losses in the boost mode is shown in Fig. 20,
udsS1(200V/div) udsS3(200V/div)
where VL is 40 V, VH is 400 V. The switching losses are taken
iLr(10A/div) as zero due to the soft-switching. As seen in Fig. 20, the losses
iLr(10A/div)
include conduction losses of power switches, copper losses of
(c) (d) magnetic devices and other losses. Conduction losses of power
Fig. 16. Experimental waveforms of soft switching for buck mode at the rated switches can be written as
power with VL=40V: (a) ZVS of Q1u, (b) ZVS of Q1d, (c) ZVS of S1, (d) ZVS of Pcon,loss  2  ( I RMS ,Q1u 2  Ron,Q1u  I RMS ,Q1d 2  Ron,Q1d
S3. (28)
 I RMS , S12  Ron,S1  I RMS , S 32  Ron, S 3 )
where IRMS is the root-mean-square (RMS) current of the
power switch and Ron is the static drain-to-source on-resistance
of the power switch.
Copper losses of magnetic devices can be written as

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Pmag ,loss  I RMS , L12  rL1  2  I RMS , Lr 2  rLr (29) LVS ripple, high VGR, wide LVS voltage range of ZVS and
simple control. Furthermore, a family of three-level BT-BDCs
where rL1 is the equivalent series resistance of L1 and rLr is with interleaving structure has been derived. Finally, the
the equivalent series resistance of Lr. effectiveness of the proposed BT-BDC and control strategy is
verified by a prototype of 1-kW, 40–60 to 400 V. Experimental
8.08W results testify that the proposed topology and control are
(16.46%)
effective for the interface between the energy storage system
17.72W
(36.10%) and DC bus.

23.29W REFERENCES
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0885-8993 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2957451, IEEE
Transactions on Power Electronics

IEEE POWER ELECTRONICS REGULAR PAPER

[16] M. Lakshmi and S. Hemamalini, “Nonisolated High Gain DC–DC Zhixing Yan was born in Zhaoqing, Guangdong,
Converter for DC Microgrids,” IEEE Trans. Ind. Electron., vol. 65, no. China, in 1995. He received the B.S. degree in
2, pp. 1205–1212, Feb. 2018. electrical engineering from Southwest Jiaotong
[17] M. Forouzesh, Y. P. Siwakoti, S. A. Gorji, F. Blaabjerg, and B. Lehman, University, Chengdu, China, in 2018.
“Step-Up DC–DC Converters: A Comprehensive Review of Voltage- He is currently pursuing the M.S. degree with the
Boosting Techniques, Topologies, and Applications,” IEEE Trans. Electric Power College, South China University of
Power Electron., vol. 32, no. 12, pp. 9143–9178, Dec. 2017. Technology, Guangzhou, China. His current research
[18] Hyun-Lark Do, “A Soft-Switching DC/DC Converter With High interests include dc/dc power conversion and solid-
Voltage Gain,” IEEE Trans. Power Electron., vol. 25, no. 5, pp. 1193– state transformer.
1200, May 2010.
[19] W. Li, W. Li, X. He, D. Xu, and B. Wu, “General Derivation Law of
Nonisolated High-Step-Up Interleaved Converters With Built-In Jun Zeng (M’11) received her Ph.D. degree in
Transformer,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1650– control theory and control engineering from the
1661, Mar. 2012. South China University of Technology, Guangzhou,
[20] Y. Zheng, S. Li, and K. M. Smedley, “Nonisolated High Step-Down China in 2007. She is a professor in the Electric
Converter With ZVS and Low Current Ripples,” IEEE Trans. Ind. Power College of the South China University of
Electron., vol. 66, no. 2, pp. 1068–1079, Feb. 2019. Technology, Guangzhou, China. Her current research
[21] K.-B. Park, G.-W. Moon, and M.-J. Youn, “Nonisolated High Step-Up interests include power electronics applications,
Stacked Converter Based on Boost-Integrated Isolated Converter,” energy management and intelligence control in
IEEE Trans. Power Electron., vol. 26, no. 2, pp. 577–587, Feb. 2011. distributed generation and integration of renewable
[22] H. Bahrami, S. Farhangi, H. Iman-Eini, and E. Adib, “A New energy to smart grid.
Interleaved Coupled-Inductor Nonisolated Soft-Switching
Bidirectional DC–DC Converter With High Voltage Gain Ratio,” IEEE Weijie Lin was born in Guangdong, China, in 1995.
Trans. Ind. Electron., vol. 65, no. 7, pp. 5529–5538, Jul. 2018. He received the B.S. degree in electrical engineering
[23] H.-L. Do, “Improved ZVS DC-DC Converter With a High Voltage from Southwest Jiaotong University, Chengdu,
Gain and a Ripple-Free Input Current,” IEEE Trans. Circuits Syst. China, in 2018. He is currently working toward his
Regul. Pap., vol. 59, no. 4, pp. 846–853, Apr. 2012. M.S. degree in power electronics and power drives at
[24] H. Ardi, A. Ajami, and M. Sabahi, “A Novel High Step-Up DC–DC South China University of Technology, Guangzhou,
Converter With Continuous Input Current Integrating Coupled Inductor China.
for Renewable Energy Applications,” IEEE Trans. Ind. Electron., vol. His current research interests include multilevel
65, no. 2, pp. 1306–1315, Feb. 2018. converters, high-frequency ac power distributed
[25] M. Forouzesh, Y. Shen, K. Yari, Y. P. Siwakoti, and F. Blaabjerg, system, and resonant converters.
“High-Efficiency High Step-Up DC–DC Converter With Dual Coupled
Inductors for Grid-Connected Photovoltaic Systems,” IEEE Trans. Junfeng Liu received the M.S. degree in control
Power Electron., vol. 33, no. 7, pp. 5967–5982, Jul. 2018. engineering from the South China University of
[26] M. Kwon, S. Oh, and S. Choi, “High Gain Soft-Switching Bidirectional Technology, Guangzhou, China, in 2005, and the
DC–DC Converter for Eco-Friendly Vehicles,” IEEE Trans. Power Ph.D. degree from the Hong Kong Polytechnic
Electron., vol. 29, no. 4, pp. 1659–1666, Apr. 2014. University, Kowloon, Hong Kong, in 2013.
[27] M. Aamir, S. Mekhilef, and H.-J. Kim, “High-Gain Zero-Voltage From 2005 to 2008, he was a Development
Switching Bidirectional Converter With a Reduced Number of Engineer of Guangdong Nortel Network, Guangzhou,
Switches,” IEEE Trans. Circuits Syst. II Express Briefs, vol. 62, no. 8, China. In 2014, he joined the South China University
pp. 816–820, Aug. 2015. of Technology, Guangzhou, where he was an
[28] K. I. Hwu, W. Z. Jiang, and P. Y. Wu, “An Expandable Four-Phase Associated Professor at School of Automation
Interleaved High Step-Down Converter With Low Switch Voltage Science and Engineering. His research interests
Stress and Automatic Uniform Current Sharing,” IEEE Trans. Ind. include power electronics applications, nonlinear control, high frequency
Electron., vol. 63, no. 10, pp. 6064–6072, Oct. 2016. power distribution system, and motion control system.
[29] J. Zeng, Z. Yan, J. Liu, and Z. Huang, “A High Voltage-Gain
Bidirectional DC-DC Converter with Full-Range ZVS Using
Decoupling Control Strategy,” IEEE J. Emerg. Sel. Top. Power
Electron., Early Access.
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Bridge Isolated Bidirectional DC–DC Converter for High-Frequency-
Link Power-Conversion System,” IEEE Trans. Power Electron., vol.
29, no. 8, pp. 4091–4106, Aug. 2014.
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Model and Parameter Extracting for High-Power High-Voltage High-
Frequency Transformers,” IEEE Trans. Power Electron., vol. 31, no. 5,
pp. 3444–3455, May 2016.
[33] Wensong Yu, Hao Qian, and Jih-Sheng Lai, “Design of High-
Efficiency Bidirectional DC–DC Converter and High-Precision
Efficiency Measurement,” IEEE Trans. Power Electron., vol. 25, no. 3,
pp. 650–658, Mar. 2010.

0885-8993 (c) 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.