Heaven’s Light is Our Guide

Department of Computer Science & Engineering

Rajshahi University of Engineering & Technology

Course Plan / Outline

A. Course Information
1. Course Title: Sessional Based on CSE CSE 2203
2. Course Code: CSE 2204
3. Prerequisite: None
4. Semester: 2nd Year Even
5. Credit: 1.50
6. Class Hours: 2.5 Hours per Week

B. Instructors’ Details
1. Name of the Instructor: Md. Zahirul Islam
2. Designation: Assistant Professor
3. Office Room: Room No. - 108
4. Contact Number: +8801855291280
5. Email: [email protected], [email protected]
6. Web link: https://www.cse.ruet.ac.bd/kmzahir61
7. Consultation Hours: TBA

C. Course Rationale
All real-world data are analog and these data are communicated from one place to another through digital
devices, whereas almost all kinds of digital devices like computer, calculator, digital machine, mobile phone
etc. use digital data. For this purpose and for designing various digital devices, digital techniques course is very
important to implement the desired devices.

D. Course Content
In this course, theoretical knowledge is implemented in the laboratory based on the course CSE 2203 (Digital
Logic Design). Lab experiments are designed according the theory course. At the end of this course students are
able to design various logic gates, circuits and students also can obtain the professional level skill like the skill
of an expert in industry to build up various gates, design various combinational logic circuits and small ICs.
E. Course Objectives
1. To acquire technical skills to design various logic gates and circuits.
2. To obtain skills to design various combinational logic circuits and small ICs

F. Course Outcomes (COs), Program Outcomes (POs), Teaching Learning and Assessment
CO CO Statement Mapped Domain/ Skills Aligned Delivery Assessment
No. PO level of level as Contents Methods and Tools
Learning per BAC Activities
Taxonomy Standard
CO1 Designing and PO3, Cognitive F1, F2 Designing ☒ Lecture ☒ Quiz
implementing PO7 (Apply & Various logic ☐ Tutorial ☒ Viva
various Create) Combination ☒ Discussion ☒ Lab Report
combinational al circuits.
☒ Interaction ☐ Project
logic circuits
for solving the ☐ Audio/Video ☐ Presentation
practical ☒ Lab Manual
problems
CO2 Designing and PO3, Cognitive F3, F4 Designing ☐ Lecture ☒ Quiz
implementing PO7 (Apply & Various ☐ Tutorial ☒ Viva
 various Create) Sequential ☒ Discussion ☒ Lab Report
sequential logic Circuits. ☒ Interaction ☐ Project
circuits for ☐ Audio/Video ☒ Presentation
solving the
☒ Lab Manual
practical
problems
CO3 Designing and PO3, Cognitive P1, T2 Designing ☒ Lecture ☒ Quiz
implementing PO7 (Apply & and ☐ Tutorial ☒ Viva
various gates by Create) Implementin ☒ Discussion ☒ Lab Report
using CMOS g Various
☒ Interaction ☒ Project
logic TTL Logic
Techniques. ☒ Audio/Video ☐ Presentation
☒ Lab Manual
* Levels in Bloom’s Cognitive Domain: Level 1: Remember, Level 2: Understand, Level 3: Apply, Level 4: Analyze, Level 5: Evaluate, Level 6: Create
* Levels in Bloom’s Affective Domain: Level 1: Receive, Level 2: Respond, Level 3: Value, Level 4: Organize, Level 5: Internalize
* Levels in Bloom’s Psychomotor Domain: Level 1: Imitate, Level 2: Manipulate, Level 3: Perfect, Level 4: Articulate, Level 5: Embody
* BAC Standard Skills: Fundamental (F), Social (S), Thinking (T), Personal (P)

G. Lecture Plan:
Week Contact Name of the Experiments: Lecture Aligned
no. Hours Material CO
1. 2.5 Hours 1. Introduction as well as Rules and Regulation of the lab. ----------- ---------
Per Week
2. 2.5 Hours Experiment No. – 1: Study of operation of all Logic Gates. PPT – 1 CO1
Per Week
3. 2.5 Hours Experiment No. – 2: Study of Binary to Gray Code Conversion. PPT – 2 CO1
Per Week Experiment No. – 3: Study of Gray to Binary Code Conversion.
Experiment No. – 4: Study of Binary to Excess - 3 Code
Conversions.
4. 2.5 Hours Experiment No. – 5: Study of Binary Adders. PPT – 3 CO1
Per Week
5. 2.5 Hours Experiment No. – 6: Study of Binary Subtractors. PPT – 4 CO1
Per Week
6. 2.5 Hours Experiment No. – 7: Study of 10 to 3 Line Encoder. PPT – 5 CO1
Per Week Experiment No. – 8: Study of 3 to 10 Line Decoder.
7. 2.5 Hours Experiment No. – 9: Study of Multiplexer and De-multiplexer PPT – 6 CO1
Per Week Circuit.
8. 2.5 Hours Experiment No. – 10: Study of Characteristics of various types PPT – 7 CO2
Per Week of Flip-Flops.
9. 2.5 Hours Experiment No. – 11: Study of 4 bit Binary up down Counter. PPT – 8 CO2
Per Week 2. Study of Johnson Counter (Experiment 10)
10. 2.5 Hours Experiment No. – 12: Study of 4 Bit Serial in Parallel out Shift PPT – 9 CO2
Per Week Register.
11. 2.5 Hours Lab Final ---------- ----------
Per Week
12. 2.5 Hours Lab Quiz Test ---------- ----------
Per Week
13. 2.5 Hours Project Submission (Project will be assigned) PPT – 10 CO3
Per Week

H. Knowledge Profile, Complex Engineering Problems and Complex Engineering Activities Mapping
Program Outcomes (POs) Knowledge Profile Complex Engineering Problem Complex Engineering
Activities
Depth Knowledge required (K3-K5, K8)

Consequence of Society/Environment
Range of Conflicting Requirements

Extent of stakeholder involvement

Project Management & Finance
Environment and Sustainability

Individual Work/Team Work

Depth of Analysis Required

Extent of Applicable Codes

Engineering Fundamentals
Engineering Knowledge

Specialist Knowledge
Modern Tools Usage

Engineering Practice

Level of Interactions
Familiarity of Issues

Range of Resources
Engineering Design
Engineer & Society

Life Long Learning

Research Literature
Design of Solution
Problem Analysis

Natural Sciences

Interdependence
Communication

Comprehension
Investigation

Mathematics

Familiarity
Innovation
Ethics

Depth

Course
Cr.
Code
PO10

PO11

PO12
PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

K1

K2

K3

K4

K5

K6

K7

K8

A1

A2

A3

A4

A5
P1

P2

P3

P4

P5

P6

P7

CSE 2204 1.50 √ √

I. Assessment and Marks Distribution
Students will be assessed on the basis of their overall performance in all the exams (class performance, reports,
quiz, viva, lab final, attendance, projects, and presentations). Final numeric reward will be the compilation of:
1. Continuous Assessment and Summative Assessment: Lab Report/ Lab Performance/ Viva/ Project/
Presentation/ Lab Final/ Attendance/ Quiz. (75%)
2. Board Viva: 25%

J. Grade Conversion Scheme

The letter grade system shall be used to assess the performance of the student and shall be as follows:
Numerical grade or % Letter grade Grade point
of Marks
80% or above A+ (A Plus) 4.0
75% to less than 80% A (A Regular) 3.75
70% to less than 75% A- (A Minus) 3.5
65% to less than 70% B+ (B Plus) 3.25
60% to less than 65% B (B Regular) 3.0
55% to less than 60% B- (B Minus) 2.75
50% to less than 55% C+ (C Plus) 2.5
45% to less than 50% C (C Regular) 2.25
40% to less than 45% D 2.0
Less than 40% F 0
Incomplete I -

K. Classroom
 Physical Classroom: TBA
 Virtual Classroom Platforms: TBA
 Virtual Classroom Code: TBA
 Virtual Classroom Instructions: TBA

L. Course Policy
1. Lab Performance and Lab Report: Lab reports needs to be submitted in each of the lab as per the
instructions of the instructors. Marks for lab performance and lab report will be awarded in each lab.
Finally, the average of all lab performance and lab report marks will be taken as the final marks.
2. Lab Final: For this course, lab final exam will be taken before the semester final. Notes or books are not
allowed in the lab final exam. Mobile phone is strictly prohibited.
3. Students Policy with Physically Handicapped: Students with disabilities are required to inform the
Department of Computer Science & Engineering of any specific requirement as soon as possible.
4. Make up class: Make up Classes is carried out when classes of scheduled time are hampered due to unwanted
situations (absence of faculty members, natural disasters etc.) in a free slot of the class schedule/routine.
Make up tests/quizzes can be taken for those students who cannot attain the tests due to sickness or weak in
understanding topics at weekend.
5. Cheating and Plagiarism: Adopting any kind of unfair means in the evaluation process will be penalized
according to the University Regulation and Code of Conduct.

M. Learning Materials:
Text Books
1. Digital System, Ronald J. Tocci
2. Digital Logic and Computer Design, Morris Mano
3. FPGA Prototyping Using Verilog Examples, Xilinx Spartan-3 Version, Pong P. Chu

Other Resources (Online Resources and Others)

1. TBA

N. Generic Skills
TBA
O. Project, Presentation & Report
TBA