Spectrum of Engineering Sciences

ISSN (e) 3007-3138 (p) 3007-312X

LOW-THD 110 V RMS, 60 HZ PROPORTIONAL-INTEGRAL

REGULATED SINGLE-PHASE FULL-BRIDGE INVERTER WITH 10 KHZ
SPWM AND LC FILTERING

Faqir Hussain

Department of Electrical Engineering, University of Engineering and Technology, Peshawar

[email protected]

DOI: https://doi.org/10.5281/zenodo.16779353

Abstract
Keywords The single-phase full-bridge inverter topology here shown illustrates a robust and
Closed-loop proportional–integral efficient means of DC input to a stable 110 V RMS AC output at 60 Hz. Sinusoidal
(PI) control, DC–AC conversion, pulse-width modulation (SPWM) with a high-frequency triangular carrier signal (10
High-frequency switching, LC kHz) allows for precise control of the four IGBT switches, and thus, the generation of
output filter, Single-phase full-bridge a high-quality AC waveform. The use of an LC low-pass filter (L = 4.06 mH, C =
inverter, Sinusoidal pulse-width 6.23 µF) further improves the output by filtering out the high-frequency components,
modulation (SPWM), Total thus contributing to the significantly low total harmonic distortion (THD) observed
harmonic distortion (THD), Voltage in voltage (--0.22%) and current. A closed-loop control system consisting of a
regulation, Renewable energy bandwidth-high PI controller (Kₚ = 21, Kᵢ = 0.03155) is tasked with maintaining
systems, Uninterrupted power the stability and quality of the output. Through constant comparison of the filtered
supplies (UPS) output with a 60 Hz reference signal, this controller adjusts the PWM duty cycle
dynamically to compensate for variations in load or DC-bus voltage. Such adaptive
Article History control allows the inverter to maintain its target output within ±2% of the nominal
Received: 04 May, 2025 value, even under severe load transients (±50%) and disturbances in the DC-bus. The
Accepted: 20 July, 2025 fast recovery time, within a fraction of a cycle, is reflective of the system's marvelous
Published: 08 August, 2025 dynamic response. Such performance attributes make the inverter design ideal for high-
quality, stable AC power sourcing applications, such as renewable energy systems and
Copyright @Author uninterruptible power supplies (UPS).
Corresponding Author: *
Faqir Hussain

INTRODUCTION
Single-phase full-bridge (H-bridge) inverters form the bidirectional current path and block voltage in both
foundation of countless DC-to-AC configurations in directions, makes it a darling in uninterruptible power
the modern power-electronic era. Its heart is a four- supplies (UPS), photovoltaic-to-grid interconnects,
semiconductor-switch bridge—most commonly IGBTs variable-frequency motor drives, and any ac application
or power MOSFETs—each associated with an anti- requiring a clean, regulated AC output [2]. In a single-
parallel diode [1]. Alternating the energization of the phase full-bridge inverter, the four switches (usually
opposite diagonal legs of the bridge causes the inverter IGBTs) are arranged as in Figure 1. The H-bridge
to switch the DC-bus polarity across its load, thus topology drives the DC input to the load in alternating
creating an alternating-voltage waveform. The polarities: one diagonal pair (S1 and S4) connects
topology's simplicity, coupled with its ability to offer a +𝑉𝑑𝑐 to the load (supplying +𝑉𝑑𝑐 /2), and the other

https://sesjournal.com | Hussain, 2025 | Page 203

Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
pair (S2 and S3) connects −𝑉𝑑𝑐 (supplying −𝑉𝑑𝑐 /2). The bridge schematic in Figure 1 makes visualization
Switching the pairs on and off at the high carrier of the power flow and switching strategy of this
frequency, the inverter produces a bipolar PWM structure easier [7].
waveform whose time-average tracks the reference sine.

Figure. 1. Schematic of the single-phase full-bridge (H-bridge) inverter. The diagonal leg pairs (S1+S4 and S2+S3)
alternate the applied voltage between +𝑉𝑑𝑐 /2 and −𝑉𝑑𝑐 /2to the load.

In control systems for critical mission equipment—e.g., But an open-loop SPWM scheme, as uncomplicated as
imaging equipment in medicine, precision laboratory it is, can't adapt to real-world perturbations: DC-bus
instruments, or control systems in nuclear reactors— voltage ripple, dynamic load transients, or line
the acceptable rate of deviation of voltage and impedance changes will all induce unwanted voltage
waveform distortion is extremely low. Any decrease in disparities or escalated harmonic distortion. To
amplitude or addition of low-order harmonics can combat the issue, we added a rapid feedback loop
degrade performance or compromise operational around the SPWM generator [5], [6]. A second-order
safety. To meet these demanding requirements, high- LC low-pass filter—designed on standard equations
performance H-bridge inverters nearly always employ 1
𝑓0 = set a fraction over 60 Hz, with damping
2𝜋√𝐿𝐶
pulse-width modulation (PWM) strategies in place of
coefficients chosen to attenuate ripple and give an
simple square-wave commutation [3]. Of the many
acceptable transient response) successfully eliminates
techniques, sinusoidal PWM (SPWM) is characterized
high-frequency switching noise, yielding an almost
by the simple correspondence between control inputs
pure 60 Hz sine wave . The filtered voltage is then
and output characteristics: a low-frequency sine
sampled and input to a proportional-integral (PI)
reference at the commanded mains frequency (e.g.,
controller operating at the carrier frequency. The PI
mains frequency 60 Hz) is continuously compared with
regulator continuously tracks the disparity between the
a high-frequency triangular carrier (10 kHz in this
measured RMS voltage and the desired setpoint of 110
example). Whenever the instantaneous reference is
V RMS, then corrects the reference amplitude for the
higher than the carrier, one of the opposing pairs of
SPWM module. This closed-loop configuration
switches is turned on; when it falls below the carrier,
effectively compensates for input and loading
the other pair is turned on . This produces a burst of
variations, thereby keeping the AC output within a few
rapid pulses, the time-averaged envelope of which
percentage points of the nominal value, even under
defines the sinewave. By varying the modulation
±50% load changes or DC-bus voltage ripple [7].
index,(𝑚)—ratio of the sine reference amplitude to the
In our MATLAB/Simulink simulation, the H-bridge
carrier amplitude—the inverter can regulate its
was modeled using ideal switch elements, an LC
fundamental output peak directly, allowing precise
output filter (L = 2 mH, C = 50 µF, size vs. attenuation
regulation of outputted RMS voltage [4].
optimized), and a discrete-time PI regulator optimized
by the Ziegler–Nichols method to a phase margin of

https://sesjournal.com | Hussain, 2025 | Page 204

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
over 45°. The carrier frequency was 10 kHz to force bridge's diagonal legs is energized "on," providing a
most of the harmonic energy above the hearing range connection between the load and +Vₙₒₘᵢₙₐₗ/2. Where
and reduce filter requirements. Simulation under step the sine falls below the triangular carrier, the other leg
changes in load—from 10 Ω to 5 00Ω resistive and is conducting, delivering –Vₙₒₘᵢₙₐₗ/2. The high-
inductive loads—and DC-input changes—from 160 V to frequency switching of these pulses, when observed
120 V—verified the loop's agility: voltage settled to through the eyes of a suitable filter, creates a near-
within 110 V ±2 V in less than 8 ms. Harmonic perfect sinusoid whose amplitude envelope traces the
analysis of the steady-state waveform produced a total reference [11]. By modulating the modulation index
harmonic distortion (THD) of about 0.22%, well 𝑉ref,peak
𝑚=
below IEEE-519 sensitivity guidelines for installations. 𝑉dc /2
The integration of SPWM with a high‐speed voltage‐ One directly adjusts the inverter's basic building block.
feedback PI control results in an inverter whose output An index of unity (m = 1) would elevate the peak of the
not only satisfies tight amplitude and distortion AC to the maximum possible by the DC bus; higher
requirements but also survives supply and load than that would clip at the bus voltage, thus resulting
disturbances reliably. Such performance makes it well‐ in serious distortion [12] . By selecting m < 1
suited for renewable energy inverters for weak grids, intentionally to begin with, we are safely within the
high‐reliability UPS systems, and high‐accuracy linear modulation range, thus waveform fidelity is
motor‐drive applications [8]. The mathematical basis guaranteed while effectively determining the nominal
of SPWM is discussed in the following sections, target of 110 V RMS (approximately 155.6 V peak)
followed by LC filter design and PI tuning procedure, from our 250 V DC source. To illustrate PWM
description of the entire Simulink architecture, and generation, Fig. 2 shows a simplified block diagram of
quantitative waveform and THD results that confirm the PWM modulator used in this inverter. In this
the effectiveness of the design. scheme, the sinusoidal reference (once again scaled by
the PI controller) is compared continuously to a 10
I. THEORY AND ANALYSIS kHz triangular carrier. When the reference is above the
A. Sinusoidal PMW Modulation carrier, one of the switch pairs in the H-bridge is turned
Sinusoidal PWM underlies contemporary single-phase on; otherwise, the other pair is on. The outputs of the
full-bridge inverter control [9]. Essentially, it places a comparators then pass through logic that imposes
low-frequency sinusoidal reference—oscillating at the complementary gating with a small dead-time (≈2 µs) to
target AC output frequency, usually 50 Hz or 60 Hz— prevent shoot-through. The result is a train of high-
over a much higher-frequency triangular carrier [10]. frequency pulses whose envelope tracks the 60 Hz sine
Wherever the instantaneous value of the sine reference reference, and these pulses drive the bridge switches.
is higher than that of the triangle wave, one of the H-

https://sesjournal.com | Hussain, 2025 | Page 205

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X

Figure. 2. Block diagram of a simplified PWM generator. The sinusoidal reference is compared repeatedly to a 10
kHz triangular carrier. Comparators produce turning-on one half-bridge at a time by gating pulses, and dead-time
logic (not shown) inserts a short off time between complementary switches to prevent simultaneous conduction.

In this scenario, C. Total Harmonic Distortion (THD) Measurements

2 × 155.6 Total Harmonic Distortion measures purity of AC
𝑚≈ ≈ 0.62
250 waveform in terms of ratio of the energy in all higher-
with the synthesized sine of the H-bridge oscillating order harmonics to the fundamental [15] .
precisely between ±155.6 V, without over-modulation. Mathematically,
The selection of a 10 kHz carrier is a practical √𝑉22 + 𝑉32 + 𝑉42 + ⋯
compromise: it diverts the most prevalent switching THD =
𝑉1
harmonics to frequencies far in excess of the 60 Hz
, where V₁ is the RMS of the fundamental and V₂, V₃,
fundamental—thus an easy target for a reasonable LC
etc., are the RMS of the 2nd, 3rd, and higher
filter—without overloading IGBT (or MOSFET)
harmonics. As a percentage, THD measures how
switching loss. A carrier too low to require an
"clean" the output of the inverter is—a very important
unrealistically large filter to suppress switching "spikes"
consideration for sensitive electronics or grid-
and one too high to cause device switching stress and
connected applications [16]. Standards like IEEE-519
thermal losses to skyrocket.
suggest voltage THD be around 5 – 8% for typical low-
voltage applications. Our requirement in simulation is
B. LC Output Filter Design and Damping
much more stringent: sub-0.5% THD, so that almost
In order to get a clean 60 Hz sine wave from the pulse
all output energy is in the desired 60 Hz sine.
train, we utilize a second-order low-pass filter, an
inductor (L) in series with the inverter output and a
D. Closed-Loop Voltage Regulation with Proportional-
capacitor (C) in parallel with the ground. The cutoff
Integral Control
frequency is given by
Open-loop SPWM gives the proper fundamental
1
𝑓𝑐 = amplitude only under ideal, steady conditions [17], [5].
2𝜋√𝐿 𝐶 Real-world load disturbances (such as a motor sucking
Plugging in L = 4.06 mH and C = 6.23 µF (our values in an unplanned burst of current) or DC-bus
from our Simulink model), we get oscillations (due to upstream converters or battery sag)
1
𝑓𝑐 ≈ ≈ 1 kHz will contaminate the output [18]. We put the SPWM
2𝜋√4.06 × 10−3 × 6.23 × 10−6 generator within a high-bandwidth feedback loop to
Positioning the corner at about 1 kHz leaves the 60 Hz compensate for these [19].
fundamental intact—no attenuation or phase shift of
any consequence—while giving steep roll-off against the 1) Sensing & Error Generation:
10 kHz switching artifacts. The filtered AC voltage is compared with the 60 Hz
Real inductors and capacitors are never ideal, so we reference voltage of 110 V RMS and sampled to be
balance parasitic resistances so that any filter resonance converted to an instantaneous error, e(t).
is in check. The inductor winding resistances, Rₗ ≈
0.001 Ω, and the capacitor equivalent series resistance, 2) Proportional-Integral (PI) Action
Rc ≈ 0.0042 Ω, leave just enough damping to prevent The controller calculates
ringing at the corner frequency without overloading 𝑡
the 50 Ω nominal output excessively [13] , [14] . These 𝑢(𝑡) = 𝐾𝑝 𝑒(𝑡) + 𝐾𝑖 ∫ 𝑒(𝜏)𝑑𝜏
milliohm-scale losses have a negligible effect on 0
Modulating reference amplitude to compensate for
efficiency but guarantee stability and controlled
imbalances.
transient response when the inverter steps or the load
abruptly changes.

https://sesjournal.com | Hussain, 2025 | Page 206

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
3) Tuning Gains 2) IGBT H-Bridge: Instead of employing the
With the ≈1 kHz bandwidth of the LC filter, controller standard "Universal Bridge" component, we employed
gains need to be high enough to correct rapidly but low four individual IGBT devices with anti-parallel diode
enough to avoid oscillatory action or noise configurations. The on-state resistance of each
amplification. Through iterative, step-response testing transistor is given as Rₒₙ = 1 mΩ to provide conduction
in Simulink, we selected Kₚ = 21 and Kᵢ = 0.03155. losses, and each device has a large snubber resistor
These give a damping ratio sufficient to eliminate (R_snub = 1×10⁵ Ω) in parallel to simulate almost ideal
voltage errors in less than an eighth of the 16.7 ms AC turn-off without unwanted stored charge. All device
cycle whenever the load doubles or the DC bus drops parameters (e.g., threshold gate and Miller capacitance)
by 20%. are set to default values, with the exception of the two
given resistances, thus ensuring the switch transitions
4) Performance Under Stress are made as close to instantaneous in time-domain
In our test cases—doubling the load from 10 Ω to 5 Ω models. The IGBTs are configured such that S1 and
(100% increase), and shifting the DC-bus from 250 V S4 switch in the positive half cycle and S2 and S3
to 200 V—this PI scheme returns the output to 110 V switch in the negative half cycle, thus providing
±2 V in less than 8 ms. The rapid recovery and steady- ±V_dc/2 across the bridge terminals.
state THD of ≈0.22% attest the efficacy of the
controller. 3) Gate-Driver Logic & SPWM Generation:

II. EXPERIMENTAL PROCEDURES (METHODOLOGY) A "Sine Wave" block creates the 60 Hz reference. Its
amplitude is set to 155.6V to precisely reach our target
A) Simulink Model Overview of 110V RMS.
In our Simulink implementation, we tried to make the A "Repeating Sequence" block will produce a
behavior and parasitics of a real inverter system as close triangular waveform of ±1 V at 10 kHz.
to real life as possible, while still keeping the power The sampling interval is set to 1
stage fully software-defined. The whole model is in one µs, consistent with the switching period required.
Simscape Electrical (Power Systems) environment, Four "Switch" blocks function as rapid comparators.
which has clear subsystems for the load, the output Within each block, the system continuously checks
filter, the DC supply, the switching bridge, and the whether 𝑽ref_scaled exceeds 𝑽tri
gate-drive network. We will now go into more detail and subsequently activates the corresponding gate
about each block: driver output.
1) DC Source: A particular Simscape "DC Voltage Under steady-state conditions, the raw (pre-filtered)
Source" block has been defined to deliver a stable and output of the inverter is a 10 kHz PWM pulse train.
unregulated 250 V output. The block's internal One cycle of this unfiltered bridge output at nominal
resistance has been set to zero intentionally, hence operating conditions is presented in Figure 3. The
modeling an ideal bus that may be powered by a high- voltage switches between +125 V and –125 V (half the
capacity battery or a stringently regulated front-end 250 V DC bus) in pulses of different widths. The
converter. In addition, a small series measurement dashed line in Figure 3 is the 60 Hz sinusoidal
resistor (0.01 Ω) is included for the sole purpose of envelope created by the reference. The high-frequency
power measurement, allowing the DC-side current to pulses that contain the switching harmonics are what
be sensed without putting a significant load on the the LC filter needs to eliminate.
source.

https://sesjournal.com | Hussain, 2025 | Page 207

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X

(a)

(b)

Figure. 3. (a) Raw (unfiltered) inverter output voltage (prior to LC filter). The waveform alternates between +125
V and –125 V at 10 kHz in a PWM pattern. The 60 Hz sinusoidal reference envelope is shown by the dashed
outline. After the LC filter, the output is almost a pure sinewave. (b) Zoomed In Version.

Logical inversion and signal-routing sub- inductive reactance X_L ≈ 0.001 Ω is essentially zero,
systems insert dead-time of 2 µs between and the load is essentially a pure resistive sink. This
complementary legs to prevent any conduction at the simplification represents a wide class of appliances or
same time that would create shoot-through. We grid‐tied inverters and allows us to concentrate on
verified the dead-time by examining gate waveform voltage regulation performance without the need for
overlays in Scope blocks. complicated load dynamics.

4) LC Output Filter: 6) Measurement and Analysis Suite: In order to check

Right next to the bridge, a series inductor (L = 4.06 steady-state and transient behavior, we provided the
mH) with an explicit series resistance R_L = 0.001 Ω model with:
drives a shunt capacitor (C = 6.23 µF) with ESR R_C A) Voltage and current sensors on DC bus and load side,
= 0.0042 Ω. These were selected to place the filter's directed through "PS-To-Simulink" converters to
natural cutoff frequency at around 1 kHz—high enough numerical logging.
above the 60 Hz fundamental to prevent phase shift, B) RMS Measurement Blocks, being designed only to
but low enough below the 10 kHz switching harmonics measure the 60 Hz frequency component, give
to exert strong attenuation. We also added a small instantaneous RMS readings of 𝑽load and 𝑰load .
parallel damping resistor (100 Ω) across the capacitor C) An FFT Analysis block, set for a 4096‐point transform
to dampen any filter resonance peaks in the 800–1,200 for a 0.1 ms sampling window, extracts harmonic
Hz region. To see the filter operate, we initialized both amplitudes to the 25th order. These harmonics are fed
inductor current and capacitor voltage states to zero into a special THD calculator where
and added an initial transient "precharge" hold of 5 ms, 𝑁
allowing the filter network to settle before the SPWM √∑ 𝑽𝟐
𝒏=𝟐 𝒏
begins. 𝐓𝐇𝐃 = × 𝟏𝟎𝟎%.
𝑽𝟏
D) Display Blocks display 𝑷in = 𝑽dc ⋅ 𝑰dc , 𝑷out =
5) Load Emulation: The load is modeled as a series R–L 𝑽load,rms ⋅ 𝑰load,rms, real‐time THD (%), and overall
branch with R = 50 Ω and L = 3 µH. At 60 Hz, the

https://sesjournal.com | Hussain, 2025 | Page 208

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
𝑷out format for later analysis in MATLAB, facilitating easy
𝜼= × 𝟏𝟎𝟎%
𝑷in waveform plotting, calculation of settling time, and
, giving instantaneous insight into converter precise spectral analysis. The Simulink design creates a
performance under step changes or steady‐state viable, high-fidelity test environment by building each
conditions. subsystem from distinctly defined component
parameters, realistic parasitic elements, and particular
7) Solver and Simulation Settings: We chose the fixed- measurement channels.
step "ode4" solver, with a step size of 1 µs, that This framework not only confirms the theoretical
simulates the 10 kHz switching dynamics accurately design specifications—110 V RMS regulation, lower
without incurring excessively long simulation times. than 0.5% total harmonic distortion, and settling
The simulation runs for 100 ms—sufficient to catch times of less than 10 milliseconds—but also lays the
both startup transients and a few mains cycles. All groundwork for future enhancements, such as non-
measured data are stored in high-resolution timeseries linear loads, grid-synchronization procedures, or
advanced modulation methods.

Figure. 4. Simulink block diagram of the closed-loop single-phase full-bridge inverter system, showing the 250 V
DC source, IGBT H-bridge, LC filter, and load. Sine and triangular waveform blocks generate SPWM gate signals,
and the PI controller closes the voltage feedback loop.

B) Control Loop and Signal Generation only the RMS) we feed the filtered waveform into
In our closed-loop design, the controller regulates the another measurement block running at full PWM rate.
SPWM reference to maintain a filtered output at
around 110 V RMS. The principal elements are: 2) Error Signal Generation
At every time step, the instantaneous error
1) Reference and Feedback Comparison 𝒆(𝒕) = 𝑽ref (𝒕) − 𝑽out (𝒕)
A 60 Hz voltage which is a sinusoid having the value of is calculated. This leaves the low-frequency (60 Hz) and
155.6 V where to peak and zero volts corresponds an any small residual high-frequency components, so the
RMS with equation: controller "sees" very small variations from the ideal
𝑽ref (𝒕) = 𝟏𝟓𝟓. 𝟔 𝐬𝐢𝐧(𝟐𝝅 ⋅ 𝟔𝟎 𝒕) sine.
The real-time sensed and feedback control output
voltage after the LC filter, 𝑽out (𝒕), is redirected from 3) PI Regulator Implementation
load. To measure its instantaneous value (rather than

https://sesjournal.com | Hussain, 2025 | Page 209

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
In Simulink, both integral and proportional actions Each simulation lasts 200 ms, including startup,
are implemented as: steady‐state, and recovery from disturbance. A 5 ms
A Gain block (gain 𝑲𝒑 = 𝟐𝟏) multiplying 𝒆(𝒕) pre-drive delay is employed to allow filter states to be
An Integrator block (gain 𝑲𝒊 = 𝟎. 𝟎𝟑𝟏𝟓𝟓) integrating initialized without noise switching. Approximately 20
𝒆(𝒕) ms thereafter, steady‐state data acquisition begins:
A Sum block to sum these two inputs together to create waveforms of 𝑉out (𝑡) and 𝐼load (𝑡) are sampled at 100
the control effort, 𝒖(𝒕). kHz, RMS values are monitored in sliding one-cycle
Therefore, windows, THD is calculated on-line. Dynamic tests
𝒕 utilize ±50 % steps in load resistance (50 Ω ↔ 25 Ω or
𝒖(𝒕) = 𝑲𝒑 𝒆(𝒕) + 𝑲𝒊 ∫ 𝒆(𝝉) 𝐝𝝉 100 Ω) and ±10 % DC-bus variations (250 V ↔ 225
𝟎
To avoid integrator windup under large transients, an V/275 V) at 𝑡 = 100 ms. In every case, we measure
anti-windup limiter limits the integrator output to ±0.5 settling time (return to within ±1 % of 110 V), peak
(in normalized units). overshoot/undershoot, and worst‐case steady‐state
error.

4) Modulation Reference Adjustment III. RESULTS AND DISCUSSION

The PI output, 𝒖(𝒕), which dynamically scales the sine A) Steady-State Waveforms
reference amplitude. It can also be visualized as adding Under nominal conditions (250 V DC, 50 Ω load), the
an offset to the threshold of the comparator. output of the filtered signal is a textbook sinusoid:
Specifically, the comparator blocks now check Voltage: 𝑉out (𝑡) 155.6 V with minimal high-frequency
𝑽ref (𝒕) × [𝟏 + 𝒖(𝒕)] ≷ 𝑽tri (𝒕) , ripple (<1 V p-p) only barely discernible with 10 kHz
so when 𝑽out < 𝑽ref , 𝒖 > 𝟎 increases the pulse width; scope zoom. RMS reading is still 110.0 V to ±6 V.
in contrast, when 𝑽out > 𝑽ref , 𝒖 < 𝟎 contracts it. 𝐼load (𝑡) ≈ 2.24 A (110 V/50 Ω), phase-aligned to the
voltage within <0.2°
5) PWM Generation and Dead-Time Figure 5 shows a typical cycle of the filtered output
The 10 kHz triangle, 𝑽tri (𝒕), is created by a Repeating voltage waveform in steady state. The waveform is
Sequence of linear ramps. Four Switch blocks compare nearly sinusoidal with a peak of ~155.6 V and a small
the scaled carrier and reference to produce raw gate residual ripple (visible only at high resolution).
commands. Complementary gating for every half-
bridge is enforced through logical inverters and a 2 μs Figure 6 illustrates the load current waveform
dead-time insertion submodule, ensuring that no two corresponding to it. Due to the fact that the load is
transistors in the same leg are ever on at the same time. primarily resistive (50 Ω), the current is almost
All transitions occur at the 1 μs simulation step—equal sinusoidal and in phase with the voltage. Its amplitude
to the PWM period—so switching transitions, dead- is approximately 2.2 A RMS (110 V/50 Ω). The filter
time intervals, and sub-cycle controller corrections are also suppresses high-frequency noise in the current –
accurately modeled. as is evident from the FFT (Figure 3), the harmonic
content of the current is insignificant (THD ≈0.2%).
C) Simulation Procedure This validates the fact that the load experiences an
almost pure sinusoidal current.

https://sesjournal.com | Hussain, 2025 | Page 210

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X

Figure 5: Steady-state output voltage waveform (110 V RMS, 60 Hz) after the LC filter.

Figure 6: Filtered output current waveform (steady-state) at the load. The 50 Ω load absorbs an almost pure 60
Hz sinusoidal current (~2.2 A RMS) in phase with the voltage. High-frequency harmonics are significantly
eliminated (THD ≈0.2%).

B) Total Harmonic Distortion Sum of all harmonics above fundamental gives

From this waveform, an FFT was performed to THD ≈ 0.22%,
quantify harmonics. Figure 7 presents the FFT spectra well below the 5% level mandated by IEEE- 519
of the output voltage and output current. FFT analysis and according to the design requirement.
gives:
𝑉1 = 110.0 V, 𝑉3 ≈ 0.10 V, 𝑉5 ≈ 0.05 V, … C) Transient Response

https://sesjournal.com | Hussain, 2025 | Page 211

Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
Load Step (–50% R): The voltage falls to 107 V These results confirm the rapid, well-damped
momentarily (–2.7%), and PI action restores it to 110V operation of the controller, as desired 𝐾𝑝 and 𝐾𝑖 gains
in 6 ms with <1% overshoot. Bus Sag (–10% Vdc): against both load and source disturbances.
Output drops to 108 V (–1.8%), recovers to 110 V in
8 ms and stabilizes without oscillations.

(a)

b)

https://sesjournal.com | Hussain, 2025 | Page 212

 Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
Figure 7: FFT spectrum of the steady-state output. (a) Voltage spectrum: the 60 Hz fundamental is shown at 0 dB,
and all harmonics (especially switching-related frequencies) are suppressed by >60 dB. (b) Current spectrum:
similarly, mostly fundamental with negligible harmonics. Both show THD ≈0.2%.

D) Dynamic Response and Regulation This boundary establishes the inverter's minimum
For the overall evaluation of closed-loop performance, supply level.
we employed sudden load and supply voltage Harmonic Performance: The FFT spectra (Figure 7)
disturbances to the inverter. validate the very high purity of the output. Without
1) Load-Step Disturbances (±50 %) resorting to any other harmonic-cancellation
Increased Load (R: 50 Ω → 25 Ω): Reducing the load methods—just straight SPWM and a properly tuned LC
impedance by half doubles the need for instantaneous filter—we have a voltage THD of ≈0.22 %. Third- and
current, reducing the filtered output voltage below the fifth-order terms at 300 Hz and 500 Hz are reduced
110 V setpoint. Our high-gain PI regulator senses the below –60 dB, and switching harmonics of higher
negative error and proportionally increases the SPWM order near 10 kHz are nicely rejected by the filter. For
reference amplitude, increasing the pulse widths. In comparison, IEEE-519 requires voltage THD ≤5 %–8
approximately one fundamental period (≈16.7 ms), the % for low-voltage grids; our design is over an order of
output is settled to within 1 % of its nominal RMS magnitude above this.
value. Full settling within ±0.5 % takes less than two
cycles (≈33 ms), with no visible overshoot or ringing IV. CONCLUSION
due to the well-damped LC filter and anti-windup This research has been able to show the ability of a
limiter in the integrator. Reduced Loading (R: 50 Ω → single-phase H-bridge inverter, SPWM-controlled at a
100 Ω): It reduces the load current to half by doubling 10 kHz switching frequency and regulated by a high-
the impedance, driving the output slightly above 110 speed proportional-integral (PI) voltage feedback loop,
V for a short time. The feedback loop instantaneously to be able to generate consistently a 110 V RMS, 60 Hz
cuts down the PWM pulses to a reduced width, AC output from any DC voltage source of equal or
returning regulation. The peak deviation is still less greater magnitude than 110 V. One of the most
than +2 % and the system stabilizes in steady-state important features of this design is that it operates in
within a single cycle, confirming symmetric response to linear SPWM mode at a modulation index of
heavier and lighter loads. approximately 0.62, well below the over-modulation
threshold. This keeps the output waveform sinusoidal
2) DC-Bus Perturbations (±10 %) and unclipped, eliminating the necessity for more
Bus Sag (Vdc: 250 V → 225 V): The 10 % voltage sag advanced modulation schemes like space-vector PWM
causes an instantaneous output deflection of or harmonic injection.
approximately –2 %. The PI loop then recovers by The inverter uses an LC filter with the components
commanding increased duty cycles and reaching full of 𝐿 = 4.06 mH and 𝐶 = 6.23 𝜇F, with realistic
RMS amplitude again after approximately 20 ms. Bus parasitic resistances. The configuration achieves a
Rise (Vdc: 250 V → 275 V): In contrast, a 10 % bus sharp cutoff around 1 kHz, which is effective in
rise in Vdc causes a temporary overvoltage +2 %; the attenuating the 10 kHz switching harmonics without
controller responds by decreasing pulse widths. significantly affecting the 60 Hz fundamental
Regulation is regained within less than 25 ms without frequency integrity. The PI controller, optimized for
oscillation. gains 𝐾𝑝 = 21 and 𝐾𝑖 = 0.03155, possesses better
Throughout all testing, the worst-case steady-state error dynamic performance. It compensates well for voltage
stayed within ±2 % of 110 V, complying with—and in oscillations caused by sudden load changes of ±50%
some tests exceeding—standard UPS performance and DC-bus disturbances of ±10% in one to two cycles.
levels. Observe here that regulation is impossible if the The worst-case steady-state error obtained is less than
DC bus drops below ~110 V, since there isn't enough ±2%, which is a reflection of robust regulation.
headroom to synthesize the desired AC amplitude. Most significantly, the inverter includes an
exceptionally low total harmonic distortion (THD) of

https://sesjournal.com | Hussain, 2025 | Page 213

Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
about 0.22% without the use of any sophisticated B. Hemanth Kumar, S. Prabhu, K. Janardhan, V.
harmonic compensation methods. Such a level of low Arun, and S. Vivekanandan, “A Switched
distortion is well beyond the needs of most grid- Capacitor-Based Multilevel Boost Inverter for
interconnection standards and places the inverter in a Photovoltaic Applications,” J CIRCUIT SYST
position to be used in applications where power quality COMP, vol. 32, no. 04, p. 2350057, Mar.
is of utmost importance. Some examples include 2023, doi: 10.1142/S0218126623500573.
renewable energy systems, uninterruptible power L. Qin, B. Duan, J. L. Soon, W. Hassan, J. Shen, and
supplies (UPS), and sensitive industrial or medical L. Zhang, “Hybrid PFM and SPWM Control
loads. Scheme for DCM Single-Leg-Integrated Boost
In the future, a number of strategies would enhance Inverter,” IEEE Trans. Ind. Electron., vol. 70,
the inverter's performance further. The inclusion of no. 12, pp. 12288–12298, Dec. 2023, doi:
sophisticated modulation techniques such as space- 10.1109/TIE.2023.3236094.
vector PWM or selective harmonic elimination would E. H. E. Aboadla, S. Khan, M. H. Habaebi, T.
decrease distortion further or enable more efficient Gunawan, B. A. Hamidah, and M. B. Yaacob,
thermal and switching stress management. The “Effect of modulation index of pulse width
inclusion of double-loop control with an inner current modulation inverter on Total Harmonic
loop would enhance transient response dramatically, Distortion for Sinusoidal,” in 2016
provide more robust fault management, and enable International Conference on Intelligent Systems
sophisticated features such as islanding detection for Engineering (ICISE), Islamabad, Pakistan:
grid-connected systems. Furthermore, switching to IEEE, Jan. 2016, pp. 192–196. doi:
higher switching frequencies—20 kHz to 50 kHz— 10.1109/INTELSE.2016.7475119.
particularly with silicon carbide (SiC) or gallium M. G. M. Abdolrasol, M. A. Hannan, S. M. S. Hussain,
nitride (GaN) devices, would decrease the size of and T. S. Ustun, “Optimal PI controller based
passive components and increase power density. Lastly, PSO optimization for PV inverter using
the modeling of real-world losses in power switches and SPWM techniques,” Energy Reports, vol. 8, pp.
magnetic devices would enable more realistic 1003–1011, Apr. 2022, doi:
predictions of thermal and efficiency that are critical to 10.1016/j.egyr.2021.11.180.
real-world hardware development. In conclusion, this S. K. Yadav, A. Patel, and H. D. Mathur, “PSO-Based
paper validates that a simple full-bridge SPWM Online PI Tuning of UPQC-DG in Real-
inverter, when supported by an optimally designed Time,” IEEE Open J. Power Electron., vol. 5, pp.
filter and an adaptive feedback control loop, can meet 1419–1431, 2024, doi:
high standards of power quality and be extremely 10.1109/OJPEL.2024.3445719.
robust in the face of real-world disturbances, which P. Bistak, M. Huba, D. Vrancic, and S. Chamraz,
occur in the field. This offers a solid foundation for “IPDT Model-Based Ziegler–Nichols Tuning
further research in academia and field implementation Generalized to Controllers with Higher-Order
in industry and commerce. Derivatives,” Sensors, vol. 23, no. 8, p. 3787,
Apr. 2023, doi: 10.3390/s23083787.
REFERENCES Y. Peng, W. Sun, and F. Deng, “Internal Model
C. I. Odeh, A. Lewicki, and M. Morawiec, “A Single- Principle Method to Robust Output Voltage
Carrier-Based Pulse-Width Modulation Tracking Control for Single-Phase UPS
Template for Cascaded H-Bridge Multilevel Inverters With Its SPWM Implementation,”
Inverters,” IEEE Access, vol. 9, pp. 42182– IEEE Transactions on Energy Conversion, vol. 36,
42191, 2021, doi: no. 2, pp. 841–852, June 2021, doi:
10.1109/ACCESS.2021.3065743. 10.1109/TEC.2020.3030894.

https://sesjournal.com | Hussain, 2025 | Page 214

Spectrum of Engineering Sciences
ISSN (e) 3007-3138 (p) 3007-312X
H. Wang et al., “Harmonic Spectra Analysis of Digital S. Mondal, S. P. Biswas, Md. R. Islam, and S. M.
SPWM in VSI With DC Bus Ripple and Dead- Muyeen, “A Five-Level Switched-Capacitor
Time Effects,” IEEE Trans. Power Electron., vol. Based Transformerless Inverter With Boosting
38, no. 8, pp. 9494–9513, Aug. 2023, doi: Capability for Grid-Tied PV Applications,”
10.1109/TPEL.2023.3272381. IEEE Access, vol. 11, pp. 12426–12443, 2023,
B. H. Kumar, M. M. Lokhande, K. R. Reddy, and V. doi: 10.1109/ACCESS.2023.3241927.
B. Borghate, “An Improved Space Vector S. Ahmad et al., “Direct Power Control Based on
Pulse Width Modulation for Nine-Level Point of Common Coupling Voltage
Asymmetric Cascaded H-Bridge Three-Phase Modulation for Grid-Tied AC Microgrid PV
Inverter,” Arab J Sci Eng, vol. 44, no. 3, pp. Inverter,” IEEE Access, vol. 10, pp. 109187–
2453–2465, Mar. 2019, doi: 10.1007/s13369- 109202, 2022, doi:
018-3586-3. 10.1109/ACCESS.2022.3213939.
J. Soomro, T. D. Memon, and M. A. Shah, “Design S. Swain and B. Subudhi, “Grid Synchronization of a
and analysis of single phase voltage source PV System With Power Quality Disturbances
inverter using Unipolar and Bipolar pulse Using Unscented Kalman Filtering,” IEEE
width modulation techniques,” in 2016 Transactions on Sustainable Energy, vol. 10, no.
International Conference on Advances in 3, pp. 1240–1247, July 2019, doi:
Electrical, Electronic and Systems Engineering 10.1109/TSTE.2018.2864822.
(ICAEES), Nov. 2016, pp. 277–282. doi: H. Wu, S.-C. Wong, C. K. Tse, and Q. Chen,
10.1109/ICAEES.2016.7888052. “Control and Modulation of Bidirectional
J. Sabarad and G. H. Kulkarni, “Comparative analysis Single-Phase AC–DC Three-Phase-Leg
of SVPWM and SPWM techniques for SPWM Converters With Active Power
multilevel inverter,” in 2015 International Decoupling and Minimal Storage
Conference on Power and Advanced Control Capacitance,” IEEE Transactions on Power
Engineering (ICPACE), Aug. 2015, pp. 232– Electronics, vol. 31, no. 6, pp. 4226–4240, June
237. doi: 10.1109/ICPACE.2015.7274949. 2016, doi: 10.1109/TPEL.2015.2477504.
M. Bartoli, A. Reatti, and M. K. Kazimierczuk, High-
frequency models of ferrite core inductorsProceedings
of IECON’94 - 20th Annual Conference of IEEE
Industrial Electronics. 1994. doi:
10.1109/IECON.1994.398065.
M. J. Ryan and R. D. Lorenz, “A high performance sine
wave inverter controller with capacitor current
feedback and ‘back-EMF’ decoupling,” in
Proceedings of PESC ’95 - Power Electronics
Specialist Conference, June 1995, pp. 507–513
vol.1. doi: 10.1109/PESC.1995.474857.
T. Sakurai and H. Haga, “Power Decoupling Control
of Electrolytic Capacitor-Less Dual-Inverter to
Reduce Interharmonic Currents Under
Periodic Load Fluctuation,” IEEJ Journal of
Industry Applications, vol. 12, no. 5, pp. 990–
999, 2023, doi: 10.1541/ieejjia.22011386.

https://sesjournal.com | Hussain, 2025 | Page 215